Stage programmable light sequencer for a toy

STAGE PROGRAMMABLE LIGHT SEQUENCER FOR A TOY

BACKGROUND OF INVENTION

0003The present invention relates to a light sequencer for a toy/ and more particularly one where low cost means enables each stage to be individually and dif ferently programmed from any other .

PRIOR ART

0005Light sequencers in toys either involved oscillator - controlled shif t registers, followed by latching switches_/ where each stage was limited to the identical time period of it s neighbor , or some multiple thereof / or the shif t register comprised a string of individually programmed 555 type of time- delay integrated circuits f ollowed by latching switches .

0006The present invention eliminates ^•'he need for costly oscillators/ latching switches_/ time - delay integrated circuits combined with latching switches . By using a hysteresis element to control the gain of an amplif ier/switch/ a simple Resistor-capacitor circuit of almost any ratio can be used to set the t ime f or each stage/ and the circuit provides all the advantages of a latching switch_/ without the need or cost of them .

SUHHARY OF THE INVENTION

0008In a light sequencer for a toy, a plurality of light s is controlled individually and in groups_/ sequentially in ring structure/ with individually progra mably set on and of f times controlled by simple resistor/capacitor circuits. Each stage has an input capacitor which capacitlvely couples its input to ground_/ and a drive- resistor through which it receives its positive and negat ive drive f ro* the previous stage_/ or f roii a power supply .

0009ET 2.

0010When the drive end of the drive- resistor is connected to a source of positive bias voltage/ the voltage across the input capacitor slowly rises . »?hen the drive end of the drive- resistor is then connected to ground_/ or a source of negative bias voltagβ/ the voltage across the input capacitor slowly declines. This action of its own would produce a triangular shaped waveform whose rise and fall times are controlled by the R- C time constant of the input capacitor and the drive-resistor/^' which can be varied to control the period of the wavef orm . The slowly rising wavefor* is connected to the input of an amplifier/switch whose gain is cont rolled by a hysteresis element_/ and whose output is connected to a load element such as a resistor or light/ as well as to the drive end of the drive-resistor of the next stage.

0011When the rising voltage across the input capacitor is below the f iring or breakdown voltage of the hysteresis element / the gain .f the amplif ier/switch is negative/ therefore it is nonconductive and provides no voltage to its load element or lisht . The drive end of the drive-resistor ,of the next s .tge now receives full positive bias through the lo-sd element or light of this stage.

0012Because the load element or light may demand anywhere f rom 10 mil amps ( . 01 Amps . > through several amperes, and the drive current going through the drive-resistor anywhere f rom a nanoampere ( 1X10" ' Amps . ) through <nX10- ^β Amps . ⁾ several microamperes/ the ratio of load current to drive is always greater than 5000 : 1. Therefore the drive current is transparent to the load .

0013When the slowly rising voltage across the input capacitor exceeds the firing or breakdown voltage of the hysteresis element _/ it

0014SUBS ^T τεiδ^¹switches - into a high - conduction state/ thereby switching the amplifier/switch into its high gain conduction state/ providing full voltage to the load element or light_/ and beginning negative bias to the drive end of th drive - resistor of the next stage/ thereby causing de '.ine in the voltage across the input capacitor of the next stage.

0015Because the gain of the amplifier/switch of the next stage is also controlled by a hysteresis element still in its high-conduction state, the load element or light of the next stage remains on, even with the voltage across its input capacitor in decimation . This state continues_* until its input capacitor voltage drops to just below the recovery voltage of the hysteresis element . At this point , the hys'eresis element recovers to its non-conduction state, the amplifier/swir . ^•■;*^■. gain goes negative and non conductive_/ turning of f the voltage to its load element or light . By this action_., however, the drive end of the drive- resistor of the stage following this one, now receives posit ive bias, which will eventually turn it on .

0016Because there is a delay between the time when the light of one stsge turns of f , and ihe next turns on , and when one turns on and the next one turns of f , and each of the times can be made dif ferent by just varying the value of the drive- resistor or input capacitor of a particular stage, the operation of this toy is much more complex than its simple structure and Jow cost would lead one to expect .

SUBSTITUTE SHEET DESCRIPTI01I OF THE DRAW IHGS

0018FIG. 1 is a schematic presentation of the preferred embodiment sectioned according to function .

0019FIG. 2 is a graph display of the switching characteristics of a hysteresis element.

0020FIG. 3 is an equivalent circuit of any 4 layer thyristor device applied as a hysteresis element .

0021FIG . 4 is a schematic of a KPU thyristor device ( programmable unijunction ) applied as a hysteresis element .

0022FIG . 5 is an alternate embodiment of the present invention sectioned correspondingly to FIG . 1.

0023FIG . 6 is a fully designed 2 - input NAND hysteresis gate asymetrical f lip - f lop_/ which completely conforms with the speci ications.* of this disclosure, and is pinned in conformance with element one of the No . 4093 quad . .

0024FIG . 7 is a pinned illustration of element one of tne No . 4093 quad , utilized in the alternate embodiment of this invention.

PREFERRED EHBODIKENT

0026Referring now to FIG . 1 there is shown a diagram of the basic elements of a stage programmable light sequencer for a toy . The negative terminal of the battery is connected to common terminal 10. Positive terminal of the battery is connected through terminal 9 of the timed automatic power turn-of f to B* terminal 11_/ or it may be directly connected to terminal 11/ to provide the positive power supply/ which is needed to power light sequencer sections-A through sections-N .

0027SUBSTITUTE SHEET Referring now to Section A of FIG. 1 transistor Q₃ is a T-MOS/ field ef fect transistor having a gate 12 source 13 and drain 14. Drain 14 is con scted to a supply of positive voltage at terminal 11 through a load circuit means which is designated in section A a ^~ l_x lamp, however it * is within the contemplation of the present invention that a plurality of lamps or resistors and LEDs can be used/ as well as a bias resistor 19 used to control power switching transistor Q_β of the timed automatic power turn - of f of section T . The source 13 is connected to a supply of negative voltage at common terminal 10 through a hysteresis element H-18. The gate 12 is connected to common terminal 10 through input capacitor C and to a source of drive voltage designated in FIG . 1 as the drain 14 of transistor Q_N of section N through drive- resist or Rύ . The .drain 14 which has just been described as driving the load means, is also the ovtput terminal of section A and provides the source of drive voltage for^' the following stage through drive- resistor RD₃. Whereas the circuit conf iguration of each stage is the same ΛS the ones preceeding and following it , it is within the contemplation of this invention to vary the nυmcer of lights υf each stage, as well as the timing of each stage Dy varying the values assigned to the drive-res' stor capacitor combinations of each stage .

PREFERRED EHBODIPENT CIRCUIT OPERATION

0029The T - MOS f ield e f f ect transistors are being used as common source ampli f iers . To the hysteresis element , however, they represent source followers providing voltage at low source impedance . The source to drain ON resistance of the T - MOS transistor can be as low as .5 Ohms.

0030SUBSTITUTE SHEET Its gate input i -nc. I. a very high 10' Oh , So the D_:. circu_it sees no load except itself. Because the drain load impedance is fixed, the voltage gain of each stage is totally controlled by t>. internal im_pedance ^" of _* the hysteresis element which switches from essentially infinate resistance prior to firing/ to very low ⁽1.3 volts saturation voltage⁾ after firing.

0031Reference is now made to the hysteresis element equivalent circuit shown' in FIG. 3. For illustration purposes Z provⁱdes -5 volts between terminal 8 and common terminal 10. The ^♦ 5 volts ⁱs conducted to _base 3 of PNP transistor ^Q> and collector 6 of NPN rrms_istor _Q2 through a 100K Ohm biasing resistor . The -5 volts reverse biases the base-emitter junction of transistor ^Q_x so there _;s no conduction between its collector 4 end the base 5 of .ran.ι.t,r _Q,. Therefore both transistors are fully turned off. Then the pos_it_ive voltage between teriunalc 1 tnd 10 exceeds by .65 _Volts dhe forward voltage drop of the base-emitter diode of 0,.⁾ πe reverse ;bιas positive voltage between termⁱnals 8 and 10, _•-ars-stor _Qx goes into conduction providing forward bⁱas to oa e 5 of transistor _Q„ there_by turning it on. When transⁱstor 0_a turns on, _its collector 6 both forward biases the base 3 of transⁱstor ^Q and clamps the reverse biasing positive voltage at the base of rrana-_βtor _Q. down to the ^' saturation voltage of ^Q- < ^• 65 volts⁾. Ther_efore the sw_itching voltage between term-nals 1 and 10 has been reduced from -5.65 volts to .1.3 volts. When the positⁱve voltage _between terminals 1 and 10 drops much below 1.3 volts^, the forward voltage drop of the base -emitter junction of both transⁱstors -ennot be overcome, and the transistors stop conducting, there^by return_ing the reverse bias to -5 volts. The difference between the _breakdown voltage of 5.65 volts and the recovery voltage of 1.3 volts is the hysteresis factor.

SUBSTITUTE SHEET 7

0033Hysteresis factors can also be generated by using asymetrical flip-flops, and such has been contemplated in our alternate embodiment as illustrated in FIG. 5.

0034Any thyristor PNPN or NPNP device can be gated to prcduce a hysteresis element of exact breakdown and recovery voltage specifications. For reasons of brevity we are limiting our illustrations.

0035FIG. 4 illustrates a programmable unijunction transistor thyristor version of the equivalent circuit of FIG.3.

0036FIG. 2 is a relative display of the drive voltage curve that is seen by the input of each of the stages, then amplified and biased across the hysteresis element. HVP represents the high voltage Breakdown point of the hysteresis element, and A/S ON the correspondingly slightly higher turn - on point of the amplifier /switch. HRY represents the low voltage recovery point of the hysteresis element, and A/S OFF the correspondingly slightly, higher turn-off point of the amplifier/switch.

0037The hysteresis controlled amplifier/switch enables each stage to convert a triangular shaped waveform input into a sharp turn on sharp turn off time delay switch, with complete versatility in progra ability. Employing differing values of resistance for the drive- resistors of each stage, while maintaining constant input capacitance values, enables each stage to have a turn-on turn-off delay that differs from its neighbors. Shunting a drive-resistor with a diode will eliminate the time delay in one direction of that particular stage. For example; connecting the anode to the input of one stagβ/ and the cathode to the drive point of the previous stage/ will enable normal time delay for turn-on/ but almost no delay for turn-off. Reversing the same diode enables almost no time delay for turn-on, but full delay for turn-off. Reference i -s now made to FIG. 1. Section- A through section -N provides a plurality of tine delay light switches/ wb*^{* »} eby section-A functions as stage I and drives the input of stage II. Stage II in turn drives the input of section-N which functions as stag-? Ill and drives the input of section-A which functions as stage I . Stage I is shown switching L_lf or one light . Stage II is shown switching l_Λ, or two lights_/ and stage III is shown switching L₃ or three lights. This is shown for illustration purposes only . It is within the scope of this invention for each stage to switch any number of lights/ and for a plurality of any number of stages to be connected in series -ήth each other or in any series parallel combination .

0038In FIG . l. Section-T functions as an independent timed automatic power turn - of f έwitch . which controls the power to sections - A through Section-N .

0039It consists of a hysteresis element controlled amplifier/switch/ whereby the load element is a f orward biasing resistor 19 in series with the base 15 emitter 16 junction of PNP transistor Q_a . Resistor 20 shunting the base emitter junction of transistor Q_β is there to shunt the collector base leakage current of transistor Q_β and to provide reverse bias/ in the absence of f orward bias current through resistor 19, thereby enabling transistor Q_β to completely turn of f . The gate 12 of transistor Q₄ is connected through a protective current surge limiting resistor S* to a parallel circuit of resistor RDT and capacitor CT. This shunts the gate 12 of transistor Q« to common terminal 10.

0040The negative polarity of a 9 volt battery is connected between common terminal 10 and input B+ terminal 9. Input B+ terminal 9 is also connected to emitter 16 of transistor Q_β, the emitter end of shunting resistor 20 and the drive end of activate switch S- 01_/ which is normally open/ but momentarily connects junction point 21 to input B* terminal 9.

0041SUBSTITUTE SHEET f

0042Operation of section-T is as follows:Switch S- 01 is momentarily depressed_/ connecting junction point 21 to input B* terminal 9 charging input capacitor CT to ♦ 9 volts . Source 13 of amplif ier/switch Q₄ presents greater than 6 volts between the top of the hysteresis element H and common terminal 10. This causes the hysteresis element H to f ire into its high conduction mode/ thereby f orward biasing the gate 12 source 13 of transistor Q₄ with +7 . 7 volts_/ completely switching on its source 13 drain 14 circuit . This connects forward bias resistor 19 to the top of the hysteresis element H which is now 1 . 3 volts above common terminal 10 representing a forward bias voltage relative to forward bias resistor 19 .n series with the base 15 emitter 16 junction of PNP transistor Q_α if 7 . 05 volts/ thereby turning on the emitter 16 collector 17 junction of PNP transistor Q_β, thereby connecting B* input terminal 9 to B* terminal 11, thus providing power to operate section-A through section-N .

0043The instant switch S- 01 is released / the B* voltage across input capacitor CT begins to decay through resistor RDT until it drops to about 1.5 volts in about 2RC . At 1.5 volts Q₄ presents less than 1. 3 volts between the top of hysteresis element H a-.J common terminal 10/ causing it to recover to its nonconducting state/ thereby turning of f transistor Q₄ which no longer f orward biases resistor 19 causing the base 15 emitter 16 junction of PNP transistor Q_β to become negatively biased through resistor 20/ and therefore turn of f emitter 16 collector 17 junction of t ransistor Q ~ . Thus disconnecting B* input terminal 9 f rom B* terminal 11/ thereby turning of f εections-A through section-N .

0044SUBSTITUTE SHEET /o

ALTERNATE EHBODIMENT

0046FIG. 5 has been sectioned and staged to correspond to FIG. 1 . There is shown a diagram of the basic elements of a stage programmable light sequencer f or a toy . The negative terminal of the battery is connected to common terminal 10. Positive terminal of the battery is connected through terminal 9 of the timed automatic power turn- of f to B+ terminal 11/ or it may be directly connected to terminal 11_/ to provide the positive power supply/ which is needed to power light sequencer sections - A through sections-N .

0047The hysteresis elements of FIG. 5_/ noted as HS₃, HSi, HS_a and HS are all part of a single No . ' 4093" quad two - input NAND hysteresis gate integrated circuit . The reason for selecting this particular integrated circuit hysteresis device/ is that it is very commonly available of f the shelf for computer applications . Each of the four elements making up the quad, consists of a 2-input NAND gate which drives a hysteresis factored f lip- f lop which drives an output switch . It works as follows: When both NAND inputs are high (This means B* ^"biased above^' operating threshhold . ), the output is low (This means the output switch is ON/ and connects the output to common . ) . Any other combination of conditions for the two inputs, results in a high (The output switch is OFF/ connecting the output terminal to B* through an internal output resistor . ) . Each of the two inputs is identical/ and addresses the hysteresis factor illustrated in FIG. 2.

0048Because this invention only requires the use of a single hysteresis device per. stage/ the f irst input of each element is permanently biased high (Tied to B* . > to enable the second input of each element to operate exactly as illustrated in FIG. 2. Either of the two inputs may be selected to be f irst or second inputs .

0049SUBSTITUTE SHEET // Referring now to Section λ of FIG. 5. HSi is a 2 input NAND hysteresis .gate , having a first input PI a second input P2 and an permanently connected to B* . Output P3 positive voltage at terminal 11 through in parallel with an external circuit <img file="WO9102336A1_D0001.tif" /> comprising , the base 15 eni er 16^'. junction of PNP transistor QT in series with lamp L_x . However_/ It is within the scope of the present Invention that a plurality of lamps or resistors and LEDs can be used. Outputs may be used to directly drive power switching transistors/ or nay be used to drive bias resistors such as RS_a used to control power switching transistor Q_β of the timed automatic power turn-of f of section T.

0050Input P2 is connected to common terminal 10 through input capacitor C_x and: to a source of drive voltage designated in FIG. 5 as the output * P10 of element HS_H of section N through drive- resistor RDi . The output P3 which has just been described as driving the Base emitter junction of PNP transistor Q₇ is also the output terminal of stage - I section A and provides the source of drive voltage for the following stage through drive-resistor RD_Z. Whereas the circuit conf iguration of each stage is the same as the ones preceeding and following it , it is within the contemplation of this invention to vary the number of lights of each stage, as well as the timing of each stage by varying the values assigned to the drive-resistor capacitor combinations of each stage .

ALTERNATE EHBODIKENT CIRCUIT OPERATION

0052FIG. 2 is a relative display of the drive voltage curve that is seen by the input of each of the stages, then amplif ied and operated on by the hysteresis factor of . the f lip - f lop. HYP re^presents the high voltage breakdown and switch - on point of the hysteresis factor asymetricai f lip- f lop . HRY represents the low voltage recovery point of the hysteresis factor asymetrlcal f lip- f lop.

SUBSTITUTE SHEET /-2

0054The hysteresis factor of the flip-flop enables each stage to convert a triangular shaped waveform input into a sharp turn on sharp turn off time delay switch, with complete versatility in programabilrty. Employing differing values of resistance for the drive - resistors of each stage, while maintaining constant input capacitance values, enables each stage to have a turn-on turn-off delay that differs from its neighbors. Shunting a drive- resistor with a diode will eliminate the time delay in one direction of that particular stage. For example; connecting the anode to the input of one stage, and the cathode to the drive point of the previous stage, will enable normal time delay for turn-on, but almost no delay for turn-off. Reversing the same diode enables altn>-^**-;t n<-> time delay for turn-on, but full delay for turn-off .

0055How hysteresis factors can be generated with asymetrical flip- flops, is shown below. And such has been contemplated in our alternate embodiment as illustrated in FIG. 5. Integrated circuit No. 4093 is normally referred to as a quad o - in^ut NAND hysteresis gate. For the purpose of analysis FIG. 6 is a fully designed 2-input NAND hysteresis gate usymetrical flip-flop.

0056Refering to FIG. G, we find that a HAND input circuit {-, really an AND circuit where the output of th entire prck-* -- ;a polarity inverted with respect to the input.

0057^Q-o and Q11 aro enhanced N channel field effect transistors whereby the drain of Q10 {&lt;^■ connected to B + terminal 11 ΛΛ*.. iti source is series connected to thn drain of Qn, and th-a SOUΓCQ of Q11 is connected to coa-aon terπiTi l 10 through α 60C" •-^■'•"i rc-"^r^-- . To have an output at point 24, th&lt;*. input ' tos -^f ■:■-"^{* *}"^* '--so transistors must be positive at the *»ame U1..0.

0058SUBSTITUTE SHEET Because when a gate is not positive, there is no conduction between its associated drain and source. When the gate of only one transistor is positive, only its drain to source is conductive, leaving the drain to source of the remaining series transistor nonconductive, and thereby not permitting the flow of current between B+ terminal lϊ and point 24. When both input gates are tied to B* terminal 11 at the same_' time, their respective drain to source circuits are conductive at the same time, thereby conducting all the voltage from B* terminal 11 to point 24. If the gate of one of these transistors is tied to B+ terminal 11 its drain to source is fully conductive (shorted). If at the same time the gate of the second transistor is now connected- to a generator of variable lower voltage B*, that transistor acts as an analog source follower, providing very high current gain, but somewhat less than unity voltage gain between its gate and point 21. <img file="WO9102336A1_D0002.tif" /> fi-.'O_/ if :.". .:^■- 1 is tied to U* terminal 11, and input 2 -st-ios the voltage illu-.L;-..t_>J in FIG. 2, the source of transistor Q_{u v}m generate the same waveform at a low source impedance at point 24, but at slightly less than unity voltage gain.

0059NPN transistors Qia and Q-- are α matched pair configured as a differential aπplifier. Their emitters are tied together to α 50 microamp cor.at-snt current sinlt . NPN transistors C **- αi.ϋ Qiu arc _ι matched pair configured as a current mirror, with transistor Qiπ acting as a precise 50 microaπip current sink. Λ VO' VJ-J divider ;_, configured, comprising a 20K resistor connected bot./si.-n £+ torninal 11 and point 22, in series w.th a second 240K resistor between points 22 and 23 and s 600K ohm resiutor between point 23 and common terminal 10. Point 22 is αl_io connected to output tem iiαl P3 through a 48K ohm resistor in sori-is with α uiodo.

0060The collector of transistor h* iϋ also connected iv B* ter»inαl 11 through the bauo - emitter junction of PUP transistor Q--> in parallel with a 100 ohm negative bias resistor.

0061SUBSTITUTE SHEET /¥

0062When the emitter-collector junctions of transistor ^Q_ιa conducts_/ it f orward biases PNP transistor Qi*⁹_/ causing conduction between its emitter - collector junction_/ which is connected to common terminal 10 through a 9. IK ohm resistor in series with the base - emitter junction of NPN transistor Qi^ "in parallel with ^' a 100k ohm negative bias resistor . Thus forward biasing and turning NPN transistor Qιτ on . When NPN transistor Qv-*^* is turned n it provides a short circuit between output terminal P3 and common terminal 10. This also serves to short point 22 to common terminal 10 through a 48K ohm res-stor and series diode, thereby clamping point 22 down to 2. 1 volts, and the base of transistor Qi-* down to _'1.5 volts at point 23.

0063Stated somewhat dif ferently, when input 1 at point PI is clamped to B* terminal 11., and input 2 at P2 is at zero voltage input , there is no voltage at point 24, the base input of Q--s . The above cited voltage divider theref ore provides + 5 volts to the base of transistor Q^*-^** at point 23. This causes the emitter of transistor Q- ^~~ to present _'4_* 35 volts to the emitter of transistor Qiz thereby reverse biasing its base emitter junction . For input 2 to overcome this reverse bias, would require greater than *5. 4 volt s at P2. As long as Qiz is reverse biased of f , t ransistor Qxβ receives no f orward bias, and is clamped of f through the 100K ohrc nega tive bias resistor at its base, and theref ore Q>-^~~ a lso receives no f orward bias at its base, and in clamped υf f through the 100K ohm negative bias resistor . Since transistor Q'-r is now clamped of f , 8+ terminal 11 is connected to output terminal P3 thr<-*ιgh a 3K ohm resistor , an>1 the output at KJ is said to be high . Ilhen the output at P3 io in high mode its Unloaded output voltage \<~ *^{• "}) volts . Since the B+ voltage at point 22 is +7 volts tho dio-le connecting p<ήnt ">?. to point P3 is reverse biased by 2 volts and remains non onHi""tin _. . Therefore the input voltaoo at the baεn of transistor Q^~.^~> is ^■»^*- volts its emitter presenting *4 . 35 volts of reverse bias to the emitter of transistor ι^~~ .

0064SUBSTITUTE SHEET When the waveform shown in FIG. 2 is presented at input 2, and point P2 reaches HYB of »5.69 volts, the base of ^Q_ιa becomes biased at +5.4 volts, or -.4 volts higher than the base of Q-^~*, thereby turning on Qia and reverse biasing Qι*». When Qia turns on/ its collector forward biases the base -emitter junction of PNP transistor Qι«, turning its emitter-collector junction on, . thereby forward biasing the base-emitter junction of transistor Q-f, turning it on. When transistor Q^*."-' turns on, it clamps output terminal P3 to common terminal 10 and also shorts point 22 through the 48 ohm resistor in series with the diode to common terminal 10, thereby reducing the B*> voltage at point 22 from 7 volts to 2.1 volts, This reduces the voltage at the base of transistor Qι» from *5 volts to ♦1.5 volts. Thereby producing the asy etery and hysteresis factor.

0065The emitter, of transistor Qι-» would now like to present +.85 volts to the*. emitter of Qiz. This cannot happen however because they share a constant current sink which is now captured by transistor Qiz. This condition will persist until the input waveform of FIG. 2 drops to HRY. At this point the 1.5 volts at point 23 exceeds the 1 volt at point P24 and the emitter of Q-^~~ captures the shared constant current sink, turning Q*z off. When Qiz turns off, Q-« and Qi' follow. Raising output P3 to high and returning the voltage at the base of transistor Q-^~~ to ⁺5 volts.

0066FIG. 7 is tho symbolic representation of element one of the No. 4093 quad, which is pinned and functions corr spondinyly to tho above. All four elements of the quod are identical to each oth r.

0067Reference is now made to FIG. 5. Section-A through section-;] provides a plurality of timo delay light switches, whereby sect ion- Λ functions as stage I and drives the input of st -_-..;-_ II. Sta-je II in turn drives the input of section- which functions as stαg III and drives the input of section-A which functions aa stage I.

0068SUBSTITUTE SHEET Stage I is shown switching i, or one light . St«g? II is shown switching L_a, or two lights_/ and stage III is shown switching L*, or three lights. This is shown for illustration purposes only . It is within the scope of this invention for each stage to switch any number of lights_/ and for a plurality of any number of stages to be connected in series with each other or in any series parallel combination.

0069In FIG .5_/ Section-T functions as an independant timed automatic power turn - of f switch which controls the power to. sections - A through Section - N . It consists of a hysteresis gate controlled amplifier /switch_/ whereby the load element of the hysteresis gate HS3, is a forward biasing resistor RS2 in series with the base 15 emitter 16 junction of PNP transistor Q_β . Resistor 20 shunting the base emitter junction of transistor Q„ is there to shunt the collector base leakage current of transistor Q_β, and to provide negative bias, in the absence of the forward bias current through resistor PS2, ihereby enabling transistor Qt- to completely turn of f .

0070Input P13 of gate HS3 is connected through a protective current surge limiting resistor RSI to a parallel circuit of resistor RDT and capacitor CT. This shunts the input P13 of gate HS3 to common terminal 10.

0071The negative polarity of a 9 volt battery is connected between common terpinal 10 and input B* terminal 9. Input B+ termina l 9 is also connected to cnitter 16 of transistor Q_j , the emitter end of shunting resistor 20 and the drive end of activate switch S- 01, which is normally open, but momentarily connects junction point 21 to input B* terøinal 9.

0072The moment Switch S-01 is depressed, it connects junction point 21 to input B* terminal 9 charging input cn cit r CT t&lt;^~ - 9 volts . The hysteresis gate HS3 analysed as FIG. 5 above, is caπc d to f ire into its low or on mode, shorting output point PU to common terminal 10. II

0073This connects forward bias resistor RS2 in series with the base 15 emitter 16 junction of PNP transistor Q_β to a forward bias voltage source which for PNP transistor Qβ, is common terminal 10. This turns on the emitter 16 collector 17 junction of PNP transistor Q«, and thereby connects B* input terminal 9 to B+ terminal 11. Thus providing power to operate section-A through section-N.

0074The instant switch S-01 is released, the B* voltage across input capacitor CT begins to decay through resistor RDT until it drops to about 1.6 volts in about 2RC. At 1.5 volts and below, the hysteresis gate described as FIG. 6 above recovers into its high state, causing output Pll to disconnect forward bias resistor RS2 from common terminal 10, thereby turning off the base 15 emitter 16 junction of PNP transistor Q« and causing the base 15 emitter 16 junction of PNP transistor Q_β to become negatively biased through resistor 20.. ^; Thus turning off emitter 16 collector 17 junction of transistor Q_β, disconnecting B*> input terminal 9 from B* terminal 11, thereby turning off sections-A through section-N.

0075Operation of section-A through Section-N follows. As stipulated above, the negative polarity of a 9 volt battery is connected to common terminal 10. The positive polarity is connected to B⁺ terminal 11, either through section-T or directly.

0076When B* is connected to positive teriiύnal 11, ali the hysteresis gates, amplifier/switches and associated loads ai.d/or lights are in off condition. The input capacitors of all of the stages begin to accumulate a positive charce through their connected drive- resistors. The stage havin? the shortest R-C time constant will reach the firing voltage of its hysteresis gate KS_X first, and thereby turn on its output (to low). and its associated amplifier/switch and light first. Since this invention feature--; complete programmability, tints could be any stagy.

SUBSTITUTE SHEET 04363

0078ι β-

0079For ease of analysis we will elect stage I to turn on f irst .

0080When stage I turns on, a positive voltage charge remains in the input capacitors of stages II and 111. Stage III continues charging through RD„ and L_a, and stage I continues to receive positive bias through RD_X and L„. Stage II' s input capacitor however, begins discharging through RD_a, and a low output of HSl which connects the drive side of RD_a to common terminal 10. Thus precluding the f iring of stage II . Stage III however, continues charging through RD„ and _a until the voltage accumulated across input capacitor C„ is suf ficient to cause input gate P9 of HSN to f ire thereby turning on amplifier/switch Q„, its lights L„ and causing the input capacitor Ci of stage I to discharge through drive - resistor RD_X, and the low output of HSN of stage III . When the voltage across input capacitor C_x of stage I drops below about 1 . 5 volts, the output P3 of Hysteresis gate HSl of stage I recovers to high ( of f ) thereby turning of f transistor Q₇ of stage I , and its lights L-* . Since output P3 is now of f , and in high mode, its output voltage rises to the voltage present at B* terminal 11. This causes input capacitor C_a to charge through drive - resistor RD_a until it reaches A/S - on . The voltage required for input P6 of stage II to f ire its output P4 into saturation . Thus turning on the amplif ier/switch of stage II, its lights a, and causing input capacitor C_n of stage III to discharge through drive - resistor RD„ and stage II . When the voltage across input capacitor C„ of stage III drops below about 1. 6 volts, the hysteresis factor causes output P10 to turn of f , recovering to high . Thereby turning of f transistor Q„ of stage III, and its lights L^. Output P10 recovering to high, also causes input capacitor Ci to begin charging through drive resistor RD_X, beginning the cycle all over again .

SUBSTITUTE SHEET