Switching in an audio system with multiple playback paths

SWITCHING IN AN AUDIO SYSTEM WITH MULTIPLE PLAYBACK PATHS

RELATED APPLICATION

0003The present disclosure is related to U.S. Pat. App. Ser. No. 15/277,465, filed September 27, 2016, and entitled "Amplifier with Configurable Final Output Stage," which is incorporated herein by reference.

FIELD OF DISCLOSURE

0005The present disclosure relates in general to circuits for audio devices, including without limitation personal audio devices, such as wireless telephones and media players, and more specifically, to systems and methods relating to switching between configurations of an audio system with multiple playback paths.

BACKGROUND

0007Personal audio devices, including wireless telephones, such as mobile/cellular telephones, cordless telephones, mp3 players, and other consumer audio devices, are in widespread use. Such personal audio devices may include circuitry for driving a pair of headphones or one or more speakers. Such circuitry often includes a power amplifier for driving an audio output signal to headphones or speakers. Generally speaking, a power amplifier amplifies an audio signal by taking energy from a power supply and controlling an audio output signal to match an input signal shape but with a larger amplitude.

0008One example of an audio amplifier is a class-D amplifier. A class-D amplifier (also known as a "switching amplifier") may comprise an electronic amplifier in which the amplifying devices (e.g., transistors, typically metal-oxide-semiconductor field effect transistors) operate as electronic switches, and not as linear gain devices as in other amplifiers (e.g., class-A, class-B, and class-AB amplifiers). In a class-D amplifier, an analog signal to be amplified may be converted to a series of pulses by pulse-width modulation, pulse-density modulation, or another method of modulation, such that the analog signal is converted into a modulated signal in which a characteristic of the pulses of the modulated signal (e.g., pulse widths, pulse density, etc.) is a function of the magnitude of the analog signal. After amplification with a class-D amplifier, the output pulse train may be converted back to an unmodulated analog signal by passing through a passive low- pass filter, wherein such low-pass filter may be inherent in the class-D amplifier or a load driven by the class-D amplifier. Class-D amplifiers are often used due to the fact that they may be more power efficient than linear analog amplifiers, in that class-D amplifiers may dissipate less power as heat in active devices as compared to linear analog amplifiers. However, class-D amplifiers may have high quiescent power when amplifying low- magnitude signals and may require a large amount of area in order to meet stringent dynamic range requirements in audio devices.

0009Accordingly, it may be desired to have an amplifier that has a configurable final output stage, wherein the final output stage is configurable between a Class-AB output stage and a Class-D output stage. However, having an amplifier with a configurable output stage may be susceptible to audio artifacts caused by switching between the modes of the final output stage. SUMMARY

0010In accordance with the teachings of the present disclosure, one or more disadvantages and problems associated with existing approaches to signal amplification in an audio system may be reduced or eliminated.

0011In accordance with embodiments of the present disclosure, a system may include a playback path and a control circuit. The playback path may have a playback input for receiving an input signal and configured to generate at a playback path output an output signal based on the input signal, wherein the playback path is configured to operate in a plurality of operational modes. The control circuit may be configured to receive a first signal from within the playback path and indicative of the input signal, receive a second signal generated from the input signal externally to the playback path, and select a selected operational mode from the plurality of operational modes based on the first signal and the second signal.

0012In accordance with these and other embodiments of the present disclosure, a method may include receiving a first signal from within a playback path and indicative of an input signal, wherein the playback path comprises a playback input for receiving the input signal and configured to generate at a playback path output an output signal based on the input signal, and wherein the playback path is configured to operate in a plurality of operational modes. The method may also include receiving a second signal generated from the input signal externally to the playback path and selecting a selected operational mode from the plurality of operational modes based on the first signal and the second signal.

0013Technical advantages of the present disclosure may be readily apparent to one skilled in the art from the figures, description and claims included herein. The objects and advantages of the embodiments will be realized and achieved at least by the elements, features, and combinations particularly pointed out in the claims.

0014It is to be understood that both the foregoing general description and the following detailed description are examples and explanatory and are not restrictive of the claims set forth in this disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

0016A more complete understanding of the present embodiments and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein:

0017FIGURE 1 is an illustration of an example personal audio device, in accordance with embodiments of the present disclosure;

0018FIGURE 2 is a block diagram of selected components of an example audio integrated circuit of a personal audio device, in accordance with embodiments of the present disclosure;

0019FIGURE 3 is a block diagram of selected components of an example amplifier, in accordance with embodiments of the present disclosure;

0020FIGURE 4 is a block diagram of selected components of an example class-AB audio output stage, in accordance with embodiments of the present disclosure;

0021FIGURE 5 is a block diagram of selected components of another example class-AB audio output stage, in accordance with embodiments of the present disclosure;

0022FIGURE 6 is a block diagram of selected components of an example preconditioning circuit, in accordance with embodiments of the present disclosure; FIGURE 7 is a circuit diagram of selected components of an example quick charge circuit, in accordance with embodiments of the present disclosure;

0023FIGURE 8 is a block diagram of selected components of another example preconditioning circuit, in accordance with embodiments of the present disclosure;

0024FIGURE 9 is a flow chart of an example method for switching between a first mode of a final output stage of an amplifier and a second mode of the final output stage of the amplifier, in accordance with embodiments of the present disclosure;

0025FIGURE 10 is a flow chart of an example method for switching between a second mode of a final output stage of an amplifier and a first mode of the final output stage of the amplifier, in accordance with embodiments of the present disclosure; and

0026FIGURE 11 is a block diagram of selected components of an example control circuit of the amplifier depicted in FIGURE 3, in accordance with embodiments of the present disclosure. DETAILED DESCRIPTION

0027FIGURE 1 is an illustration of an example personal audio device 1, in accordance with embodiments of the present disclosure. FIGURE 1 depicts personal audio device 1 coupled to a headset 3 in the form of a pair of earbud speakers 8 A and 8B. Headset 3 depicted in FIGURE 1 is merely an example, and it is understood that personal audio device 1 may be used in connection with a variety of audio transducers, including without limitation, headphones, earbuds, in-ear earphones, and external speakers. A plug 4 may provide for connection of headset 3 to an electrical terminal of personal audio device 1. Personal audio device 1 may provide a display to a user and receive user input using a touch screen 2, or alternatively, a standard liquid crystal display (LCD) may be combined with various buttons, sliders, and/or dials disposed on the face and/or sides of personal audio device 1. As also shown in FIGURE 1, personal audio device 1 may include an audio integrated circuit (IC) 9 for generating an analog audio signal for transmission to headset 3 and/or another audio transducer.

0028FIGURE 2 is a block diagram of selected components of an example audio IC 9 of a personal audio device, in accordance with embodiments of the present disclosure. In some embodiments, example audio IC 9 may be used to implement audio IC 9 of FIGURE 1. As shown in FIGURE 2, a microcontroller core 18 may supply a digital audio input signal DIG_IN to a digital-to-analog converter (DAC) 14, which may convert the digital audio input signal to an analog input signal VIN. DAC 14 may supply analog signal VIN to an amplifier 16 which may amplify or attenuate analog input signal VIN to provide an audio output signal VOUT, which may operate a speaker, headphone transducer, a line level signal output, and/or other suitable output. In some embodiments, digital audio input signal DIG_IN may be a digital signal with significant out-of-band noise, such as a pulse-density modulated signal, a pulse- width modulated signal, or a pulse-code modulated signal.

0029FIGURE 3 is a block diagram of selected components of an example amplifier 16, in accordance with embodiments of the present disclosure. As shown in FIGURE 3, amplifier 16 may include a first stage 22 (e.g., an analog front end) configured to receive analog input signal VIN at an amplifier input of amplifier 16 and generate an intermediate signal VINT which is a function of analog input signal VIN, a final output stage 24 configured to generate audio output signal VOUT at an amplifier output of amplifier 16 as a function of intermediate signal VINT, a signal feedback network 26 coupled between the amplifier output and the amplifier input, and a control circuit 28 for controlling the operation of certain components of amplifier 16, as described in greater detail below.

0030First stage 22 may include any suitable analog front end circuit for conditioning analog input signal VIN for use by final output stage 24. For example, first stage 22 may include one or more analog integrators 32 cascaded in series, as shown in FIGURE 3.

0031Final output stage 24 may include any suitable driving circuit for driving audio output signal VOUT as a function of intermediate signal VINT (thus, also making audio output signal VOUT a function of analog input signal VIN) wherein final output stage 24 is switchable among a plurality of modes including at least a first mode in which final output stage 24 generates audio output signal VOUT as a modulated output signal which is a function of intermediate signal VINT and a second mode in which final output stage 24 generates audio output signal VOUT as an unmodulated output signal which is a function of intermediate signal VINT. TO carry out this functionality, final output stage 24 may include a class-D audio output stage 42 which may be enabled in the first mode (and disabled in the second mode) to generate audio output signal VOUT as a modulated output signal which is a function of intermediate signal VINT and a class-AB audio output stage 44 which may be enabled in the second mode (and disabled in the first mode) to generate audio output signal VOUT as an unmodulated output signal which is a function of intermediate signal VINT-

0032Class-D audio output stage 42 may comprise any suitable system, device, or apparatus configured to amplify intermediate signal VINT and convert intermediate signal VINT into a series of pulses by pulse-width modulation, pulse-density modulation, or another method of modulation, such that intermediate signal VINT is converted into a modulated signal in which a characteristic of the pulses of the modulated signal (e.g., pulse widths, pulse density, etc.) is a function of the magnitude of intermediate signal VINT. After amplification by class-D audio output stage 42, its output pulse train may be converted back to an unmodulated analog signal by passing through a passive low-pass filter, wherein such low-pass filter may be inherent in output circuitry of class-D audio output stage 42 or a load driven by final output stage 24. As shown in FIGURE 3, class-D audio output stage 42 may include a control input for receiving a control input from control circuit 28 in order to selectively enable class-D audio output stage 42 during the first mode and disable class- D audio output stage 42 during the second mode (e.g., prevent class-D audio output stage 42 from driving the amplifier output of amplifier 16 by disabling or decoupling a supply voltage from class-D audio output stage 42 or by disabling or decoupling driving devices of the amplifier output of amplifier 16).

0033Class-AB audio output stage 44 may comprise any suitable system, device, or apparatus configured to amplify intermediate signal VINT with a linear gain and convert intermediate signal VINT into an unmodulated audio output signal VOUT. For example, in some embodiments, unmodulated audio output signal VOUT may include a continuous -time baseband signal (e.g., an audio baseband signal). As shown in FIGURE 3, class-AB audio output stage 44 may include a control input for receiving a control input from control circuit 28 in order to selectively enable class-AB audio output stage 44 during the second mode and disable class-AB audio output stage 44 during the first mode (e.g., prevent class-AB audio output stage 44 from driving the amplifier output of amplifier 16 by disabling or decoupling a supply voltage from class-AB audio output stage 44 or by disabling or decoupling driving devices of the amplifier output of amplifier 16). Example implementations of class-AB audio output stage 44 are depicted in FIGURES 4 and 5 and described in greater detail below.

0034As shown in FIGURE 3, final output stage 24 may include a signal feedback network 50 for feeding back a signal indicative of audio output signal VOUT to the input of final output stage 24, thus forming a feedback loop around Class-AB audio output stage 44. For example, as shown in FIGURE 3, signal feedback network 50 may include resistors and/or other suitable circuit elements.

0035In some embodiments, a signal gain (e.g., VOUT/VINT) of final output stage 24 in the first mode may be approximately equal to the signal gain of final output stage 24 in the second mode. In these and other embodiments, an offset (e.g., direct current offset) of final output stage 24 in the first mode may be approximately equal to the offset of final output stage 24 in the second mode.

0036As shown in FIGURE 3, final output stage 24 may also include a preconditioning circuit 49 coupled to one or both of the output terminals of the amplifier output of amplifier 16, with preconditioning circuit 49 having a control input received from control circuit 28 for controlling functionality of preconditioning circuit 49, as described in greater detail below. In some embodiments, preconditioning circuit 49 may be configured to precondition at least one of a voltage (e.g., voltage VOUT) and a current of the output (e.g., a current flowing into a load coupled across the terminals of voltage VOUT) of final output stage 24 prior to switching between modes of final output stage 24 in order to limit audio artifacts caused by switching final output stage 24 between modes. For example, preconditioning circuit 49 may precondition at least one of the voltage and the current of the output of final output stage 24 prior to switching between modes of final output stage 24 by charging each of the output terminals of the output of final output stage 24 to a common mode voltage of a class-AB output driver stage integral to class-AB audio output stage 44. In these and other embodiments, preconditioning circuit 49 may be configured to perform a switching sequence to switch between modes of final output stage 24, such that at all points of the switching sequence, output terminals of the output of final output stage 24 have a known impedance.

0037Signal feedback network 26 may include any suitable feedback network for feeding back a signal indicative of audio output signal VOUT to the amplifier input of amplifier 16. For example, as shown in FIGURE 3, signal feedback network 26 may include variable feedback resistors 48, wherein resistances of variable feedback resistors 48 are controlled by control signals received from control circuit 28, as described in greater detail below.

0038Thus, final output stage 24 may operate as an open-loop switched- mode driver in the first mode and may operate as a continuous-time closed-loop amplifier in the second mode. In addition, when the final output stage is operating in the second mode, amplifier 16 may comprise a first feedback loop including signal feedback network 26 and a second feedback loop coupled between the amplifier output and the intermediate output implemented by signal feedback network 50.

0039Control circuit 28 may include any suitable system, device, or apparatus configured to receive information indicative of digital audio input signal DIG_IN, audio output voltage VOUT, intermediate signal VINT, and/or another operational characteristic of amplifier 16, and based at least thereon, control operation of one or more components of amplifier 16. For example, control circuit 28 may be configured to, based on a characteristic of digital audio input signal DIG_IN and/or analog input signal VIN (e.g., which may be determined from receiving and analyzing digital audio input signal DIG_IN, analog input signal VIN, intermediate signal VINT and/or audio output signal VOUT), switch between the first mode and the second mode of final output stage 24. Such characteristic may include one or more of a frequency of analog input signal VIN, an amplitude of analog input signal VIN, a signal- to-noise ratio of analog input signal VIN, a noise floor of analog input signal VIN, or another noise characteristic of analog input signal VIN. For example, in some embodiments, control circuit 28 may be configured to switch final output stage 24 from the first mode to the second mode when an amplitude of analog input signal VIN decreases below a threshold amplitude, and may be configured to switch final output stage 24 from the second mode to the first mode when an amplitude of analog input signal VIN increases above the same threshold amplitude or another threshold amplitude. In some embodiments, to reduce audio artifacts associated with switching between modes, control circuit 28 may also be configured to switch between modes only when the amplitude of audio output signal VOUT is approximately zero (e.g., when a modulated signal generated by class-D audio output stage 42 is at its minimum voltage in its generated pulse train). In these and other embodiments, control circuit 28 may further be configured to, in order to reduce audio artifacts induced by switching between the two modes, cause final output stage 24 to switch between the first mode and the second mode at an approximate completion of a modulation period of the modulated output signal output by Class-D audio output stage 42, and cause final output stage 24 to switch between the second mode and the first mode at an approximate beginning of another modulation period of the modulated output signal output by Class-D audio output stage 42.

0040In these and other embodiments, control circuit 28 may further be configured to, in order to reduce audio artifacts induced by switching between the two modes, control preconditioning circuit 49 and components thereof as described elsewhere in this disclosure.

0041In addition, control circuit 28 may also be configured to perform calibration of final output stage 24. For example, control circuit 28 may receive and analyze intermediate signal VINT and audio output signal VOUT to determine a gain of class-D audio output stage 42 (e.g., the signal gain of final output stage 24 in the first mode) and a gain of class-AB audio output stage 44 (e.g., the signal gain of final output stage 24 in the second mode), and based thereon, modify the gain of class-D audio output stage 42 and/or the gain of class-AB audio output stage 44 in order to calibrate the signal gain of final output stage 24 in the second mode to match the signal gain of final output stage 24 in the first mode. As another example, control circuit 28 may receive and analyze intermediate signal VINT and/or audio output signal VOUT to determine an offset (e.g., direct current offset) of class- D audio output stage 42 (e.g., the offset of final output stage 24 in the first mode) and an offset of class-AB audio output stage 44 (e.g., the offset of final output stage 24 in the second mode), and based thereon, modify the offset of class-D audio output stage 42 and/or the offset of class-AB audio output stage 44 in order to calibrate the offset of final output stage 24 in the second mode to match the offset of final output stage 24 in the first mode.

0042In these and other embodiments, control circuit 28 may also be configured to control characteristics of first stage 22 (e.g., integrator 32) and/or signal feedback network 26. Control circuit 28 may maintain such characteristics and structure of first stage 22 and signal feedback network 26 as static when switching between the first mode and the second mode of final output stage 24 and when switching between the second mode and the first mode. Maintaining the characteristics and structure of first stage 22 and signal feedback network 26 as static when switching between modes allows the modes to share the same analog front end and feedback network, thus reducing or minimizing the likelihood of mismatched signal gain and offset between the modes, and thus reducing or minimizing audio artifacts caused by switching between modes. However, after control circuit 28 has switched final output stage 24 to the second mode (e.g., amplifier output driven by class- AB audio output stage 44), control circuit 28 may modify characteristics of first stage 22 and/or signal feedback network 26 in order to decrease a noise floor of amplifier 16. For example, in some embodiments, control circuit 28 may modify characteristics of integrator 32 (e.g., resistances and/or capacitances of filters internal to integrator 32) and/or other components of first stage 22 in order to decrease a noise floor of amplifier 16 when final output stage 24 operates in the second mode. As another example, in these and other embodiments, control circuit 28 may modify characteristics of signal feedback network 26 (e.g., resistances of variable feedback resistors 48) in order to decrease a noise floor of amplifier 16 when final output stage 24 operates in the second mode. When making such modification, control circuit 28 may, before switching final output stage 24 from the second mode to the first mode, return such characteristics to their unmodified states.

0043FIGURE 4 is a block diagram of selected components of an example class-AB audio output stage 44A, in accordance with embodiments of the present disclosure. In some embodiments, class-AB audio output stage 44 of amplifier 16 may be implemented using class-AB audio output stage 44A. As depicted, class-AB audio output stage 44A may include a class-AB driver stage 90, switches 92, and switches 94 arranged along with signal feedback network 50 as shown in FIGURE 4. In operation, when switching between modes of final output stage 24 from its class-D mode of operation to class-AB mode of operation, such switching may first involve powering on components of class-AB audio output stage 44A including class-AB driver stage 90 from a powered-off or powered-down state. After powering on components of class-AB audio output stage 44A including class-AB driver stage 90, switches 92 may be activated (e.g., closed, enabled, turned on) and switches 94 deactivated (e.g., opened, disabled, turned off) under the control of control signals communicated from control circuit 28 to allow operation of class-AB audio output stage 44A to settle into a normal steady-state operation before coupling the output of class-AB driver stage 90 to the output of final output stage 24. After class-AB output stage 44A has settled (and other conditions for switching between modes of final output stage 24 have been satisfied, as described elsewhere in this disclosure), switches 94 may be activated and switches 92 deactivated under the control of control signals communicated from control circuit 28 in order to couple the output of class-AB driver stage 90 to the output of final output stage 24.

0044FIGURE 5 is a block diagram of selected components of another example class-AB audio output stage 44B, in accordance with embodiments of the present disclosure. In some embodiments, class-AB audio output stage 44 of amplifier 16 may be implemented using class-AB audio output stage 44B. Class-AB audio output stage 44B may in many respects be similar to class-AB audio output stage 44A of FIGURE 4, and thus, only the main differences between class-AB audio output stage 44B and class-AB audio output stage 44A may be described below. As shown in FIGURE 5, class-AB audio output stage 44B may include a p-type metal-oxide-semiconductor field-effect transistor (p-MOSFET) 96, an n- type metal-oxide-semiconductor field-effect transistor (N-MOSFET) 98, and additional switches 94 beyond those present in class-AB audio output stage 44A of FIGURE 4. The characteristics of p-MOSFET 96 and N-MOSFET 98 may be such that they replicate characteristics of analogous devices integral to that of class-AB driver stage 90.

0045Thus, in operation, when switching between modes of final output stage 24 from its class-D mode of operation to class-AB mode of operation, switches 92 may be activated and switches 94 deactivated under the control of control signals communicated from control circuit 28 to allow operation of class-AB audio output stage 44B to settle into a normal steady-state operation before coupling the output of class-AB driver stage 90 to the output of final output stage 24. After class-AB output stage 44B has settled (and other conditions for switching between modes of final output stage 24 have been satisfied, as described elsewhere in this disclosure), switches 94 may be activated and switches 92 deactivated under the control of control signals communicated from control circuit 28 in order to couple the output of class-AB driver stage 90 to the output of final output stage 24. Accordingly, during the process of switching between modes of final output stage 24 from its class-D mode of operation to class-AB mode of operation, the replica of class-AB driver stage 90 formed by p-MOSFET 96 and N-MOSFET 98 may precondition at least one of the voltage (e.g., voltage VOUT) and the current of the output of final output stage 28 by charging the output to a common mode voltage of class-AB driver stage 90 using a replica of class-AB driver stage 90 to provide the common mode voltage.

0046Although FIGURE 5 depicts that the replica of class-AB driver stage 90 formed by p-MOSFET 96 and N-MOSFET 98 is present within class-AB audio output stage 44B, in some embodiments, such replica and one or more other components depicted in FIGURE 5 as integral to class-AB audio output stage 44B may instead be integral to preconditioning circuit 49 described elsewhere herein.

0047FIGURE 6 is a block diagram of selected components of an example preconditioning circuit 49A, in accordance with embodiments of the present disclosure. In some embodiments, preconditioning circuit 49 of amplifier 16 may be implemented using preconditioning circuit 49A. As shown in FIGURE 6, preconditioning circuit 49A may include a clamp 46 and a quick charge circuit 47. Clamp 46, which may be embodied as a switch, may be coupled between the output terminals of the amplifier output of amplifier 16, with clamp 46 having a control input received from control circuit 28 for selectively enabling clamp 46 (to short the output terminals together) and disabling clamp 46, as described in greater detail below. Quick charge circuit 47 may include any suitable circuit for preconditioning at least one of the voltage (e.g., voltage VOUT) and the current of the output of final output stage 24 to a particular voltage and/or current (e.g., to a common- mode voltage of class-AB audio output stage 44).

0048FIGURE 7 is a circuit diagram of selected components of an example quick charge circuit 47, in accordance with embodiments of the present disclosure. As depicted in FIGURE 7, quick charge circuit 47 may include a flip-flop 100, logic NOR gate 102, n- MOSFET 104, n-MOSFET 106, p-MOSFET 108, n-MOSFET 110, p-MOSFET 112, and n-MOSFET 114 arranged as shown in FIGURE 7. In operation, when quick charge circuit 47 is enabled in accordance with one or more control signals communicated from control circuit 28, quick charge circuit 47 may charge the output terminals (which may be coupled together via clamp 46) of final output stage 24 to a common mode voltage V_CM, which may be a common mode voltage of class-AB audio output stage 44. In operation, n-MOSFET 104 and n-MOSFET 106 may charge the output terminals of final output stage 24, with a current-mode feedback which controls the voltage to which the output terminals are charged. Accordingly, quick charge circuit 47 may also precondition a current on the output of final output stage 24 based on a load present across the terminals of the output of final output stage 24.

0049FIGURE 8 is a block diagram of selected components of another example preconditioning circuit 49B, in accordance with embodiments of the present disclosure. In some embodiments, preconditioning circuit 49 of amplifier 16 may be implemented using preconditioning circuit 49B. As shown in FIGURE 8, preconditioning circuit 49B may include a clamp 46, a capacitor 39, and switches 41 and 43 arranged as shown. Clamp 46 of preconditioning circuit 49B may be similar to that of clamp 46 of preconditioning circuit 49A. When preconditioning circuit 49B is enabled under the control of control signals communicated from control circuit 28, clamp 46 may be enabled to short the output terminals of final output stage 24 together, switch 43 may be activated, and switch 41 deactivated to allow charge present on capacitor 39 to charge each of the output terminals of final output stage 24 to a common mode voltage V_cm. When preconditioning circuit 49B is disabled under the control of control signals communicated from control circuit 28, clamp 46 may be disabled, switch 41 may be activated, and switch 43 deactivated to allow capacitor 39 to charge to common mode voltage V_cm. Those of skill in the art may recognize that a dual equivalent current source and inductor may be substituted in place of voltage Vcm and capacitor 39 such that the inductor may precondition a current of the output terminals of final output stage 24 when preconditioning circuit 49B is enabled.

0050FIGURE 9 is a flow chart of an example method 51 for switching between a first mode of a final output stage 24 of amplifier 16 and a second mode of final output stage 24 of amplifier 16, in accordance with embodiments of the present disclosure. According to some embodiments, method 51 begins at step 52. As noted above, teachings of the present disclosure are implemented in a variety of configurations of personal audio device 1. As such, the preferred initialization point for method 51 and the order of the steps comprising method 51 may depend on the implementation chosen.

0051At step 52, control circuit 28 may monitor intermediate signal VINT, audio output signal VOUT, or another signal indicative of analog input signal VIN, to determine if analog input signal VIN has decreased from above to below a threshold amplitude. If analog input signal VIN has decreased from above to below the threshold amplitude, method 51 may proceed to step 53. Otherwise, method 51 may remain at step 52 until such threshold amplitude crossing occurs.

0052At step 53, control circuit 28 may monitor audio output signal VOUT to determine when the amplitude of audio output signal VOUT is approximately zero (e.g., when a modulated signal generated by class-D audio output stage 42 is at its minimum voltage in its generated pulse train). If audio output signal VOUT has reached approximately zero, method 51 may proceed to step 54. Otherwise, method 51 may remain at step 53 until audio output signal VOUT reaches approximately zero.

0053At step 54, control circuit 28 may cause class-AB amplifier 44 to power on from a powered-off or powered-down state, which state class-AB amplifier 44 may operate in order to save power when final output stage 24 is operating in the class-D mode.

0054At step 55, control circuit 28 may monitor audio output signal VOUT to determine when class-AB amplifier 44 has settled into a steady-state operation from being powered on. Once class-AB amplifier 44 has settled, method 51 may proceed to step 56.

0055At step 56, control circuit 28 may enable clamp 46, thus shorting the output terminals at the amplifier output of amplifier 16 together, forcing audio output signal VOUT to zero. At step 57, control circuit 28 may disable class-D amplifier 42. For example, class-D amplifier 42 may be disabled by deactivating switches integral to class-D amplifier 42 such that the output terminals of class-D amplifier 42 are in a high-impedance state.

0056At step 58, class-AB audio output stage 44 and/or preconditioning circuit 49 may ramp a common mode voltage of audio output signal VOUT to a predetermined value (e.g., a common-mode voltage equal to one -half of a supply voltage for class-AB audio output stage 44). At step 60, control circuit 28 may fully enable class-AB audio output stage 44 such that audio output signal VOUT is an unmodulated signal which is a function of intermediate signal VINT. For example, class-AB amplifier 44 may be enabled by activating switches integral to class-AB amplifier 44 (e.g., switches 94 depicted in FIGURES 4 and 5) such that the output terminals of a class-AB driver stage (e.g., class-AB driver stage 90) integral to class-AB amplifier 44 are coupled to the output terminals of final output stage 24. In some embodiments, steps 56 through 60 may take place when the modulated output signal output by class-D audio output stage 42 is at an approximate completion of a modulation period. At step 62, control circuit 28 may disable clamp 46, thus allowing audio output signal VOUT to take on a non-zero value driven by class-AB audio output stage 44. After completion of step 62, method 51 may end.

0057Although FIGURE 9 discloses a particular number of steps to be taken with respect to method 51 , method 51 may be executed with greater or fewer steps than those depicted in FIGURE 9. In addition, although FIGURE 9 discloses a certain order of steps to be taken with respect to method 51, the steps comprising method 51 may be completed in any suitable order.

0058Method 51 may be implemented using personal audio device 1 or any other system operable to implement method 51. In certain embodiments, method 51 may be implemented partially or fully in software and/or firmware embodied in computer-readable media and executable by a controller.

0059FIGURE 10 is a flow chart of an example method 70 for switching between a second mode of final output stage 24 of amplifier 16 and a first mode of final output stage 24 of amplifier 16, in accordance with embodiments of the present disclosure. According to some embodiments, method 70 begins at step 72. As noted above, teachings of the present disclosure are implemented in a variety of configurations of personal audio device 1. As such, the preferred initialization point for method 70 and the order of the steps comprising method 70 may depend on the implementation chosen.

0060At step 72, control circuit 28 may monitor intermediate signal VINT, audio output signal VOUT, or another signal indicative of analog input signal VIN, to determine if analog input signal VIN has increased from below to above a threshold amplitude (which may be the same threshold as that of step 52, or a different threshold). If analog input signal VIN has increased from below to above the threshold amplitude, method 70 may proceed to step 73. Otherwise, method 70 may remain at step 72 until such threshold amplitude crossing occurs.

0061At step 73, control circuit 28 may monitor audio output signal VOUT to determine when the amplitude of audio output signal VOUT is approximately zero (e.g., when audio output signal VOUT experiences a zero crossing). If audio output signal VOUT is approximately zero, method 70 may proceed to step 74. Otherwise, method 70 may remain at step 73 until audio output signal VOUT is approximately zero. At step 74, control circuit 28 may cause class-D amplifier 42 to power on from a powered-off or powered-down state, which state class-D amplifier 42 may operate in order to save power when final output stage 24 is operating in the class-AB mode.

0062At step 75, control circuit 28 may monitor audio output signal VOUT to determine when class-D amplifier 42 has settled into a steady-state operation from being powered on. Once class-D amplifier 42 has settled, method 70 may proceed to step 76.

0063At step 76, control circuit 28 may enable clamp 46, thus shorting the output terminals at the amplifier output of amplifier 16 together, forcing audio output signal VOUT to zero. At step 77, control circuit 28 may disable class-AB amplifier 44. For example, class-AB amplifier 44 may be disabled by activating switches integral to class-AB amplifier 44 (e.g., switches 94 depicted in FIGURES 4 and 5) such that the output terminals of a class-AB driver stage (e.g., class-AB driver stage 90) integral to class-AB amplifier 44 are decoupled to the output terminals of final output stage 24.

0064At step 78, preconditioning circuit 49 (or another auxiliary amplifier, not shown in FIGURE 3) may ramp a common mode voltage of audio output signal VOUT to zero. At step 80, control circuit 28 may fully enable class-D audio output stage 42 such that audio output signal VOUT is a modulated signal which is a function of intermediate signal VINT. For example, class-D amplifier 42 may be enabled by activating switches integral to class- D amplifier 42 such that the output terminals of class-D amplifier 42 are coupled to the output terminals of final output stage 24. In some embodiments, steps 76 through 80 may take place when the modulated output signal output by class-D audio output stage 42 is at an approximate beginning of a modulation period.

0065At step 82, control circuit 28 may disable clamp 46, thus allowing audio output signal VOUT to take on a non-zero value driven by class-D audio output stage 42. After completion of step 82, method 70 may end.

0066Although FIGURE 10 discloses a particular number of steps to be taken with respect to method 70, method 70 may be executed with greater or fewer steps than those depicted in FIGURE 10. In addition, although FIGURE 10 discloses a certain order of steps to be taken with respect to method 70, the steps comprising method 70 may be completed in any suitable order. Method 70 may be implemented using personal audio device 1 or any other system operable to implement method 70. In certain embodiments, method 70 may be implemented partially or fully in software and/or firmware embodied in computer-readable media and executable by a controller.

0067A particular challenge in determining whether to switch between modes of final output stage 24 is that detection of in-band signal levels for such switching requires low- pass filtering. However, such a low-pass filter adds latency to the determination of whether to switch nodes. Thus, for a rising magnitude of an input signal, the latency in such determination of whether to switch modes (e.g., from the second mode with Class AB output stage 44 enabled to the first mode with Class D output stage 42 enabled) may cause switching to occur too slowly, such that signal clipping of the output signal occurs.

0068FIGURE 11 is a block diagram of selected components of an example control circuit 28 of amplifier 16 depicted in FIGURE 3, in accordance with embodiments of the present disclosure. Such components of control circuit 28 may reduce or eliminate the challenge described above with respect to low-pass filter inducing latency in the control of switching between modes.

0069As shown in FIGURE 11, control circuit 28 may include a ones density detector 122, an inline filter 124, an offline filter 126, comparators 128, 130, and 132, and a logical OR gate 134.

0070Ones density detector 122 may include any system, device, or apparatus configured to determine (particularly in embodiments in which digital audio input signal DIG_IN is a pulse-density modulated signal) a density of logical ones of digital audio input signal DIG_IN and generate an output signal indicative of such density. Such output signal may be received by comparator 128 and compared by comparator 128 against a threshold density THRA in order to generate an intermediate switching signal SWA.

0071Inline filter 124 may include any suitable filter configured to receive digital audio input signal DIG_IN and low-pass filter digital audio input signal DIG_IN to generate a low-pass filtered version of digital audio input signal DIG_IN. Such filtered signal may be received by comparator 130 and compared by comparator 130 against a threshold density THRB in order to generate an intermediate switching signal SWB. As its name indicates, inline filter 124 may be integral to the signal path between digital audio input signal DIG_IN and audio output signal VOUT, and thus may generate an output signal FILT that may represent an intermediate voltage internal to DAC 14, first stage 22, or any other suitable portion of amplifier 16 comprising the signal path between digital audio input signal DIG_IN and audio output signal VOUT.

0072Offline filter 126 may include any suitable filter configured to receive digital audio input signal DIG_IN and low-pass filter digital audio input signal DIG_IN to generate a low-pass filtered version of digital audio input signal DIG_IN. Such filtered signal may be received by comparator 132 and compared by comparator 132 against a threshold density THRC in order to generate an intermediate switching signal SWC. As its name indicates, offline filter 126 may be external to the signal path between digital audio input signal DIG_IN and audio output signal VOUT. Because it is external to the signal path, offline filter 126 may be of a higher latency (and thus greater accuracy) than inline filter 124.

0073Logical OR gate 134 may perform a logical OR operation on the intermediate switching signals SWA, SWB, and SWC and generate a switching signal SWITCH that indicates that final output stage 24 of amplifier 16 should switch from the second mode (e.g., Class-AB output stage 44 enabled) to the first mode (e.g., Class-D output stage 42 enabled) in response to digital audio input signal DIG_IN increasing in magnitude. Accordingly, an assertion of any of switching signals SWA, SWB, and SWC may trigger a switch between the second mode to the first mode of final output stage 24. Due to their individual characteristics, the combination of ones density detector 122 and comparator 128 may be best suited for detecting threshold crossings of fast-rising signal magnitudes of digital audio input signal DIG_IN, the combination of inline filter 124 and comparator 130 may be best suited for detecting threshold crossings of medium-rising signal magnitudes of digital audio input signal DIG_IN, and the combination of offline filter 126 and comparator 132 may be best suited for detecting threshold crossings of slow-rising signal magnitudes of digital audio input signal DIG_IN. Accordingly, control circuit 28 may efficiently switch from the second mode (e.g., Class-AB output stage 44 enabled) to the first mode (e.g., Class-D output stage 42 enabled) of final output stage 24 while reducing or eliminating audio artifacts of switching.

0074The various thresholds THRA, THRB, and THRC may be equal/equivalent, or may be different. For example, in some embodiments, threshold THRB may be larger than threshold THRC to account for noise present in inline filter 124 and/or noise present in all or a portion of the signal path between digital audio input signal DIG_IN and audio output signal VOU_T. Thus, control circuit 28 may set threshold THRB relative to threshold THRC by measuring a difference between the filtered signal output by inline filter 124 and the filtered signal output by offline filter 126 when digital audio input signal DIG_IN is zero, such that the difference is indicative of noise present in inline filter 124, and setting threshold THRB based on the difference.

0075Although the foregoing contemplates use of the components of control circuit 28 depicted in FIGURE 11 to switch between a second mode and a first mode of final output stage 24, the systems and methods used herein may be applied to any audio system which employs a threshold for switching between operating modes of the audio system and/or active signal paths of the audio system. For example, in some embodiments, systems and methods identical or similar to those described above may be employed for use in noise gating, whereby for low magnitudes of an audio input signal, an output signal of an audio system is forced to zero, so as to avoid audio output of noise present in the signal path. Thus, referring to FIGURE 11 , control circuit 28 may set threshold THRB for exiting a noise-gating mode of operation of an audio system by measuring a difference between the filtered signal output by inline filter 124 and the filtered signal output by offline filter 126 when digital audio input signal DIG_IN is zero, such that the difference is indicative of noise present in an audio signal path, and setting threshold THRB based on the difference.

0076As used herein, when two or more elements are referred to as "coupled" to one another, such term indicates that such two or more elements are in electronic communication or mechanical communication, as applicable, whether connected indirectly or directly, with or without intervening elements.

0077This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative.

0078All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are construed as being without limitation to such specifically recited examples and conditions. Although embodiments of the present inventions have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the disclosure.