Semiconductor device and method for producing same

Semiconductor device and its manufacturing method

The present invention relates to a semiconductor device provided with a transistor and a diode, and a manufacturing method for the same.

Conventionally, what was indicated in literature shown below, for example as this kind of art is known (refer to patent documents and JP, 2005-183563, A). Art of a semiconductor device which equipped this literature with a diode which uses a hetero semiconductor field as an anode and makes a drift field a trench [in which a gate electrode was embedded at Mizouchi] type transistor with a cathode is indicated. A hetero semiconductor field which constitutes an anode of a diode is arranged at the predetermined intervals along with a gate electrode so that it may be inserted into an adjacent gate electrode.

0003In the above-mentioned conventional semiconductor device, arrangement formation of the hetero semiconductor field is carried out to a gate electrode in a plane direction of a semiconductor substrate so that a gate electrode may be adjoined. That is, a field which forms a hetero semiconductor field was needed for a plane direction of a semiconductor substrate. As a result, area efficiency of an element in a semiconductor substrate was bad, and it had become the hindrance at the time of raising a degree of location.

0004Then, it is in the present invention being made in view of the above, and a place made into the object improving area efficiency, and providing a semiconductor device which raised a degree of location, and a manufacturing method for the same.

0005In order to solve the above-mentioned subject, the present invention forms an anode field in a bottom of a slot in which a gate electrode was formed, or a drift field directly under a slot, A contact hole is formed in the depth which reaches an anode field at Mizouchi, a sauce electrode is laid under the contact hole via an inner wall insulation film, and an anode field and a sauce electrode are electrically connected in the state where it was insulated with a gate electrode by an inner wall insulation film.

<figref num="1">Drawing 1 is a sectional view showing composition of a semiconductor device concerning Embodiment 1 of the present invention.</figref><figref num="2A">Drawing 2A is a process sectional view showing a manufacturing method of a semiconductor device concerning Embodiment 1 of the present invention.</figref><figref num="2B">Drawing 2B is a process sectional view showing a manufacturing method of a semiconductor device concerning Embodiment 1 of the present invention.</figref><figref num="2C">Drawing 2C is a process sectional view showing a manufacturing method of a semiconductor device concerning Embodiment 1 of the present invention.</figref><figref num="2D">It is a process sectional view showing a manufacturing method of a semiconductor device which requires Drawing 2D for Embodiment 1 of the present invention.</figref><figref num="2E">Drawing 2E is a process sectional view showing a manufacturing method of a semiconductor device concerning Embodiment 1 of the present invention.</figref><figref num="2F">Drawing 2F is a process sectional view showing a manufacturing method of a semiconductor device concerning Embodiment 1 of the present invention.</figref><figref num="2G">Drawing 2G is a process sectional view showing a manufacturing method of a semiconductor device concerning Embodiment 1 of the present invention.</figref><figref num="2H">Drawing 2H is a process sectional view showing a manufacturing method of a semiconductor device concerning Embodiment 1 of the present invention.</figref><figref num="2I">Drawing 2I is a process sectional view showing a manufacturing method of a semiconductor device concerning Embodiment 1 of the present invention.</figref><figref num="2J">Drawing 2J is a process sectional view showing a manufacturing method of a semiconductor device concerning Embodiment 1 of the present invention.</figref><figref num="3">Drawing 3 is a sectional view showing composition of a semiconductor device concerning Embodiment 2 of the present invention.</figref><figref num="4A">Drawing 4A is a process sectional view showing a manufacturing method of a semiconductor device concerning Embodiment 2 of the present invention.</figref><figref num="4B">Drawing 4B is a process sectional view showing a manufacturing method of a semiconductor device concerning Embodiment 2 of the present invention.</figref><figref num="4C">Drawing 4C is a process sectional view showing a manufacturing method of a semiconductor device concerning Embodiment 2 of the present invention.</figref><figref num="5">Drawing 5 is a top view showing composition of a semiconductor device concerning Embodiment 3 of the present invention.</figref><figref num="6">Drawing 6 is a top view showing other composition of a semiconductor device concerning Embodiment 3 of the present invention.</figref><figref num="7">Drawing 7 is a top view showing other composition of a semiconductor device concerning Embodiment 3 of the present invention.</figref><figref num="8">Drawing 8 is a top view showing other composition of a semiconductor device concerning Embodiment 3 of the present invention.</figref><figref num="9">Drawing 9 is a top view showing composition of a semiconductor device concerning Embodiment 4 of the present invention.</figref><figref num="10">Drawing 10 is a top view showing other composition of a semiconductor device concerning Embodiment 4 of the present invention.</figref><figref num="11">Drawing 11 is a top view showing other composition of a semiconductor device concerning Embodiment 4 of the present invention.</figref>

Hereinafter, an embodiment for carrying out the present invention using a drawing is described.

(Embodiment 1) Drawing 1 is a figure showing composition of a semiconductor device concerning Embodiment 1 of the present invention. Using a semiconductor substrate of silicon carbide, a semiconductor device of Embodiment 1 shown in Drawing 1 is provided with MOSFET and a diode, and is constituted. In Drawing 1, it is N type high concentration (N) of silicon carbide.⁺N type low concentration (N) which becomes one principal surface of semiconductor substrate 101 of a model from silicon carbide^-Drift field 102 which comprised an epitaxial layer of a model is formed.

In one principal surface (surface) of drift field 102, they are P type ウェル field 103 and N.⁺Sauce field 104 of a model is formed. P type ウェル field 103 and N⁺Slot 105 of the depth which penetrates sauce field 104 of a model and reaches drift field 102 is formed. Anode field 106 is formed by introduction of alternative impurities in drift field [directly under] 102 of slot 105, and the upper surface of anode field 106 is making the bottom of slot 105. In this Embodiment 1, this anode field 106 is formed with P type conducted type of current, constitutes a PN junction type diode and functions as an anode of this diode in a bonded surface with an N type drift field.

Gate dielectric film 107 is formed in the side of slot 105, and a bottom of slot 105 so that drift field 102, ウェル field 103, and sauce field 104 may be touched. Gate electrode 108 is laid under the side of a slot via gate dielectric film 107. Interlayer insulation film 109 was formed in the upper surface of gate electrode 108, and gate electrode 108 is covered.

As it is enclosed by gate electrode 108, contact hole 110 is formed in slot 105. In contact hole 110, sauce electrode 112 is formed via inner wall insulation film 111 which carries out the tunic of the side of gate electrode 108. Sauce electrode 112 is formed on sauce field 104 and interlayer insulation film 109. This sauce electrode 112 is making ohmic connection of sauce field 104 and the anode field 106 by low resistance electrically. Sauce electrode 112 and gate electrode 108 are insulated with interlayer insulation film 109 and inner wall insulation film 111.

Electrically, by low resistance, ohmic connection of the Dorain electrode 113 is made, and it is formed in the principal surface (back) of another side of semiconductor substrate 101.

Next, a manufacturing method of a semiconductor device applied to this Embodiment 1 using a manufacturing process sectional view showing in Drawing 2A - the Drawing J is explained.

First, in a process shown in Drawing 2A, it is N.⁺To one principal surface of semiconductor substrate 101 of a model, it is N.^-Drift field 102 which consists of an epitaxial layer of silicon carbide of a model is formed. Although some polytypes (crystal many forms) exist in silicon carbide, it explains as typical 4H here. Semiconductor substrate 101 has a thickness of tens to about hundreds of micrometers. In drift field 102, one E14 to 1E18 cm-3 and thickness are formed, for example for impurity density as several micrometers - tens of micrometers.

Next, in a process shown in Drawing 2B, they are P type ウェル field 103 and N to drift field 102 by ion implantation.⁺Sauce field 104 of a model is formed. In order to pattern an ion implantation field, mask material may be formed on drift field 102 according to a process shown below. For example, a silicon oxide film can be used as mask material, and a heat CVD method and a plasma CVD method can be used as a deposition method.

Then, resist is patterned on mask material (not shown). The general photolithographic method can be used as the method of patterning. Patterned resist is used as a mask and etching removal of the mask material is carried out alternatively. Wet etching and dry etching, such as reactive ion etching, using fluoric acid as an etching method can be used.

After carrying out etching removal of the mask material alternatively, oxygen plasma, sulfuric acid, etc. remove resist. Patterned mask material is used as a mask, the ion implantation of P type and the N type impurities is carried out, and they are P type ウェル field 103 and N.⁺Sauce field 104 of a model is formed. As P type impurities, aluminum and boron can be used, for example. As N type impurities, nitrogen can be used, for example. It can control that a crystal defect arises to a pouring field by carrying out the ion implantation of the temperature of semiconductor substrate 101 in the state where it heated at about 600 ℃, at this time.

ウエッチ etching using fluoric acid removes mask material after ion implantation. Then, it is activated by heat-treating impurities which carried out ion implantation. Temperature of about 1700 ℃ can be used as heat treatment temperature, and argon and nitrogen can be conveniently used as an atmosphere. This heat treatment process may be carried out after a process shown in figure 2D explained henceforth.

Next, slot 105 is formed in drift field 102 in a process shown in Drawing 2C. First, mask material 201 is formed on sauce field 104. As mask material 201, an insulating film patterned like a process shown in previous Drawing 2B can be used. Then, mask material 201 is used as a mask and slot 105 is formed. As a method of forming a slot, the dry etching method is used suitably. The depth of slot 105 is made into the depth until it penetrates ウェル field 103 and sauce field 104 and reaches drift field 102.

Next, in a process shown in Drawing 2D, P type anode field 106 is alternatively formed in drift field [directly under] 102 of slot 105. Ion implantation can be used as a formation method of anode field 106. As a mask at the time of ion implantation, mask material 201 used at a process shown in previous Drawing 2C can be used. Thereby, anode field 106 can be alternatively formed in drift field [directly under] 102 of slot 105 with a セルフア line. About ionic species used for ion implantation, and substrate temperature, since it is the same as that of a process shown in previous Drawing 2B, it omits here.

Next, in a process shown in Drawing 2E, deposition formation of the gate dielectric film 107 is carried out at a thickness of about 100-1000A on the upper surface (bottom of slot 105) of anode field 106, the side of slot 105, and sauce field 104. As gate dielectric film 107, a silicon oxide film is used suitably and a thermal oxidation method, a heat CVD method, a plasma CVD method, the sputtering method, etc. are used as a deposition method.

After carrying out deposition formation of the gate dielectric film 107, in order to reduce interface semi- grade of ウェル field 103 and gate dielectric film 107, annealing treatment may be performed at temperature of about 1000 ℃ in atmosphere, such as nitrogen, argon, and N2O*.

Then, deposition formation of the polycrystalline silicon 202 which serves as gate electrode 108 in slot 105 and on sauce field 104 via gate dielectric film 107 and which introduced impurities is carried out. A general low-pressure CVD method can be used as a deposition method.

Next, in a process shown in Drawing 2F, etchback of the whole surface of polycrystalline silicon 202 is carried out, and polycrystalline silicon 202 other than an inside of slot 105 is removed. Or a resist pattern is formed on polycrystalline silicon 202, the mask of this register pattern is carried out, for example, using dry etching, polycrystalline silicon 202 is removed alternatively and patterned. This removes polycrystalline silicon 202 other than an inside of slot 105.

Next, in a process shown in Drawing 2G, interlayer insulation film 109 is alternatively formed on polycrystalline silicon 202. As interlayer insulation film 109, a silicon oxide film is used suitably. As a formation method, polycrystalline silicon 202 can be formed by carrying out thermal oxidation alternatively. Since the thermal oxidation rate is quicker than silicon carbide, when thermal oxidation of the polycrystalline silicon is carried out, it can form interlayer insulation film 109 with a セルフア line on polycrystalline silicon 202. Or a resist pattern is formed on interlayer insulation film 109 which deposited and deposited interlayer insulation film 109 using a heat CVD method, a plasma CVD method, the sputtering method, etc. first. Then, this resist pattern may be used as a mask and interlayer insulation film 109 on sauce field 104 may be removed alternatively.

Next, in a process shown in Drawing 2H, opening formation of the contact hole 110 is carried out at interlayer insulation film 109 and polycrystalline silicon 202. As a formation method, dry etching which used as a mask resist patterned by photo lithography can be used. Gate electrode 108 which consists of polycrystalline silicon by this so that contact hole 110 may be surrounded is formed. In Drawing 2H, it is illustrating about a case where gate dielectric film 107 is left to a bottom of contact hole 110. On the other hand, etching removal of the gate dielectric film 107 of a bottom of contact hole 110 may be carried out alternatively, and the partial upper surface of anode field 106 may be exposed.

Next, inner wall insulation film 111 is formed in the side which an inner wall of contact hole 110, i. e., gate electrode 108, exposed in a process shown in Drawing 2I. As a formation method, thermal oxidation of the gate electrode 108 consisting of polycrystalline silicon can be carried out, and it can be formed. Or deposition formation of the inner wall insulation film 111 can also be carried out using a heat CVD method, a plasma CVD method, the sputtering method, etc.

Next, in a process shown in Drawing 2J, the surface of anode field 106 of contact hole 110 directly under is exposed alternatively. As the exposure method, anisotropic dry etching removes alternatively gate dielectric film 107 of a bottom of contact hole 110.

Thickness of interlayer insulation film 109 is thickly formed rather than thickness of gate dielectric film 107 left behind to the bottom of contact hole 110 at this time, and inner wall insulation film 111. Even after this etches gate dielectric film 107 left behind to the bottom of contact hole 110, it can leave interlayer insulation film 109. It becomes possible to carry out etching removal of the gate dielectric film 107 of slot 105 bottom alternatively by using anisotropic dry etching, without etching inner wall insulation film 111 of a wall in contact hole 110. As it is enclosed by gate electrode 108 by carrying out such a process, contact hole 110 can be formed with a セルフア line in slot 105.

Then, deposition formation of the sauce electrode 112 is carried out so that ohmic connection may be electrically made by low resistance to ウェル field 103, sauce field 104, and anode field 106. Deposition formation of the Dorain electrode 113 is carried out in the principal surface of another side of semiconductor substrate 101.

although nickel シリサイド is suitably used as sauce electrode 112 and the Dorain electrode 113 -- Cobalt Thilly Said and チタンシ LISA -- alloys, such as an id, may be sufficient. As a deposition method, the vapor-depositing method, the sputtering method, a CVD method, etc. can be used. It does not matter as an electrode structure of lamination structure which laminated titanium and aluminum on sauce electrode 112 and the Dorain electrode 113. After depositing nickel first, アニール is given at temperature of about 1000 ℃, and silicon carbide and nickel are made to alloy as a formation method of nickel シリサイド.

A semiconductor device concerning Embodiment 1 shown in Drawing 1 is completed through the above process.

Next, fundamental operation in a semiconductor device of composition of being shown in Drawing 1 is explained.

A semiconductor device of composition of being shown in Drawing 1 is controlling potential of gate electrode 108, where positive predetermined potential's is impressed to the Dorain electrode 113 on the basis of potential of sauce electrode 112, and functions as a transistor. That is, a reversal layer will be formed in a channel field of ウェル field 103 of the side of gate electrode 108 if voltage between gate electrode 108 and sauce electrode 112 is carried out more than predetermined threshold voltage. Thereby, a transistor will be in an ON state and current will flow through it into sauce electrode 112 from the Dorain electrode 113.

On the other hand, if voltage between gate electrode 108 and sauce electrode 112 is made below into predetermined threshold voltage, a reversal layer will disappear, a transistor will be in an OFF state, and current will be intercepted. In this state, a hundreds to thousands of v high voltage is impressed between drain sauce depending on voltage currently impressed to sauce electrode 112 and the Dorain electrode.

When negative predetermined potential is impressed to the Dorain electrode 113 on the basis of potential of sauce electrode 112, P type ウェル field 103 and anode field 106 are used as an anode, and reflux current flows into a diode which used N type drift field 102 as a cathode. That is, this diode will function as a channeling-back diode.

Thus, in the above-mentioned Embodiment 1, it is forming anode field 106 in drift field [directly under] 102 of slot 105, and it becomes possible to use drift field [directly under] 102 of slot 105 as a formation field of a flowing-back diode. Compared with a case where this forms a diode in a plane direction to a substrate along with a gate electrode like before, area efficiency of a substrate at the time of forming an element can be improved. Therefore, it becomes possible to raise a degree of location of a semiconductor device provided with a transistor and a channeling-back diode.

Anode field 106 and sauce electrode 112 which were formed in drift field [directly under] 102 of slot 105 are electrically connected by low resistance via contact hole 110 formed so that gate electrode 108 might be penetrated. This becomes possible to reduce parasitism resistance between anode field 106 and sauce electrode 112, and it can provide a low loss semiconductor device which reduced a loss at the time of flowing-back operation.

In MOSFET generally formed in a silicon carbide board, since the Dorain electric field became high compared with MOSFET formed in a silicon substrate, a measure, such as thickening thickness of a bottom of gate dielectric film conventionally, was needed. For this reason, ON resistance of MOSFET was getting worse.

On the other hand, in the above-mentioned Embodiment 1, MOSFET can ease the Dorain electric field impressed to a bottom of gate dielectric film 107 at the time of OFF by forming anode field 106 in drift field [directly under] 102 of slot 105. As a result, a low loss semiconductor device provided with a flowing-back diode can be provided, controlling aggravation of ON resistance of MOSFET.

It is difficult to form a low resistance, P type field in silicon carbide generally. In order to ease the Dorain electric field, a concentration inclination which made low concentration a bottom of P type anode field 106, and made the upper part high concentration is required. Therefore, only by forming anode field 106 in drift field [directly under] 102 of slot 105, sheet resistance of anode field 106 in the depth direction of Drawing 1 becomes high, and aggravation of parasitism resistance by variation within a field and sheet resistance of reflux current arises.

On the other hand, in the above-mentioned Embodiment 1, since it is directly connected with sauce electrode 112 by low resistance right above [of it], anode field 106 becomes possible [controlling variation in reflux current within a field].

Since a diode which uses anode field 106 as an anode is a PN junction type diode, it has the same standup voltage as a PN junction type diode formed in ウェル field 103 and drift field 102. For this reason, since uniform reflux current flows into a field at the time of flowing-back operation, generating of current variation can be controlled.

According to the above-mentioned Embodiment 1, slot 105 of the depth which penetrates ウェル field 103 and sauce field 104 first, and reaches drift field 102 is formed, and anode field 106 is formed in drift field [directly under] 102 of slot 105. Then, gate electrode 108 is laid underground in slot 105 via gate dielectric film 107, and contact hole 110 which exposes the surface of anode field 106 to gate electrode 108 is formed. Then, burial formation of the sauce electrode 112 electrically connected with anode field 106 in the state where it was insulated with gate electrode 108 by inner wall insulation film 111 is carried out in contact hole 110. A channeling-back diode can be formed in drift field [directly under] 102 of slot 105 by passing through such a manufacturing process. Compared with a case where this forms a diode in a plane direction to a substrate along with a gate electrode like before, area efficiency of a substrate at the time of forming an element can be improved. Therefore, a manufacturing method which raises a degree of location of a semiconductor device provided with a transistor and a channeling-back diode can be provided.

It is carrying out burial formation of the sauce electrode 112 via inner wall insulation film 111 in contact hole 110 formed in gate electrode 108 in slot 105, It becomes possible to electrically connect anode field 106 formed in drift field [directly under] 102 of slot 105 in the state where it was insulated with gate electrode 108, and sauce electrode 112. Thereby, anode field 106 and sauce electrode 112 are connectable by low resistance in the state where it was insulated with gate electrode 108. As a result, a manufacturing method which can manufacture a low loss semiconductor device can be provided.

Rather than thickness of gate dielectric film 107 left behind to the bottom of contact hole 110, and inner wall insulation film 111, interlayer insulation film 109 is formed thickly. Even if it is after this etches gate dielectric film 107 left behind to the bottom of contact hole 110, it can leave interlayer insulation film 109. As a result, a diode can be formed directly under slot 105 with sufficient controllability.

When etching gate dielectric film 107 left behind to the bottom of contact hole 110, anisotropic dry etching is used. Thereby, without carrying out etching removal of the inner wall insulation film 111 of a wall in contact hole 110, gate dielectric film 107 can be removed alternatively and the surface of anode field 106 can be exposed. As a result, it becomes possible to form contact hole 110 with a セルフア line, and can form a low loss semiconductor device with which a diode was formed in drift field [directly under] 102 of slot 105 with sufficient controllability.

(Embodiment 2) Drawing 3 is a sectional view showing composition of a semiconductor device concerning Embodiment 2 of the present invention.

A different point from Embodiment 1 in this Embodiment 2 forms anode field 106 in a bottom of slot 105, and silicon carbide from which this anode field 106 constitutes drift field 102 is a point currently formed by different different-species material. Since it is the same as that of previous Embodiment 1, other composition and fundamental operations are omitted here.

Anode field 106 of this Embodiment 2 is formed in a bottom of slot 105 to anode field 106 of previous Embodiment 1 being formed in drift field [directly under] 102 of slot 105.

As different-species material which constitutes anode field 106, for example, charges of a metallic material, such as titanium, aluminum, nickel, and molybdenum, or drift field 102 differs from a band gap, semiconducting materials, such as polycrystalline silicon, can be used. When anode field 106 is formed at a charge of a metallic material, in a bonded surface of anode field 106 and drift field 102, shot key junction is formed and a Schottky diode consists of both. This Schottky diode has the function to send channeling-back current like a PN junction type diode explained by previous Embodiment 1.

On the other hand, a Schottky diode is a uni-Poral diode and can constitute a low loss diode which controlled a reverse recovery electric charge compared with a diode (bipolar diode) of Embodiment 1.

Next, polycrystalline silicon explains a manufacturing method of a semiconductor device at the time of forming anode field 106 using figure 4 A-C. About a process before a process shown in Drawing 4A, it is the same as that of a process shown in previous Drawing 2A - Drawing 2B of Embodiment 1.

After a process shown in Drawing 2B is completed, in a process shown in Drawing 4A, slot 105 is formed using mask material 201 like a process shown in previous Drawing 2C. If the depth which forms anode field 106 at this time considers it as the same depth as Drawing 2C, a different point from a process shown in Drawing 2C will be formed more deeply than the depth formed at a process which shows the depth of slot 105 in Drawing 2C. This is for forming anode field 106 in a bottom in slot 105 by this Embodiment 2 to forming in drift field [directly under] 102 of slot 105 in previous Embodiment 1.

Next, in a process shown in Drawing 4B, deposition formation of the polycrystalline silicon 401 is carried out on the whole surface so that it may be filled up in slot 105 at least. A general low-pressure CVD method can be used as a deposition method.

Next, in a process shown in Drawing 4C, whole surface etchback of the polycrystalline silicon 401 which carried out deposition formation is carried out, and polycrystalline silicon 401 other than mask material 201 used at a process shown in previous Drawing 4A and a bottom of slot 105 is removed alternatively. Thereby, if it is from different-species material of polycrystalline silicon 401 at a bottom of slot 105, anode field 106 is formed.

About subsequent processes, since it is the same as that of a process or subsequent ones shown in Drawing 2E of previous Embodiment 1, it omits here.

Thus, in the above-mentioned Embodiment 2, since anode field 106 which has the same function as previous Embodiment 1 is formed in a bottom of slot 105, an effect acquired by Embodiment 1 and same effect can be acquired.

In this Embodiment 2, silicon carbide of drift field 102 is forming anode field 106 by different different-species material, and it constitutes a uni-Poral type diode between anode field 106 and drift field 102. The uni-Poral diode can control a reverse recovery electric charge compared with a diode (bipolar diode) of previous Embodiment 1. A semiconductor device provided with a low loss diode by this can be provided.

Anode field 106 is formed with polycrystalline silicon. This forms a hetero-junction by junction of a semiconductor with which band gaps differ in a bonded surface of anode field 106 and drift field 102. As a result, anode field 106 which consists of polycrystalline silicon is used as an anode, and a hetero-junction type diode which uses drift field 102 of silicon carbide as a cathode is constituted. The hetero-junction diode formed from silicon carbide operates as a uni-Poral diode as indicated, for example in patent documents of patent No. 4211642. For this reason, it becomes possible to control a reverse recovery electric charge compared with a diode of previous Embodiment 1, and can provide a semiconductor device provided with a low loss diode.

By forming anode field 106 with polycrystalline silicon, compared with a case where it forms with metal or an alloy, metallic contamination to gate dielectric film 107 can be controlled, and it can control that interface semi- grade increases. It can control by this that ON resistance of MOSFET increases, and can provide a low loss semiconductor device.

A silicon oxide film can be formed by oxidizing polycrystalline silicon. Thereby, when gate dielectric film 107 is formed by thermal oxidation, the side and the bottom of gate dielectric film 107 can be formed with the same silicon oxide film. As a result, it becomes possible to control electric field concentration by discontinuity of material which forms gate dielectric film 107, and can provide a reliable semiconductor device.

(Embodiment 3) Drawing 5 - Drawing 8 are top views showing a layout of a plane direction (the direction of the principal surface of a semiconductor substrate) of a semiconductor device concerning Embodiment 3 of the present invention.

Drawing 5 - Drawing 8 are figures which looked at the state where sauce electrode 112 of a semiconductor device shown in Drawing 1 was removed, from a top, and a section which met an A-A line of Drawing 5 is equivalent to a section shown in Drawing 1. In an example of a layout shown in Drawing 5 - Drawing 8, contact hole 110 formed in slot 105 is arranged intermittently (discrete). Here, in Drawing 5 - Drawing 8, a transverse direction of space is made into the direction of X to a plane (principal surface) of semiconductor substrate 101, and it explains below by making a lengthwise direction into the direction of Y.

In composition shown in Drawing 5, slot 105 is formed in the direction of Y in a plane (principal surface) of semiconductor substrate 101 continuously (the shape of a straight line), and is discretely arranged in parallel to [two or more] the direction of X. Contact hole 110 formed in slot 105 is discretely arranged to each slot 105. Contact hole 110 formed in adjacent slot 105 is arranged in the shape of a straight line in the direction of X. Width (W1) of slot 105 in a portion in which contact hole 110 is formed is formed more greatly (W1&gt;W2) than width (W2) of slot 105 in a portion in which contact hole 110 is not formed.

It becomes possible to lengthen length around slot 105 (channel width of a transistor), maintaining a value beforehand decided by specification etc. in distance between slot-contact holes (L1) by adopting such composition in addition to an effect acquired by previous Embodiments 1 and 2. This becomes possible to reduce ON resistance of MOSFET, and it can provide a low loss semiconductor device. Here, distance between slot-contact holes (L1) is the distance between the side of slot 105, and the side of contact hole 110.

Composition shown in Drawing 6 arranges alternately (un-countering) contact hole 110 formed in each adjacent slot 105 to composition shown in Drawing 5. Others are the same as that of composition of Drawing 5.

It becomes possible to be shortened by adopting such composition compared with composition which shows gate inter electrode distance (L2) in previous Drawing 5 compared with composition shown in Drawing 5, and composition which shows a gate pitch (L3) in Drawing 5 similarly. Thereby, compared with composition shown in Drawing 5, a degree of location of a semiconductor device can be raised further. It becomes possible to reduce ON resistance of MOSFET, and can provide a low loss semiconductor device. Here, as shown in Drawing 5 and Drawing 6, gate inter electrode distance (L2) is the distance between gate electrodes 108 formed in adjacent slot 105, and a gate pitch (L3) is the distance between the centers of adjacent slot 105.

In composition shown in Drawing 7, slot 105 is formed in the shape of a mesh (meshes of a net). As these meshes of a net are shown in Drawing 7, one meshes of a net are square shape. Contact hole 110 is arranged at each intersection (portion which slot 105 in every direction intersects) of meshes of a net.

It becomes possible to raise density of meshes of a net, maintaining a value beforehand decided by specification etc. in distance between slot-contact holes (L1) by adopting such composition. Thereby, a degree of location of a semiconductor device can be raised. It becomes possible to reduce ON resistance of MOSFET, and can form a low loss semiconductor device with sufficient controllability.

Although slot 105 is formed in the shape of a mesh (meshes of a net) like previous Drawing 7 in composition shown in Drawing 8, as a different point from Drawing 7 is shown in Drawing 8, one meshes of a net are the shape of a hexagon. Contact hole 110 is arranged at each peak (portion which slot 105 intersects) of meshes of a net.

It becomes possible to raise density of meshes of a net, maintaining a value beforehand decided by specification etc. in distance between slot-contact holes (L1) by adopting such composition. Thereby, a degree of location of a semiconductor device can be raised. It becomes possible to reduce ON resistance of MOSFET, and can form a low loss semiconductor device with sufficient controllability.

in addition -- although shape of one meshes of a net illustrated a quadrangle and a hexagon above -- other polygons -- it may be circular. In that case, contact hole 110 can be arranged along with a polygonal vertex and the circular circumference.

(Embodiment 4) Drawing 9 - Drawing 11 are top views showing a layout of a plane direction (the direction of the principal surface of a semiconductor substrate) of a semiconductor device concerning Embodiment 4 of the present invention.

Drawing 9 - Drawing 11 are figures which looked at the state where sauce electrode 112 of a semiconductor device shown in Drawing 1 was removed, from a top. In an example of a layout shown in Drawing 9 - Drawing 11, contact hole 110 is continuously formed to contact hole 110 being discretely arranged in previous Drawing 5 - Drawing 8.

In composition shown in Drawing 9, contact hole 110 is formed on a straight line along inside of slot 105 formed in a lengthwise direction of space.

Since contact hole 110 is continuously formed by adopting such composition, anode field 106 becomes possible [connecting with sauce electrode 112 embedded continuously right above / of it / in contact hole 110]. Thereby, connection area of anode field 106 and sauce electrode 112 can increase, and it can connect both by low resistance. As a result, a low loss semiconductor device which reduced ON resistance of a diode can be provided.

In composition shown in Drawing 10, if slot 105 shows in previous Drawing 7, meshes of a net are similarly formed in the shape of [square] meshes of a net, and contact hole 110 is also continuously formed in the shape of meshes of a net along inside of slot 105 of the shape of these meshes of a net.

In composition shown in Drawing 11, if slot 105 shows in previous Drawing 8, meshes of a net are similarly formed in the shape of [of a hexagon] meshes of a net, and contact hole 110 is also continuously formed in the shape of meshes of a net along inside of slot 105 of the shape of these meshes of a net.

Since contact hole 110 is continuously formed by adopting such composition, anode field 106 becomes possible [connecting with sauce electrode 112 embedded continuously right above / of it / in contact hole 110]. Thereby, connection area of anode field 106 and sauce electrode 112 can increase, and it can connect both by low resistance. As a result, a low loss semiconductor device which reduced ON resistance of a diode can be provided.

As mentioned above, in each above-mentioned Embodiment 1-4, although it is illustrating about a unit cell in a sectional view of a semiconductor device, it may have multiple connection structure which gathered and repeated a unit cell. It may be made to equip the outermost periphery of a device with electrolysis relief structure which consists of girdling or termination structure.

This application claims a right of priority based on the Japan patent application No. 092962 [2011 to] for which it applied on April 19, 2011, and the contents of this application are included in a specification of the present invention by reference.

According to the present invention, since an anode field is formed in a bottom of a slot in which a gate electrode was formed, or a drift field directly under a slot, a diode can be formed in a perpendicular direction of a substrate to a gate electrode. As a result, area efficiency of an element in a semiconductor substrate can be improved, and a degree of location can be raised.