Method and device for correcting clock jitter

Method and device for correcting clock jitter

The present invention relates to the field of communication, and more specifically, to a method and apparatus for correcting clock jitter in the field of communication. Background technique

The Common Public Radio Interface (CPRI) defines the interface relationship between the radio equipment controller (EC) and the radio equipment (adio equipment, RE), and constitutes a remote system of the base station.

Currently there are not only non-packet CPRI transmissions but also packet CPRI transmissions. In packet CPRI transmission, the CPRI base frame is encapsulated in an Ethernet frame for transmission. At this time, the CPRI base frame will pass through the Ethernet and reach the receiving end.

For example, when the REC sends a CPRI base frame to the RE via Ethernet, the REC generates a CPRI base frame under the action of the CPRI master clock. Each CPRI base frame has a length of 260.4 ns, and there is no space between adjacent CPRI base frames. interval. In order to send the CPRI base frame to the Ethernet, the CPRI clock needs to be converted to the Ethernet clock and the CPRI base frame data is carried in the Ethernet frame. The frame head distance of adjacent Ethernet frames is expected to be kept at 260.4 ns. However, after the Ethernet frame is output to the Ethernet link, the forwarding of the Ethernet switch isolates the clocks of both parties of the communication, and introduces a large clock jitter for the Ethernet frame, so that the header distance of the Ethernet frame received by the RE There is large jitter. After the RE converts the Ethernet clock to the CPRI slave clock through clock domain conversion, for the CPRI base frame obtained from the Ethernet frame, the length of each CPRI base frame appears large jitter, which is difficult to meet the REC master clock required by the CPRI system. The jitter between the and RE slave clocks is less than 0.002ppm, which makes it difficult for the RE slave clocks to lock to the REC master clock, which adversely affects subsequent CPRI base frame processing.

It can be seen that when the Ethernet frames carrying CPRI base frame data are transmitted in Ethernet, due to the existence of clock jitter, although the Ethernet frames output from the REC have equal inter-frame intervals, the Ethernet frames received by the RE The interval between frames appears jittery, and the interval between ether frames becomes disordered. Due to the inter-frame interval jitter between the Ethernet frames, the CPRI base frames extracted from the Ethernet frames appear jitter. The interval between the CPRI base frames is large and small, which cannot meet the jitter index required by the CPRI system. The rapid processing of frames in real time caused great difficulties, and even caused subsequent collapse of CPRI base frame processing. Summary of the invention

The embodiments of the present invention provide a method and an apparatus for correcting clock jitter, which can reduce the impact of the clock jitter introduced by Ethernet on subsequent system processing, so that the requirements for limiting clock jitter can be met, and the clock jitter can be limited to an acceptable range of the index .

An aspect of the present invention provides a method for correcting clock jitter, including: inputting the received data into a buffer according to an Ethernet clock recovered from received data, the received data including an Ethernet frame and an adjacent Ethernet frame The interval between frames; during the process of reading the received data from the buffer according to the local clock, if the amount of received data buffered in the buffer exceeds the first threshold, it is deducted from the interval between frames A first predetermined amount of invalid data, or, if the amount of received data buffered in the buffer is lower than a second threshold, insert a second predetermined amount of invalid data in the inter-frame space to obtain the data from the buffer Output data output, wherein the local clock is synchronized with the Ethernet clock.

In another aspect of the present invention, an apparatus for correcting clock jitter is provided, including: a clock recovery module, configured to recover an Ethernet clock from received data, the received data including an Ethernet frame and an adjacent Ethernet frame Inter-frame interval; buffer, used to buffer the received data input according to the Ethernet clock; local clock, used to provide the clock frequency for reading the received data from the buffer; jitter correction module, used to During the process of reading the received data from the buffer according to the local clock, if the amount of received data buffered in the buffer exceeds the first threshold, the first predetermined amount is deducted from the inter-frame interval Invalid data, or, if the data volume of the received data buffered in the buffer is lower than the second threshold, inserting a second predetermined amount of invalid data in the inter-frame interval to obtain output data output from the buffer, The local clock is synchronized with the Ethernet clock.

Based on the above technical solution, the received data is input into the buffer according to the Ethernet clock, and the buffer is output according to the local clock synchronized with the Ethernet clock. The relationship between the amount of data buffered in the buffer and the threshold is used to inter-frame the received data. The interval data is removed and inserted, so that the clock jitter introduced by Ethernet can be corrected, so that the output data output from the buffer has a smooth data flow form, thereby reducing the impact of the clock jitter introduced by Ethernet on subsequent system processing. Limit clock jitter to an acceptable range for subsequent system processing. BRIEF DESCRIPTION

In order to more clearly explain the technical solutions of the embodiments of the present invention, the drawings required in the embodiments will be briefly described below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, without paying any creative work, other drawings can be obtained based on these drawings.

FIG. 1 is a schematic diagram of an example of an application scenario.

2 is a flowchart of a method for correcting clock jitter according to an embodiment of the present invention.

3 is a flowchart of a method for correcting clock jitter by subtracting and inserting invalid data according to an embodiment of the present invention. flow chart. Implementation block diagram.

FIG. 6 is a schematic diagram of a specific example for implementing the method shown in FIG. 5.

7 is an implementation block diagram of a specific example of a method for correcting clock jitter according to an embodiment of the present invention. FIG. 8 is a structural block diagram of an apparatus for correcting clock jitter according to an embodiment of the present invention.

9 is a structural block diagram of another device for correcting clock jitter according to an embodiment of the present invention.

The technical solutions of the embodiments of the present invention will be described clearly and completely in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are a part of the embodiments of the present invention rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present invention. Body scene. This specific scenario is just an example, and does not limit the protection scope of the present invention in any way.

In the application scenario shown in FIG. 1, the sending end may be REC, and the receiving end is RE; or, the sending end may also be RE, and the receiving end is REC. For simplicity of description, the following uses the sending end as a REC and the receiving end as an example.

For example, REC generates CPRI base frames based on the CPRI clock, and each CPRI base frame can be

260.4ns. In order to transmit the CPRI base frame through Ethernet, after the clock domain conversion processing and frame conversion processing, the valid data in the CPRI base frame is encapsulated in the Ethernet frame. Among them, the clock domain conversion in the REC can convert the CPRI clock to the Ethernet clock, and the frame conversion in the REC can be solved by deciphering the CPRI base frame, extracting the valid data in it, and then carrying the valid data in the Ethernet frame to form a combination In the Ethernet frame, the interval between each Ethernet frame and the subsequent frame is 260.4 ns. However, since the clock domain conversion introduces a small random jitter A, the interval between each Ethernet frame plus the subsequent frame is 260.4ns+A.

During the transmission of the Ethernet frame via Ethernet, due to the influence of the Ethernet switch, a large random jitter B is introduced for the Ethernet frame. Therefore, the header interval of the Ethernet frame received by the RE is 260.4ns+A+B, Exceeded the limit of 0.002ppm.

If the CPRI base frame is obtained directly from the Ethernet frame received by the RE, the CPRI base frame will have a large clock jitter, which cannot meet the requirements of the CPRI standard to maintain the clock jitter within 0.002ppm. Subsequent processing of the CPRI base frame Will be affected, and even cause the system to crash. Therefore, the Ethernet frame received by the RE needs to be corrected for clock jitter.

The clock jitter correction module in the RE uses the method for correcting clock jitter according to an embodiment of the present invention, so that the Ethernet frames received by the RE with a larger clock jitter can be sorted out, so that the distance between the frame heads of adjacent Ethernet frames Maintained at 260.4ns+C, C is random jitter with variance less than 0.002ppm. After the clock domain conversion process and the frame conversion process, the CPRI base frame with a length of 260.4 ns+D can be output for the system that subsequently processes the CPRI base frame. The clock domain conversion in the RE can convert the Ethernet clock to the CPRI clock. The frame conversion in the RE can extract the valid data of the CPRI base frame from the Ethernet frame, and then compose the valid data into the CPRI base frame. Since the new jitter brought by the clock domain conversion process is very small, the jitter D of the CPRI base frame obtained in the RE can still be maintained within a random jitter of less than 0.002 ppm. Therefore, for the CPRI base frame sent by the REC and the CPRI base frame received by the RE, the clock jitter can be controlled within 0.002 ppm, In order to meet the requirements of the CPRI standard for clock jitter indicators, it is conducive to the processing of subsequent systems. In addition, since the Ethernet clock and the CPRI clock used in the RE are generated based on the local clock, if the local clock is a high-stability clock, the Ethernet clock and the CPRI clock are both high-stability clocks.

Next, a method for correcting clock jitter according to an embodiment of the present invention will be described in detail with reference to FIG. 2. As shown in the figure, the method of FIG. 2 includes:

In S210, the received data is input into the buffer according to the Ethernet clock recovered from the received data, and the received data includes an inter-frame interval between the Ethernet frame and the adjacent Ethernet frame.

As an example, the received data may be the above-mentioned Ethernet frame transmitted through high-speed Ethernet; and the Ethernet frame may be used to carry CPRI frame data.

In S220, in the process of reading the received data from the buffer according to the local clock, if the data amount of the received data buffered in the buffer exceeds the first threshold, the first predetermined amount of invalid data is deducted from the inter-frame interval, if When the data amount of the received data buffered in the buffer is lower than the second threshold, a second predetermined amount of invalid data is inserted in the inter-frame interval to obtain output data output from the buffer, where the local clock is synchronized with the Ethernet clock.

For the buffer that buffers the received data, the write clock of the buffer is an Ethernet clock, which can be recovered from the received data, and the read clock of the buffer is a local clock, which needs to be synchronized with the Ethernet clock. The Ethernet domain is isolated from the local clock domain through a buffer. The buffer can be a piece of storage space created in the memory to buffer the received data and help to correct the clock jitter during the input and output of the received data.

The received data buffered by the buffer includes an Ethernet frame and an inter-frame interval. Data under other protocols can be carried in the Ethernet frame. For example, the data under the CPRI protocol may be carried in the Ethernet frame, and the CPRI frame data may be transmitted through the Ethernet frame.

According to an embodiment of the present invention, the local clock may be a high-stability clock. In this way, the local clock has better stability, which is beneficial to subsequent system processing.

The correction of the clock jitter can be achieved by multiplying and reducing the invalid data in the inter-frame interval in S220.

Hereinafter, a flowchart of a method for correcting clock jitter by subtracting and inserting data according to an embodiment of the present invention will be described in detail with reference to FIG. 3.

The received data is continuously input into the buffer under the action of the recovered Ethernet clock, and the received data is continuously read from the buffer according to the local clock. In order to correct the clock jitter in the process of reading the received data from the buffer, the invalid data in the inter-frame interval may be processed with more deductions and less compensation, as follows.

In S310, the data amount of the received data buffered in the buffer is counted.

In S320, it is determined whether the data amount of the received data buffered in the buffer is greater than the first threshold. The first threshold may be the sum of the fixed value M and the predetermined number of samples Th1 included in the Ethernet frame. Thl may be a predetermined number of samples contained in an Ethernet frame of a known length in an ideal case. For example, in a CPRI system, Thl may be an Ethernet frame encapsulated with CPRI data times the frequency of an Ethernet clock. The fixed value M may be equal to Thl, in which case the first threshold is 2 Thl. When the data buffered in the buffer exceeds the first threshold, it means that the speed of writing the buffer is faster than the speed of the reading buffer, and the operation of deducting invalid data between the frames needs to be performed, so proceed to S330; when the data buffered in the buffer When the first threshold is not exceeded, proceed to S340. Of course, the first threshold may also be other values. The size of the buffer is not less than the first threshold. In S330, when the amount of data in the buffer is greater than the first threshold, the invalid data in the inter-frame interval is deducted, and the deducted number is the first predetermined amount.

The data of the inter-frame interval may have a fixed format, for example, the inter-frame interval data may start with a Terminate symbol, followed by an Idle symbol, so the receiving end can easily determine which part of the received data belongs to the inter frame interval.

The deducted invalid data may be idle characters, which does not affect the basic structure of the inter-frame space. Each time the invalid data is deducted, only one invalid data can be deducted, that is, the invalid data read within one local clock cycle can be deducted. In this way, the effect of smoothly deducting invalid data can be achieved, and excessive deviations caused by excessive deductions can be avoided.

In S340, it is determined whether the data amount of the received data buffered in the buffer is lower than the second threshold. The second threshold may be the difference between the fixed value M and the predetermined number of samples Th1 included in the Ethernet frame. The meaning of Thl is as described above. The fixed value M may be equal to Thl, in which case the second threshold is 0. When the data buffered in the buffer is lower than the first threshold, it means that the speed of writing the buffer is lower than the speed of the reading buffer. There is no data buffered in the buffer, and the operation of inserting invalid data into the inter-frame interval needs to be performed, so advance to S350; when the data buffered in the buffer is not lower than the first threshold, proceed to S310. Of course, the second threshold may also be other values.

For example, assume that the first threshold is the sum of M and TT, the second threshold is the difference between M and TT, and that TT is an integer multiple of the maximum Ethernet frame length. If M is larger and TT is larger, the fixed delay will be larger. Considering that the smaller the delay, the better. You can set TT to an Ethernet frame length. Since the second threshold cannot be a negative number, and considering that storing M data means bringing a fixed delay of M clock cycles, it is desired that the smaller M is the better, then M can be set to TT. Therefore, both M and TT can be set to one Ethernet frame length.

In S350, when the amount of data in the buffer is less than the second threshold, invalid data is inserted in the inter-frame interval, and the number of insertions is the second predetermined amount.

The inserted invalid data may be an idle character, which does not affect the basic structure of the inter-frame space. Each time invalid data is inserted, only one invalid data can be inserted, that is, one invalid data is inserted within one local clock cycle. In this way, the effect of smoothly inserting invalid data can be achieved, avoiding the introduction of additional deviation when too many are inserted.

In addition, in the process of multiplying and compensating the invalid data of the inter-frame interval, the local clock needs to synchronize two clocks, and the synchronization method described in conjunction with FIG. 4 may also be used. Since the output data output from the buffer is multi-deducted and compensated in the process of reading data from the buffer, the output data output from the buffer is the received data after undergoing multi-deduction and supplement.

In the method shown in FIG. 4, based on the output data output from the buffer, the local clock is synchronized with the Ethernet clock.

In S410, frame synchronization is performed on the output data, the number of ether frames included in the output data is determined, and the first count value is obtained.

Since the Ethernet frame has a fixed frame header format, it is possible to determine how many Ethernet frames are included in the output data by performing frame synchronization on the output data. The initial value of the counter for recording the number of Ethernet frames is 0, and the counter is incremented by 1 every time it synchronizes to an Ethernet frame header. In this article, the count value recorded in the counter is called the first count value, and is represented by suml.

In S420, based on a local clock, the number of Ethernet frames is counted according to a predetermined time length between adjacent Ethernet frame headers to obtain a second count value.

Since the length of time between the headers of adjacent Ethernet frames can be preset, the local clock can be used as the criterion. When the predetermined time length expires, it is considered that an Ethernet frame has passed. For example, in the application scenario shown in FIG. 1, the predetermined time length between adjacent Ethernet frame headers is 260.4 ns, and every time the local clock reaches 260.4 ns, it is considered that an Ethernet frame has passed.

In the case where the number of ether frames is determined by timing a predetermined length of time, the initial value of the counter that records the number of ether frames is also 0, and whenever the local clock reaches the predetermined length of time, the count of the counter is increased 1. In this article, the count value recorded in the counter is called the second count value, and is represented by sum2.

In S430, based on the first count value and the second count value, the local clock is adjusted to be synchronized with the Ethernet clock.

According to an embodiment of the present invention, a fuzzy control algorithm may be used to determine the adjustment amount of the local clock, adjust the local clock frequency according to the adjustment amount, and gradually converge to synchronize the local clock with the Ethernet clock. The specific adjustment process can be combined with the description made with reference to FIG. 6. In the example of adjusting the local clock shown in FIG. 6, based on the first count value and the second count value, a fuzzy control algorithm is used to obtain a digital signal; the digital signal is converted into an analog signal and input into a phase-locked loop (Phase- Locked Loop (PLL) includes a constant temperature oscillator, wherein the phase locked loop generates a local clock based on a local crystal oscillator.

Next. First, the implementation block diagram of the method for synchronizing the local clock with the Ethernet clock will be described with reference to FIG. 5, and then the specific example in FIG. 6 will be used to describe how to adjust the local clock. In FIG. 5, the initial value of the first count value suml of counter 1 and the second count value of counter 2 sum2 are 0, and both start counting at the same time. For example, from the beginning of receiving the first ether frame, counter 1 and Counter 2 counts at the same time.

The output data Din output from the buffer after being deducted and inputted is input to the frame synchronization module. Frame synchronization is performed on the Ethernet frame in the frame synchronization module, and every synchronization to an Ethernet frame increases the first count value suml of counter 1 by 1.

The second count value sum2 of the counter 2 is driven by the local clock, and the second count value sum2 is incremented by 1 every time the predetermined time length between adjacent Ethernet frame headers is counted. For example, in the application scenario shown in FIG. 1, the counter 2 is driven by the local clock using the CPRI base frame period as a unit, and whenever the CPRI base frame period is counted up, the second count value sum2 is incremented by 1.

Compare suml and sum2, input the result of the comparison to the fuzzy control system, and adjust the frequency of the local clock through the output generated by the fuzzy control system. The fuzzy control system is a control system that adopts a fuzzy control algorithm. The larger the input, the greater the correction intensity, thereby achieving rapid convergence of the output. As described with reference to FIG. 5, the second count value sum2 is obtained by frame synchronizing the output data Din output from the buffer.

Calculate the difference between suml and sum2 with a fixed calculation time period to obtain Xn, where n represents the nth calculation time period. In addition, Xn is cached at two levels, and the relative difference between the counter difference in the current period and the counter difference in the previous period is calculated, that is, ΔΧ=Χη-Χη-ι. If the Ethernet clock is higher than the local clock, ΔΧ increases positively; if the Ethernet clock is lower than the local clock, ΔΧ increases negatively.

Within each calculation time period, ΔX and Xn are input into the fuzzy control system under the enable of the timer. The fuzzy control system performs table look-up calculation based on the values of Xn and ΔΧ, and obtains an adjustment value L for adjusting the local clock frequency. The adjustment value L is a digital signal. The adjustment value L can be obtained by looking up the fuzzy control table shown in Table 1.

<img file="WO2012106910A1_D0001.tif" /> -2&lt;X_n &lt;0 O.Olppm 0.00 lppm O.OOlppm 0 0

Xn = 0 0.00 lppm O.OOlppm 0 -O.OOlppm -O.OOlppm

0 &lt;Xn&lt;2 0 0 -O.OOlppm -O.OOlppm -O.Olppm

2 &lt;X_n 0 0 -O.Olppm -O.Olppm -O.Olppm If the obtained adjustment value L is 0, it means that the local clock and the Ethernet clock have the same frequency. If the adjustment value L is not 0, the digital signal needs to be sent to a digital-to-analog converter (DAC). The DAC converts the digital signal to an analog signal, and inputs the analog signal into a thermostatic oscillator (Oven Controlled Crystal Oscillator, OCXO) included in a phase-locked loop that generates a local clock based on a local crystal oscillator, so that the local clock generated by the phase-locked loop can be adjusted Frequency of.

According to the method for correcting clock jitter provided by an embodiment of the present invention, received data is input into the buffer according to the Ethernet clock, and the buffer is output according to the local clock synchronized with the Ethernet clock, using the relationship between the amount of data buffered in the buffer and the threshold , The inter-frame interval data in the received data is removed and inserted, so that the clock jitter introduced by Ethernet can be corrected, so that the output data output from the buffer has a smooth data flow form, thereby reducing the clock jitter introduced by Ethernet The impact on subsequent system processing can limit the clock jitter to an acceptable range for subsequent system processing. In addition, since the clock jitter in the output data output from the buffer can be removed, a smoother data stream can be obtained, which is beneficial to subsequent real-time processing of the data stream and reduces the storage space overhead required for subsequent processing. Block diagram of the implementation. In this specific example, it not only includes the stability adjustment part that corrects the clock jitter, but also includes the accuracy adjustment part that synchronizes the local clock with the Ethernet clock.

The specific example shown in FIG. 7 may be located in the clock jitter correction module at the receiving end in the application scenario shown in FIG. 1. In the example shown in FIG. 7, taking REC as the sending end and RE as the receiving end as an example, and REC and RE both use a clock source whose frequency stability is better than that required by the CPRI standard, that is, both REC and RE can use a highly stable clock .

The E may include a 10GE PHY unit, a PLL, an XAUI (10 Gigabit Attachment Unit Interface, 10 Gigabit Attachment Unit Interface) unit, a buffer, a local clock, a stability adjustment part, and an accuracy adjustment part.

The 10GE PHY unit is the physical layer interface of 10GE Ethernet. In addition to providing data signals, it also provides the clock signal recovered from the network card. The recovered clock signal is the Ethernet clock, and the clock is used as the clock reference for the XAUI unit to read data. And the write clock of the buffer.

The PLL is a hardware phase-locked loop. By referring to the local clock, the clock recovered from the 10GE PHY unit is adjusted to filter out high-frequency components in the recovered Ethernet clock.

The XAUI unit is an extension of XGMII (1 OGigabit Media Independent Interface, media-independent 10G interface) that works in the Ethernet model to connect the physical layer and the media access control layer. Here, XAUI requires both the clock signal from the PLL and the data signal from the 10GE PHY unit.

The buffer is used to isolate the Ethernet clock domain and the local clock domain, which can ensure that no overflow or underflow occurs when the received data traverses different clock domains. At the same time, the buffer can be used as a data access container during the multi-buckle and small-compensation operation, which is beneficial to the adjustment of frequency stability.

The frequency stability of the local clock itself is better than the index requirements. In both REC and RE, a highly stable clock can be used as the local clock to avoid introducing large clock jitter.

The operation of the stability adjustment part can refer to the description in conjunction with FIG. 3. When adjusting stability, that is, correcting clock jitter, if the amount of data buffered in the buffer exceeds the first threshold, the invalid data is deducted from the inter-frame interval; if the amount of data buffered in the buffer is lower than the second threshold, then Invalid data is inserted in the interframe space.

The accuracy adjustment part may include a counter counting module and a fuzzy control system, and the operation of the accuracy adjustment part may refer to the description in conjunction with FIGS. 5 and 6. When adjusting the accuracy, that is, synchronizing the local clock with the Ethernet clock, the first count value and the second count value can be obtained by two counters, the first count value is obtained by frame synchronization, and the second count value is The local clock is obtained. The fuzzy control algorithm is used to obtain the frequency adjustment signal for the two count values. The frequency adjustment signal is quantized into a digital signal and sent to the DAC (as shown in Figure 6). The analog signal output by the DAC is then input to the OCXO frequency adjustment of the PLL that generates the local clock. Port to adjust the local clock.

The stability adjustment part and the accuracy adjustment part alternately operate, that is, the local clock after the accuracy adjustment is used as the read clock of the buffer to continue to read and receive data from the buffer, and make more deductions during the reading process The clock jitter introduced by Ethernet is corrected, and the data with more deductions and less complements is used as input data for accuracy adjustment to continue to help the accuracy adjustment of the local clock.

In addition, the output data output from the buffer is sent to the subsequent processing system for processing. For example, in the application scenario of FIG. 1, the Ethernet frame output from the buffer has a stable inter-frame interval due to clock jitter correction, and after smoothing and other operations, a stable CPRI base frame can be obtained for subsequent processing. Since the subsequent processing on the Ethernet frame output by the buffer is the same as that in the prior art, for the sake of simplicity, it will not be repeated here.

Above, the method for correcting clock jitter according to an embodiment of the present invention has been described. Below, combined

8 and 9 describe an apparatus for correcting clock jitter according to an embodiment of the present invention.

FIG. 8 is a structural block diagram of an apparatus 800 for correcting clock jitter according to an embodiment of the present invention. The device 800 includes a clock recovery module 810, a buffer 820, a local clock 830, and a jitter correction module 840. The device 800 may be located in the receiving end device. The device 800 receives data from the Ethernet and sends the Ethernet frame output from the buffer to a subsequent processing module such as decapsulation. The clock recovery module 810 may be a network card, and may recover the clock from the received data. The jitter correction module 840 may be a processor, which performs multi-deduction and small-compensation operations on the output data of the buffer.

The clock recovery module 810 can be used to recover the Ethernet clock from the received data, and the received data includes the inter-frame space between the Ethernet frame and the adjacent Ethernet frame. The buffer 820 may be used to buffer received data input according to the Ethernet clock. The local clock 830 may be used to provide a clock frequency for reading received data from the buffer 820. The jitter correction module 840 may be used to read the received data from the buffer 820 according to the local clock, if the data amount of the received data buffered in the buffer 820 exceeds the first threshold, the first predetermined amount is deducted from the inter-frame interval Invalid data or, if the amount of received data buffered in the buffer 820 is lower than the second threshold, insert a second predetermined amount of invalid data in the inter-frame interval to obtain output data output from the buffer 820, where The local clock is synchronized with the Ethernet clock.

For the above and other operations and/or functions of the clock recovery module 810, the buffer 820, the local clock 830, and the jitter correction module 840, reference may be made to the corresponding description in the method of FIG. 2 described above. In order to avoid repetition, details are not described herein.

According to the device for correcting clock jitter provided by an embodiment of the present invention, by inputting received data into the buffer according to the Ethernet clock and outputting the buffer according to the local clock synchronized with the Ethernet clock, the buffer in the buffer can be used The relationship between the amount of data and the threshold removes and inserts the inter-frame interval data in the received data, so that the clock jitter introduced by Ethernet can be corrected, so that the output data output from the buffer has a smooth data flow form, which can be reduced The impact of clock jitter introduced by Ethernet on subsequent system processing can limit clock jitter to an acceptable range for subsequent system processing.

9 is a structural block diagram of an apparatus 900 for correcting clock jitter according to an embodiment of the present invention. The clock recovery module 910, the buffer 920, the local clock 930, and the jitter correction module 940 of the device 900 are substantially the same as the clock recovery module 810, the buffer 820, the local clock 830, and the jitter correction module 840 of the device 800.

According to an embodiment of the present invention, the apparatus 900 may further include a synchronization module 950. The synchronization module 950 may be used to synchronize the local clock with the Ethernet clock based on the output data.

For example, the synchronization module 950 may include a first counter unit 952, a second counter unit 954, and an adjustment unit 956. The first counter unit 952 may be used to perform frame synchronization on the output data, determine the number of ether frames included in the output data, and obtain a first count value. The second counter unit 952 may be used to count the number of Ethernet frames according to a predetermined time length between adjacent Ethernet frame headers based on a local clock to obtain a second count value. The adjusting unit 956 may be used to adjust the local clock based on the first count value and the second count value to synchronize with the Ethernet clock.

According to an embodiment of the present invention, the adjustment unit 956 may include a calculation subunit 956-1, a digital-to-analog converter 956-2, and a phase locked loop 956-3. The calculation subunit 956-1 may be used to obtain a digital signal based on the first count value and the second count value using a fuzzy control algorithm. The digital-to-analog converter 956-2 can be used to convert a digital signal to an analog signal, and input the analog signal to the constant temperature oscillator included in the phase locked loop. Phase-locked loop 956-3 can be used to generate a local clock based on a local crystal oscillator.

According to an embodiment of the present invention, the local clock 930 may be a high-stability clock.

According to an embodiment of the present invention, the first threshold may be the sum of the fixed value and the predetermined number of samples included in the Ethernet frame, and the second threshold may be the difference between the fixed value and the predetermined number of samples included in the Ethernet frame.

According to an embodiment of the present invention, the first predetermined number is one and the second predetermined number is one. The above and other operations and/or functions of the first counter unit 952, the second counter unit 954, the adjustment unit 956, the calculation sub-unit 955-1, the digital-to-analog converter 956-2, and the phase locked loop 956-3 can be referred to the above figures The corresponding descriptions in 2 to 6 are not repeated here in order to avoid repetition.

According to the device for correcting clock jitter provided by the embodiment of the present invention, by multiplying and subtracting the invalid data of the inter-frame interval, the clock jitter introduced by Ethernet can be effectively corrected, so that a more stable data flow can be obtained, which is beneficial to Subsequent real-time processing of data streams reduces the storage space overhead required for subsequent processing.

Those skilled in the art may realize that the method steps and units described in the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the mutual interaction between hardware and software Alternately, in the above description, the steps and composition of each embodiment have been generally described in terms of function. Whether these functions are performed in hardware or software depends on the specific application of the technical solution and design constraints. A person skilled in the art may use different methods for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of the present invention.

The method steps described in conjunction with the embodiments disclosed herein may be implemented by hardware, a software program executed by a processor, or a combination of both. Software programs can be placed in random access memory

(RAM). Memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM or any other form of storage medium known in the technical field in.

Although some embodiments of the present invention have been shown and described, those skilled in the art should understand that various modifications can be made to these embodiments without departing from the principle and spirit of the present invention, and such modifications should fall It is within the scope of the present invention.