Debug signaling in a multiple processor data processing system

A system includes a first processor (12), a second processor (14), a first clock (54) coupled to the first processor, and a third clock (56) coupled to the first processor and to the second processor. The first processor includes debug circuitry (58) coupled to receive the third clock, synchronization circuitry (48, 43) coupled to receive the first clock, wherein the synchronization circuitry receives a first request to enter a debug mode and provides a first synced debug entry request signal (51 or 25) and wherein the first synced debug entry request signal is synchronized with respect to the first clock, and an input for receiving a second synced debug entry request signal (27) from the second processor wherein the first processor waits to enter the debug mode until the first synced debug entry request signal and the second synced debug entry request signal are both asserted.