Pre-fetching and caching data in a communication processor's register set

Circuitry (100) to free the core processor (104) from performing the explicit read operation required to read data into the internal register set. The processor's register set (603B) is expanded and a "shadow register" set (603C) is provided. While the core processor (104) is processing one event the "context" and "data" and other associated information for the next event is loaded into the shadow register set (603C). When the core processor (104) finishes processing an event, the core processor (104) switches to the shadow register set (603C) and it can begin processing the next event immediately. With short service routines, there might not be time to fully pre-fetch the "context" and "data" associated with the next event before the current event ends. In this case, the core processor (104) still starts processing the next event and the pre-fetch continues during the event processing.