Nova Patents
WO0035102A1

Interleaving / deinterleaving device and method for communication system

Abstract

A device for sequentially storing input bit symbols of a given interleaver size N in a memory at an address from 1 to N and reading the stored bit symbols from the memory. The device comprises a look-up table for providing a first variable m and a second variable J satisfying the equation N=2<m>xJ; and an address generator for generating a read address depending on the first and second variables m and J provided from the look-up table. The read address is determined by 2<m>(K mod J) + BRO(K/J), where K (0</=K</=(N-1)) denotes a reading sequence and BRO is a function for converting a binary value to a decimal value by bit reversing.

WO0035102A1, drawing sheet 1
Sheet 1 of 6

Term

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10 claims: 6 independent, 4 dependent

  1. 1
    CLAIMS:1. A method for sequentially storing N input bit symbols in a memory at an address from 1 to N and for reading the stored bit symbols from the memory, comprising the steps of: providing a first variable m and a second variable J satisfying the equation N=2 m xJ;and reading a Kth (0<K≤(N-1)) bit symbol at an address determined by 2 m (K mod J) + BRO(K/J) where BRO is a function for converting a binary value to a decimal value by bit reversing.
  2. 4
    A method for sequentially storing input bit symbols of a given interleaver size N in a memory at an address from 1 to N and reading the stored bit symbols from the memory, wherein a bit symbol is read at an address determined by the equation 2 m x r + s, wherein when the interleaver size N is expressed as a binary value, an integer equal to or smaller than the number of consecutive zero bits from the LSB is defined as a first variable m, a decimal value determined by converting a binary value corresponding to the truncated bits other than the consecutive zero bits is defined as a second variable J, a decimal value determined by expressing a quotient obtained by dividing a reading sequence K (0<K<(N-1)) by the second variable J as a binary value, bit reversing said binary value and converting the bit-reversed binary value to said decimal value is defined as a fourth variable s, and a remainder determined by dividing the reading sequence K by the second variable J is defined as a third variable r.
  3. 5
    A method for sequentially storing input bit symbols of a given interleaver size N in a memory at an address from 1 to N and reading the stored bit symbols from the memory, comprising the steps of:defining, when N is expressed as a binary value, the number of consecutive zero bits from the LSB as a first variable m, and converting a binary value corresponding to the truncated bits other than the consecutive zero bits to a decimal value to define a second variable J;calculating a third variable r corresponding to a remainder obtained by dividing a reading sequence K by the second variable J;expressing a quotient obtained by dividing the reading sequence K by the second variable J as a binary value, bit-reversing said binary value and converting the bit-reversed binary value to a decimal value, so as to defined said decimal value as a fourth variable s;and reading a bit symbol at an address determined by 2 m x r + s.
  4. 6
    A device for sequentially storing input bit symbols of a given interleaver size N in a memory at an address from 1 to N and reading a bit symbol stored at an address R from the memory, comprising:a look-up table for providing a first variable m and a second variable J satisfying the equation N=2 m xJ;and an address generator for generating a read address depending on the first and second variables m and J provided from the look-up table, the read address being determined by 2 m (K mod J) + BRO(K/J) where K (0<K<(N-1)) denotes a reading sequence, and BRO is a function for converting a binary value to a decimal value by bit reversing.
  5. 9
    A device for sequentially storing input bit symbols of a given interleaver size N in a memory at an address from 1 to N and reading the bit symbols from the memory, comprising:a look-up table for providing a first variable m and a second variable J, wherein when N is expressed as a binary value, the first variable m indicates the number of consecutive zero bits from the LSB and the second variable J indicates a decimal value corresponding to the truncated bits other than consecutive zero bits an address generator for generating a read address determined by 2 m xr+s, where s is a decimal value determined by expressing a quotient obtained by dividing a reading sequence K (0<K≤(N-1)) by the second variable J as a binary value, bit reversing said binary value and converting the bit-reversed binary value to said decimal value, and r is a remainder determined by dividing the reading sequence K by the second variable J.
  6. 10
    A device for sequentially storing input bit symbols of a given interleaver size N in a memory at an address from 1 to N and reading the bit symbols from the memory, comprising:a look-up table for providing a first variable m and a second variable J, wherein when N is expressed as a binary value, the first variable m indicates the number of consecutive zero bits from the LSB and the second variable J indicates a decimal value corresponding to the truncated bits other than consecutive zero bits from the LSB;and an address generator for generating a read address depending on the first and second variables m and J provided from the look-up table, the read address being determined by 2 m (K mod J) + BRO(K/J) where K (0<K≤(N-1)) denotes a reading sequence, and BRO is a function for converting a binary value to a decimal value by bit reversing.
Independent claims6