On-chip reliability monitor and method

BACKGROUND

Field of the Invention

0001The present invention relates to device reliability and, more particularly, to an on-chip reliability monitor and method.

Description of Related Art

0002Various mechanisms (e.g., hot carrier injection, time-dependent dielectric breakdown, negative-bias temperature instability (NBTI), positive-bias temperature instability (PBTI), etc.) associated with different classes of devices incorporated into integrated circuit (IC) chips can cause chip performance to degrade over time as a result of stress conditions (e.g., high temperatures and/or voltages). Typically, in order to predict how IC chips in a given semiconductor technology will perform over time and in response to high stress conditions, all devices available in that given semiconductor technology are subjected to accelerated voltage and/or temperature stress tests in a laboratory environment at the wafer or module levels and/or in a test system environment. Then, based on the results of the accelerated stress testing, performance degradation models and end of life (EOL) predictions are generated. Typically, in order to monitor an IC chip's reliability, a power-on hours (POH) monitor is used to track the amount of time the chip is powered-on and the number of POHs is compared to the end of life predictions. Unfortunately, the environmental assumptions associated with the selected sample of products used for making performance degradation models and end of life predictions may be different than the actual environmental conditions in other products. For example, the operating temperature, operating voltage, power-on-hours (POH), etc. of IC chips may vary from product to product. Thus, the resulting performance degradation models and EOL predictions may not be applicable across all products. In this case, tracking POHs alone may result in chip failures before the predicted EOL (as measured in POHs) or, alternatively, may result in chips being scrapped too early.

SUMMARY

0003In view of the foregoing, disclosed herein are an on-chip reliability monitor and reliability monitoring method. The reliability monitor can include a test circuit with a test device, a reference circuit with a reference device and a comparator circuit connected to the test circuit and the reference circuit. The reliability monitor can be alternatingly operable in stress and test modes and, specifically, can periodically switch from operation in the stress mode to operation in the test mode and back again. During each stress mode, the test device can be subjected to stress conditions that emulate the operating conditions of an on-chip functional device while the reference device remains essentially unstressed. During each test mode, the stress conditions can be removed from the test device and the comparator circuit can compare a parameter of the test device to the same parameter of the reference device and can output a status signal based on the difference between the parameters. Specifically, the comparator circuit can switch the status signal from one value to another when the difference between the parameters reaches a predetermined threshold amount and can ensure that the status signal remains constant once switched. It should be noted that, when the parameter at issue is known to change at a relatively high rate in response to applied stress at the beginning of life and to change at a relatively low rate in response to applied stress towards the end of life and when a small delta in that parameter is difficult to detect, multiple reliability monitors can be cascaded together in order to more accurately monitor stress-induced changes near the end of life, as described in greater detail below.

0004More particularly, disclosed herein is an embodiment of an integrated circuit (IC) chip that includes a substrate and a reliability monitor on the substrate. The reliability monitor can include a test circuit with a test device and a reference circuit with a reference device. Both the test device and the reference device can be essentially identical to an on-chip functional device. The reliability monitor can further include a comparator circuit that is connected to both the test circuit and the reference circuit. The reliability monitor can be alternatingly operable in stress and test modes (e.g., can periodically switch from operation in a stress mode to operation in a test mode and back), when the IC chip is powered on. During each stress mode, the test device can be subjected to stress conditions that emulate the operating conditions of the on-chip functional device while the reference device remains essentially unstressed. During each test mode, the stress conditions can be removed from the test device and the comparator circuit can compare a specific parameter (referred to as a test parameter) of the test device to the same parameter (referred to as a reference parameter) of the reference device and can output a status signal based on the difference between the test parameter and the reference parameter. Specifically, the comparator circuit can switch the status signal from one value to another (e.g., from low to high, logic value ‘0’ to ‘1’) when the difference between the test parameter and the reference parameter reaches a predetermined threshold amount and can further ensure that the status signal remains constant once switched. This switch in the value of the status signal will be indicative of the on-chip functional device being powered on for some predetermined number of hours (e.g., for X power-on hours (POHs)).

0005Also disclosed herein is another embodiment of an integrated circuit (IC) chip that includes a substrate and multiple cascaded reliability monitors on the substrate. Specifically, oftentimes a parameter at issue is known to change at a relatively high rate in response to applied stress at the beginning of life and to change at a relatively low rate in response to applied stress towards the end of life. Furthermore, a small delta in that parameter may be difficult to detect. In this case, multiple essentially identical reliability monitors can be cascaded together in order to more accurately monitor stress-induced changes particularly near the end of life.

0006Each reliability monitor can include a test circuit with a test device and a reference circuit with a reference device. Both the test device and the reference device can be essentially identical to an on-chip functional device. Each reliability monitor can further include a comparator circuit that is connected to both the test circuit and the reference circuit. Each reliability monitor can be alternatingly operable in stress and test modes when the IC chip is powered on and that particular reliability monitor is enabled. Specifically, once enabled, a reliability monitor can periodically switch from operation in the stress mode to operation in the test mode and back again. During each stress mode, the test device can be subjected to stress conditions that emulate the operating conditions of the on-chip functional device while the reference device remains essentially unstressed. During each test mode, the stress conditions can be removed from the test device and the comparator circuit can compare a specific parameter (referred to as a test parameter) of the test device to the same parameter (referred to as a reference parameter) of the reference device and can output a status signal based on the difference between the test parameter and the reference parameter. Specifically, the comparator circuit can switch the status signal from one value to another (e.g., from low to high, from logic value ‘0’ to ‘1’) when the difference between the test parameter and the reference parameter reaches a predetermined threshold amount and can further ensure that the status signal remains constant once switched.

0007The multiple cascaded reliability monitors can include at least a first reliability monitor, which is enabled by an enable signal, and a second reliability monitor, which is coupled to the first reliability monitor and which is only enabled when the status signal output from the first reliability monitor switches values.

0008Also disclosed herein is a reliability monitoring method for a functional device on an integrated circuit (IC) chip and, thereby for the IC chip. The method can include providing an IC chip that includes, on a substrate, a functional device and one or more reliability monitors for the functional device, as discussed above with regard to the structure embodiments.

0009The method can further include powering on the IC chip and, after powering on the IC chip, enabling a reliability monitor so that the reliability monitor alternatingly operates in stress and test modes (e.g., so that the reliability monitor periodically switches from operation in a stress mode to operation in a test mode and back, when the IC chip is powered on). Operating the reliability monitor in the stress mode includes subjecting the test device to stress conditions that emulate the operating conditions of the on-chip functional device and leaving the reference device unstressed. Operating the reliability monitor in the test mode includes removing the stress conditions from the test device, comparing a test parameter of the test device to a reference parameter of the reference device, and outputting a status signal based on a difference between the test parameter and the reference parameter. Specifically, a value of the status signal can be switched (e.g., from low to high, from logic value ‘0’ to ‘1’) when the difference between the test parameter and the reference parameter reaches a predetermined threshold amount. The method can further include ensuring that the status signal remains constant, once switched. This switch in the value of the status signal will be indicative of the on-chip functional device being powered on for some predetermined number of hours (e.g., for X power-on hours (POHs)).

0010Optionally, the IC chip can include, not just a single reliability monitor, but rather multiple cascaded reliability monitors that are essentially identical (e.g., at least a first reliability monitor and a second reliability monitor coupled to the first reliability monitor). In this case, the method can include using an enable signal to enable the first reliability monitor such that the first reliability monitor alternatingly operates in the stress and test modes. Then, when a status signal output from the first reliability monitor switches values, using the status signal from the first reliability monitor to enable the second reliability monitor so that the second reliability monitor alternatingly operates in the stress and test modes.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The present invention will be better understood from the following detailed description with reference to the drawings, which are not necessarily drawn to scale and in which:

<figref idref="DRAWINGS">FIG. <b>1</b></figref> is a block diagram illustrating embodiments of an integrated circuit (IC) chip with on-chip reliability monitor(s);

<figref idref="DRAWINGS">FIG. <b>2</b></figref> is a graph showing threshold voltage shifts over time for two different field effect transistors (FETs) having different gate oxide thicknesses;

<figref idref="DRAWINGS">FIG. <b>3</b>A</figref> is a schematic diagram illustrating an exemplary reliability monitor and includes sub-diagrams of an exemplary test circuit, an exemplary reference circuit and an exemplary comparator circuit that can be incorporated into the reliability monitor;

<figref idref="DRAWINGS">FIG. <b>3</b>B</figref> is a sub-diagram detailing an exemplary status latch that can be incorporated into the comparator circuit of <figref idref="DRAWINGS">FIG. <b>3</b>A</figref>;

<figref idref="DRAWINGS">FIG. <b>4</b></figref> is a timing diagram for the reliability monitor shown in <figref idref="DRAWINGS">FIGS. <b>3</b>A-<b>3</b>B</figref>;

<figref idref="DRAWINGS">FIG. <b>5</b></figref> is a schematic diagram illustrating an alternative test circuit that can be incorporated into the reliability monitor of <figref idref="DRAWINGS">FIG. <b>3</b>A</figref>;

<figref idref="DRAWINGS">FIG. <b>6</b></figref> is schematic diagram illustrating multiple cascaded reliability monitors;

<figref idref="DRAWINGS">FIG. <b>7</b></figref> is a graph with discrete curves illustrating exemplary threshold voltage shifts exhibited by test device in each of multiple cascaded reliability monitors; and

<figref idref="DRAWINGS">FIG. <b>8</b></figref> is a flow diagram illustrating a reliability monitoring method.

DETAILED DESCRIPTION

0021As mentioned above, various mechanisms (e.g., hot carrier injection, time-dependent dielectric breakdown, negative-bias temperature instability (NBTI), positive-bias temperature instability (PBTI), etc.) associated with different classes of devices incorporated into integrated circuit (IC) chips can cause chip performance to degrade over time as a result of stress conditions (e.g., high temperatures and/or voltages). Typically, in order to predict how IC chips in a given semiconductor technology will perform over time and in response to high stress conditions, all devices available in that given semiconductor technology are subjected to accelerated voltage and/or temperature stress tests in a laboratory environment at the wafer or module levels and/or in a test system environment. Then, based on the results of the accelerated stress testing, performance degradation models and end of life (EOL) predictions are generated. Typically, in order to monitor an IC chip's reliability, a power-on hours (POH) monitor is used to track the amount of time the chip is powered-on and the number of POHs is compared to the end of life predictions. Unfortunately, the environmental assumptions associated with the selected sample of products used for making performance degradation models and end of life predictions may be different than the actual environmental conditions in other products. For example, the operating temperature, operating voltage, power-on-hours (POH), etc. of IC chips may vary from product to product. Thus, the resulting performance degradation models and EOL predictions may not be applicable across all products. In this case, tracking POHs alone may result in chip failures before the predicted EOL (as measured in POHs) or, alternatively, may result in chips being scrapped too early.

0022In view of the foregoing, disclosed herein are an on-chip reliability monitor and reliability monitoring method. The reliability monitor can include a test circuit with a test device, a reference circuit with a reference device and a comparator circuit connected to the test circuit and the reference circuit. The reliability monitor can be alternatingly operable in stress and test modes and, specifically, can periodically switch from operation in the stress mode to operation in the test mode and back again. During each stress mode, the test device can be subjected to stress conditions that emulate the operating conditions of an on-chip functional device while the reference device remains essentially unstressed. During each test mode, the stress conditions can be removed from the test device and the comparator circuit can compare a parameter of the test device to the same parameter of the reference device and can output a status signal based on the difference between the parameters. Specifically, the comparator circuit can switch the status signal from one value to another when the difference between the parameters reaches a predetermined threshold amount and can ensure that the status signal remains constant once switched. It should be noted that, when the parameter at issue is known to change at a relatively high rate in response to applied stress at the beginning of life and to change at a relatively low rate in response to applied stress towards the end of life and when a small delta in that parameter is difficult to detect, multiple reliability monitors can be cascaded together in order to more accurately monitor stress-induced changes near the end of life, as described in greater detail below.

0023<figref idref="DRAWINGS">FIG. <b>1</b></figref> is a block diagram illustrating embodiments of an integrated circuit (IC) chip <b>100</b>. The IC chip <b>100</b> can include a substrate <b>101</b> and a functional circuit <b>110</b> on the substrate <b>101</b>. The functional circuit <b>110</b> can be, for example, a circuit required for operation of a product (e.g., a memory circuit, processing circuit, etc.). In any case, this functional circuit <b>110</b> can include, for example, at least one functional device <b>111</b> and, optionally, more than one functional device (e.g., see functional devices <b>111</b>_1-n). The functional devices <b>111</b>_1-ncan be active devices, such as field effect transistors (FETs) or any other type of active semiconductor device.

0024The IC chip <b>100</b> can further include, on the same substrate <b>101</b>, at least one reliability monitor <b>150</b> and, optionally, more than one reliability monitor (e.g., see reliability monitors <b>150</b>_1-n) for the given on-chip functional device <b>111</b> and, thereby for the functional circuit <b>110</b> itself. Such a reliability monitor <b>150</b> can include a test circuit <b>120</b> with a test device <b>121</b>, a reference circuit <b>130</b> with a reference device <b>131</b>, and a comparator circuit <b>140</b> coupled to the test circuit <b>120</b> and to the reference circuit <b>130</b>. The reliability monitor <b>150</b> can further be configured to impart stress on the test device <b>121</b> such that the test device <b>121</b> and the given on-chip functional device <b>111</b> are concurrently subjected to essentially the same stress conditions (e.g., temperature and/or voltage bias conditions) over time and, thus, such that the test device <b>121</b> and the given on-chip functional device <b>111</b> are susceptible to the same failure mechanism (e.g., hot electron injection, time-dependent dielectric breakdown, etc.). The reliability monitor <b>150</b> can also be configured to output a status signal <b>152</b> (e.g., a flag) to indicate whether or not a performance parameter (e.g., a saturation drain current, a threshold voltage, etc.) of the test device <b>121</b> has degraded by some predetermined threshold amount due to the failure mechanism.

0025For example, a reliability monitor <b>150</b> can be configured to output a status signal <b>152</b> that indicates when the saturation drain current of the test device <b>121</b> has decreased by some predetermined threshold amount and/or when the threshold voltage of the test device <b>121</b> has increased by some predetermined threshold voltage amount. Those skilled in the art will recognize that the threshold voltage and saturation drain current are inversely related. That is, saturation drain current will typically decrease when the threshold voltage increases.

0026Specifically, a reliability monitor <b>150</b> can be configured so that, when the IC chip <b>100</b> is powered on and the reliability monitor <b>150</b> is enabled by an enable signal, it alternatingly operates in stress and test modes and, particularly, so that it periodically switches from operation in a stress mode to operation in a test mode and back again. During each stress mode, the test device <b>121</b> can be subjected to specific stress conditions that emulate the operating conditions of the on-chip functional device <b>111</b>, thereby making the test device <b>121</b> susceptible to the same failure mechanism(s) as the on-chip functional device <b>111</b>. During this stress mode, the reference device <b>131</b> remains essentially unstressed. During each test mode, the stress conditions can be removed from the test device <b>121</b> and the comparator circuit <b>140</b> can compare a specific performance parameter (referred to as a test parameter, such as saturation drain current or threshold voltage) of the test device <b>121</b> to the same performance parameter (referred to as a reference parameter) of the reference device <b>131</b> and can output a status signal <b>152</b> based on the difference between the test parameter and the reference parameter. That is, the comparator circuit <b>140</b> can switch the status signal <b>152</b> from one value to another (e.g., from low to high, from logic value ‘0’ to ‘1’) when the difference between the test parameter and the reference parameter reaches a predetermined threshold amount. The comparator circuit <b>140</b> can further be configured to ensure that the status signal <b>152</b> remains constant once switched and to ensure that, when the IC chip <b>100</b> is powered off and back on again, the status signal <b>152</b> will be automatically reset to its last held value. Thus, when the IC chip <b>100</b> is powered off and then back on, the status signal <b>152</b> of an enabled reliability monitor <b>150</b> will be reset to low (i.e., to a logic value ‘0’) if it was low when the IC chip <b>100</b> was powered off and will be reset to high (i.e., to a logic value ‘1’) if it was high when the IC chip <b>100</b> was powered off.

0027The IC chip <b>100</b> also includes a timing circuit <b>160</b>, which receives a primary clock signal <b>161</b> (CLKP) and which outputs multiple additional clock signals (e.g., clock signal <b>162</b> (STRESSN) and clock signal <b>163</b> (SETP)). The clock signals <b>161</b>-<b>163</b> are received by the reliability monitor <b>150</b> and, in conjunction with several internally generated signals (e.g., clock signal <b>164</b> (STRESSP), clock signal <b>165</b> (SENSEP), clock signal <b>166</b> (SENSEN), latch signal <b>167</b> (SENSEP_D) and latch signal <b>168</b> (LATCHP_D)) control the timing of the various components of the reliability monitor <b>150</b>, as discussed in greater detail below, so that the reliability periodically switches to the test mode, so that the duration of the test mode is sufficient to allow for capture of the status of the test device <b>121</b> (i.e., to compare the specific performance parameter of the test device <b>121</b> and the reference device <b>131</b>) and so that the reliability monitor otherwise operates in the stress mode.

0028Additionally, it should be noted that, based on empirical data and/or simulation data, the predetermined threshold amount of degradation can be some threshold amount known or expected to occur over the course of a given number of power-on-hours (POHs) starting at the beginning of life (BOL) of the device. Thus, the switch in the value of the status signal <b>152</b> will be indicative of the on-chip functional device being powered on for that given number of hours (e.g., for X power-on hours (POHs)).

0029For example, the predetermined threshold amount of degradation, which triggers switching of the value of the status signal <b>152</b> from low to high, can be that amount of degradation expected to be exhibited by the on-chip functional device <b>111</b> upon reaching the number of POHs specified in end of life (EOL) predictions. In this case, only a single reliability monitor <b>150</b> would be needed on the IC chip <b>100</b> and the status signal <b>152</b> (i.e., the flag) would indicate whether or not the predicted EOL has been reached and, thus, whether or not the functional circuit <b>110</b> should be considered reliable.

0030Oftentimes, however, the performance parameter at issue (e.g., saturation drain current, threshold voltage, etc.) will change at a relatively high rate in response to applied stress at the BOL, but will change at a relatively low rate in response to the same applied stress towards EOL. Furthermore, the small delta in the performance parameter towards EOL may be difficult to detect. For example, <figref idref="DRAWINGS">FIG. <b>2</b></figref> is a graph showing threshold voltage shifts over time for two different field effect transistors (FETs), one with a first gate oxide thicknesses (e.g., 16 nm) and and the other with a second gate oxide thickness (e.g., 200 nm), that are subjected to the same operating conditions from BOL to EOL (e.g., 100° C. and 0.95 Vgs). As illustrated, both of these FETs exhibit a large increase in threshold voltage due to some failure mechanism (e.g., due to negative bias temperature instability (NBTI)) in the first 20,000 POHs, but the rate of change significantly decreases over time. Those skilled in the art will recognize that threshold voltage shifts are typically inversely related to saturation drain current shifts.

0031In this case (i.e., when EOL parameter shifts are small and difficult to detect), multiple essentially identical reliability monitors <b>150</b>_1-ncan be cascaded together in order to more accurately monitor stress-induced changes particularly near EOL. The cascaded reliability monitors can include, for example, first reliability monitor <b>150</b>₁that is enabled by an initial enable signal <b>151</b> and monitors the given on-chip functional device <b>111</b> during the initial X POHs of the IC chip <b>100</b>, with a second reliability monitor <b>150</b>₂that is enabled by the status signal <b>1521</b> only after the initial X POHs has been reached and that monitors the given on-chip functional device <b>111</b> for the next X POHs of the IC chip <b>100</b>, and so on. With this configuration, the first reliability monitor <b>150</b>₁in the cascade of reliability monitors <b>150</b>_1-nwill monitor the performance parameter of a corresponding test device during the initial X POHs of the IC chip <b>100</b>, when a relatively large change will occur in performance parameter of the on-chip functional device <b>111</b>; whereas the last reliability monitor <b>150</b>_nin the cascade of reliability monitors <b>150</b>_1-nwill monitor the performance parameter of another test device in the last X POHs of the IC chip <b>100</b>, when only a relatively small change will occur in the performance parameter of the on-chip functional device <b>111</b>. However, since the test device <b>121</b> in the last reliability monitor <b>150</b>_nis only subjected to the stress conditions during the last X POHs of the IC chip <b>100</b>, it will exhibit a relatively large change in the performance parameter. This relatively large change in the performance parameter of the test device <b>121</b> of the last reliability monitor <b>150</b>, can be readily detected and will occur concurrently with a relatively small change in the performance parameter of the on-chip functional device <b>111</b> near its EOL. Thus, only when the status signal <b>152</b>_n(i.e., the flag) of the last reliability monitor <b>150</b>, of the multiple cascaded reliability monitors <b>150</b>_1-nswitches values (e.g., from low to high, from logic value ‘0’ to ‘1’) will the functional circuit <b>110</b> be deemed no longer reliable and the IC chip <b>100</b> be deemed to have reached the EOL.

0032<figref idref="DRAWINGS">FIG. <b>3</b>A</figref> is a schematic diagram illustrating an exemplary reliability monitor <b>150</b> and includes sub-diagrams of an exemplary test circuit <b>120</b>, an exemplary reference circuit <b>130</b> and an exemplary comparator circuit <b>140</b> that can be incorporated into the reliability monitor <b>150</b>. <figref idref="DRAWINGS">FIG. <b>3</b>B</figref> is a sub-diagram detailing an exemplary status latch <b>143</b> that can be incorporated into the comparator circuit <b>140</b> of <figref idref="DRAWINGS">FIG. <b>3</b>A</figref>. <figref idref="DRAWINGS">FIGS. <b>3</b>A and <b>3</b>B</figref> also identify various signals that can be used to control the test circuit <b>120</b>, reference circuit <b>130</b> and comparator circuit <b>140</b>.

0033For purpose of illustration, the given on-chip functional device <b>111</b> to be monitored by this reliability monitor <b>150</b> can be an N-type field effect transistor (NFET) (e.g., a current source). During IC chip operations, this NFET can be subjected to specific stress conditions (e.g., specific temperature and/or voltage bias conditions) and these specific stress conditions can make the functional device susceptible to a particular failure mechanism, namely, hot electron injection-induced saturation drain current degradation.

0034The exemplary test circuit <b>120</b> includes a test device <b>121</b>, which is an NFET that is essentially identical to the functional device to be monitored. Furthermore, the exemplary test circuit <b>120</b> can be configured to impart specific stress conditions on the test device <b>121</b> over time and specifically when the reliability monitor <b>150</b> is enabled and operating in the stress mode. These stress conditions can be essentially the same as those concurrently encountered by the functional device <b>111</b> such that the test device <b>121</b> is similarly susceptible to hot electron injection-induced saturation drain current degradation. The test circuit <b>120</b> can further be configured to remove the stress conditions, when the reliability monitor <b>150</b> periodically switches operation to the test mode so as to allow the test device <b>121</b> to be tested. Specifically, the exemplary test circuit <b>120</b> can further include a plurality of P-type field effect transistors (PFETs) <b>301</b>-<b>304</b>; an analog voltage multiplexor <b>305</b>; and an inverter <b>306</b>. The source of the test device <b>121</b> can be electrically connected to ground and the drain of the test device <b>121</b> can be electrically connected to the drains of a first PFET <b>301</b> and a second PFET <b>302</b> (also referred to herein as a pass gate device). Additionally, the source of the second PFET <b>302</b> can be electrically connected to the drain of a third PFET <b>303</b> (also referred to herein as a pre-charge device) and to the drain of a fourth PFET <b>304</b>. The sources of the first PFET <b>301</b>, the third PFET <b>303</b> and the fourth PFET <b>304</b> can be electrically connected to a first supply voltage (e.g., VDD). The gate of the test device <b>121</b> can be selectively connected to a second supply voltage (stress voltage (VSTRESS)) or to a third supply voltage (read voltage (VREAD)) by the multiplexer <b>305</b>. It should be noted that VSTRESS can be sufficiently high to place the test device <b>121</b> in the high stress or overdrive condition during the stress mode (e.g., to 0.55V), whereas the VREAD can be lower than the VSTRESS so that the high stress conditions are removed from the test device <b>121</b> during the test mode. The gates of the first PFET <b>301</b> and the third PFET <b>303</b> can be controlled by the STRESSN clock signal <b>162</b>, which is output from the timing circuit <b>160</b>. The inverter <b>306</b> can receive and invert the STRESSN clock signal <b>162</b>, outputting an inverted clock signal <b>164</b> (STRESSP) that controls the gate of the second PFET <b>302</b>.

0035The timing circuit <b>160</b> can be configured so that the STRESSN clock signal <b>162</b> generally has a low value that causes the reliability monitor <b>150</b> to operate in the stress mode and further so that periodically (i.e., at some desired interval) it switches to a high value and stays high only for some relatively short duration sufficient to allow for the capture of the status of the test device <b>121</b> (i.e., to compare the specific performance parameter of the test device <b>121</b> and the reference device <b>131</b>). Since the STRESSP clock signal <b>164</b> is inverted as compared to the STRESSN clock signal <b>162</b>, during the stress mode, the STRESSP clock signal <b>164</b> will be high and the STRESSN clock signal <b>162</b> will be low; whereas, during the test mode, the STRESSP clock signal <b>164</b> will be low and the STRESSN clock signal <b>162</b> will be high.

0036Within the test circuit <b>120</b>, timing of the multiplexor <b>305</b> and the third PFET <b>303</b> (the pre-charge device) can be such that, during the stress mode, the test node <b>307</b> (DUTI) of the test circuit <b>120</b> at the drains of the third PFET <b>303</b> and fourth PFET <b>304</b> and at the source of the second PFET <b>302</b> can be held at the first supply voltage (VDD) and the test device <b>121</b> can be biased with VSTRESS (e.g., 0.55V) on its gate and about 0.8V drain to source in order to mimic the bias conditions of the on-chip functional device <b>111</b>. During the test mode, the aforementioned high stress condition can be shut off and, specifically, the third PFET <b>303</b> (i.e., the pre-charge device) can be shut off, VREAD can be applied to the gate of the test device <b>121</b>, and the current at the drain of the test device <b>121</b> can be coupled to the test node <b>307</b> (DUTI) of the test circuit <b>120</b> by the second PFET <b>302</b> (the pass gate device).

0037The reference device <b>131</b> of the reference circuit <b>130</b>, as shown in <figref idref="DRAWINGS">FIG. <b>3</b>A</figref>, is also an NFET that is essentially identical to the functional device <b>111</b> at issue and, thus, also essentially identical to the test device <b>121</b>. The reference circuit <b>130</b> can further be configured so that the reference device <b>131</b> is not susceptible to hot electron injection-induced saturation drain current degradation. For example, in addition to the reference device <b>131</b>, the reference circuit <b>130</b> can include a PFET <b>311</b> (also referred to herein as a pre-charge device), another PFET <b>312</b> (also referred to herein as a pass gate device) and an NFET <b>313</b> electrically connected in series between the first supply voltage (VDD) and ground. The reference circuit <b>130</b> can also include a reference node <b>317</b> (REFI) at the interface between the PFET <b>311</b> and the PFET <b>312</b>. The gate of the PFET <b>311</b> can be controlled by the STRESSN clock signal <b>162</b> and the gates of the PFET <b>312</b> and NFET <b>313</b> can be controlled by the STRESSP clock signal <b>164</b>. The source of the reference device <b>131</b> can be electrically connected to ground and the drain of the reference device <b>131</b> can be electrically connected to a node at the drains of the PFET <b>312</b> and NFET <b>313</b>. The reference circuit <b>130</b> can further include a multiplexor and another NFET <b>314</b>. The gate of the reference device <b>131</b> can be electrically connected to the drain of the NFET <b>314</b>. The source of the NFET <b>314</b> can be electrically connected to ground and the gate of the NFET <b>314</b> can be controlled by the STRESSP clock signal <b>164</b>. The gate of the reference device <b>131</b> can further be selectively connected to a fourth supply voltage (VREAD+ΔV) by the multiplexor, which includes coupled P-type and N-type pass gate FETs <b>315</b>-<b>316</b> that are controlled by the STRESSN clock signal <b>162</b> and STRESSP clock signal <b>164</b>, respectively. The fourth supply voltage can be equal to the third supply voltage (VREAD), plus a voltage adder. The voltage adder can correspond to the change in current (ΔI) that is known or expected to occur at the drain of the test device <b>121</b> when the predetermined threshold amount of saturation drain current degradation occurs, thereby indicating that a given number of power-on-hours (POHs) has passed.

0038During the test mode, controlling the gate of the test device <b>121</b> with the third supply voltage (VREAD) and the reference device <b>131</b> with the fourth supply voltage, which is equal to the third supply voltage plus the voltage adder (VREAD+ΔV), ensures that status signal <b>152</b> will stay low until a device degradation in test device <b>121</b> is sufficient to reduce its drain current below the drain current of reference device <b>131</b>. When the drain current of test device <b>121</b> becomes less than the drain current of reference device <b>131</b>, status signal <b>152</b> will switch high to indicate a given number of power-on-hours (POHs) has passed.

0039As mentioned above, during the stress mode, the STRESSP clock signal <b>164</b> will be high and the STRESSN clock signal <b>162</b> will be low; whereas, during the test mode, the STRESSP clock signal <b>164</b> will be low and the STRESSN clock signal <b>162</b> will be high. Thus, during the stress mode, the reference node <b>317</b> (REFI) of the reference circuit <b>130</b> will be pre-charged to the first supply voltage (VDD) by the PFET <b>311</b> (the pre-charge device) and the reference device <b>131</b> will have a 0-Volt bias on the gate and, thus, will be unstressed. As a result, the reference device <b>131</b> will maintain its intrinsic strength throughout the life of the IC chip <b>100</b>. During the test mode, VREAD+ΔV will be applied to the gate of reference device <b>131</b> by the adjacent multiplexor and the current at the drain of the reference device <b>131</b> will be coupled to the reference node <b>317</b> of the reference circuit <b>130</b> through PFET <b>312</b> (the pass gate device).

0040The comparator circuit <b>140</b> can include: a current mirror <b>141</b> with hysteresis (also referred to herein as a current sense with hysteresis); a voltage latch <b>142</b>; a status latch <b>143</b>; and an internal signal generator <b>144</b>.

0041The current mirror <b>141</b> can specifically be a cascaded mirror circuit that includes a first leg <b>341</b> and a second leg <b>342</b>, each of which are connected through an N-type field effect transistor (NFET) <b>358</b> (i.e., a foot device) to ground at one end and to the first supply voltage (VDD) at the opposite end. The first leg <b>341</b> can include two p-type field effect transistors (PFETs) <b>361</b>-<b>362</b> and an NFET <b>347</b> (also referred to herein as a current source) connected in series between the first supply voltage (VDD) and the NFET <b>358</b>. The second leg <b>342</b> can similarly include two PFETs <b>363</b>-<b>364</b> and an NFET <b>350</b> (also referred to herein as a current source) connected in series between the first supply voltage (VDD) and the NFET <b>358</b>. The gates of the NFETs <b>347</b> and <b>350</b> (i.e., of the current sources at the bottom of each leg) can be electrically connected to a fifth supply voltage (bias gate voltage (VBIAS)). The first leg <b>341</b> can include a pair of first nodes <b>343</b> and <b>345</b>. One first node <b>343</b> can be located at the junction between the PFETs <b>361</b>-<b>362</b> and can be coupled to the test node <b>307</b> of the test circuit <b>120</b>. The other first node <b>345</b> (MIRROR) can be located at the junction between the PFET <b>362</b> and the NFET <b>347</b> and, as discussed in greater detail below, can be coupled to the voltage latch <b>142</b>. The second leg <b>342</b> can have a pair of second nodes <b>344</b> and <b>346</b>. One second node <b>344</b> can be located at the junction between the PFETs <b>363</b>-<b>364</b> and can be coupled to the reference circuit <b>130</b> at the reference node <b>317</b> of the reference circuit <b>130</b>. The other second node <b>346</b> (OUT) can be located at the junction between the PFET <b>364</b> and the NFET <b>350</b> and, as discussed in greater detail below, can be coupled to the voltage latch <b>142</b>. The gates of the PFETs <b>361</b>-<b>364</b> and the first node <b>345</b> (MIRROR) of the first leg <b>341</b> can all be identically biased during the different modes by means of a current source (e.g., PFET <b>367</b>), which is coupled to the gates of the PFETs <b>361</b>-<b>364</b> and to the output node <b>345</b> through an adjacent multiplexor (e.g., through the coupled N-type and P-type pass gate FETs <b>365</b>-<b>366</b>).

0042The voltage latch <b>142</b> can be a voltage sense amplifier, which includes a pair of cross-coupled inverters. The cross-coupled inverters can include a first inverter (PFET <b>354</b> connected in series to an NFET <b>353</b>) and a second inverter (PFET <b>356</b> connected in series to an NFET <b>355</b>). Each inverter can be electrically connected at one end to the first supply voltage (VDD) through a PFET <b>359</b> and at the opposite end to ground through an NFET <b>357</b>. A sense node A at the interface between the PFET <b>354</b> and NFET <b>353</b> of the first inverter can control the gates of the PFET <b>356</b> and NFET <b>355</b> in the second inverter and can further be electrically connected to the first node <b>345</b> (MIRROR) of the first leg <b>341</b> of the current mirror <b>141</b> through an adjacent multiplexor (e.g., through the coupled N-type and P-type pass gate FETs <b>348</b>-<b>349</b>). Another sense node B at the interface between the PFET <b>356</b> and NFET <b>355</b> of the second inverter can control the gates of the PFET <b>354</b> and the NFET <b>353</b> of the first inverter and can be electrically connected to the second node <b>346</b> (OUT) of the second leg <b>342</b> of the current mirror <b>141</b> through an adjacent multiplexor (e.g., through the coupled N-type and P-type pass gate FETs <b>351</b>-<b>352</b>).

0043The status latch <b>143</b> can be a sample and hold latch that is coupled to both the sense node A and the sense node B of the voltage latch <b>142</b>. <figref idref="DRAWINGS">FIG. <b>3</b>B</figref> is a schematic diagram illustrating an exemplary status latch <b>143</b> that can be incorporated into the comparator circuit <b>140</b>. As illustrated, this status latch <b>143</b> includes a tri-state inverter, which is a latch formed from inverters <b>401</b> and <b>402</b> and pass gate FETs <b>411</b>-<b>415</b>.

0044As mentioned above, during the stress mode, the STRESSP clock signal <b>164</b> will be high and the STRESSN clock signal <b>162</b> will be low; whereas, during the test mode, the STRESSP clock signal <b>164</b> will be low and the STRESSN clock signal <b>162</b> will be high.

0045Thus, during the stress condition, the NFET <b>358</b> (foot device) of the current mirror <b>141</b> can be turned off so that the internal nodes float to VDD or slightly below. However, during the test mode, the NFETs <b>347</b> and <b>350</b> (current sources) at the bottoms of the first leg <b>341</b> and the second leg <b>342</b>, respectively, of the current mirror <b>141</b> will be biased by the bias gate voltage (VBIAS) in order to provide a small current through the PFETs <b>361</b>-<b>362</b> in the first leg <b>341</b> of the current mirror <b>141</b> and also through the PFETs <b>363</b>-<b>364</b> in the second leg <b>342</b> of the current mirror <b>141</b>. As a result, a test current will flow through the PFET <b>361</b> and the node <b>343</b> of the first leg <b>341</b> and into the test circuit <b>120</b> to the drain of the test device <b>121</b>. The first leg <b>341</b> of the current mirror <b>141</b> will sense this test current and will output an analog test voltage at the node <b>345</b> (MIRROR). Additionally, a reference current will flow through the PFET <b>363</b> and the node <b>344</b> of the second leg <b>342</b> and into the reference circuit <b>130</b> to the drain of the reference device <b>131</b>. The second leg <b>342</b> of the current mirror <b>141</b> will sense the reference current and will output an analog reference voltage at the node <b>346</b> (OUT).

0046During the test mode, the voltage latch <b>142</b> will sense the analog test voltage at the node <b>345</b> (MIRROR) and the analog reference voltage at the node <b>346</b> (OUT) and will further convert the analog test voltage to a digital test voltage at sense node A and the analog reference voltage to a digital reference voltage at sense node B. More specifically, the SETP clock signal <b>163</b>, which like the STRESSN clock signal <b>162</b> is output by the timing circuit <b>160</b>, can control the NFET <b>357</b> and can further be provided as an input to a signal generator <b>144</b>, which includes multiple series-connected inverters <b>371</b>-<b>374</b> for internally generating the following signals: pass gate signal <b>165</b> (SENSEP), pass gate signal <b>166</b> (SENSEN), latch signal <b>167</b> (SENSEP_D) and latch signal <b>168</b> (LATCHP_D), in sequence. The timing circuit <b>160</b> can further be configured to ensure that the SETP clock signal <b>163</b> will go high a short interval after the STRESSN clock signal <b>162</b> goes high and, thereby after the reliability monitor has entered the test mode. This causes the analog test voltage on the node <b>345</b> (MIRROR) of the first leg <b>341</b> of the current mirror <b>141</b> and the analog reference voltage on the node <b>346</b> (OUT) of the second leg <b>342</b> of the current mirror <b>141</b> to pass to the sense nodes A and B, respectively, of the voltage latch <b>142</b>. Upon firing of the latch signals SENSEP_D and LATCHP_D <b>167</b>-<b>168</b>, the voltage latch <b>142</b> will latch the voltage difference between A and B either low or high (i.e., to logic value ‘0’ or ‘1’).

0047Additionally, during the test mode, the states of the sense nodes A and B of the voltage latch <b>142</b> are passed to the status latch <b>143</b>. The status latch <b>143</b> senses the digital test voltage and the digital reference voltage on sense nodes A and B, respectively, and outputs the status signal based on the difference between those voltages. Specifically, referring to <figref idref="DRAWINGS">FIG. <b>3</b>B</figref>, the enable signal (ENABLEP) initializes the latch so that output node Q is low and, thus, so that the status signal <b>152</b> is low (i.e., at logic value ‘0’) shortly after power-on and before a full cycle of CLKP clock signal <b>161</b> occurs. The voltage levels on the sense nodes A and B are latched when the CLKP clock signal <b>161</b> goes low. The status latch <b>143</b> is further configured with clock inhibiting logic such that once the test device <b>121</b> weakens to the point where the status latch <b>143</b> detects that sense node B is low and sense node A is high, further clock signals are fenced off so as to maintain the latched state with output node Q going high (i.e., to a logic value ‘1’) and status signal <b>152</b> (flag) also switching from low to high (i.e., switching from logic value ‘0’ to logic value ‘1’), thereby indicating that the test device <b>121</b> has been under stress long enough to show a degradation. Additionally, when the output node Q goes high, the output node QN will go low. This locks the NAND gate <b>421</b> so that its output is low (i.e., a logic value of ‘0’) and keeps the clock signal CLKP low (i.e., at a logic value of ‘0’) to prevent further changes to the status latch state.

0048Furthermore, when the output node Q goes high, the hysteresis function of current mirror <b>141</b> is enabled. Specifically, hysteresis is activated once the output node Q switches from low to high and, thus, when the status signal <b>152</b> has also switched values from low to high. Hysteresis alters the balance within the current mirror <b>141</b> in favor of sensing that the difference in the saturation drain current between the test device <b>121</b> and the reference device <b>131</b> is above the predetermined threshold amount. Doing this prevents noises from causing the analog test voltage and the analog reference voltages on the nodes <b>345</b> and <b>346</b> of the current mirror <b>141</b>, respectively, to chatter and glitch at the onset of the test mode. Hysteresis continues to provide such noise immunity in order to ensure that the status signal <b>152</b> (flag) remains high for as long as the IC chip <b>100</b> is powered on. Furthermore, the state of status signal <b>152</b> will be maintained even when the power is cycled (i.e., even when the supply VDD is removed from the circuitry and subsequently restored). That is, the state of the status signal <b>152</b> (flag), which is output by the status latch <b>143</b>, will be reset to its last held state when the IC chip is powered off and back on again.

0049<figref idref="DRAWINGS">FIG. <b>4</b></figref> is an exemplary timing diagram illustrating the timing of some of the signals, which, as discussed above, control operation of the reliability monitor <b>150</b> shown in <figref idref="DRAWINGS">FIGS. <b>3</b>A-<b>3</b>B</figref>.

0050The initial enable signal <b>151</b> can be automatically set high (i.e., at a logic value of ‘1’) when the IC chip <b>100</b> is powered on. This enable signal ENABLEP enables the comparator circuitry and, particularly, allows the reliability monitor <b>150</b> to periodically switch from operation in a stress mode to operation in a test mode and back again.

0051As mentioned above, the timing circuit <b>160</b> can receive the CLKP clock signal <b>161</b> and, based on the CLKP clock signal <b>161</b>, can output both a STRESSN clock signal <b>162</b> and a SETP clock signal <b>163</b>. These three clock signal <b>161</b>-<b>163</b> can be received by the reliability monitor <b>150</b> and, in conjunction with several internally generated signals (e.g., signals <b>164</b>-<b>168</b>), can control the timing of the various components <b>120</b>, <b>130</b> and <b>140</b> of the reliability monitor <b>150</b> so that operation periodically switches to the test mode, so that the duration of the test mode is sufficient to allow for capture of the status of the test device <b>121</b> (i.e., to compare the specific performance parameter of the test device <b>121</b> and the reference device <b>131</b>) and so that the reliability monitor <b>150</b> otherwise operates in the stress mode.

0052The CLKP clock signal <b>161</b> can be a free running clock signal that oscillates at some desired frequency. The timing circuit <b>160</b> can include an N-bit counter as well as control logic. The N-bit counter can be set to translate the frequency of the CLKP clock signal <b>161</b> to a desired interval to be used to periodically test the test device <b>121</b> (i.e., to periodically switch operation of the reliability monitor <b>150</b> from the stress mode to the test mode and back). For example, it may be desirable to test the test device <b>121</b> every 1 us, for a 1 GHz clock (i.e., Ins clock period). In this case, the N-bit counter could be set to 1000 such that the reliability monitor switches from the stress mode to the test mode whenever the counter decrements to 0 after 1000 clock pulses (1000*1 ns=1 us). When the counter reaches 0 (i.e., when COUNTER=0), the control logic will cause the STRESSN clock signal <b>162</b> to go high. This, in turn, will cause the STRESSP clock signal <b>164</b> to go low (i.e., to a logic value of ‘0’) and, thereby cause the reliability monitor <b>150</b> to enter the test mode during which the high stress conditions are removed from the test device <b>121</b> and the comparison between the parameters of the test device <b>121</b> and reference device <b>131</b> is initiated. The control logic can further cause the SETP clock signal <b>163</b> to go high a short interval after the STRESSN clock signal <b>162</b> goes high and to go low again before the STRESSN clock signal <b>162</b> goes back to low. A high SETP clock signal will cause the comparator circuit <b>140</b> to latch the differential current between test device <b>121</b> and the reference device <b>131</b> and output the status signal <b>152</b> (flag). If the difference in the parameter at issue (e.g., saturation drain current) between the test device <b>121</b> and the reference device <b>131</b> is below the predetermined threshold amount, the status signal <b>152</b> will remain low (see the left side of the timing diagram); however, when the difference becomes greater than the predetermined threshold amount, the status signal will switch from low to high (see the right side of the timing diagram).

0053It should be noted that the exemplary circuitry described above and illustrated in <figref idref="DRAWINGS">FIGS. <b>3</b>A-<b>3</b>B</figref> is not intended to be limiting. For example, the reliability monitor <b>150</b> could be configured with a different test circuit <b>120</b>′, as shown in <figref idref="DRAWINGS">FIG. <b>5</b></figref>, in order to monitor a different on-chip functional device (e.g., a different NFET), which is subjected to different stress conditions that make the functional device susceptible to a different failure mechanism such as positive bias temperature instability (PBTI) hot electron injection-induced saturation drain current degradation. In this case, the exemplary test circuit <b>120</b>′ would replace the test circuit <b>120</b> shown in <figref idref="DRAWINGS">FIG. <b>3</b>A</figref>. The test circuit <b>120</b>′ includes a test device <b>121</b>′, which is an NFET that is essentially identical to the functional device to be monitored. As with the previously described test circuit <b>120</b>, the exemplary test circuit <b>120</b>′ can be configured to impart specific stress conditions on the test device <b>121</b>′ over time and specifically when the reliability monitor <b>150</b> is enabled and operating in the stress mode. These stress conditions can be essentially the same as those concurrently encountered by the functional device <b>111</b> such that the test device <b>121</b>′ is similarly susceptible to PBTI. Specifically, during the stress mode, the test device <b>121</b>′ can be biased in inversion so as to be susceptible to PBTI. A multiplexor and, particularly, coupled N-type and P-type pass gate FETs <b>501</b>-<b>502</b> that are controlled by clock signals STRESSN and STRESSP, respectively, can be connected to the gate of the test device <b>121</b>. During the test mode, the multiplexor can apply the gate voltage VREAD to the gate of the test device <b>121</b>′, thereby biasing device <b>121</b>′ in the saturated region for testing and, particularly, for comparison to the reference device <b>131</b>.

0054As mentioned above, and illustrated in <figref idref="DRAWINGS">FIG. <b>1</b></figref>, a single reliability monitor <b>150</b> could be used on an IC chip <b>100</b> with the status signal <b>152</b> (i.e., the flag) indicating whether or not the predicted EOL has been reached. However, optionally, when EOL parameter shifts are small and difficult to detect, multiple essentially identical reliability monitors <b>150</b>_1-ncan be cascaded together in order to more accurately monitor stress-induced changes particularly near EOL.

0055<figref idref="DRAWINGS">FIG. <b>6</b></figref> is a circuit diagram illustrating, in greater detail, three such cascaded reliability monitors <b>150</b>_1-3. As illustrated, the cascaded reliability monitors <b>150</b>_1-3include a first reliability monitor <b>150</b>₁that is enabled by an initial enable signal <b>151</b> ENABLEP, when the ENABLEP signal goes high. When the first reliability monitor <b>150</b>₁is enabled, the CLKP, STRESSN, and SETP signals cause the first reliability monitor <b>150</b>₁to periodically switch operation between the stress and test modes and to output a status signal <b>1521</b> that eventually switches from low to high indicating that the initial X POHs (e.g., 10,000 POHs) have been reached. The cascaded reliability monitors <b>150</b>_1-3further include a second reliability monitor <b>150</b>₂that receives the status signal <b>1521</b> from the first reliability monitor <b>150</b>₁and that is enabled only when the status signal <b>1521</b> has gone high. In other words, the status signal <b>1521</b> functions as the enable signal ENABLEP for the second reliability monitor <b>150</b>₂. When the second reliability monitor <b>150</b>₂is enabled, the CLKP, STRESSN, and SETP signals cause the second reliability monitor <b>150</b>₂to periodically switch operation between the stress and test modes and to output a status signal <b>152</b>₂that eventually switches from low to high indicating that the 2X POHs (e.g., 20,000 POHs) have been reached. The cascaded reliability monitors <b>150</b>_1-3further include a third reliability monitor <b>150</b>₃that receives the status signal <b>152</b>₂from the second reliability monitor <b>150</b>₂and that is enabled only when the status signal <b>152</b>₂has gone high. In other words, the status signal <b>152</b>₃functions as the enable signal ENABLEP for the third reliability monitor <b>150</b>₃. When the third reliability monitor <b>150</b>₃is enabled, the CLKP, STRESSN, and SETP signals cause the third reliability monitor <b>150</b>₃to periodically switch operation between the stress modes and test modes and to output a status signal <b>152</b>₃that eventually switches from low to high indicating that the 3X POHs (e.g., 30,000 POHs) and the predicted EOL of the IC chip <b>100</b> have been reached. See also the timing diagram of <figref idref="DRAWINGS">FIG. <b>4</b></figref> and the detailed discussion above with regard to the various signal values necessary to cause the switching of reliability monitor operation from the stress mode to the test mode and back.

0056<figref idref="DRAWINGS">FIG. <b>7</b></figref> is a graph with discrete curves illustrating the threshold voltage shifts exhibited by the test devices in each of the cascaded reliability monitors <b>150</b>_1-3. These curves show that the threshold voltage shifts do not occur until after the given reliability monitor is enabled and that in each case the threshold voltage shifts are initially very large, but the rate of change decreases dramatically after approximately 20,000 POHs. With the configuration shown in <figref idref="DRAWINGS">FIG. <b>6</b></figref>, since the test device in the third reliability monitor <b>150</b>₃is only subjected to stress conditions during the last X POHs of the IC chip <b>100</b>, it will exhibit a relatively large change in the performance parameter. This relatively large change can be readily detected and will occur concurrently with a relatively small change in the performance parameter of the on-chip functional device at issue near its EOL. Thus, only when the status signal <b>152</b>₃switches values (e.g., from low to high, from logic value ‘0’ to ‘1’) will the functional circuit be deemed no longer reliability and the IC chip <b>100</b> be deemed to have reached the EOL.

0057Also disclosed herein is a reliability monitoring method for a functional device on an integrated circuit (IC) chip and, thereby for the IC chip. Referring to the flow diagram of <figref idref="DRAWINGS">FIG. <b>8</b></figref> in combination with <figref idref="DRAWINGS">FIGS. <b>1</b>-<b>7</b></figref> above, the method can include providing an IC chip <b>100</b> that includes, on a substrate <b>101</b>, a functional device <b>111</b>, one or more reliability monitors <b>150</b>_1-3for the functional device <b>111</b>, and a timing circuit <b>160</b> for controlling the timing of the various components of the reliability monitor(s) <b>150</b>_1-3, as discussed in detail above with regard to the structure embodiments.

0058The method can further include powering on the IC chip <b>100</b> (see process <b>802</b>) and, after powering on the IC chip <b>100</b>, enabling a reliability monitor <b>150</b> and using clock signals to control the reliability monitor <b>150</b> so that the reliability monitor alternatingly operates in stress and test modes (i.e., so that the reliability monitor <b>150</b> periodically switches from operation in a stress mode to operation in a test mode and back, when the IC chip is powered on) (see process <b>804</b>). Operating the reliability monitor <b>150</b> in the stress mode (see process <b>808</b>) includes subjecting a test device <b>121</b> of a test circuit <b>120</b> of the reliability monitor <b>150</b> to stress conditions that emulate the operating conditions of a given on-chip functional device <b>111</b>. For example, in one embodiment, the functional device <b>111</b> and the test device <b>121</b> of the exemplary test circuit <b>120</b> (see <figref idref="DRAWINGS">FIG. <b>3</b>A</figref>) can be essentially identical NFETs, the functional device <b>111</b> can be susceptible to hot electron injection-induced saturation drain current degradation and, during the stress mode, the stress conditions bias the test device <b>121</b> such that it is similarly susceptible to hot electron injection-induced saturation drain current degradation. In another embodiment, the functional device <b>111</b> and the test device <b>121</b>′ of the exemplary test circuit <b>120</b>′ (see <figref idref="DRAWINGS">FIG. <b>5</b></figref>) can also be essentially identical NFETs; however, in this case the functional device <b>111</b> can be susceptible to positive bias temperature instability (PBTI) and the stress conditions bias the test device <b>121</b>′ in inversion so that the test device is similarly susceptible to PBTI. It should be noted that, during the stress mode, a reference device <b>131</b> of a reference circuit <b>130</b> of the reliability monitor <b>150</b> remains unstressed. In any case, the reliability monitor <b>150</b> can continue to operate in the stress mode for some regular interval, which is set by the timing circuit <b>160</b> and, particularly, by decrementing a counter based on a clock period (see process <b>810</b>). As long as the counter is still counting down (i.e., has not reached 0), the reliability monitor can continue to operate in the stress mode (see process <b>812</b>).

0059Once the counter counts down to 0, it can be reset (see process <b>814</b>) and operation of the reliability monitor can be switched to the test mode (see process <b>816</b>). Operating the reliability monitor <b>150</b> in the test mode at process <b>816</b> includes removing the stress conditions from the test device <b>121</b>, comparing a test parameter of the test device <b>121</b> to a reference parameter of the reference device <b>131</b> (see process <b>818</b>) and outputting a status signal <b>152</b> based on a difference between the test parameter and the reference parameter. The process <b>818</b> of comparing a test parameter of the test device <b>121</b> to a reference parameter of a reference device <b>131</b> can include, for example: generating an analog test voltage based on a test current flowing to the test device <b>121</b> and generating an analog reference voltage based on a reference current flowing to the reference device <b>131</b>; converting the analog test voltage to a digital test voltage and converting the analog reference voltage to a digital reference voltage; and either keeping the value of the status signal <b>152</b> low when the digital test voltage is the same as the digital reference voltage or switching the value of the status signal <b>152</b> to high when the digital test voltage is different from the digital reference voltage. Specifically, a finding at process <b>818</b> that the digital test voltage and the digital reference voltage are the same indicates that the difference between the test parameter and the reference parameter is below a predetermined threshold amount. Thus, the value of the status signal <b>152</b> will remain low and operation of the reliability monitor <b>150</b> in the stress mode can again be initiated at process <b>808</b>. However, a finding at process <b>818</b> that the digital test voltage and the digital reference voltage are different indicates that the difference between the test parameter and the reference parameter is above the predetermined threshold amount at process <b>818</b>. Thus, the value of the status signal <b>152</b> will be switched (e.g., from low to high), thereby setting the flag for that reliability monitor <b>150</b> (see process <b>820</b>). The method can further include ensuring that this status signal <b>152</b> remains constant, once it is switched to high at process <b>820</b>. This switch in the value of the status signal <b>152</b> will be indicative of the on-chip functional device <b>111</b> being powered on for some predetermined number of hours (e.g., for X power-on hours (POHs)).

0060If this is the only reliability monitor on the IC chip <b>100</b>, then a determination can be made that the IC chip is at EOL (see processes <b>822</b> and <b>826</b>). However, if, as illustrated in <figref idref="DRAWINGS">FIGS. <b>1</b> and <b>6</b></figref>, the IC chip <b>100</b> includes multiple cascaded reliability monitors <b>150</b>_1-3(e.g., at least a first reliability monitor <b>150</b>₁, a second reliability monitor <b>150</b>₂coupled to the first reliability monitor <b>150</b>₁, and so on) and if not all flags of all reliability monitors have been set, operation of the next reliability monitor in the cascade of reliability monitors <b>150</b>_1-3can be initiated (see processes <b>822</b> and <b>824</b>). In this case, the method can include using an initial enable signal <b>151</b> to enable the first reliability monitor <b>150</b>₁such that the first reliability monitor <b>150</b>₁alternatingly operates in the stress and test modes. The method can further include using the status signal <b>1521</b> output by the first reliability monitor <b>150</b>₁to enable the second reliability monitor <b>150</b>₂. That is, the method can include, when the status signal <b>1521</b> output from the first reliability monitor <b>150</b>₁switches values, automatically enabling the second reliability monitor <b>150</b>₂so that the second reliability monitor <b>150</b>₂alternatingly operates in the stress and test modes. In this case, the switch in the values of the status signal <b>1521</b> output by the first reliability monitor <b>150</b>₁(e.g., from low to high, 0 to 1) will be indicative of the on-chip functional device being powered on for some predetermined number of hours (e.g., for X power-on hours (POHs)). A subsequent switch in values of the status signal <b>152</b>₂output by the second reliability monitor <b>150</b>₂(e.g., from low to high, 0 to 1) will be indicative of the on-chip functional device being powered on for another X power-on hours (POHs) (i.e., for 2X power-on hours). Optionally, the method can further include using the status signal <b>152</b>₂output by the second reliability monitor <b>150</b>₂to enable a third reliability monitor <b>150</b>₃. That is, the method can further include, when the status signal <b>152</b>₂output from the second reliability monitor <b>150</b>₂switches values, automatically enabling a third reliability monitor <b>150</b>₃so that the third reliability monitor <b>150</b>₃alternatingly operates in the stress and test modes. A subsequent switch in values of the status signal <b>152</b>₃output by the third reliability monitor <b>150</b>₃(e.g., from low to high, 0 to 1) will be indicative of the on-chip functional device being powered on for yet another X power-on hours (POHs) (i.e., for 3X power-on hours). In this case, only when it is determined at process <b>822</b> that all flags of all reliability monitors in a cascade of reliability monitors have been set, will the IC chip be determined to be at EOL at process <b>826</b>.

0061It should be understood that the terminology used herein is for the purpose of describing the disclosed structures and methods and is not intended to be limiting. For example, as used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Additionally, as used herein, the terms “comprises” “comprising”, “includes” and/or “including” specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Furthermore, as used herein, terms such as “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, “upper”, “lower”, “under”, “below”, “underlying”, “over”, “overlying”, “parallel”, “perpendicular”, etc., are intended to describe relative locations as they are oriented and illustrated in the drawings (unless otherwise indicated) and terms such as “touching”, “in direct contact”, “abutting”, “directly adjacent to”, “immediately adjacent to”, etc., are intended to indicate that at least one element physically contacts another element (without other elements separating the described elements). The term “laterally” is used herein to describe the relative locations of elements and, more particularly, to indicate that an element is positioned to the side of another element as opposed to above or below the other element, as those elements are oriented and illustrated in the drawings. For example, an element that is positioned laterally adjacent to another element will be beside the other element, an element that is positioned laterally immediately adjacent to another element will be directly beside the other element, and an element that laterally surrounds another element will be adjacent to and border the outer sidewalls of the other element. The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed.

0062The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.