USRE49331E

Masks formed based on integrated circuit layout design having cell that includes extended active region

Claim Score by NHIP

Abstract

A set of masks corresponds to an integrated circuit layout. The integrated circuit layout includes a first cell having a first transistor region and a second transistor region, and a second cell having a third transistor region and a fourth transistor region. The first cell and the second cell adjoin each other at side cell boundaries thereof, the first transistor region and the third transistor region are formed in a first continuous active region, and the second transistor region and the fourth transistor region are formed in a second continuous active region. The set of masks is formed based on the integrated circuit layout.

USRE49331E, drawing sheet 1 — Sheet 1 of 10

Term

6.4 yearsleft in the term

Expires 27 February 2033.

39 claims: 6 independent, 33 dependent

1
A set of masks corresponding to an integrated circuit layout, the integrated circuit layout comprising:a first cell comprising a first transistor region and a second transistor region;a second cell comprising a third transistor region and a fourth transistor region, wherein the first cell and the second cell adjoin each other at side cell boundaries thereof, the first transistor region and the third transistor region are formed in a first continuous active region, and the second transistor region and the fourth transistor region are formed in a second continuous active region;and a middle gate strip electrically continuously extending from the first transistor region to the second transistor region, along a line at which the first cell adjoins the second cell, wherein the set of masks is formed based on the integrated circuit layout.
9
A set of masks corresponding to an integrated circuit layout, the integrated circuit layout comprising:a first cell comprising a first active region and a first side boundary;a second cell comprising a second active region and a second side boundary along the first side boundary;a first gate strip in the first cell parallel to the first side boundary and overlying the first active region;a second gate strip in the second cell parallel to the second side boundary and overlying the second active region;and a dummy gate strip parallel to and between the first gate strip and the second gate strip, wherein the dummy gate strip overlies one of the first active region or and the second active region , and the dummy gate strip is electrically continuous , wherein the set of masks is formed based on the integrated circuit layout.
15
A set of masks corresponding to an integrated circuit layout, the integrated circuit layout comprising:a first cell comprising a first active region and a first side boundary;a second cell comprising a second active region and a second side boundary along the first side boundary;a first gate strip in the first cell parallel to the first side boundary and overlying the first active region;a second gate strip in the second cell parallel to the second side boundary and overlying the second active region;a blank region abutting the first active region and the second active region;a first dummy gate strip in the first cell between the first gate strip and the first side boundary, and overlying the first active region and the blank region;and a second dummy gate strip in the second cell between the second gate strip and the second side boundary, and overlying the second active region and the blank region , wherein the second dummy gate strip is electrically continuous with the first dummy gate strip , wherein the set of masks is formed based on the integrated circuit layout.
21
A device, the device comprising:a first cell comprising a first transistor region and a second transistor region;a second cell comprising a third transistor region and a fourth transistor region, wherein the first cell and the second cell adjoin each other at side cell boundaries thereof, the first transistor region and the third transistor region are formed in a first continuous active region, and the second transistor region and the fourth transistor region are formed in a second continuous active region;and a middle gate strip electrically continuously extending from the first transistor region to the second transistor region, along a line at which the first cell adjoins the second cell.
28
Broadest claimClaim Score 64, broad(NHIP)A device, the device comprising:a first cell comprising a first active region and a first side boundary;a second cell comprising a second active region and a second side boundary along the first side boundary;a first gate strip in the first cell parallel to the first side boundary and overlying the first active region;a second gate strip in the second cell parallel to the second side boundary and overlying the second active region;and a dummy gate strip parallel to and between the first gate strip and the second gate strip, wherein the dummy gate strip is electrically continuous and overlies the first active region and the second active region.
34
A device, the device comprising:a first cell comprising a first active region and a first side boundary;a second cell comprising a second active region and a second side boundary along the first side boundary;a first gate strip in the first cell parallel to the first side boundary and overlying the first active region;a second gate strip in the second cell parallel to the second side boundary and overlying the second active region;a blank region abutting the first active region and the second active region;a first dummy gate strip between the first gate strip and the first side boundary, and overlying the first active region and the blank region;and a second dummy gate strip overlying the second active region and the blank region, wherein the second dummy gate strip is electrically continuous with the first dummy gate strip.

Independent claims6

49 paragraphs in 4 sections, as filed

PRIORITY CLAIM

0001The present application is a divisional of U.S. application Ser. No. 13/779,104, filed Feb. 27, 2013, which claims the priority of U.S. Provisional Application No. 61/747,751, filed Dec. 31, 2012, which are incorporated herein by reference in their entireties.

BACKGROUND

0002In the design of integrated circuits, particularly digital circuits, standard cells having fixed functions are widely used. Standard cells are typically pre-designed and saved in cell libraries. During an integrated circuit design process, the standard cells are retrieved from the cell libraries and placed into desired locations. Routing is then performed to connect the standard cells with each other and with other circuits on the chip.

0003Pre-defined design rules are followed when placing the standard cells into the desired locations. For example, spacing the active regions apart from the cell boundaries, so that when neighboring cells are abutted, the active regions of neighboring cells will not adjoin each other. The precaution associated with the active regions; however, incurs area penalties. The reserved space between the active regions and the cell boundaries results in a significant increase in the areas of the standard cells. In addition, because the active regions are spaced apart from the cell boundaries, when the standard cells are placed abutting each other, the active regions will not be joined, even if some of the active regions in the neighboring cells need to be electrically coupled. The spaced apart active regions have to be electrically connected using metal lines. The performance of the resulting device is worse than if the active regions are continuous.

0004Layout patterns and configurations can affect yield and design performance of the standard cells.

BRIEF DESCRIPTION OF THE DRAWINGS

0005For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

0006<figref idref="DRAWINGS">FIGS. 1A and 1B</figref> are a first transistor region and a second transistor region of a single standard cell in accordance with one or more embodiments;

0007<figref idref="DRAWINGS">FIGS. 2A through 2C</figref> are layouts of different arrangements and types of standard cells in accordance with one or more embodiments.

0008<figref idref="DRAWINGS">FIG. 3</figref> is a layout of a pair of standard cells having continuous active regions in accordance with one or more embodiments;

0009<figref idref="DRAWINGS">FIG. 4</figref> is a layout of a single standard cell having an extended active region in accordance with one or more embodiments;

0010<figref idref="DRAWINGS">FIG. 5</figref> is a layout of a single standard cell having an extended active region and dummy poly biasing in accordance with one or more embodiments;

0011<figref idref="DRAWINGS">FIG. 6</figref> is a layout of a single standard cell having an extended active region with active region biasing and separate dummy poly biasing in accordance with one or more embodiments;

0012<figref idref="DRAWINGS">FIG. 7</figref> is a layout of a single standard cell having an extended active region and biasing at a drain region in accordance with one or more embodiments; and

0013<figref idref="DRAWINGS">FIG. 8</figref> is a layout of a single standard cell having an extended active region and biasing at a source region in accordance with one or more embodiments.

0014<figref idref="DRAWINGS">FIG. 9</figref> is a layout of a pair of standard cells in accordance with one or more embodiments.

DETAILED DESCRIPTION

0015The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative, and do not limit the scope of the disclosure.

0016One or more embodiments of integrated circuit design layouts including standard cells are shown. Throughout the various views and embodiments, like reference numbers are used to designate like elements. In some embodiments, an integrated circuit is manufactured by performing one or more lithographic processes, growing processes, etching processes, or other processes based on a set of masks. In some embodiments, a set of masks is fabricated based on an integrated circuit design layout that depicts a plurality of features of the integrated circuit in various component layers.

0017<figref idref="DRAWINGS">FIGS. 1A and 1B</figref> are a first transistor region and a second transistor region of a single standard cell in accordance with one or more embodiments.

0018In <figref idref="DRAWINGS">FIGS. 1A and 1B</figref>, according to one or more embodiments, portions of a single standard cell 100 (e.g., an inverter cell) are depicted separately for facilitating the illustration of the present disclosure. The present disclosure is not limited to generating layouts of inverter cells and is applicable for generating layouts of other types of circuits including, for example, AND, OR, XOR, XNOR gates, and the like.

0019The standard inverter cell 100 includes upper and lower boundaries 100a and 100b and left and right cell boundaries 100c and 100d as indicated by the dashed lines shown in <figref idref="DRAWINGS">FIGS. 1A and 1B</figref>. The first transistor region (e.g., a PMOS transistor 110) of the standard inverter cell 100 as shown in <figref idref="DRAWINGS">FIG. 1A</figref> includes a p-type active region 114 (as indicated by the dimensions Xa by Ya) including source region 114a (as indicated by the dimensions Xb by Ya) and drain region 114b (as indicated by the dimensions Xc by Ya) and a first portion of an active gate strip 115 as a gate G1. The source and drain regions 114a and 114b are on opposite sides of gate G1. Further, dummy gate strips 116 are placed at left and right boundaries 100c and 100d. Dummy gate strips 116 do not act as a gate to any transistors. Each dummy gate strip 116 has only one-half a width inside the standard inverter cell 100 and the other half is outside the standard inverter cell 100. Active gate strip 115 and dummy gate strips 116 are parallel to each other and equally spaced apart. Gate strip 115 and dummy gate strips 116 are formed of polysilicon or other conductive materials such as metals, metal alloys and metal silicides. Further, a VDD power supply line is connected to source region 114a by a metal connection (e.g., a metal line 117 and contact plug 118), and supplies a voltage level VDD.

0020The second transistor region (e.g., an NMOS transistor 119) of the standard inverter cell 100 as shown in <figref idref="DRAWINGS">FIG. 1B</figref> includes a second portion of gate strip 115 as a gate G2 and an n-type active region (i.e., oxide-dimensioned region (OD)) 120 (as indicated by the dimensions Xa by Yb) including a source region 120a (as indicated by the dimensions Xb by Yb) and a drain region 120b (as indicated by the dimensions Xc by Yb). Active regions 114 and 120 are spaced apart from each other by an isolation region 122 (e.g., a shallow trench isolation (STI) region) as shown in <figref idref="DRAWINGS">FIG. 1B</figref>. A VSS power supply line is connected to source region 120a by a metal connection (e.g., a metal line 127 and a contact plug 128) and supplies a ground level or negative voltage level. Gate strip 115 includes a gate pitch P which is measured from an edge of gate strip 115 to a respective edge of a neighboring gate strip (e.g., dummy gate 116).

0021A width “w” of standard inverter cell 100 is defined by a measurement from left to right boundaries 100c and 100d. The cell width is also referred to as the cell pitch. A length of standard inverter cell 100 is defined by the measurement from upper to lower boundaries 100a and 100b. In one or more embodiments, edges of active regions 114 and 120 are spaced apart from the right and left boundaries 100c and 100d by a distance a as shown in <figref idref="DRAWINGS">FIG. 1A</figref>.

0022<figref idref="DRAWINGS">FIGS. 2A through 2C</figref> are layouts of different arrangements and types of standard cells in accordance with one or more embodiments.

0023In <figref idref="DRAWINGS">FIG. 2A</figref>, the single standard inverter cell 100 (on the left of reference line R1) abuts another standard inverter cell 130 (on the right of reference line R1). The standard cell 130 includes the same features as that of standard inverter cell 100 and therefore a detailed description thereof is omitted. The adjoining cells 100 and 130 are adjoined at their side boundaries (i.e., the right side boundary 100d of cell 100 and the left side boundary 130c of the cell 130). A dummy gate strip 116 is at the adjoining cell boundaries 100d and 130c, between the active regions 114 of the PMOS transistor regions 110 of both cells 100 and 130 and between the active regions 120 of the NMOS transistor regions 119 of both cells 100 and 130. As such, drain regions 114b and 120b of cell 100 are disposed to the left of the dummy gate strip 116, and source regions 114a and 120a of cell 130 are disposed to the right of the dummy gate strip 116.

0024Further, in one or more embodiments, the active regions 114 of the cells 100 and 130 are discrete (i.e., spaced apart from each other), and the active regions 120 of cells 100 and 130 are also discrete. In one or more embodiments, active regions of adjoining cells are continuous in <figref idref="DRAWINGS">FIG. 2B</figref> as explained below, to prevent area penalties, i.e., increased area usage, during a layout design process, and to increase gate density and the long OD region (LOD) effect. LOD effect refers the improved performance and reduced process variation as a result of a long, continuous OD region in comparison with a shorter, discrete OD region.

0025In <figref idref="DRAWINGS">FIG. 2B</figref>, standard inverter cells 100 (on the left of reference line R2) and 130 (on the right of reference line R2) are adjoined at side boundaries 100d and 130c. Further, the standard inverter cells 100 and 130 include a continuous active region 132 (as indicated by the dimensions X1 by Y1) in the PMOS transistor regions 110 and a continuous active region 134 (as indicated by dimensions X1 by Y2) in the NMOS transistor 119. The dummy gate strip 116 and adjacent drain region 114b of the standard inverter cell 100 and adjacent source region 114a of the standard inverter cell 130 together form a parasitic transistor (e.g., transistor P1 in the PMOS transistor region 110). The dummy gate strip 116 and adjacent drain region 120b and adjacent source region 120a together form a parasitic transistor (e.g., transistor N1 in the NMOS transistor region 119). As a result, unwanted capacitance exists between the parasitic transistors P1 and N1 because of these parasitic transistors P1 and N1 are within close proximity to each other. The resulting unwanted capacitance affects circuit performance.

0026<figref idref="DRAWINGS">FIG. 2C</figref> is another example of a standard cell 140 according to one or more embodiments. The standard cell 140 is similar to the standard cell 100; however, in standard cell 140, an extended active region 142 (as indicated by the dimensions X2 by Y3) is included in the PMOS transistor region 110 and an extended active region 143 (as indicated by the dimensions X2 by Y4) is included in the NMOS transistor region 119. The standard cell 140 is referred to as a poly on OD edge (PODE) cell. As shown, extended active regions 142 and 143 extend over an edge of dummy gate strips 116 at side boundaries 140c and 140d of the standard cell 140. When two PODE type standard cells are abutted (as depicted in <figref idref="DRAWINGS">FIG. 9</figref>), a blank region 149 exists between the two cells such that the cells have discrete OD regions similar to that shown in <figref idref="DRAWINGS">FIG. 1B</figref>. In cases with devices where the edge of the OD regions have some sinking or recess effect, the use of PODE type standard cells resolve this issue by extending the poly to the OD edge. When the OD is recessed at the edge and other layers need to be placed above the recess, the device performance is potentially degraded. Thus, in order to avoid the OD recess, a poly is used to block the OD edge. If two PODE type standard cells abut each other, the devices should be separated (as depicted in <figref idref="DRAWINGS">FIG. 9</figref>).

0027<figref idref="DRAWINGS">FIG. 3</figref> is a layout of an example variation of a combination of the standard cells 100 (on the left of reference line R3) and 130 (on the right of reference line R3) as similarly shown in <figref idref="DRAWINGS">FIG. 2B</figref>. The layout of <figref idref="DRAWINGS">FIG. 3</figref> includes continuous active regions 132 and 134 and is used for illustrating an operation for eliminating parasitic capacitance within the continuous active regions 132 and 134.

0028As shown in <figref idref="DRAWINGS">FIG. 3</figref>, the standard cells 100 and 130 are the same as shown in <figref idref="DRAWINGS">FIG. 2B</figref>, therefore a description of the elements is omitted. In one or more embodiments, a poly cut is performed (as depicted by box A) to separate upper and lower portions of the dummy gate strip 116. The upper portion (i.e., the portion above box A) is electrically connected to the VDD power supply line and the lower portion (i.e., the portion below box A) is electrically connected to the VSS power supply line. The electrical connection to VDD and VSS is made by metal connections to turn off the parasitic transistors (P1 and N1). For example, poly metal VDD connection is used to electrically couple the VDD power supply line to a metal line 117 at the source region 114a of the second standard cell 130. Also, poly metal VSS connection is used to electrically couple the VSS power supply line to a metal line 127 at the source region 120a of the second standard cell 130.) The use of the continuous active regions 132 and 134 provides the benefit of regaining gate density and the LOD effect.

0029<figref idref="DRAWINGS">FIG. 4</figref> is a layout of a standard cell 150 having an oxide diffusion (OD) extension layers including extended active regions 152 and 154 in accordance with one or more embodiments. The standard cell 150 in <figref idref="DRAWINGS">FIG. 4</figref> is a single standard cell having OD extension layers and is similar to the standard cell 100 shown in <figref idref="DRAWINGS">FIGS. 1A and 1B</figref> except in the PMOS transistor region 110 includes three additional gate strips (115b, 115c, and 115d) and an additional source region 114c. The gate strip 115b is between and functions as the gate electrode for the drain region 114b and the additional source region 114c. The gate strip 115c can be used for connection with another device or as a dummy gate strip.

0030The standard cell 150 includes the first gate strip 115a, the second gate strip 115b, and the third gate strip 115c are in parallel with each other. Upper and lower boundaries 150a and 150b are at opposite ends of the standard cell 150, and left and right side boundaries 150c and 150d are parallel to the plurality of gate strips 115a, 115b and 115c. The PMOS transistor 110 comprises a first portion of the first gate strip 115a as a first gate G1 and a first portion of the second gate strip 115b as a second gate G2.

0031The PMOS transistor 110 further includes the extended active region 152 (as indicated by dimensions X3 by Y5) including a first source region 114a and a first drain region 114b at opposite sides of the first gate G1, and the first drain region 114b and a second source region 114c at opposite sides of the second gate G2. The active region 152 is extended by two gate pitches (i.e., one gate pitch on each side). The use of an extended active region allows the metal (M0) poly to be positioned in the active OD region and therefore there is no degradation regarding the device size.

0032Standard cell 150 further includes a NMOS transistor 119 including a second portion of the first gate strip 115a as a third gate G3 and a second portion of the second gate strip 115b as a fourth gate G4, the second extended active region 154 (as indicated by dimensions X3 by Y6) includes a third source region 120a opposite first source region 114a of the PMOS transistor 110 and adjacent to third gate G3, and a second drain region 120b opposite second source region 114c and adjacent to fourth gate G4.

0033First and second source regions 114a and 114c of PMOS transistor 110 are connected with VDD power supply line by metal connections (e.g., metal line 117 and contact plugs 118). Further, third source region 120a of NMOS transistor 119 is connected with VSS power supply line by a metal connection (e.g., metal line 127 and contact plug 128). In one or more embodiments, first gate strip 115a is an active gate strip and second gate strip 116 is a dummy gate strip. Further, according to one or more embodiments, gate strip 115d is a non-operative floating poly and gate strip 115c is an active gate strip for other devices (not shown).

0034In one or more embodiments, first drain region 114b of PMOS transistor 110 is electrically connected with second drain region 120b of NMOS transistor 119 by a metal connection.

0035<figref idref="DRAWINGS">FIG. 5</figref> is a layout of a single standard cell 160 having extended active regions and dummy poly biasing to prevent parasitic capacitance in accordance with one or more embodiments. The layout of standard cell 160 is similar to the layout of standard cell 150 shown in <figref idref="DRAWINGS">FIG. 5</figref>. Compared with standard cell 150, PMOS transistor 110 and NMOS transistor 119 include extended active region 161 (as indicated by dimensions X4 and Y7) and extended active region 162 (as indicated by dimensions X4 and Y8) which are extended by one gate pitch at one side (e.g., a left side boundary 160c) of standard cell 160 instead of both sides. In the example depicted in <figref idref="DRAWINGS">FIG. 5</figref>, the active regions 161 and 162 are not extended beyond the third source region 114c of PMOS transistor 110 of standard cell 160 and second drain region 120b of NMOS transistor 119. Therefore, third source region 114c of PMOS transistor 110 of standard cell 160 and second drain region 120b of NMOS transistor 119 align near the side cell boundary 160d.

0036Standard cell 160 further includes a third gate strip 115c parallel to first gate strip 115a and includes an upper portion as a fifth gate G5 and a lower portion as a sixth gate G6. First and second dummy source regions 164 and 165 corresponding to PMOS transistor 110 and NMOS transistor 119 are defined within the extension of the active regions 161 and 162. First and second dummy source regions 164 and 165 are disposed to the left of the third gate strip 115c and adjacent to a side boundary (e.g., the left side boundary 160c). VDD power supply line is electrically connected to first dummy source region 164 and VSS power supply line is electrically connected to second dummy source region 165 by metal connections. Use of first and second dummy source regions 164 and 165 at boundary 160c prevents the generation of parasitic capacitance, and protects the source region 114a and the LOD effect as a result of the extended active regions 161 and 162.

0037In one or more embodiments, third gate strip 115c is a dummy gate strip and is biased at VDD power supply line or the VSS power supply line.

0038In some embodiments, some or all layouts of standard cells for NOT, AND, OR, XOR, or XNOR gates, and/or the like are arranged in a manner that the source regions are positioned adjacent to the cell side boundaries, such as side boundaries 160c and 160d of cell 160. Accordingly, generation of parasitic transistors at the side boundaries 160c and 160d when abutting another cell is prevented.

0039<figref idref="DRAWINGS">FIG. 6</figref> is a layout of single standard cell 160′ with active region biasing and separate dummy poly biasing in accordance with one or more embodiments. In <figref idref="DRAWINGS">FIG. 6</figref>, compared with the standard cell 160 in <figref idref="DRAWINGS">FIG. 5</figref>, a poly cut is performed (as depicted box “A”) at fifth gate G5 and sixth gate G6 and fifth gate G5 is electrically connected with VDD power supply line by a metal connection, and sixth gate G6 is electrically connected with VSS power supply line by a metal connection. Since the fifth gate G5 and the sixth gate G6 are cut, and the fifth gate G5 which corresponds to a parasitic transistor, is connected to power, the connection of fifth gate G5 to power disables the fifth gate G5 Further, sixth gate G6 is connected to ground and is not used as a transistor.

0040<figref idref="DRAWINGS">FIG. 7</figref> is a layout of a single standard cell 170 having extended active region 171 (as indicated by dimensions X5 by Y9) and extended active region 172 (as indicated by dimensions X5 by Y10) in accordance with one or more embodiments. Active regions 171 and 172 are extended by one gate pitch at a right side of standard cell 170. Some of the elements within standard cell 170 are the same as standard cell 160 therefore a description thereof is omitted.

0041In <figref idref="DRAWINGS">FIG. 7</figref>, third gate strip 115c is parallel to and adjacent to second gate strip 115b and includes the upper portion as the fifth gate G5 and the lower portion as the sixth gate G6. First and second dummy source regions 174 and 175 are defined within the corresponding active regions 171 and 172 and are disposed to the right of the gate strip 115c along a side boundary 170d of standard cell 170. First dummy source region 174 and second source region 114c are at opposite sides of fifth gate G5, and second dummy source region 175 and second drain region 120b are at opposite sides of sixth gate G6. VDD power supply line is electrically connected to first dummy source region 174 and VSS power supply line is electrically connected to second dummy source region 175. As shown in <figref idref="DRAWINGS">FIG. 7</figref>, in one or more embodiments, source region 175 is electrically coupled to VSS (i.e., also referred to as biasing performed at a drain side of NMOS transistor 119). Third gate strip 115c is connected with VSS power supply line to effectively disable the parasitic transistor formed by the drain region 120b, the source region 175, and the gate G6.

0042<figref idref="DRAWINGS">FIG. 8</figref> is a layout of a single standard cell 180 having an extended active region 181 (as indicated by dimensions X6 by Y11) and an extended active region 182 (as indicated by dimensions X6 by Y12) and performing biasing at a source region in accordance with one or more embodiments.

0043In <figref idref="DRAWINGS">FIG. 8</figref>, standard cell 180 is an inverter, for example, and includes first, second and third gate strips 115a, 115b and 115c parallel with each other. Upper and lower boundaries 180a and 180b on opposite ends of standard cell 180 and left and right side boundaries 180c and 180d parallel to first, second and third gates 115a, 115b and 115c. A PMOS transistor 110 includes a first portion of first gate strip 115a as a first gate G1, first extended active region 181 including a first source region 114a and a first drain region 114b at opposite sides of first gate G1, a first portion of second gate strip 115b as a second gate G2, a first dummy source region 184 and first source region 114a disposed opposite second gate G2, and a first portion of third gate strip 115c as a third gate G3 and a second dummy source region 185 and first drain region 114b disposed opposite third gate G3.

0044Standard cell 180 further includes NMOS transistor 119 including a second portion of first gate strip 115a as a fourth gate G4, second extended active region 182 including a second source region 120a opposite first source region 114a and second source region 120a and second drain region 120b disposed at opposite sides of the fourth gate G4. A second portion of second gate strip 115b as a fifth gate G5, and a third dummy source region 186 and second source region 120a are disposed at opposite sides of the fifth gate G5, and a second portion of third gate strip 120c as a sixth gate G6, the second drain region 120b and a third drain region 120c are disposed at opposite sides of sixth gate G6. First dummy source region 184, second dummy source region 185 and first source region 114a are connected with VDD power supply line by metal connections, and third dummy source region 186, and second source region 120a are connected with the VSS power supply line by metal connections. As shown, first, second and third source regions 184, 185 and 186 are disposed along the side boundaries 180c and 180d of standard cell 180. Biasing is performed on the source side of the standard cell 180. The first, second and third drain regions 114b, 120b and 120c are connected together and act as an output of the inverter.

0045<figref idref="DRAWINGS">FIG. 9</figref> illustrates a pair of PODE type standard cells according to one or more embodiments. As shown in <figref idref="DRAWINGS">FIG. 9</figref>, two PODE type standard cells 140 (on the left of reference line R4) and 190 (on the right of reference line R4) are provided. Details regarding the standard cell 140 are discussed above with regards to <figref idref="DRAWINGS">FIG. 2C</figref>. Standard cell 190 has cell boundaries 190a, 190b, 190c and 190d and further comprises the same components as that of standard cell 140, therefore a detailed description of standard cell 190 is omitted to avoid unnecessary repetition. As mentioned above, when PODE type standard cells 140 and 190 are abutted as shown in <figref idref="DRAWINGS">FIG. 9</figref>, blank region 149 exists between the two cells such that the cells have discrete OD regions similar to that shown in <figref idref="DRAWINGS">FIG. 2A</figref>.

0046One or more embodiments include a set of masks corresponding to an integrated circuit layout. The integrated circuit layout comprises a first cell comprising a first transistor region and a second transistor region, and a second cell comprising a third transistor region and a fourth transistor region. The first cell and the second cell adjoin each other at side cell boundaries thereof, the first transistor region and the third transistor region are formed in a first continuous active region, and the second transistor region and the fourth transistor region are formed in a second continuous active region. The set of masks is formed based on the integrated circuit layout.

0047One or more embodiments include a set of masks corresponding to an integrated circuit layout. The integrated circuit layout comprises a first cell comprising a first active region and a first side boundary, and a second cell comprising a second active region and a second side boundary along the first side boundary. The integrated circuit layout further comprises a first gate strip in the first cell parallel to the first side boundary and overlying the first active region, a second gate strip in the second cell parallel to the second side boundary and overlying the second active region, and a dummy gate strip parallel to and between the first gate strip and the second gate strip, wherein the dummy gate strip overlies at least one of the first active region or the second active region. The set of masks is formed based on the integrated circuit layout.

0048One or more embodiments include a set of masks corresponding to an integrated circuit layout. The integrated circuit layout comprises a first cell comprising a first active region and a first side boundary, and a second cell comprising a second active region and a second side boundary along the first side boundary. The integrated circuit layout further comprises a first gate strip in the first cell parallel to the first side boundary and overlying the first active region, a second gate strip in the second cell parallel to the second side boundary and overlying the second active region, a blank region abutting the first active region and the second active region, a first dummy gate strip in the first cell between the first gate strip and the first side boundary, and overlying the first active region and the blank region, and a second dummy gate strip in the second cell between the second gate strip and the second side boundary, and overlying the second active region and the blank region. The set of masks is formed based on the integrated circuit layout.

0049Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.

Contents4

Every citation, both ways

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US7808051B2	Cites	United States of America	Applicant
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6 members in 1 office

This recordMember, by publication datePriority claim

Priority claims3

Priority claims
Document	Office	Kind	Date
201261747751	United States of America	P	2012-12-31
201313779104	United States of America	A	2013-02-27
201514826553	United States of America	A	2015-08-14

Members6

Family members, oldest first
Document	Office	Kind
US2014183647A1	United States of America	A1	2014-07-03
US9123565B2	United States of America	B2	2015-09-01
US2015356225A1	United States of America	A1	2015-12-10
US9317646B2	United States of America	B2	2016-04-19
USRE49331EThis record	United States of America	E	2022-12-13
US2023072698A1	United States of America	A1	2023-03-09

83 transactions on the USPTO file

Allowed after 3 non-final rejections, 1 final rejection and 1 RCE.

Non-final rejections: 3
Final rejections: 1
RCEs: 1
Appeals: 0

Over time

Point at a mark for the transaction

Transactions

Prosecution transactions, newest first
	Event	Code
2023-10-04	Payment of Maintenance Fee, 8th Year, Large EntityM1552	M1552
2022-12-13	Recordation of Patent Grant MailedPGM/	PGM/
2022-11-23	Email NotificationEML_NTR	EML_NTR
2022-11-22	Issue Notification MailedAllowedWPIR	WPIR
2022-11-08	Dispatch to FDCD1935	D1935
2022-11-08	Application Is Considered Ready for IssuePILS	PILS
2022-10-27	Issue Fee Payment VerifiedN084	N084
2022-10-27	Issue Fee Payment ReceivedIFEE	IFEE
2022-08-02	Electronic ReviewELC_RVW	ELC_RVW
2022-08-02	Email NotificationEML_NTF	EML_NTF
2022-08-02	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2022-07-28	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2022-03-17	Disposal for a RCE / CPA / R129AbandonedABN9	ABN9
2022-03-17	Date Forwarded to ExaminerFWDX	FWDX
2022-03-16	Request for Continued Examination (RCE)RCEX	RCEX
2022-03-16	Workflow - Request for RCE - BeginBRCE	BRCE
2022-03-15	Email NotificationEML_NTR	EML_NTR
2022-03-15	Mail Advisory Action (PTOL - 303)MCTAV	MCTAV
2022-03-10	Advisory Action (PTOL-303)CTAV	CTAV
2022-03-09	Date Forwarded to ExaminerFWDX	FWDX
2022-03-08	Response after Final ActionA.NE	A.NE
2022-02-28	Email NotificationEML_NTR	EML_NTR
2022-02-28	Mail Examiner Interview Summary (PTOL - 413)MEXIN	MEXIN
2022-02-23	Interview Summary - Applicant Initiated - TelephonicEXAT	EXAT
2022-02-23	Interview Summary RecordEXIN	EXIN
2022-01-11	Electronic ReviewELC_RVW	ELC_RVW
2022-01-11	Email NotificationEML_NTF	EML_NTF
2022-01-11	Mail Final Rejection (PTOL - 326)Final rejectionMCTFR	MCTFR
2022-01-06	Final RejectionFinal rejectionCTFR	CTFR
2021-12-04	Date Forwarded to ExaminerFWDX	FWDX
2021-12-02	Response after Non-Final ActionA...	A...
2021-12-02	Oath or Declaration Filed (Including Supplemental)C602	C602
2021-12-02	Substitute Specification FiledC604	C604
2021-12-02	New or Additional Drawing FiledC614	C614
2021-12-02	Request for Extension of Time - GrantedXT/G	XT/G
2021-08-10	Electronic ReviewELC_RVW	ELC_RVW
2021-08-10	Email NotificationEML_NTF	EML_NTF
2021-08-10	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2021-08-03	Non-Final RejectionNon-final rejectionCTNF	CTNF
2021-06-24	Date Forwarded to ExaminerFWDX	FWDX
2021-06-22	Response after Non-Final ActionA...	A...
2021-03-31	Electronic ReviewELC_RVW	ELC_RVW
2021-03-31	Email NotificationEML_NTF	EML_NTF
2021-03-31	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2021-03-25	Non-Final RejectionNon-final rejectionCTNF	CTNF
2021-02-16	Case Docketed to Examiner in GAUDOCK	DOCK
2021-01-19	Date Forwarded to ExaminerFWDX	FWDX
2021-01-15	Response after Non-Final ActionA...	A...
2021-01-15	Oath or Declaration Filed (Including Supplemental)C602	C602
2020-10-20	Electronic ReviewELC_RVW	ELC_RVW
2020-10-20	Email NotificationEML_NTF	EML_NTF
2020-10-20	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2020-10-15	Non-Final RejectionNon-final rejectionCTNF	CTNF
2020-09-30	Information Disclosure Statement consideredIDSC	IDSC
2019-07-23	Notice of Reissue Published in Official GazetteNRE.	NRE.
2019-02-26	Paralegal Reissue Review CompletePRIR	PRIR
2019-02-05	Paralegal Reissue Review CompletePRIR	PRIR
2019-02-05	Paralegal Reissue Review CompletePRIR	PRIR
2019-01-16	Case Docketed to Examiner in GAUDOCK	DOCK
2019-01-15	Case Docketed to Examiner in GAUDOCK	DOCK
2019-01-14	Email NotificationEML_NTR	EML_NTR
2019-01-14	Application Is Now CompleteCOMP	COMP
2019-01-14	Filing Receipt - UpdatedFLRCPT.U	FLRCPT.U
2019-01-13	Application Dispatched from OIPEOIPE	OIPE
2019-01-13	FITF set to NO - revise initial settingFTFI	FTFI
2018-11-23	Additional Application Filing FeesADDFLFEE	ADDFLFEE
2018-11-23	A statement by one or more inventors satisfying the requirement under 35 USC 115, Oath of the ApplicOATHDECL	OATHDECL
2018-11-05	Email NotificationEML_NTR	EML_NTR
2018-11-05	Notice of Incomplete ReplyINCR	INCR
2018-10-23	Additional Application Filing FeesADDFLFEE	ADDFLFEE
2018-04-23	Electronic ReviewELC_RVW	ELC_RVW
2018-04-23	Email NotificationEML_NTF	EML_NTF
2018-04-23	Email NotificationEML_NTR	EML_NTR
2018-04-23	Filing ReceiptFLRCPT.O	FLRCPT.O
2018-04-23	Notice Mailed--Application Incomplete--Filing Date AssignedINCD	INCD
2018-04-21	Application ready for PDX access by participating foreign officesCCRDY	CCRDY
2018-04-18	Information Disclosure Statement (IDS) FiledM844	M844
2018-04-18	Claim Preliminary AmendmentCLAIM	CLAIM
2018-04-18	Applicants have given acceptable permission for participating foreignAPPERMS	APPERMS
2018-04-18	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2018-04-18	Cleared by OIPE CSRL194	L194
2018-04-18	Entity Status Set To Undiscounted (Initial Default Setting or Status Change)BIG.	BIG.
2018-04-18	Initial Exam Team nnIEXX	IEXX

2 legal events, as the office reported them to INPADOC

Over the term

Point at a mark for the event

Events

Legal events, newest first
	Event	Code
2023-10-04	Maintenance fee paymentMAFP	MAFP
2018-04-18	Fee payment procedureENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP	FEPP