Power converter with demand pulse isolation

CROSS-REFERENCE TO RELATED APPLICATIONS

0001This applicationNotice: The following multiple reissue applications have been filed for the reissue of U.S. Pat. No. 9,071,152: (1) reissue application Ser. No. 15/090,929, filed on Apr. 5, 2016 and reissued as U.S. Reissue Pat. No. RE47,031; (2) reissue application Ser. No. 15/168,998 (the present application), filed on May 31, 2016, which is a reissue continuation of Ser. No. 15/090,929; and (3) reissue application Ser. No. 15/202,746, filed on Jul. 6, 2016, which is a reissue continuation of Ser. No. 15/090,929. U.S. Pat. No. 9,071,152 claims the benefit of the filing dates of U.S. provisional application Nos. 61/667,473, filed on Jul. 03, 2012, and 61/727,795, filed on Nov. 19, 2012, the teachings of both of which are incorporated herein by reference in their entirety.

BACKGROUND

00021. Field of the Invention

0003The present invention relates to electronics and, more specifically but not exclusively, to switched-mode power converters.

00042. Description of the Related Art

0005This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.

0006Switched-mode DC-DC power converters, often powered by rectified DC from AC mains, are ubiquitous as plug-in adapters used to power a plethora of electronic devices.

0007A typical such converter is copiously documented in the Power Integrations Design example report DER-227. Such converters are also taught in U.S. Pat. No. 4,459,651 and U.S. Patent Application Publication Nos. 2011/0026277 A1 and 2011/0018590 A1. Such converters typically generate commutation pulses on the mains side of galvanic isolation circuitry.

0008Some known converters use forms of absorption modulation to convey feedback information through the power transformer. In U.S. Pat. No. 8,000,115, a temporary decrease in the loading of a transformer secondary winding during a flyback pulse generates a corresponding voltage disruption of the same pulse, which disruption is detected on another transformer winding to effect primary-winding-side converter control. In U.S. Pat. No. 5,973,945, a similar method is taught, but instead of unloading a flyback pulse, temporary loading of a forward power pulse is taught. The circuitry for extracting the resulting information-bearing current disruption in the transformer primary circuit is quite involved. A similar absorption modulator is taught in U.S. Pat. No. 4,996,638.

0009Converters are also known wherein an analog voltage reflection of the converter output voltage seen on a primary-side winding is processed to generate a primary-side analog feedback signal which is used to control the commutating signals applied to the commutating switch to regulate converter output on its secondary side. Such feedback methods are taught in U.S. Pat. Nos. 4,597,036 and 3,889,173. Such methods are becoming less common due to the difficulty of reliably processing the analog information reflected into a primary-side winding to obtain an accurate feedback signal.

0010U.S. Pat. No. 4,937,727 teaches a mains-side pulse generator that is pulse-width controlled by a voltage-responsive clamp on the output side of a galvanic isolation barrier.

BRIEF DESCRIPTION OF THE DRAWINGS

0011Other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements.

0012<figref idref="DRAWINGS">FIG. 1</figref> shows a schematic diagram of a power converter according to an embodiment of the present invention using a blocking oscillator.

0013<figref idref="DRAWINGS">FIG. 2</figref> shows a schematic diagram of a power converter according to another embodiment of the present invention using a blocking oscillator.

0014<figref idref="DRAWINGS">FIG. 3</figref> shows a schematic diagram of a power converter according to an embodiment of the present invention using a simple transformer.

0015<figref idref="DRAWINGS">FIG. 4</figref> shows a schematic diagram of a power converter according to an embodiment of the present invention using a separate pulse transformer.

DETAILED DESCRIPTION

0016<figref idref="DRAWINGS">FIG. 1</figref> shows a schematic diagram of a power converter <b>10</b>a. A DC voltage source <b>5</b>a, external to this converter, which may be derived from AC mains, may be connected to an earth ground <b>6</b>a. Terminals <b>11</b>a and <b>12</b>a constitute a power input port that places source <b>5</b>a in circuit with a primary winding <b>101</b>a of a transformer <b>100</b>a and with a commutating switch <b>200</b>a, which is usually a MOSFET but may be a BJT or any other suitable electronic switch. For the diagrammed embodiment, switch <b>200</b>a is a MOSFET having a source S, a gate G, and a drain D. Transformer <b>100</b>a also comprises a regeneration winding <b>102</b>a which is referenced to source S of MOSFET <b>200</b>a, is connected through a capacitor <b>202</b>a to gate G of MOSFET <b>200</b>a, and is poled to provide regenerative feedback to gate G of MOSFET <b>200</b>a. Connected between terminal <b>11</b>a and gate G of MOSFET <b>200</b>a is a resistor <b>201</b>a which charges capacitor <b>202</b>a to enhance MOSFET <b>200</b>a at a slow pulse rate. Thus, MOSFET <b>200</b>a, transformer <b>100</b>a, capacitor <b>202</b>a, and resistor <b>201</b>a form an input-side blocking oscillator which acts as a driver circuit toggling ON and OFF MOSFET <b>200</b>a.

0017Transformer <b>100</b>a also comprises a secondary winding <b>104</b>a which may be connected to a floating common terminal <b>14</b>a. A diode <b>300</b>a and a capacitor <b>301</b>a form a rectifier circuit to rectify and filter voltage pulses from winding <b>104</b>a to supply power through a power output port comprising terminals <b>13</b>a and <b>14</b>a to an external load represented by resistor <b>7</b>a connected in circuit therewith, one end of which may be referred to a floating common <b>8</b>a. The power input port <b>11</b>a/<b>12</b>a and the power output port <b>13</b>a/<b>14</b>a may be galvanically isolated from each other.

0018Flyback pulses of transformer <b>100</b>a occur when MOSFET <b>200</b>a ceases conduction, i.e., turns OFF. Winding <b>104</b>a is poled to cause diode <b>300</b>a to rectify only these flyback pulses.

0019Forward pulses, of opposite polarity to the flyback pulses, occur while MOSFET <b>200</b>a is ON. Another diode <b>500</b>a, poled to rectify forward pulses, and another capacitor <b>501</b>a form an auxiliary rectifier circuit to rectify and filter forward pulses from winding <b>104</b>a, and to store energy for triggering the input-side blocking oscillator formed by MOSFET <b>200</b>a, transformer <b>100</b>a, capacitor <b>202</b>a, and resistor <b>201</b>a. Resistor <b>201</b>a is made sufficiently large to set a low free-running frequency of the blocking oscillator, perhaps 1 KHz or less, to minimize power consumption. Nevertheless, the miniscule power thus provided suffices to charge capacitor <b>501</b>a to a voltage related, through the turns ratio of transformer <b>100</b>a, to the voltage at the power input port, even with the power output port short-circuited.

0020This magnetically-coupled blocking oscillator may be triggered through any transformer winding magnetically coupled thereto. Therefore, just as MOSFET <b>200</b>a may be turned ON through winding <b>102</b>a, it may as easily be triggered through winding <b>104</b>a. To trigger thusly, diode <b>500</b>a is briefly short-circuited by a switch <b>502</b>a which is driven by a demand pulse generator <b>503</b>a to source a pulse of energy from capacitor <b>501</b>a into transformer <b>100</b>a. When this is done, the voltage at the cathode of diode <b>500</b>a falls rapidly to the voltage on its anode, also being the voltage across capacitor <b>501</b>a. Since winding <b>104</b>a is coupled to winding <b>101</b>a, the voltage on drain D of MOSFET <b>200</b>a also rapidly falls from near the voltage on terminal <b>11</b>a to near the voltage on terminal <b>12</b>a. Since winding <b>102</b>a is also magnetically coupled, the voltage at its node shared with capacitor <b>202</b>a abruptly rises, turning ON MOSFET <b>200</b>a. This triggering action occurs in a few tens of nanoseconds. Until regeneration is established in MOSFET <b>200</b>a through winding <b>102</b>a, triggering energy is supplied by capacitor <b>501</b>a of the auxiliary rectifier circuit. However, once regeneration is established in MOSFET <b>200</b>a, capacitor <b>501</b>a is charged for the duration of the ON time of MOSFET <b>200</b>a, fully replacing any energy lost during triggering. The demand pulse generator <b>503</b>a may be used to adjust the commutation frequency of the converter <b>10</b>a to cause its output to attain a desired value, as will be described below.

0021It is important to understand certain important advantages of this embodiment. Firstly, this embodiment allows minimal, simple, and robust circuitry to be galvanically associated with the power input port where high voltages and mains transients may be expected. According to this embodiment, more complex and vulnerable regulation circuitry may be galvanically associated with the power output port where voltages are often lower and protection is more easily implemented. Secondly, the control of a flyback converter that may cross from the discontinuous conduction mode (DCM), through the critical conduction mode, to the continuous conduction mode (CCM), is well known to be problematic. This embodiment simply avoids that problem. In the embodiment shown in <figref idref="DRAWINGS">FIG. 1</figref>, transformer <b>100</b>a is used during the conduction of MOSFET <b>200</b>a as a forward converter supplying the auxiliary rectifier circuit, and during the flyback of transformer <b>100</b>a as a flyback converter supplying power to the power output port. During these cycle portions, it is difficult and impractical to re-trigger the blocking oscillator through transformer <b>100</b>a to generate another energy-bearing cycle. Once the flyback pulse has reset the inductance of transformer <b>100</b>a, i.e., has depleted energy from its magnetic field, transformer <b>100</b>a is free, until the next ON time of MOSFET <b>200</b>a, to be used as a magnetically coupled isolator to convey trigger information between its windings. In <figref idref="DRAWINGS">FIG. 1</figref>, the information thus conveyed is a pulse from pulse generator <b>503</b>a which, responsive to the output of comparator <b>401</b>a, indicates the need for another energy-bearing cycle, and moreover re-triggers the blocking oscillator to provide that energy-bearing cycle. Since it is difficult or impractical to re-trigger until transformer <b>100</b>a energy has been depleted, this converter will, if driven as hard as possible, approach critical conduction, but refuse to enter the critical conduction mode.

0022This converter may be fitted with a reference voltage <b>400</b>a and a comparison circuit <b>401</b>a. When the voltage at terminal <b>13</b>a falls below the comparison voltage, comparison circuit <b>401</b>a causes pulse generator circuit <b>503</b>a to pulse, turning ON switch <b>502</b>a, triggering an energy-bearing ON cycle of the blocking oscillator, and charging capacitor <b>301</b>a. As load <b>7</b>a drains capacitor <b>301</b>a, terminal <b>13</b>a voltage repeatedly falls to the voltage of reference <b>400</b>a, causing comparison circuit <b>401</b>a to initiate energy-bearing ON cycles. An interesting property of this embodiment is that the bottom of its output ripple corresponds to the voltage of reference <b>400</b>a, and the amplitude of its ripple decreases with increased current in load <b>7</b>a.

0023<figref idref="DRAWINGS">FIG. 2</figref> shows a schematic diagram of a power converter <b>10</b>b. As in converter <b>10</b>a of <figref idref="DRAWINGS">FIG. 1</figref> above, converter <b>10</b>b is powered, through terminals <b>11</b>b and <b>12</b>b, from an external source <b>5</b>b, that may be referred to earth ground <b>6</b>b. Power from converter <b>10</b>b flows through terminals <b>13</b>b and <b>14</b>b through a load <b>7</b>b, which may be referred to a floating common <b>8</b>b. A MOSFET <b>200</b>b, preferably ON Semiconductor type NDD02N60, forms an input-side blocking oscillator with a (preferably 1 nF) capacitor <b>202</b>b, a (preferably 66 megohm) resistor <b>201</b>b, and a transformer <b>100</b>b. Transformer <b>100</b>b comprises a winding <b>101</b>b, preferably about 250 uH, and windings <b>102</b>b and <b>104</b>b, preferably about 3.09 uH each, and a winding <b>103</b>b, preferably about 193 nH, which may be a single turn. A capacitor <b>212</b>b provides a short local circuit for high frequency currents and preferably comprises a 4.7 uF capacitor and a 100 nF capacitor (neither explicitly shown) in parallel. A resistor <b>210</b>b, preferably about 180 ohms, and a capacitor <b>211</b>b, preferably about 10 pF, filter out capacitive spikes generated by fast transitions of MOSFET <b>200</b>b. When MOSFET <b>200</b>b is turned on, the current therein rises, but is limited by a transistor <b>208</b>b, the base of which is driven by a voltage across a resistor <b>209</b>b, which voltage is responsive to current through MOSFET <b>200</b>b. When MOSFET <b>200</b>b current reaches about 250 mA, transistor <b>208</b>b shunts current at gate G of MOSFET <b>200</b>b to ground, limiting gate G voltage to prevent further current rise. With current rise prevented, the voltages across the windings of transformer <b>100</b>b collapse. Thus, a regenerative turn-OFF of MOSFET <b>200</b>b begins, and the voltage at its drain D flies positive past the voltage on terminal <b>11</b>b until the energy in its magnetic field finds a current path through one of its windings. A corresponding negative voltage occurs at the shared node of winding <b>102</b>b and a capacitor <b>204</b>b, preferably about 100 pF, which immediately couples through a resistor <b>207</b>b, preferably about 47 ohms, vigorously turning off MOSFET <b>200</b>b. Within a few nanoseconds, the same transition couples through a resistor <b>203</b>b, preferably about 1K, and a capacitor <b>202</b>b, preferably about 1 nF, to join the signal passing through capacitor <b>204</b>b, to reinforce the OFF transition at gate G of MOSFET <b>200</b>b. Both the OFF and ON transitions at gate G of MOSFET <b>200</b>b are regenerative and follow the path just described. To prevent damage to MOSFET <b>200</b>b, its gate voltage should be limited. Resistor <b>203</b>b and a diode <b>205</b>b, preferably an 8.2 volt zener, form an L-network to limit that voltage. Since the voltage at the cathode of diode <b>205</b>b is capacitively coupled to resistor <b>207</b>b, and resistor <b>201</b>b is pulling up on resistor <b>207</b>b, the gate G voltage of MOSFET <b>200</b>b would be free to rise, turn ON MOSFET <b>200</b>b continually, and perhaps damage its gate, if means for limiting gate voltage were not provided. Another zener diode <b>206</b>b, preferably the zenered base-emitter junction of an NXP type PMBT 3904, is used to limit the gate voltage rise. This device is used because, at high temperature, excess leakage of diode <b>205</b>b would shunt to ground the current of resistor <b>201</b>b, preventing the blocking oscillator from starting. Most of the current from winding <b>102</b>b, being too great for diode <b>206</b>b to conduct without damage, flows in diode <b>205</b>b.

0024As in <figref idref="DRAWINGS">FIG. 1</figref>, when the voltage at the node of winding <b>104</b>b and a diode <b>300</b>b, preferably type 1N4148, flies back, the energy in transformer <b>100</b>b is dumped into a capacitor <b>301</b>b, preferably 4.7 uF, ultimately to be consumed by load <b>7</b>b. As in <figref idref="DRAWINGS">FIG. 1</figref>, a diode <b>500</b>b, preferably type 1N4148, and a capacitor <b>501</b>b, preferably 220 nF, form a forward converter to supply an auxiliary voltage.

0025Please note that, in this embodiment, the poling of winding <b>104</b>b, diode <b>300</b>b, and diode <b>500</b>b are reversed, and the output polarity is reversed, with respect to <figref idref="DRAWINGS">FIG. 1</figref>. This reversal illustrates that this embodiment will function with either poling, and that polarity is of little practical concern in an isolated supply. The rectifiers and windings are so poled that the auxiliary supply forms a forward converter, and the output forms a flyback converter with the remaining circuitry. A switch <b>502</b>b is, in this embodiment, a PNP transistor, preferably type MMBT 3906. This switch also coacts with another winding <b>103</b>b of transformer <b>100</b>b, which may be a single turn, and a capacitor <b>504</b>b, to form an output-side triggering blocking oscillator <b>503</b>b corresponding to pulse generator <b>503</b>a of <figref idref="DRAWINGS">FIG. 1</figref>, which triggering blocking oscillator is magnetically coupled through transformer <b>100</b>b to the above-described input-side, power-blocking oscillator comprising MOSFET <b>200</b>b. Thus, an input-side, master blocking oscillator comprising MOSFET <b>200</b>b and an output-side, slave blocking oscillator comprising switch <b>502</b>b are magnetically coupled to each other through transformer <b>100</b>b. The auxiliary voltage of capacitor <b>501</b>b flows through a resistor <b>406</b>b, preferably 27K, to feed another zener diode <b>400</b>b, preferably another zenered PMBT3904, corresponding to reference <b>400</b>a of <figref idref="DRAWINGS">FIG. 1</figref>. A capacitor <b>407</b>b, preferably 100 nF, bypasses diode <b>400</b>b at high frequencies. A dual transistor <b>402</b>b, preferably NXP type BS846, is connected as a current mirror, and mirrors the current in a resistor <b>404</b>b, the latter current being set by the reference voltage of diode <b>400</b>b. This current sets the free running oscillation frequency of blocking oscillator/pulse generator <b>503</b>b. Since the transformer <b>100</b>b current flowing in MOSFET <b>200</b>b is set by transistor <b>208</b>b, the per-cycle energy in transformer <b>100</b>b is quantized. Setting the current in resistor <b>404</b>b, preferably 100K, therefore sets a maximum frequency of blocking oscillator/demand-pulse generator <b>503</b>b, thereby setting the maximum frequency for these energy-quantized cycles, thus limiting maximum converter power, even in the event of an output short-circuit. A diode <b>403</b>b, preferably type 1N4148, compensates the base-emitter voltage of dual-transistor <b>402</b>b. Dual transistor <b>402</b>b, resistor <b>404</b>b, diode <b>403</b>b, and a resistor <b>405</b>b form a current comparator corresponding to comparator <b>401</b>a of <figref idref="DRAWINGS">FIG. 1</figref>. Resistor <b>405</b>b, preferably about 82K for a 5V output, provides feedback by robbing resistor <b>404</b>b current from the current mirror of dual-transistor <b>402</b>b as output voltage increases, thus setting operating frequency roughly in proportion to the demand of load <b>7</b>b.

0026<figref idref="DRAWINGS">FIG. 3</figref> shows a schematic diagram of a power converter <b>10</b>c arranged to use a simple, two-winding transformer. The function of converter <b>10</b>c closely parallels that of converters <b>10</b>a and <b>10</b>b of <figref idref="DRAWINGS">FIGS. 1 and 2</figref>, save that components have been added to replace the functions of regenerative (tickler) windings needed by blocking oscillators. As in the previous figures, a source <b>5</b>c may be referenced to an earth ground <b>6</b>c, and load <b>7</b>c may be referenced to a floating common <b>8</b>c. As in <figref idref="DRAWINGS">FIG. 1</figref>, a transformer <b>100</b>c primary winding <b>101</b>c is in circuit with a switch <b>200</b>c and terminals <b>11</b>c and <b>12</b>c. As in <figref idref="DRAWINGS">FIG. 1</figref>, flyback pulses on a secondary winding <b>104</b>c of transformer <b>100</b>c charge a capacitor <b>301</b>c through a diode <b>300</b>c to supply energy to the load <b>7</b>c through terminals <b>13</b>c and <b>14</b>c. As in <figref idref="DRAWINGS">FIG. 1</figref>, forward pulses on the secondary winding of transformer <b>100</b>c charge a capacitor <b>501</b>c through a diode <b>500</b>c. As in <figref idref="DRAWINGS">FIG. 1</figref>, a comparison circuit <b>401</b>c compares the voltage on the output terminal <b>13</b>c with a reference <b>400</b>c. As in <figref idref="DRAWINGS">FIG. 1</figref>, a switch <b>502</b>c is driven by a demand pulse generator <b>503</b>c.

0027We now depart from the <figref idref="DRAWINGS">FIGS. 1 and 2</figref> function. A fast oscillator <b>505</b>c, preferably about 100 KHz, drives an AND gate <b>506</b>c which is also driven by comparison circuit <b>401</b>c. If the voltage between terminals <b>13</b>c and <b>14</b>c is smaller than that of reference <b>400</b>c, gate <b>506</b>c passes oscillator <b>505</b>c pulses to trigger pulse generator <b>503</b>c, which initiates, through transformer <b>100</b>c additional energy-bearing pulses by eventually driving switch <b>200</b>c, as described below. If, however, the output voltage is adequate, then gate <b>506</b>c does not pass oscillator <b>505</b>c pulses.

0028The pulses of energy from capacitor <b>501</b>c sourced to transformer <b>100</b>c, thoughthrough a switch <b>502</b>c, during the pulse of generator <b>503</b>c, under the command of gate <b>506</b>c, appear as voltage pulses across the primary winding of transformer <b>100</b>c. These pulses are detected and processed to logic levels by a demand pulse detector <b>215</b>c and passed through an OR gate <b>214</b>c to a pulse generator that turns ON switch <b>200</b>c to energize transformer <b>100</b>c to begin an energy-bearing cycle. When switch <b>200</b>c turns OFF, the subsequent flyback pulse charges capacitor <b>301</b>c through diode <b>300</b>c, as previously described. Since capacitor <b>501</b>c is charged from the converter forward pulse, its voltage persists even in the presence of a short-circuit load, allowing the converter to recover once the short-circuit is removed.

0029Had no energy-bearing cycle ever occurred, there might be insufficient, or no, charge in capacitor <b>501</b>c to be used to initiate energy-bearing cycles as described above. Therefore, a slow pulse oscillator <b>213</b>c, preferably about 1 KHz, is also connected to gate <b>214</b>c, through which it initiates energy-bearing cycles by triggering a pulse generator <b>216</b>c, thus turning on switch <b>200</b>c. These infrequent pulses cause energy-bearing cycles that are sufficient to charge capacitor <b>501</b>c, which also may supply power to generator <b>503</b>c, gate <b>506</b>c, oscillator <b>505</b>c, reference <b>400</b>c, and comparison circuit <b>401</b>c. Of course, slow oscillator <b>213</b>c must somehow be powered along with gate <b>214</b>c and pulse generator <b>216</b>c. A bias supply (not shown but well known in the art) powered from terminals <b>11</b>c and <b>12</b>c, may be used to power these components of the circuit.

0030<figref idref="DRAWINGS">FIG. 4</figref> shows a schematic diagram of a power converter <b>10</b>d, comprising a separate transformer <b>110</b>d to transmit demand pulses across a galvanic isolation barrier. As in <figref idref="DRAWINGS">FIG. 1</figref> above, converter <b>10</b>d is powered, through terminals <b>11</b>d and <b>12</b>d, from an external source <b>5</b>d, and power output from converter <b>10</b>d flows through terminals <b>13</b>d and <b>14</b>d.

0031Input voltage from terminals <b>11</b>d and <b>12</b>d powers a slow oscillator <b>213</b>d, preferably of less than 1 KHz frequency, and a start-up regulator <b>232</b>d which, through a supply node +<b>5</b>d, initially powers, with a voltage preferably about 4V, logic and drive circuitry described below. Each label “+<b>5</b>d” in <figref idref="DRAWINGS">FIG. 4</figref> refers to a supply node that is initially about 4 volts when the input-side logic is starting to function and about 5 volts when in regulation. A capacitor <b>221</b>d and a resistor <b>222</b>d differentiate transitions of a slow pulse oscillator <b>213</b>d to provide pulses of about 200 nS duration. These pulses pass thoughthrough a NAND gate <b>223</b>d to clock a D-type flip-flop <b>220</b>d through a node CKa.

0032Responsive to its clock pulse, flip-flop <b>220</b>d turns ON a switch <b>200</b>d, preferably a MOSFET, ON Semiconductor type NDD02N60, which is in circuit with a primary winding <b>101</b>d of a transformer <b>100</b>d, with a sense resistor <b>209</b>d, and with terminals <b>11</b>d and <b>12</b>d. Current then flows in this circuit, and the voltage of source <b>5</b>d is impressed upon primary winding <b>101</b>d. According to the turns-ratio between primary winding <b>101</b>d and a secondary winding <b>104</b>d of transformer <b>100</b>d, a voltage appears across winding <b>104</b>d. This latter voltage charges a capacitor <b>416</b>d through a diode <b>417</b>d.

0033As current in resistor <b>209</b>d rises, a voltage is applied to an input of a comparator <b>217</b>d, which voltage is compared with a reference <b>216</b>d, also connected to an input of comparator <b>217</b>d. When current in resistor <b>209</b>d exceeds a value set by reference <b>216</b>d, comparator <b>217</b>d issues a reset signal which propagates through NAND gates <b>218</b>d and <b>219</b>d to a node/Ra where the reset signal resets flip-flop <b>220</b>d, turning OFF switch <b>200</b>d.

0034When switch <b>200</b>d is turned ON, unavoidable gate-to-source capacitance of MOSFET switch <b>200</b>d causes a current spike in resistor <b>209</b>d. To prevent comparator <b>217</b>d from prematurely resetting flip-flop <b>220</b>d responsive to this spike, the rise of node Qa charges a capacitor <b>231</b>d through a resistor <b>230</b>d to reach the threshold of a gate <b>219</b>d in about 75 nS, prior to which the low voltage of capacitor <b>231</b>d inhibits gate <b>219</b>d from resetting flip-flop <b>220</b>d.

0035Prior to its rise, node Qa has been low, and a complementary node/Qa has been high. When node Qa rises, node/Qa falls, discharging a capacitor <b>229</b>d through a resistor <b>228</b>d to the threshold of NAND gate <b>218</b>d in about 2 uS, and thoughthrough NAND gate <b>219</b>d resetting flip-flop <b>220</b>d, thus limiting the maximum ON time of switch <b>200</b>d, should comparator <b>217</b>d fail to reset flip-flop <b>220</b>d.

0036In addition to limiting ON times of switch <b>200</b>d, it is desirable to limit maximum frequency of these ON times. To this end, the voltage across a capacitor <b>226</b>d is charged to a logic high through a resistor <b>225</b>d and applied to a node Da, the D-input of flip-flop <b>220</b>d. When node/Qa falls, capacitor <b>226</b>d is discharged through a diode <b>227</b>d, slowly to be recharged through resistor <b>225</b>d. Until the capacitor <b>226</b>d voltage is recharged to the D-input threshold voltage, flip-flop <b>220</b>d is inhibited from turning ON switch <b>200</b>d.

0037When switch <b>200</b>d is turned OFF, the energy in the magnetic field of transformer <b>100</b>d generates flyback voltage across its windings. Flyback voltage of winding <b>104</b>d is rectified by a diode <b>300</b>d and begins to charge a filter capacitor <b>301</b>d to begin to supply output voltage to terminals <b>13</b>d and <b>14</b>d. This flyback voltage also raises the voltage on capacitor <b>416</b>d, causing diode <b>417</b>d to turn OFF and a diode <b>418</b>d to turn ON, charging a capacitor <b>419</b>d. Voltage across capacitor <b>419</b>d supplies an auxiliary regulator <b>420</b>d, which in turn powers a fast oscillator <b>505</b>d, preferably of about 60 KHz frequency. Regulator <b>420</b>d also powers logic and drive circuitry on the winding <b>104</b>d side of the power converter.

0038The ON pulses of switch <b>200</b>d responsive to oscillator <b>213</b>d are sufficiently frequent to start the converter of this embodiment, but insufficiently frequent to drive it to full output. To initiate more frequent pulses, an oscillator <b>505</b>d drives a capacitor <b>507</b>d and a resistor <b>508</b>d to supply differentiated pulses of about 100 nS width to a NAND gate <b>509</b>d, which in turn drives a primary winding <b>111</b>d of demand pulse transformer <b>110</b>d, thus producing demand pulses across a secondary winding <b>112</b>d thereof. These winding <b>112</b>d pulses are conveyed through a NAND gate <b>223</b>d to clock flip-flop <b>220</b>d at up to the frequency of oscillator <b>505</b>d.

0039If all of the pulses of oscillator <b>505</b>d were allowed to clock flip-flop <b>220</b>d, under some conditions, the converter of this embodiment would produce excess output. To regulate this output, a flip-flop <b>412</b>d is used to gate the pulses passed by NAND gate <b>509</b>d. At a node CKc, oscillator <b>505</b>d clocks a flip-flop <b>412</b>d, which generates a logic high at a node Qc only when a logic high is present at a node Dc at the rising edge of its clock. Thus, pulses driving transformer <b>110</b>d are permitted responsive to a logic high only at node Dc.

0040It would be wasteful of power to drive winding <b>111</b>d for the full duration of the differentiated pulse at resistor <b>508</b>d. Therefore, when switch <b>200</b>d turns ON causing a negative transition at the dotted end of winding <b>101</b>d, a corresponding negative transition appears at the dotted end of winding <b>104</b>d. This transition is coupled through a small capacitor <b>414</b>d, preferably about 10 pF, through a current-limiting resistor <b>415</b>d to a node/Rc, the reset input of flip-flop <b>412</b>d, which is normally held high by a resistor <b>413</b>d. Thus, once the turning ON of switch <b>200</b>d has propagated through transformer <b>100</b>d, flip-flop <b>412</b>d is reset, usually in less than 20 nS.

0041Node Dc is usually held at a logic high by a resistor <b>411</b>d, thus enabling pulses gated by flip-flop <b>412</b>d. However, between terminals <b>13</b>d and <b>14</b>d is disposed a voltage divider comprising resistors <b>408</b>d and <b>409</b>d, the voltage at the junction of which is applied to an input of a comparator <b>401</b>d. Should the voltage at that junction exceed the voltage of a reference <b>400</b>d, also applied to a comparator <b>401</b>d input, an output of comparator <b>401</b>d will drop to a logic low, drawing current through a diode <b>410</b>d, thus presenting a logic low at node Dc and, after clocking, responsively at node Qc, inhibiting pulses through gate <b>509</b>d that would otherwise turn ON switch <b>200</b>d. Thus, the voltage between terminals <b>13</b>d and <b>14</b>d is regulated responsive to the voltage of reference <b>400</b>d.

0042Since the voltage between terminals <b>11</b>d and <b>12</b>d may be high, perhaps 375V, and the desired regulated voltage at node +<b>5</b>d is typically 5V, it might be inefficient to obtain the power to supply the logic and drive circuitry associated with winding <b>101</b>d from regulator <b>232</b>d. Therefore, transformer <b>100</b>d is fitted with an auxiliary winding <b>102</b>d, which is connected in circuit with an inductor <b>235</b>d, a diode <b>241</b>d, and a switch <b>233</b>d, preferably a MOSFET. While switch <b>200</b>d is ON, current flows in this circuit. When switch <b>200</b>d turns OFF, diode <b>241</b>d also turns OFF and energy in inductor <b>235</b>d generates a positive flyback voltage, causing current through a diode <b>236</b>d to charge a filter capacitor <b>237</b>d, raising the voltage of node +<b>5</b>d. As node +<b>5</b>d approaches 5V, regulator <b>232</b>d ceases to supply energy to node +<b>5</b>d, but continues to power a voltage reference <b>242</b>d, which drives an input of a comparator <b>240</b>d. Should the voltage of node +<b>5</b>d exceed 5V, the voltage at the junction of resistors <b>238</b>d and <b>239</b>d, connected to another input of comparator <b>240</b>d, will exceed that of reference <b>242</b>d, causing the output of comparator <b>240</b>d at node Db to drop to a logic low.

0043A flip-flop <b>234</b>d drives node Qb to turn ON switch <b>233</b>d responsive to clock pulses on node Qa, and to a logic high being present at node Db. When node Db drops to a logic low, node Qb follows it upon the next clock, and switch <b>233</b>d turns OFF. In this state, inductor <b>235</b>d no longer receives energy and no longer charges capacitor <b>237</b>d through diode <b>236</b>d. Thus, node +<b>5</b>d is regulated to approximately 5V, and the energy supplying node +<b>5</b>d is provided efficiently through transformer <b>100</b>d.

0044In one embodiment, the invention is a switched-mode power-converter comprising a power input port, a transformer comprising windings, a commutating switch connected in circuit with the input port and a winding of the transformer, a driver circuit for toggling the commutating switch, a power output port, a rectifier circuit for supplying power to the power output port, a reference voltage or current source, a comparison circuit for comparing the voltage or current at the power output port with the reference voltage or current, and a demand pulse source circuit coupled to the transformer for transmitting galvanically isolated trigger information through the transformer to the driver circuit responsive to the comparison circuit.

0045The converter may comprise as its driver circuit a blocking oscillator comprising the converter transformer. The converter may further comprise an input-side, master blocking oscillator for power conversion and an output-side, slave blocking oscillator for generating demand pulses. Both blocking oscillators may be mutually coupled through the converter power transformer or may drive separate transformers.

0046The converter may comprise inductive, capacitive, opto-coupled, or piezoelectric galvanic isolation circuitry to transmit demand pulses across the galvanic isolation barrier.

0047The converter may have one or more output rectifier circuits poled to rectify flyback pulses of its transformer.

0048The converter may comprise one or more auxiliary rectifier circuits which may be poled as forward converters.

0049The converter may be powered by a rectifier circuit to provide an AC/DC converter.

0050It should be understood that replicas of pulses generated and applied to one winding of the power transformer appear, suitably modified by turns-ratio, across all other windings of the power transformer.

0051Though blocking oscillators usually require tickler windings, single output embodiments of this invention may comprise a power transformer with as few as two, and in excess of five windings, with multiple output embodiments possibly comprising yet more windings.

0052Startup pulse generation circuitry resides on the powered side of the isolation barrier, though its pulses appear on both sides of the isolation barrier. This circuitry may comprise a blocking oscillator, another form of oscillator with drive circuitry to turn ON the commutating switch, or this circuitry may comprise an external source of pulses.

0053Demand pulse generator circuitry resides with the output port to be regulated, though its pulses appear on both sides of the isolation barrier. This circuitry may comprise a slave blocking oscillator, another form of oscillator with drive circuitry to turn ON the demand pulse generator switch, or may be externally applied.

0054Demand pulses may be generated to regulate the power converter to provide either a desired output voltage or a desired output current responsive to the voltage across or a current through an output port.

0055Between the commencement of start-up and the attainment of regulation, a pulse generator sources pulses to turn ON the commutating switch. This pulse generator may be the same generator that sources regulation pulses, or may be a separate pulse generator.

0056Each internal pulse generator is powered. The startup pulse generator is powered from the input port. The demand pulse generator is only indirectly powered from the input port by DC-DC power conversion through the power transformer and one or more rectifiers and filters powering the power output port with which the generator is associated.

0057Power for pulse generation circuitry may be rectified from either forward pulses, from flyback pulses, or both, appearing across one or more power transformer windings. Rectification of forward pulses helps to assure startup.

0058Windings, switches, and diodes may be poled to provide either polarity of input, and either polarity of output.

0059In each of the embodiments of <figref idref="DRAWINGS">FIGS. 1-4</figref>, galvanic isolation circuitry transfers (i) power from the input-port side to the output-port side of the power converter and (ii) demand pulses from the output-port side to the input-port side. In particular, in <figref idref="DRAWINGS">FIG. 1</figref>, the galvanic isolation circuitry consists of transformer <b>100</b>a, which transfers (i) power from winding <b>101</b>a to winding <b>104</b>a and (ii) demand pulses from winding <b>104</b>a to winding <b>102</b>a. In <figref idref="DRAWINGS">FIG. 2</figref>, the galvanic isolation circuitry consists of transformer <b>100</b>b, which transfers (i) power from winding <b>101</b>b to winding <b>104</b>b and (ii) demand pulses from winding <b>104</b>b to winding <b>102</b>b. In <figref idref="DRAWINGS">FIG. 3</figref>, the galvanic isolation circuitry consists of transformer <b>100</b>c, which transfers (i) power from winding <b>101</b>c to winding <b>104</b>c and (ii) demand pulses from winding <b>104</b>c to winding <b>101</b>c. In <figref idref="DRAWINGS">FIG. 4</figref>, the galvanic isolation circuitry consists of (i) transformer <b>100</b>d, which transfers power from winding <b>101</b>d to winding <b>104</b>d and (ii) transformer <b>110</b>d, which transfers demand pulses from winding <b>111</b>d to winding <b>112</b>d. Winding <b>102</b>d generates the bias supply for powering the +<b>5</b>d node.

0060In each of the embodiments of <figref idref="DRAWINGS">FIGS. 1-4</figref>, a demand pulse generator on the output-port side of the converter generates the demand pulses that are conveyed to the input-port side of the converter via the galvanic isolation circuitry. In <figref idref="DRAWINGS">FIGS. 1, 2, and 3</figref>, the demand pulse generator comprises elements <b>503</b>a, <b>503</b>b, and <b>503</b>c, respectively. In <figref idref="DRAWINGS">FIG. 4</figref>, the demand pulse generator comprises NAND Gate <b>509</b>d and flip-flop <b>412</b>d.

0061In each of the embodiments of <figref idref="DRAWINGS">FIGS. 1-4</figref>, slow-pulse source circuitry generates pulses on the input side of the power converter. In <figref idref="DRAWINGS">FIGS. 1 and 2</figref>, the slow-pulse source circuitry is the corresponding input-side blocking oscillator. In <figref idref="DRAWINGS">FIGS. 3 and 4</figref>, the slow-pulse source circuitry is slow oscillator <b>213</b>c and slow oscillator <b>213</b>d, respectively. Note that, depending on the particular implementation, the slow-pulse source circuitry may be implemented internal to or external to the switched-mode power converter. Similarly, depending on the particular implementation, fast oscillator <b>505</b>c and fast oscillator <b>505</b>d of <figref idref="DRAWINGS">FIGS. 3 and 4</figref>, respectively, may be implemented internal to or external to the switched-mode power converter.

0062Embodiments of the invention may be implemented as (analog, digital, or a hybrid of both analog and digital) circuit-based processes, including possible implementation as one or more integrated circuits (such as an ASIC or an FPGA), a multichip module, a single card, or a multicard circuit pack.

0063Also for purposes of this description, the terms “couple,” “coupling,” “coupled,” “connect,” “connecting,” or “connected” refer to any manner known in the art or later developed in which energy or signals are allowed to be transferred between two or more elements, and the interposition of one or more additional elements is contemplated, although not required. Conversely, the terms “directly coupled,” “directly connected,” etc., imply the absence of such additional elements.

0064Also, for purposes of this disclosure, it is understood that all gates are powered from a fixed voltage power domain (or domains) and ground unless shown otherwise. Accordingly, all digital signals generally have voltages that range from approximately ground potential to that of one of the power domains and transition (slew) quickly. However and unless stated otherwise, ground may be considered a power source having a voltage of approximately zero volts, and a power source having any desired voltage may be substituted for ground. Therefore, all gates may be powered by at least two power sources, with the attendant digital signals therefrom having voltages that range between the approximate voltages of the power sources.

0065Signals and corresponding nodes or ports may be referred to by the same name and are interchangeable for purposes here.

0066Transistors are typically shown as single devices for illustrative purposes. However, it is understood by those with skill in the art that transistors will have various sizes (e.g., gate width and length) and characteristics (e.g., threshold voltage, gain, etc.) and may consist of multiple transistors coupled in parallel to get desired electrical characteristics from the combination. Further, the illustrated transistors may be composite transistors.

0067The terms “source,” “drain,” and “gate” should be understood to refer either to the source, drain, and gate of a MOSFET or to the emitter, collector, and base of a bipolar device when an embodiment of the invention is implemented using bi-polar transistor technology. p Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value of the value or range.

0068It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain embodiments of this invention may be made by those skilled in the art without departing from embodiments of the invention encompassed by the following claims.

0069The use of figure numbers and/or figure reference labels in the claims is intended to identify one or more possible embodiments of the claimed subject matter in order to facilitate the interpretation of the claims. Such use is not to be construed as necessarily limiting the scope of those claims to the embodiments shown in the corresponding figures.

0070It should be understood that the steps of the exemplary methods set forth herein are not necessarily required to be performed in the order described, and the order of the steps of such methods should be understood to be merely exemplary. Likewise, additional steps may be included in such methods, and certain steps may be omitted or combined, in methods consistent with various embodiments of the invention.

0071Although the elements in the following method claims, if any, are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.

0072Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term “implementation.”

0073The embodiments covered by the claims in this application are limited to embodiments that (1) are enabled by this specification and (2) correspond to statutory subject matter. Non-enabled embodiments and embodiments that correspond to nonstatutory subject matter are explicitly disclaimed even if they fall within the scope of the claims.