Semiconductor device with super junction region

CROSS REFERENCE TO RELATED APPLICATION

0001This application claims benefit of priority under 35USC § 119 to Japanese patent application No. 2002-74633, filed on Mar. 18, 2002, the contents of which are incorporated by reference herein.

BACKGROUND OF THE INVENTION

00021. Field of the Invention

0003The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, and in particular, to a structure of a junction terminating region portion of a power semiconductor device which is suitable for a switching element for electric power.

00042. Related Background Art

0005In response to the demand to make electrical power equipment compact and high-performance in recent years in the power electronics field, performance improvements with respect to making lowering loss, increasing speed and improving the ruggedness have been carried out in addition to making them have a high breakdown voltage and making them able to handle great current in the power semiconductor devices. Among them, a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has been established as a key device in the switching power source field or the like because of the high-speed switching performance thereof.

0006Because the MOSFET is a majority carrier device, the MOSFET has an advantage that there is no minority carrier storage time and switching is fast. However, on the other hand, because there is no electric conductivity modulation, a device which has a high breakdown voltage is disadvantageous with respect to the ON-state resistance as compared with a bipolar device such as an IGBT (Insulated Gate Bipolar Transistor) or the like. This results from the fact that the higher the breakdown voltage a device has, the more the ON-state resistance of the MOSTFET increases, because it is necessary to make an n type base layer thicker and to make the impurity concentration lower in order to obtain a higher breakdown voltage in the MOSFET.

0007The ON-state resistance of the power MOSFET greatly depends on the electrical resistance in a conductive layer (n type drift layer) portion. Further, the impurity concentration determining the electrical resistance at the n type drift layer cannot rise to greater than or equal to the limit, in accordance with the breakdown voltage of the pn junction which the p type base and the n type drift layer form. Therefore, a trade-off relationship exists between the device breakdown voltage and the ON-state resistance. It is important to improve this trade-off for a low electric power consumption device. In this trade-off, there is a limit which is determined by the material of the device, and this limit must be exceeded in order to realize a low ON-state resistance device exceeding existing power devices.

0008As one example of MOSFETs for solving this problem, a structure is known in which a resurf structure called a super junction structure is buried in an n type drift layer. A conventional power MOSFET having a super junction structure will be described with reference to <figref idref="DRAWINGS">FIG. 36</figref>. Note that, in the following figures, like parts are denoted by like reference numerals, and detailed descriptions thereof will be omitted.

0009<figref idref="DRAWINGS">FIG. 36</figref> is a cross-sectional view showing a schematic structure of one example of a conventional power MOSFET. In the MOSFET shown in the view, an n+ type drain layer <b>100</b> is formed on one surface of an n− type drift layer <b>102</b>, and a drain electrode <b>40</b> is formed on the n+ type drain layer <b>100</b>. Further, a plurality of p type base layers <b>108</b> are selectively formed in the other surface portion of the n− type drift layer <b>102</b>, and n+ type source layers <b>110</b> are selectively formed in the surfaces of the respective p type base layers <b>108</b>. Further, a gate electrode <b>114</b> is formed on the surface region of the n− type drift layer <b>102</b> which are sandwiched by the adjacent p type base layers <b>108</b>, the surfaces of the p type base layers <b>108</b> sandwiching the n− type drift layer <b>102</b>, and the surface region of the portions of the n+ type source layer <b>110</b> facing each other via the p type base layers <b>108</b> and the n− type drift layer <b>102</b>, with a gate insulating film <b>112</b> interposed therebetween. Further, source electrodes <b>116</b> are respectively formed on the region of the surfaces of the n+ type source layer <b>110</b> and the surface of the p type base layer <b>108</b> so as to sandwich the gate electrode <b>114</b>. Moreover, in the n− type drift layer <b>102</b> between the p type base layer <b>108</b> and the n+ type drain layer <b>100</b>, a p type drift layer <b>106</b>, which is formed so as to form a resurf layer and is connected to the p type base layer <b>108</b>, is formed. In this way, the power MOSFET shown in <figref idref="DRAWINGS">FIG. 36</figref> has a vertical type resurf structure in which the p type drift layers <b>106</b> and the portions of the n− type drift layers <b>102</b> sandwiched by these p type drift layers <b>106</b> are alternately repeated in the lateral direction.

0010In an OFF-state, a depletion layer spreads at junctions between these p type drift layers <b>106</b> and n− type drift layers <b>102</b>. Even if the impurity concentration of the n− type drift layers <b>102</b> is made high, the n− type drift layers <b>102</b> and the p type drift layers <b>106</b> are completely depleted before breaking down. In accordance therewith, a breakdown voltage which is the same as that of the conventional MOSFET can be obtained.

0011The impurity concentration of the n− type drift layer <b>102</b> does not depend on a breakdown voltage of the device, but it depends on the width of the p type drift layer <b>106</b> and the width of the n− type drift layer <b>102</b> itself between these p type drift layers <b>106</b>. If the width of the n− type drift layer <b>102</b> and the width of the p type drift layer <b>106</b> are made narrower, the impurity concentration of the n− type drift layer <b>102</b> can be made much higher, and a greater reduction of the ON-state resistance and a higher breakdown voltage can be achieved.

0012At the time of designing such a MOSFET, the impurity concentrations of the n− type drift layer <b>102</b> and the p type drift layer <b>106</b> are important to determine the breakdown voltage and the ON-state resistance. In principle, due to the respective impurity concentrations of the n− type drift layer <b>102</b> and the p type resurf layer <b>106</b> being made equal, the impurity concentrations equivalently become zero, the high breakdown voltage can be obtained.

0013However, with respect to the semiconductor device having a conventional super junction structure, no structure has been developed which is effective for obtaining a high breakdown voltage in a blocking state (OFF-state) or at the time of turning-off at a junction terminating region portion which is positioned at the outer periphery of an element active region portion (hereinafter referred to as a cell region portion) and which is a region portion for maintaining the breakdown voltage by attenuating the electrical field by extending the depletion layers. Therefore, because the way of spreading of the depletion layers in the cell region portion and the junction terminating region portion are different from one another, the optimum impurity concentrations are different from one another. Accordingly, if the device is manufactured such that the impurity amounts in the cell region portion and the junction terminating region portion are the same, the breakdown voltage at the terminating portion decreases, and an electric field locally concentrates at this place. As a result, there are cases in which the device is broken. In this way, there is the problem that a sufficiently high breakdown voltage cannot be obtained by the entire device in the prior art.

0014Further, because there are dispersions among the processes at the time of actual manufacturing, it is difficult to make the respective impurity amounts of the n− type drift layer <b>102</b> and the p type drift layer <b>106</b> completely equal, and the breakdown voltage deteriorates in accordance therewith. Accordingly, it is necessary to carry out designing of the device in consideration of such a decrease of the breakdown voltage due to the process margin. In order to lower the ON-state resistance, it is effective to raise the impurity concentration of the n− type drift layer <b>102</b>. On the other hand, the process margin for the breakdown voltage is determined by the difference in the impurity amounts between the n− type drift layer <b>102</b> and the p type drift layer <b>106</b>. Therefore, when the impurity amount of the n− type drift layer <b>102</b> is increased, because the difference itself determining the process margin is not changed, the ratio between the allowed impurity amount and the impurity amount of the n− type drift layer <b>102</b> becomes small. Namely, the process margin becomes small.

BRIEF SUMMARY OF THE INVENTION

0015According to a first aspect of the present invention, there is provided a semiconductor device comprising:

0016a first—first conductivity type semiconductor layer which includes a cell region portion and a junction terminating region portion, the junction terminating region portion being a region portion which is positioned in an outer periphery of the cell region portion to maintain a breakdown voltage by extending a depletion layer to attenuate an electric field;

0017a second-first conductivity type semiconductor layer which is formed on one surface of the first—first conductivity type semiconductor layer;

0018a first main electrode which is electrically connected to the second-first conductivity type semiconductor layer;

0019first-second conductivity type semiconductor layers which are formed in the cell region portion of the first—first conductivity type semiconductor layer in substantially vertical directions to the one surface of the first—first conductivity type semiconductor layer, respectively, and which are periodically disposed in a first direction which is an arbitrary direction parallel to the one surface;

0020a second—second conductivity type semiconductor layer which is selectively formed in the other surface portion of the first—first conductivity type semiconductor layer so as to contact the first-second conductivity type semiconductor layers;

0021a third-first conductivity type semiconductor layer which is selectively formed in the surface portion of the second—second conductivity type semiconductor layer;

0022a second main electrode which is formed so as to contact the second—second conductivity type semiconductor layer and the third-first conductivity type semiconductor layer;

0023a control electrode which is formed on the surface of the first—first conductivity type semiconductor layer sandwiched by the adjacent second—second conductivity type semiconductor layers, the surface of the adjacent second—second conductivity type semiconductor layers and the surface of the third-first conductivity type semiconductor layer, with a gate insulating film interposed therebetween; and

0024third-second conductivity type semiconductor layers which are formed in the junction terminating region portion and are periodically disposed in at least one direction of the first direction and a second direction perpendicular to the first direction.

0025According to a second aspect of the invention, there is provided a method of manufacturing a semiconductor device having a super junction structure with a first conductivity type semiconductor layer on which a trench groove whose aspect ratio is R is provided and a second conductivity type semiconductor layer which is buried in the trench groove, the method of manufacturing the semiconductor device comprising:

0026forming a trench groove having an aspect ratio of R/N (N is a natural number greater than 1) in a first conductivity type semiconductor layer;

0027epitaxially growing a second conductivity type semiconductor layer so as to bury the trench groove;

0028removing the second conductivity type semiconductor layer until a surface of the first conductivity type semiconductor layer is exposed;

0029epitaxially growing the first conductivity type semiconductor layer on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer such that the thickness of the first conductivity type semiconductor layer increases by a length which is substantially the same as a depth of the trench groove formed by the first process;

0030selectively removing the first conductivity type semiconductor layer such that the second conductivity type semiconductor layer which is buried in the trench groove formed by the first process is exposed; and

0031repeating the epitaxially growing the second conductivity type semiconductor layer through selectively removing the first conductivity type semiconductor layer (N−1) times.

BRIEF DESCRIPTION OF THE DRAWINGS

0032<figref idref="DRAWINGS">FIG. 1</figref> is a plan view showing a schematic structure of a first embodiment of a semiconductor device according to the present invention.

0033<figref idref="DRAWINGS">FIG. 2</figref> is a cross-sectional view taken along the cutting line A—A of the semiconductor device shown in <figref idref="DRAWINGS">FIG. 1</figref>.

0034<figref idref="DRAWINGS">FIG. 3</figref> is a cross-sectional view taken along the cutting line B—B of the semiconductor device shown in <figref idref="DRAWINGS">FIG. 1</figref>.

0035<figref idref="DRAWINGS">FIG. 4</figref> is a plan view showing a schematic structure of a second embodiment of a semiconductor device according to the present invention.

0036<figref idref="DRAWINGS">FIG. 5</figref> is a cross-sectional view taken along the cutting line A—A of the semiconductor device shown in <figref idref="DRAWINGS">FIG. 4</figref>.

0037<figref idref="DRAWINGS">FIG. 6</figref> is a cross-sectional view taken along the cutting line B—B of the semiconductor device shown in <figref idref="DRAWINGS">FIG. 4</figref>.

0038<figref idref="DRAWINGS">FIG. 7</figref> is a plan view showing a schematic structure of a third embodiment of a semiconductor device according to the present invention.

0039<figref idref="DRAWINGS">FIG. 8</figref> is a plan view showing a schematic structure of a fourth embodiment of a semiconductor device according to the present invention.

0040<figref idref="DRAWINGS">FIG. 9</figref> is a cross-sectional view taken along the cutting line A—A of the semiconductor device shown in <figref idref="DRAWINGS">FIG. 8</figref>.

0041<figref idref="DRAWINGS">FIG. 10</figref> is a cross-sectional view showing a modified example of the semiconductor device shown in <figref idref="DRAWINGS">FIG. 8</figref>.

0042<figref idref="DRAWINGS">FIG. 11</figref> is a plan view showing a schematic structure of a fifth embodiment of a semiconductor device according to the present invention.

0043<figref idref="DRAWINGS">FIG. 12</figref> is a cross-sectional view taken along the cutting line A—A of the semiconductor device shown in <figref idref="DRAWINGS">FIG. 11</figref>.

0044<figref idref="DRAWINGS">FIG. 13</figref> is a plan view showing a schematic structure of a sixth embodiment of a semiconductor device according to the present invention.

0045<figref idref="DRAWINGS">FIG. 14</figref> is cross-sectional view taken along the cutting line A—A of the semiconductor device shown in <figref idref="DRAWINGS">FIG. 12</figref>.

0046<figref idref="DRAWINGS">FIG. 15</figref> is cross-sectional view taken along the cutting line B—B of the semiconductor device shown in <figref idref="DRAWINGS">FIG. 12</figref>.

0047<figref idref="DRAWINGS">FIG. 16</figref> is a plan view showing a modified example of the present embodiment shown in <figref idref="DRAWINGS">FIG. 12</figref>.

0048<figref idref="DRAWINGS">FIG. 17</figref> is a plan view showing a schematic structure of a seventh embodiment of a semiconductor device according to the present invention.

0049<figref idref="DRAWINGS">FIG. 18</figref> is a cross-sectional view taken along the cutting line A—A of the semiconductor device shown in <figref idref="DRAWINGS">FIG. 17</figref>.

0050<figref idref="DRAWINGS">FIG. 19</figref> is a plan view showing a schematic structure of an eighth embodiment of a semiconductor device according to the present invention.

0051<figref idref="DRAWINGS">FIG. 20</figref> is a cross-sectional view taken along the cutting line A—A of the semiconductor device shown in <figref idref="DRAWINGS">FIG. 19</figref>.

0052<figref idref="DRAWINGS">FIG. 21</figref> is a cross-sectional view taken along the cutting line B—B of the semiconductor device shown in <figref idref="DRAWINGS">FIG. 19</figref>.

0053<figref idref="DRAWINGS">FIG. 22</figref> is a plan view showing a schematic structure of a ninth embodiment of a semiconductor device according to the present invention.

0054<figref idref="DRAWINGS">FIG. 23</figref> is a cross-sectional view taken along the cutting line A—A of the semiconductor device shown in <figref idref="DRAWINGS">FIG. 22</figref>.

0055<figref idref="DRAWINGS">FIG. 24</figref> is a plan view showing a schematic structure of a tenth embodiment of a semiconductor device according to the present invention.

0056<figref idref="DRAWINGS">FIG. 25</figref> is a cross-sectional view taken along the cutting line A—A of the semiconductor device shown in <figref idref="DRAWINGS">FIG. 24</figref>.

0057<figref idref="DRAWINGS">FIG. 26</figref> is across-sectional view taken along the cutting line B—B of the semiconductor device shown in <figref idref="DRAWINGS">FIG. 24</figref>.

0058<figref idref="DRAWINGS">FIG. 27</figref> is a cross-sectional view showing a schematic structure of an eleventh embodiment of a semiconductor device according to the present invention.

0059<figref idref="DRAWINGS">FIG. 28</figref> is a graph showing relationships between a p type dopant amount and a breakdown voltage with respect to a cell region portion and a junction terminating region portion, respectively.

0060<figref idref="DRAWINGS">FIG. 29</figref> is a cross-sectional view showing a schematic structure of a twelfth embodiment of a semiconductor device according to the present invention.

0061<figref idref="DRAWINGS">FIG. 30</figref> is a graph showing changes in the breakdown voltage with respect to the impurity balance of a p type resurf layer and an n− type drift layer.

0062<figref idref="DRAWINGS">FIG. 31</figref> is a cross-sectional view showing a schematic structure of a thirteenth embodiment of a semiconductor device according to the present invention.

0063<figref idref="DRAWINGS">FIG. 32</figref> is a cross-sectional view showing a schematic structure of a fourteenth embodiment of a semiconductor device according to the present invention.

0064<figref idref="DRAWINGS">FIG. 33</figref> is a cross-sectional view showing a schematic structure of a fifteenth embodiment of a semiconductor device according to the present invention.

0065<figref idref="DRAWINGS">FIG. 34</figref> is a cross-sectional view showing a schematic structure of a sixteenth embodiment of a semiconductor device according to the present invention.

0066<figref idref="DRAWINGS">FIGS. 35A through 35F</figref> are schematic cross-sectional views showing one embodiment of a method of manufacturing the semiconductor device according to the present invention.

0067<figref idref="DRAWINGS">FIG. 36</figref> is a cross-sectional view showing a schematic structure of a power MOSFET having a super junction structure in accordance with a prior art.

DETAILED DESCRIPTION OF THE INVENTION

0068Several embodiments of the present invention will be described with reference to the drawings. Hereinafter, first, embodiments of a semiconductor device according to the present invention will be described, and finally, an embodiment of a method of manufacturing the semiconductor device according to the present invention will be described.

0069(A) Embodiments of the Semiconductor Device

0070Hereinafter, a power MOSFET having a super junction structure will be described. However, the semiconductor device according to the present invention is not limited to a power MOSFET, and can be applied to an SBD or MPS diode having a super junction structure, a switching element such as an SIT, a JFET, an IGBT, or the like, and a complex element or an integrated element of the diodes and the switching elements.

0071(1) First Embodiment

0072<figref idref="DRAWINGS">FIG. 1</figref> is a plan view showing a schematic structure of a first embodiment of the semiconductor device according to the present invention. <figref idref="DRAWINGS">FIG. 2</figref> and <figref idref="DRAWINGS">FIG. 3</figref> are cross-sectional views of the semiconductor device of the present embodiment along taken along the cutting lines A—A and B—B of <figref idref="DRAWINGS">FIG. 1</figref>, respectively. As is clear in comparison with <figref idref="DRAWINGS">FIG. 36</figref>, the semiconductor device <b>1</b> of the present embodiment is characterized in that n− type drift layers <b>26</b> and p-type drift layers <b>28</b> are formed not only in a cell region portion, but are formed also up to the vicinity of the periphery of a junction terminating region portion. Hereinafter, the structure of the semiconductor device <b>1</b> of the present embodiment will be described in even more detail.

0073The semiconductor device <b>1</b> of the present embodiment has an n+ type drain layer <b>20</b>, a drain electrode <b>40</b>, the n type drift layers <b>26</b>, the p type drift layers <b>28</b>, p type base layers <b>30</b>, an n+ type source layer <b>32</b>, a source electrode <b>38</b>, an insulated gate electrode <b>36</b>, and a fieldplate electrode <b>48</b>.

0074The drain electrode <b>40</b> is formed on one surface of the n+ type drain layer <b>20</b>, and is formed on the bottom surface in <figref idref="DRAWINGS">FIG. 2</figref> and <figref idref="DRAWINGS">FIG. 3</figref>. The p type drift layers <b>28</b> are respectively structured in the n type semiconductor layers <b>26</b> so as to be in a striped shape from the boundary surface with the n+ type drain layer <b>20</b> up to the surface portion of the n type semiconductor layers <b>26</b> which represent the other surface portion, i.e., the top surface portion in <figref idref="DRAWINGS">FIG. 2</figref> and <figref idref="DRAWINGS">FIG. 3</figref>, of the n+ type drain layer <b>20</b>. The respective stripe-shaped p type drift layers <b>28</b> are arranged not only in the cell region portion, but also up to the junction terminating region portion at predetermined intervals in a predetermined direction which is horizontal to the surface of the n+ type drain layer <b>20</b>. Regions sandwiched between these p type drift layers <b>28</b> in the n type semiconductor layers <b>26</b> structure the n type drift layers <b>26</b>. With respect to the widths and the impurity concentration of both of the n type semiconductor layers <b>26</b> and the p type drift layers <b>28</b>, for example, when each of their widths is 5 μm, the impurity concentration is about 4×10¹⁵cm⁻³, respectively, and when each of the widths is 1 μm, the impurity concentration is about 2×10¹⁶cm⁻³, respectively.

0075The p type base layers <b>30</b> are selectively formed in the surface portion in the n type semiconductor layers <b>26</b> so as to connect to the p type drift layers <b>28</b>. The n+ type source layers <b>32</b> are selectively formed in the surface portion of the p type base layers <b>30</b>. The source electrodes <b>38</b> are formed so as to connect the adjacent n+ type source layer <b>32</b> on the surface of the p type base layer <b>30</b> and the p type base layer <b>30</b> sandwiched thereby. Moreover, the insulated gate electrode <b>36</b> is disposed via an insulating film <b>34</b> above the surface of the n type drift layer <b>26</b>, the surface of the p type base layer <b>30</b> adjacent to the surface of the n type drift layer <b>26</b>, and the surface of the n+ source layer <b>32</b> contacting the p type base layer <b>30</b>, so as to be surrounded by the source electrodes <b>38</b>. In accordance with such a structure, the semiconductor device <b>1</b> constitutes an n channel MOSFET for electron injection in which the surface portion of the p type base layer <b>30</b> immediately under the insulated gate <b>36</b> is a channel region. In the present embodiment, a case in which a planer type gate structure is provided will be described. However, a trench type gate structure may be used. This point is the same for the following respective embodiments as well.

0076The semiconductor device <b>1</b> also comprises a p type base layer <b>30</b>a which is formed so as to surround the cell region portion in the surface portion at the vicinity of the boundary with the cell region portion in the junction terminating region portion. The p type base layer <b>30</b>a is discretely connected to the p type drift layer <b>28</b>a which is closest to the cell region portion among the p type drift layers <b>28</b>a provided in the junction terminating region portion. On the surface of the junction terminating region portion, an insulating film <b>46</b> is formed on the part other than a part of the p type base layer <b>30</b>a. A fieldplate electrode <b>48</b> is formed on the insulating film <b>46</b> so as to surround the cell region, and contacts the surface of the p type base layer <b>30</b>a, and is electrically connected to the source electrodes <b>38</b>. In the periphery of the junction terminating region, a high-concentration n+ type channel stopper layer <b>42</b> is formed on the surface portion of the n type drift layer <b>26</b>, and the electrode <b>44</b> is formed on the n+ channel stopper layer <b>42</b>.

0077The broken lines in <figref idref="DRAWINGS">FIG. 2</figref> and <figref idref="DRAWINGS">FIG. 3</figref> denote equipotential lines, which are the result of a simulation in which calculation is carried out by using the conditions that the widths of the n type drift layer <b>26</b> and the p type drift layer <b>28</b> are 8 μm, the impurity concentrations thereof are 2×10¹⁵cm⁻³, and the thickness thereof are 50 μm.

0078When the semiconductor device <b>1</b> of the present embodiment turns off in a direction (the A—A direction of <figref idref="DRAWINGS">FIG. 1</figref>, and hereinafter referred to as vertical direction) intersecting the stripe longitudinal direction (the B—B direction of <figref idref="DRAWINGS">FIG. 1</figref>, and hereinafter referred to as the horizontal direction) of the drift layers <b>26</b> (<b>26</b>a), <b>28</b> (<b>28</b>a) in plan view, the depletion progresses from a side close to the cell region portion of the n type drift layer <b>26</b>a and the p type drift layer <b>28</b>a toward the periphery of the device, and in the horizontal direction, the depletion progresses over the boundary surface at the same time from the device peripheral portions of the drift layers <b>26</b>a and <b>28</b>a to the cell region portion. At this time, electrons are discharged to the drain electrode <b>40</b> via the n+ type drain layer <b>20</b> from the n type drift layer <b>26</b>a, and on the other hand, positive holes are discharged to the source electrode <b>38</b> via the p type base layer <b>30</b>a and to the fieldplate electrode <b>48</b> from the p type drift layer <b>28</b>a. However, in the vertical direction, the positive holes are discharged so as to cross the junction between the n type drift layer <b>26</b>a and the p type drift layer <b>28</b>a. Moreover, in a blocking state (at the time when the device is off), because the intervals between the equipotential lines are made uniform by the fieldplate electrode <b>48</b>, as shown in <figref idref="DRAWINGS">FIG. 2</figref> and <figref idref="DRAWINGS">FIG. 3</figref>, the electric field is attenuated thereby. As a result, the semiconductor device <b>1</b> can obtain a stable high breakdown voltage.

0079Note that the structure of the n type drain layer <b>20</b> is not limited to the form shown in <figref idref="DRAWINGS">FIG. 1</figref> through <figref idref="DRAWINGS">FIG. 3</figref>, and for example, an epitaxial wafer substrate, a layer in which a predetermined depth of the epitaxial wafer substrate is subjected to thermal diffusion, a diffusion layer in which an impurity is subjected to thermal diffusion, or the like can be applied. Further, the present embodiment is the two-layer structure of the n type drain layer <b>20</b> and the n type semiconductor layer <b>26</b>. However, an intermediate layer whose concentration continuously changes may be set between these two layers. Further, in the present embodiment, as shown in <figref idref="DRAWINGS">FIG. 2</figref> and <figref idref="DRAWINGS">FIG. 3</figref>, the fieldplate electrode <b>48</b> is formed on the insulating film <b>46</b> having a uniform thickness. However, the present invention is not limited thereto, and for example, as in eleventh through sixteenth embodiments which will be described later, it may be set such that the thickness of the insulating film <b>46</b> is made to gradually become greater as the insulating film <b>46</b> approaches the peripheral portion. These points are the same for following second through tenth embodiments as well.

0080(2) Second Embodiment

0081<figref idref="DRAWINGS">FIG. 4</figref> is a plan view showing a schematic structure of a second embodiment of a semiconductor device according to the present invention. <figref idref="DRAWINGS">FIG. 5</figref> and <figref idref="DRAWINGS">FIG. 6</figref> are cross-sectional views of the semiconductor device of the present embodiment taken along the cutting lines A—A and B—B of <figref idref="DRAWINGS">FIG. 4</figref>, respectively.

0082The semiconductor device <b>2</b> of the present embodiment has, in place of the fieldplate electrode <b>48</b> which the semiconductor <b>1</b> shown in <figref idref="DRAWINGS">FIG. 1</figref> has, a p− type resurf layer <b>52</b> which is connected to the p type base layer <b>30</b>a disposed so as to surround the cell region in the junction terminating region portion, and which is formed so as to further surround the p type base layer <b>30</b>a. The other structures of the semiconductor device <b>2</b> are substantially the same as those of the semiconductor device <b>1</b> shown in <figref idref="DRAWINGS">FIG. 1</figref>.

0083As shown by the equipotential lines in <figref idref="DRAWINGS">FIG. 2</figref> and <figref idref="DRAWINGS">FIG. 3</figref>, also by providing such a p− type resurf layer <b>52</b>, the electric field is attenuated at the time when the device is off. Therefore, a stable high breakdown voltage can be obtained.

0084(3) Third Embodiment

0085<figref idref="DRAWINGS">FIG. 7</figref> is a plan view showing a schematic structure of a third embodiment of a semiconductor device according to the present invention. Note that a cross-sectional view taken along the cutting line A—A in the view is substantially the same as <figref idref="DRAWINGS">FIG. 2</figref>.

0086The semiconductor device <b>3</b> of the present embodiment is characterized in that p type drift layers <b>54</b>, <b>54</b>a have a circular plane shape, which is different from the above-described embodiments. Due to the p type drift layers being structured in such a shape, the depletion layers can be extended in all directions in a plane which is horizontal to the surface of the device.

0087Note that, in <figref idref="DRAWINGS">FIG. 7</figref>, although an example of circular patterns is shown, there may be polygonal patterns such as quadrangular patterns, hexagonal patterns, or the like. Further, it may be formed such that the n type drift layers <b>26</b> have a pattern. Further, in the same way as in the above-described second embodiment, a resurf layer can be applied in place of the fieldplate electrode <b>48</b>.

0088(4) Fourth Embodiment

0089<figref idref="DRAWINGS">FIG. 8</figref> is a plan view showing a schematic structure of a fourth embodiment of a semiconductor device according to the present invention. <figref idref="DRAWINGS">FIG. 9</figref> is a cross-sectional view of the semiconductor device of the present embodiment taken along the cutting line A—A of <figref idref="DRAWINGS">FIG. 8</figref>.

0090Differently from the above-described first though third embodiments, a semiconductor device <b>4</b> of the present embodiment has an n− type base layer <b>68</b> as the n type base layer in the junction terminating region portion, the concentration of the n− type base layer <b>68</b> being lower than that of the n type drift layer <b>26</b> in the cell region portion. Moreover, the semiconductor device <b>4</b> does not have drift layers in the junction terminating region portion other than a p type drift layer <b>27</b> which will be described later. The p type base layer <b>30</b>a and a plurality of p type guard ring layers <b>62</b> are selectively formed so as to surround the cell region portion in the surface portion of the n− type base layer <b>68</b>. Below the p type base layer <b>30</b>a, the p type drift layer <b>27</b> is formed so as to correspond to the arrangement of the p type base layer <b>30</b>a, and thus, the p type base layer <b>30</b>a is connected to the drain electrode <b>40</b> via the drain layer <b>20</b>.

0091In this way, in accordance with the present embodiment, even when a plurality of drift layers are not provided in the junction terminating region portion, a stable high breakdown voltage can be obtained by a single super junction structure surrounding the cell region portion and the p type guard ring layers <b>62</b> formed so as to surround the cell region portion in the same way in the surface portion of the periphery of the super junction structure.

0092A cross-sectional view of a modified example of the present embodiment is shown in <figref idref="DRAWINGS">FIG. 10</figref>. A semiconductor device <b>4</b>′ shown in the view has, in the junction terminating region portion, n type base layers <b>22</b> whose concentration is the same as that of the n type drift layer <b>26</b> in the cell region portion, and p type drift layers <b>29</b> are provided in the junction terminating region portion and are connected to p type guard ring layers <b>62</b>′ which are selectively provided on the surface portion of the n type base layers <b>22</b>. Moreover, in the peripheral portion of the junction terminating region portion, a p type drift layer <b>29</b>′ is formed so as to be exposed on the surface of the n type base layers <b>22</b>. In accordance with these structures, a stable high breakdown voltage can be obtained because the equipotential lines spreading in the junction terminating region portion are made flat. As a result, a decrease of the breakdown voltage in the junction terminating region portion can be suppressed.

0093(5) Fifth Embodiment

0094<figref idref="DRAWINGS">FIG. 11</figref> is a plan view showing a schematic structure of a fifth embodiment of a semiconductor device according to the present invention. <figref idref="DRAWINGS">FIG. 12</figref> is a cross-sectional view of the semiconductor device of the present embodiment taken along the cutting line A—A of <figref idref="DRAWINGS">FIG. 11</figref>. Note that the cross-sectional view taken along the cutting line B—B of <figref idref="DRAWINGS">FIG. 11</figref> is the same as the <figref idref="DRAWINGS">FIG. 3</figref>.

0095The present embodiment provides a junction terminating regional structure which is suitable for a semiconductor device having an insulating film formed parallel to the horizontal direction in the n type drift layer <b>26</b> in the cell region portion.

0096As shown in <figref idref="DRAWINGS">FIG. 11</figref> and <figref idref="DRAWINGS">FIG. 12</figref>, in the semiconductor device <b>5</b> of the present embodiment, a trench groove <b>64</b> is formed in a horizontal direction in the n type drift layer <b>26</b> (<b>26</b>a), and an insulating film <b>66</b> is formed therein. Such an insulating film can be manufactured by forming the stripe shaped trench grooves <b>64</b> so as to extend from the cell region portion to the junction terminating region portion on the substrate structured from, for example, a low-concentration n− type base layer <b>68</b>, and by applying thermal diffusion after an n type impurity and a p type impurity are introduced into the side walls of the trench grooves <b>64</b> by using a method such as an ion injection or the like. Thereby, the n type drift layer <b>26</b> (<b>26</b>a) and the p type drift layer <b>28</b> (<b>28</b>a) are formed so as to surround the insulating film <b>66</b>. Accordingly, in the junction terminating region portion, the insulating film <b>66</b> and the both drift layers <b>26</b>a, <b>28</b>a extend in the horizontal direction up to the vicinity of the peripheral portion. However, the insulating film <b>66</b> and the drift layers are not formed in the vertical direction.

0097This is because that, if the insulating film <b>66</b> and the drift layers <b>26</b>a, <b>28</b>a are formed in the vertical direction, the positive holes in the p type drift layer <b>28</b>a are not discharged at the time of turning-off because of the insulating film <b>66</b>, and as a result, the depletion layer does not extend and an electric field concentrates at the cells at the outermost periphery, which may break the device.

0098As shown in <figref idref="DRAWINGS">FIG. 12</figref>, the semiconductor device <b>5</b> of the present embodiment further comprises the field plate electrode <b>48</b> provided above the low-concentration n− type base layer <b>68</b> in the junction terminating region via the insulating film <b>46</b> so as to surround the cell region. Therefore, the depletion layer sufficiently extends, and a high breakdown voltage can be obtained.

0099(6) Sixth Embodiment

0100<figref idref="DRAWINGS">FIG. 13</figref> is a plan view showing a schematic structure of a sixth embodiment of a semiconductor device of the present invention. <figref idref="DRAWINGS">FIG. 14</figref> and <figref idref="DRAWINGS">FIG. 15</figref> are cross-sectional views of the semiconductor device of the present embodiment taken along the cutting lines A—A, B—B of <figref idref="DRAWINGS">FIG. 13</figref>.

0101Differently from the fifth embodiment which is described above, with respect to a semiconductor device <b>6</b> of the present embodiment, the insulating film <b>66</b> is formed only in the cell region portion, and does not extend to the junction terminating region portion. Moreover, in the junction terminating region portion of the semiconductor device <b>6</b>, both the n type drift layers and the p type drift layers are not formed. In the present embodiment, the n− type base layer <b>68</b> whose concentration is lower than that of the n type drift layer <b>26</b> is formed in the junction terminating region portion, and the p type base layer <b>30</b>a and a plurality of p type guard ring layers <b>62</b> are selectively formed so as to surround the cell region on the surface portion of the n− type base layer <b>68</b>. The source electrode <b>38</b>a contacts the surface of the p type base layer <b>30</b>a. Further, below the p type base layer <b>30</b>a, the p type drift layer <b>27</b> is formed so as to correspond to the arrangement of the p type base layer <b>30</b>a, and thereby the p type base layer <b>30</b>a is connected to the drain electrode <b>40</b> via the drain layer <b>20</b>. In accordance with such a structure of the junction terminating region portion, the semiconductor device <b>6</b> of the present embodiment can obtain a sufficiently high breakdown voltage.

0102<figref idref="DRAWINGS">FIG. 16</figref> is a plan view showing a modified example of the present embodiment. In a semiconductor device <b>6</b>′ of the present example, an insulating film <b>72</b> is formed also in a vertical direction only in the cell region portion, and then the insulating film <b>72</b> has a reticulated plan shape. Other structures of the semiconductor device <b>6</b>′ are substantially the same as those of the semiconductor device <b>6</b> shown in <figref idref="DRAWINGS">FIG. 13</figref>. Even when the insulating film <b>72</b> has such a structure in the cell region portion, the semiconductor device <b>6</b>′ can obtain a sufficiently high breakdown voltage because the insulating film <b>72</b> does not extend to the junction terminating region portion and the p type guard ring layers <b>62</b> are formed in the junction terminating region portion.

0103(7) Seventh Embodiment

0104<figref idref="DRAWINGS">FIG. 17</figref> is a plan view showing a schematic structure of a seventh embodiment of a semiconductor device according to the present invention. <figref idref="DRAWINGS">FIG. 18</figref> is a cross-sectional view of the semiconductor device of the present embodiment taken along the cutting line A—A of <figref idref="DRAWINGS">FIG. 17</figref>. Note that the cross-sectional view taken along the cutting line B—B of <figref idref="DRAWINGS">FIG. 17</figref> is the same as <figref idref="DRAWINGS">FIG. 3</figref>.

0105In addition to the structure of the semiconductor device <b>5</b> in the above mentioned fifth embodiment, a semiconductor device <b>7</b> of the present embodiment further comprises insulating films <b>76</b> formed in the vertical direction in the junction terminating region portion, and n type drift layers <b>166</b> and p type drift layers <b>168</b> which are respectively formed in the vertical direction in the junction terminating region portion and which are periodically disposed in the horizontal direction. In accordance with such a structure, the depletion layers sufficiently extend at the time of turning-off because the positive holes in the p type drift layers <b>168</b> are discharged in the vertical direction in the same way as in the horizontal direction, and a high breakdown voltage can thus be obtained.

0106(8) Eighth Embodiment

0107<figref idref="DRAWINGS">FIG. 19</figref> is a plan view showing a schematic structure of an eighth embodiment of a semiconductor device according to the present invention. <figref idref="DRAWINGS">FIG. 20</figref> and <figref idref="DRAWINGS">FIG. 21</figref> are cross-sectional views of the semiconductor device of the present embodiment taken along the cutting lines A—A and B—B of <figref idref="DRAWINGS">FIG. 19</figref>, respectively.

0108In the present embodiment, differently from the fifth embodiment shown in <figref idref="DRAWINGS">FIG. 11</figref>, the insulating films <b>76</b> and the drift layers <b>26</b>a, <b>28</b>a, which are formed so as to extend from the cell region portion toward the junction terminating region portion, are periodically disposed in the vertical direction as well, and are formed up to the vicinity of the periphery of the junction terminating region portion. Further, on the surface portion of the junction terminating region portion, a p− type resurf layer <b>52</b> having a predetermined width is provided so as to surround the cell region. Moreover, electrodes <b>78</b> for voltage fixing are provided above or on the respective p type drift layers <b>28</b>a<b>4</b> through <b>28</b>a<b>7</b> periodically disposed in the vertical direction in the junction terminating region portion (see <figref idref="DRAWINGS">FIG. 20</figref>). These electrodes <b>78</b> are extendedly formed so as to bend in circular arcs having a center in common with the corner portion of a source electrode <b>38</b>a with a constant interval between one another, and so as to intersect the p type drift layers <b>28</b>al through <b>28</b>a<b>3</b>. The electrodes <b>78</b> are connected to these p type drift layers <b>28</b>a<b>1</b> through <b>28</b>a<b>3</b> at the extended portions (see <figref idref="DRAWINGS">FIG. 21</figref>).

0109In the semiconductor device <b>8</b> of the present embodiment, with the structure described above, positive holes in the p type drift layers <b>28</b>a<b>4</b> through <b>28</b>a<b>7</b> periodically provided in the vertical direction are discharged via the electrodes <b>78</b> at the time of turning-off. Therefore, the depletion layers are uniformly extended in the two directions of the horizontal and the vertical directions. Thus, a high breakdown voltage can be maintained.

0110(9) Ninth Embodiment

0111<figref idref="DRAWINGS">FIG. 22</figref> is a plan view showing a schematic structure of a ninth embodiment of a semiconductor device according to the present invention. <figref idref="DRAWINGS">FIG. 23</figref> is a cross-sectional view of the semiconductor device of the present embodiment taken along the cutting line A—A of <figref idref="DRAWINGS">FIG. 22</figref>. Note that the cross-sectional view taken along the cutting line B—B of <figref idref="DRAWINGS">FIG. 22</figref> is the same as <figref idref="DRAWINGS">FIG. 3</figref>.

0112Differently from the above-described eighth embodiment, in a semiconductor device <b>9</b> of the present embodiment, insulating films <b>84</b>, which are formed in stripe shapes in the respective horizontal directions in the junction terminating region portion and which are periodically disposed in the vertical direction, and n type drift layers <b>172</b> which are formed so as to surround the insulating films <b>84</b>, are respectively divided in the horizontal direction, and are formed so as to be lattice-shaped in a plan view. Thereby, portions of the p type drift layers <b>178</b> in the horizontal directions are connected to one another in the vertical directions. In accordance with the connecting structure of the p type drift layers <b>178</b> in the vertical direction, positive holes are discharged at the time of turning-off. Further, in the same way as in the first embodiment described above, the semiconductor device <b>9</b> of the present embodiment comprises a fieldplate electrode <b>48</b> which is formed so as to connect to the p type base layer <b>30</b>a formed so as to surround the cell region and which is formed so as to extend onto the insulating film <b>46</b> formed on the junction terminating region portion. Thereby the electric field in the junction terminating region portion is attenuated. As a result, a sufficiently high breakdown voltage can be obtained.

0113(10) Tenth Embodiment

0114<figref idref="DRAWINGS">FIG. 24</figref> is a plan view showing a schematic structure of a tenth embodiment of a semiconductor device according to the present invention. <figref idref="DRAWINGS">FIG. 25</figref> and <figref idref="DRAWINGS">FIG. 26</figref> are cross-sectional views of the semiconductor device of the present embodiment taken along the cutting lines A—A and B—B of <figref idref="DRAWINGS">FIG. 24</figref>, respectively.

0115A semiconductor device <b>10</b> of the present embodiment comprises Resistive Field Plates RFPs (which are hereinafter called as RFPs) <b>50</b> which are made from semi-insulated polysilicon or the like and are formed in the junction terminating region portion so as to surround the cell region, in place of the p− type resurf layer <b>52</b> and the electrode <b>78</b> of the semiconductor device <b>8</b> shown in <figref idref="DRAWINGS">FIG. 19</figref>. The RFPs <b>50</b> are, directly or via the p type base layer <b>30</b> in the vicinity of the boundary with the cell region, connected to the source electrode <b>38</b>a, and are connected to the p type drift layers <b>28</b>a. In particular, the p type drift layers <b>28</b>a<b>1</b> and <b>28</b>a<b>2</b>, which correspond to the portion at which the p type drift layers <b>28</b> in the cell region portion are extended in the horizontal direction, contact the RFPs <b>50</b> over substantially the entire length thereof (see <figref idref="DRAWINGS">FIG. 26</figref>). Further, the p type drift layers <b>28</b>a<b>4</b> through <b>28</b>a<b>7</b>, which are periodically formed in the vertical direction in the junction terminating region portion, discretely contact the RFPs <b>50</b> over a width corresponding to the width of the cell region portion in the horizontal direction (see <figref idref="DRAWINGS">FIG. 25</figref>).

0116With such a structure, a sufficient high breakdown voltage can be realized in the semiconductor device <b>10</b> because positive holes are discharged from the p type drift layers <b>28</b>a to the source electrodes <b>38</b>a via the RFPs <b>50</b> at the time of turning-off.

0117(11) Eleventh Embodiment

0118<figref idref="DRAWINGS">FIG. 27</figref> is a cross-sectional view showing a schematic structure of an eleventh embodiment of a semiconductor device according to the present invention.

0119A vertical type power MOSFET <b>11</b> shown in <figref idref="DRAWINGS">FIG. 27</figref> comprises a semiconductor layer <b>102</b> forming a n− base layer, an n+ drain layer <b>100</b>, a drain electrode <b>40</b>, a plurality of p type resurf layers <b>106</b>, <b>130</b> forming the super junction structure, p type base layers <b>108</b>, n+ type source layers <b>110</b>, gate electrodes <b>114</b>, and source electrodes <b>116</b>.

0120The n+ type drain layer <b>100</b> is formed on one surface of the n− type base layer <b>102</b>, i.e., on the bottom surface in <figref idref="DRAWINGS">FIG. 27</figref>, and the drain electrode <b>40</b> is formed on the n+ drain layer <b>100</b>.

0121The p type resurf layers <b>106</b>, <b>130</b> are periodically disposed in a predetermined direction not only in the cell region portion but also in the junction terminating region portion, on the other surface portion of the n− type base layer <b>102</b>, i.e., the top surface portion in <figref idref="DRAWINGS">FIG. 27</figref>. Thereby, a super junction structure is formed, and the p type resurf layer <b>106</b> functions as the p type drift layer <b>106</b>. Further, region portions sandwiched by these p type drift layers <b>106</b> of the n− type base layers <b>102</b> function as the n− type drift layer <b>102</b>.

0122The p type base layer <b>108</b> is selectively formed so as to connect to the p type drift layer <b>106</b> at the surface portion of the n− type base layer <b>102</b> in the cell region portion. The n+ type source layer <b>110</b> is selectively diffusion-formed so as to have a striped plane shape in the surface portion of the p type base layer <b>108</b>. The p type base layer <b>108</b> is formed such that, for example, when its impurity concentration is about 3×10¹⁷cm⁻³, the depth is about 2.0 μm, and the n+ type source layer <b>110</b> is formed such that, for example, when its impurity concentration is about 1×10²⁰cm⁻³, the depth is about 0.2 μm.

0123The gate electrode <b>114</b> is formed via a gate insulating film <b>112</b> e.g. an Si oxide film <b>112</b> whose film thickness is 0.1 μm on the surface region from the surface of the n+ type source layer <b>110</b> and the surface of the p type base layer <b>108</b> up to the surface of the adjacent p type base layer <b>108</b> and the surface of the n+ type source layer <b>110</b> via the surface of the n− type drift layer <b>102</b>. The gate electrode <b>114</b> is formed so as to be a striped plane shape. The source electrode <b>116</b> is formed so as to be a striped plane shape on the surface region of the n+ type source layer <b>110</b> in the surface portion of the p type base layer <b>108</b>, the surface region of the p type base layer <b>108</b>, and the surface region of the adjacent n+ type source layer <b>110</b>. The source electrodes <b>116</b> are disposed so as to sandwich the gate electrode <b>114</b>.

0124On the super junction structure in the junction terminating region portion of the vertical type power MOSFET <b>11</b>, a conductive film <b>117</b> such as metal, polysilicon, or the like is formed via the insulating film <b>126</b>. Thereby, a field plate structure is constituted in the junction terminating region portion. Note that a field stopper <b>42</b> is provided on the surface portion of the periphery of the device, which is formed from an n layer and stops depletion.

0125With such a structure, the super junction structure portion in the junction terminating region portion is rapidly depleted by the field plate <b>128</b> at the time of applying high voltage, and the junction terminating region portion then equivalently becomes a low impurity concentration layer. Therefore, the concentration of an electric field in the junction terminating region portion is suppressed, and a high breakdown voltage is maintained. Note that even if a resurf layer is formed on the surface portion in the junction terminating region portion, the super junction structure portion is rapidly depleted in the same way as the field plate. Therefore, the same effects can be obtained. In <figref idref="DRAWINGS">FIG. 27</figref>, the field plate <b>117</b> has a structure having an electric potential which is the same as the source electrode <b>116</b>. However, it is not limited to this structure, and the field plate <b>117</b> may be manufactured so as to have the same electric potential as the gate electrode <b>114</b>.

0126Due to the impurity amount of the p type drift layer <b>130</b> in the junction terminating region portion being greater than the impurity amount of the p type drift layer <b>106</b> in the cell region portion, decrease of breakdown voltage in the junction terminating region portion can be suppressed. The impurity amount of the p type drift layers <b>106</b>, <b>130</b> is a product of the width and the impurity concentration, respectively.

0127In <figref idref="DRAWINGS">FIG. 27</figref>, although the p type drift layer <b>130</b> in the junction terminating region portion is formed so as to have a width which is wider than that of the p type drift layer <b>106</b> in the cell region portion, the p type drift layer <b>130</b> is formed so as to have an impurity concentration which is the same as that of p type drift layer <b>106</b>. Thereby, the impurity amount of the p type dopant in the junction terminating region portion increases, and as a result, decrease of breakdown voltage in the junction terminating region portion can be suppressed.

0128Note that the present invention is not limited to this structure. For example, when the width of the p type drift layer <b>106</b> in the cell region portion and the width of the p type drift layer <b>130</b> in the junction terminating region portion are made to be the same, and only the impurity concentration in the junction terminating region portion is made to be higher, the same effects can be obtained.

0129<figref idref="DRAWINGS">FIG. 28</figref> is a graph showing changes in breakdown voltage when the amount of the p type impurity is changed, with respect to the cell region portion and the junction terminating region portion, respectively. The abscissa of the graph is the ratio of the impurity amount Np of the p type drift layer with respect to the impurity amount Nn of the n− type drift layer. As shown in the graph, it can be understood that, in the cell region portion, the highest breakdown voltage can be obtained when the impurity amount of the n− type drift layer and the impurity amount of the p type drift layer are equal (the unbalance is 0%), and if the impurity amount of the p type drift layer is relatively higher or lower, the breakdown voltage symmetrically decreases around the point of 0% in accordance with the proportion. On the other hand, it can be understood that, in the junction terminating region portion, the highest breakdown voltage can be obtained when the impurity amount of the p type drift layer is relatively 10% higher. Thus, the optimum impurity amounts of the p type drift layer in the cell region portion and in the junction terminating region portion are different from one another. If the p type drift layer is formed also in the junction terminating region portion so as to have a concentration which is the same as the optimum concentration for the p type drift layer in the cell region portion, the breakdown voltage in the junction terminating region portion decreases. As is clear from <figref idref="DRAWINGS">FIG. 28</figref>, the optimum impurity amount in the junction terminating region portion is higher than that in the cell region portion.

0130The impurity amount of the p type drift layer in the cell region portion is optimally set to 80 to 120% of that of the n− type drift layer, including the process margin. The impurity amount of the p type drift layer in the junction terminating region portion is optimally set to 90 to 130% of that of the n− type drift layer, including the process margin. Therefore, the impurity amount of the p type drift layer at the terminating portion is preferably set to 75 to 163% of the impurity amount of the p type drift layer in the cell region portion. The impurity amount of the p type drift layer, at which the highest breakdown voltage can be obtained, is higher at the terminating portion. Therefore, the impurity amount of the p type drift layer at the terminating portion is more preferably set to 100 to 163% of the impurity amount in the cell region portion.

0131The method for forming the super junction structure may be any of, for example, a method in which an ion injection and buried crystal growth are repeated, a method in which a trench groove is formed and buried epitaxy is carried out, and a method in which an ion injection is carried out from an oblique direction after a trench groove is formed.

0132It is possible to increase the p type drift layer concentration in the junction terminating region portion in accordance with each method of forming the super junction structure.

0133In the method in which the super junction structure is formed by repeating ion injection and buried crystal growth, ion injection may be carried out individually in the cell region portion and in the junction terminating region portion, or an ion injection may be carried out at the same time in the cell region portion and the junction terminating region portion, with the mask opening width for ion injection being changed.

0134In the method in which, after a trench groove is formed, the trench groove interior is buried with crystal growth, or in the method in which the super junction structure is formed by carrying out ion injection or gaseous phase diffusion from an oblique direction, the trench groove width or the mesa width may be varied in the cell region portion and the junction terminating region portion.

0135Further, if the impurity amount of the p type drift layer is made to be the same in the cell region portion and in the junction terminating region portion, and the impurity amount of the n− type drift layer in the junction terminating region portion is made to be lower than that in the cell region portion, the same effects can be obtained.

0136(12) Twelfth Embodiment

0137<figref idref="DRAWINGS">FIG. 29</figref> is a cross-sectional view showing a schematic structure of a twelfth embodiment of a semiconductor device according to the present invention.

0138The semiconductor device <b>12</b> of the present embodiment is characterized in that the super junction structure is structured by p type drift layers whose cell pitches are different from one another in the cell region portion and the junction terminating region portion. Specifically, a cell pitch of a p type drift layer <b>132</b> in the junction terminating region portion is made to be narrower than that of the p type drift layer <b>106</b> in the cell region portion. Due to the cell width in the junction terminating region portion being made narrow, depletion in the junction terminating region portion then rapidly proceeds at the time of turning-off. As a result, a lowering of the breakdown voltage in the junction terminating region portion is suppressed.

0139<figref idref="DRAWINGS">FIG. 30</figref> is a graph showing changes in breakdown voltage with respect to the impurity balance between the p type drift layer and the n− type drift layer. The impurity concentration of the n− type drift layer is set to 2.5×10¹⁵cm⁻³. Comparing a case in which the cell pitch is 16 μm and a case in which the cell pitch is 8 μm, the decrease in the breakdown voltage is smaller with respect to the balance of the impurity in the case of 8 μm in which the cell pitch is narrower than 16 μm. Thereby, it can be understood that the margin with respect to the impurity concentration balance can be made larger by making the cell pitch narrower.

0140Moreover, focusing on the impurity amount balance between the n− type drift layer and the p type drift layer, even if the cell width is changed, the optimum impurity amount of the p type drift layer at which the highest breakdown voltage is obtained is greater than the impurity amount of the n− type drift layer. On the basis of this, it can be understood that, even in a case in which the cell width in the junction terminating region portion is made narrow, it is preferable that the impurity amount of the p type drift layer in the junction terminating region portion is greater than that in the cell region portion.

0141(13) Thirteenth Embodiment

0142<figref idref="DRAWINGS">FIG. 31</figref> is a cross-sectional view showing a schematic structure of a thirteenth embodiment of a semiconductor device according to the present invention.

0143The semiconductor device <b>13</b> of the present embodiment is characterized in the shape of a p type drift layer <b>134</b> in the junction terminating region portion. Specifically, the p type drift layer <b>134</b> is buried so as not to have a pillar-shaped cross-sectional shape as in the respective embodiments described above but so as to have a circular cross sectional shape. If the p type drift layer <b>134</b> structuring the super junction structure have such a circular cross sectional shape in the cell region portion, once it is depleted by turning-off in the p type drift layer, the depletion is maintained. However, in the present embodiment, the p type drift layers <b>134</b> in the junction terminating region portion does not affect the on operation of the semiconductor device <b>13</b> because the p type drift layers <b>134</b> in circular cross sectional shapes are formed only in the junction terminating region portion.

0144When the method in which ion injection and buried crystal growth are repeated is used in forming the super junction structure, if the cell pitch of the super junction structure in the junction terminating region portion is made narrow, the amount of dopant injecting ions is reduced in the terminating region. The p type drift layer <b>134</b> of the present embodiment has a structure which can be obtained when diffusion after burying and growing is used in order to solve such a problem. Specifically, in accordance with diffusion after burying and growing, the concentration of the buried p layer is higher in the cell region portion and is lower in the junction terminating region portion. As a result, the upper and lower p layers are connected in the cell region portion, and the p type drift layer is formed in a pillar-shaped cross sectional shape. But in the junction terminating region portion, the respective buried layers are not connected, and have circular cross sectional shapes. However, if the cell pitch is made too narrow in the junction terminating region portion, the p type drift layers which are adjacent to one another are connected to one another. Therefore, the cell pitch in the junction terminating region portion is preferably set to a value greater than or equal to half of the cell pitch in the cell region portion.

0145(14) Fourteenth Embodiment

0146<figref idref="DRAWINGS">FIG. 32</figref> is a cross-sectional view showing a schematic structure of a fourteenth embodiment of a semiconductor device according to the present invention. A semiconductor device <b>14</b> of the present embodiment is formed such that the cell width of the super junction structure in the junction terminating region portion is narrower than the cell width in the cell region portion, and is formed such that the mesa width of the p type drift layer <b>136</b> in the junction terminating region portion is relatively wider. Thereby, the impurity concentration of the p type drift layer <b>136</b> in the junction terminating region portion can be made higher than that in the cell region portion. With such a structure, lowering of the breakdown voltage in the junction terminating region portion can be suppressed in the semiconductor device <b>14</b> of the present embodiment.

0147(15) Fifteenth Embodiment

0148<figref idref="DRAWINGS">FIG. 33</figref> is a cross-sectional view showing a schematic structure of a fifteenth embodiment of a semiconductor device according to the present invention. As is clear in comparison with the semiconductor device <b>11</b> shown in <figref idref="DRAWINGS">FIG. 27</figref>, a semiconductor device <b>15</b> of the present embodiment is characterized in that it further comprises an n− type drift layer <b>142</b> provided between the super junction structure and the n+ drain layer <b>100</b>, and the n− type drift layer <b>142</b> and the super junction structure also constitute n type drift layers. The n− type drift layer <b>142</b> is formed so as to have an impurity concentration which is lower than that of the n− type drift layer <b>102</b> in the super junction structure. Even when such an n− type drift layer <b>142</b> is provided, because the breakdown voltage is determined by the depletion of the upper super junction structure, a junction terminating regional structure can be designed as in the semiconductor devices <b>1</b> through <b>10</b> in the super junction structure described above. In the semiconductor device <b>15</b> of the present embodiment, due to the width of the p type drift layer <b>130</b> in the junction terminating region portion being made wider than that of the p type drift layer <b>106</b> in the cell region portion, the p type impurity amount of the super junction structure in the junction terminating region portion is made greater than that in the cell region portion in the same way as in the eleventh embodiment shown in <figref idref="DRAWINGS">FIG. 27</figref>. Thereby, a decrease in the breakdown voltage in the junction terminating region portion can be suppressed.

0149(16) Sixteenth Embodiment

0150<figref idref="DRAWINGS">FIG. 34</figref> is a cross-sectional view showing a schematic structure of a sixteenth embodiment of a semiconductor device according to the present invention. In the same way as in the fifteenth embodiment described above, in a semiconductor device <b>16</b> shown in <figref idref="DRAWINGS">FIG. 34</figref>, n type drift layers are constituted by the n− type drift layer <b>142</b> and the super junction structure. The n− type drift layer <b>142</b> has an impurity concentration which is lower than that of the n− type drift layer <b>102</b> in the super junction structure. In the present embodiment, as the structure of the junction terminating region portion, due to the cell pitch of the super junction structure in the junction terminating region portion being made narrower than the cell pitch in the cell region portion, the margin with respect to the concentration balance between the p type drift layer <b>132</b> and the n− type drift layer <b>102</b> can be made wider. Moreover, if the impurity amount of the p type drift layer <b>132</b> in the junction terminating region portion is made greater than that in the cell region portion, a decrease in the breakdown voltage in the junction terminating region portion can be further suppressed.

0151(B) Embodiment of the Method of Manufacturing Semiconductor Device

0152<figref idref="DRAWINGS">FIGS. 35A through 35F</figref> are schematic cross-sectional views showing one embodiment of a method of manufacturing the semiconductor device according to the present invention. The present embodiment provides a method in which the super junction structures in the respective embodiments of the semiconductor device of the present invention described above are formed by carrying out crystal growth a small number of times.

0153In a conventional process in which ion injection and buried crystal growth are repeated, because the p type resurf layer (p type drift layer) is formed by diffusion, the crystal growth film thickness of one time cannot be made thick. Therefore, it is necessary to repeat ion injection and buried crystal growth five to seven times. Further, as another conventional process, there is a method in which the trench groove is buried with crystal growth after the trench groove is formed. In this case, the number of buried growths can be one time. However, such buried crystal growth has been difficult because the value of the aspect ratio of the trench groove anticipated in the super junction structure is high, specifically greater than or equal to 5.

0154As shown in <figref idref="DRAWINGS">FIGS. 35A through 35F</figref>, the manufacturing method of the present embodiment is characterized in that a trench buried crystal growth of low aspect ratio is repeated a plurality of times. Specifically, first, a trench groove <b>154</b> whose aspect ratio is half of the aspect ratio which will be finally required is formed in the n− type semiconductor layer <b>151</b> (<figref idref="DRAWINGS">FIG. 35A</figref>), and a p− type semiconductor layer <b>156</b> is epitaxially grown so as to bury the trench groove <b>154</b> (<figref idref="DRAWINGS">FIG. 35B</figref>). Next, the p− type semiconductor layer <b>156</b> is withdrawn back until the surface of the n− type semiconductor layer <b>151</b> is exposed, and a semiconductor layer <b>158</b> buried in the trench groove is obtained (<figref idref="DRAWINGS">FIG. 35C</figref>). Thereafter, the n− type semiconductor layer is further epitaxially grown so as to cover the n− type semiconductor layer <b>151</b> and the p− type semiconductor layer <b>158</b>, and an n− type semiconductor layer <b>160</b> having a film thickness which is the same as the film thickness of the p− type semiconductor layer <b>158</b> is formed (<figref idref="DRAWINGS">FIG. 35D</figref>). Next, a trench groove <b>162</b> matching the trench groove <b>154</b> is formed in the n− type semiconductor layer <b>160</b> (<figref idref="DRAWINGS">FIG. 35E</figref>). Finally, the n− type semiconductor layer <b>164</b> is epitaxially grown so as to cover the n− type semiconductor layer <b>153</b> and the p− type semiconductor layer <b>158</b> (<figref idref="DRAWINGS">FIG. 35F</figref>). In accordance with the semiconductor device manufacturing method of the present embodiment, because buried growth can be carried out with relative easy, the super junction structure can thus be formed by a number of crystal growths which is less than that of the conventional process in which ion injection and buried crystal growth are repeated.

0155Note that, in the present embodiment, the super junction structure can be formed by carrying out trench buried crystal growths twice. However, the present invention is not limited thereto. For example, the trench buried crystal growth may be repeated three times or more with the aspect ratio per one time being set to one of third of a required aspect ratio. Further, if the super junction structures of the first time and the second time are formed in a striped shape and are formed so as to intersect one another, alignment can be exactly carried out.

0156Embodiments of the present invention have been described above. However, the present invention is not limited to these embodiments, and can be modified and achieved within the scope and the sprits thereof. For example, in the respective embodiments described above, the super junction structure, the p type base layer, the n+ source layer, and the gate electrode are formed in striped shapes. However, they may be formed so as to be in lattice shapes or staggered shapes. Furthermore, vertical power MOSFETs using silicon (Si) serving as semiconductor materials have been described. However, as other materials, for example, diamond can be used in addition to compound semiconductors such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), or the like.