Integrated circuit for clock generation for memory devices

This patent application claims priority from German Patent Application No. 10 2007 020 005.8, filed 27 Apr. 2007, and from U.S. Provisional Patent Application No. 61/016,674, filed 26 Dec. 2007.

id="REI-00002" date="20180313"

PRIORITY/RELATED APPLICATIONS

id="REI-00002"

This Application is a Reissue Divisional of application Ser. No. 13/252,779, which is a Reissue Application of U.S. Pat. No. 7,668,022, Ser. No. 12/110,684, which claims priority from German Patent Application No. 10 2007 020 005.8, filed 27 Apr. 2007, and from U.S. Provisional Patent Application No. 61/016,674, filled 26 Dec. 2007.

FIELD OF THE INVENTION

The invention relates to an integrated electronic device for generating clock signals for DDR double data rate (DDR) memory devices.

BACKGROUND

On a typical buffered dual in-line memory module (DIMM) board, a number of memory modules and a memory buffer are arranged. The memory buffer constitutes the interface between the memory controller and the memory modules spread over the board. The memory modules (as, for example, Dynamic Random Access Memories or DRAMs) require a specific and precise timing at their data, address and clock inputs. As the memory boards (DIMM boards) have a dense routing in terms of numerous wires, providing suitable and exact timing of the data and address signals, as well as the corresponding clock signals, places a high requirement on the memory buffers. If the memory buffers fail to meet the requirements, the timing at the inputs to the memory devices may be different from the timing at the corresponding outputs of the controlling devices, which may impair the overall performance of the memory systems. In order to satisfy the different timing requirements, conventional solutions shift the phase of the clock signals. For this purpose, phase locked loops (PLL) with phase mixers or delay locked loops (DLL) are used to optimize the phase relationship of a clock signal with regard to a data signal. However, PLLs and DLLs consume a considerable amount of chip area. Further, as data throughput of the memory buffering devices increases, the power consumption and the heat produced in the memory buffering devices, in particular in the DLLs and PLLs, creates problems.

SUMMARY

It is an object of the invention to provide an electronic device for generating clock signals for DDR memory devices on DIMM boards suitable to flexibly satisfy the timing requirements, while being small in size and having less power consumption and less area consumption.

An electronic device for generating clock signals for DDR memory devices on DIMM boards according to a described example embodiment is adapted to transfer data and clock signals to and/or from a plurality of memory devices on a DIMM board. The electronic device includes a data buffer for buffering data; a clock divider for dividing a first clock signal having a first clock frequency to generate a second clock signal having a second clock frequency, the second clock frequency being an integer multiple of the first clock frequency; and a shift register including multiple flip-flops. The flip-flops have clock inputs for receiving the first clock signal. The shift register receives the second clock signal as a data input signal. In the shift register, the data output of a preceding flip-flop is coupled to the data input of a following flip-flop, so as to shift the second clock signal through the shift register in response to the first clock signal, thereby generating a plurality of shifted clock signals at the outputs of the flip-flops. A multiplexer coupled to the outputs of the flip-flops for selecting a shifted clock signal serves as an output clock signal for transmission of the buffered data to a memory device.

A memory buffer according to a described embodiment exploits the presence of two different clock signals (first and second clock signals) with different clock frequencies to generate a respective phase-shifted clock output signal to be used for data transmission of the buffered data. Clock dividers and shift registers were generally considered to be inappropriate for high speed and high precision clock generation, as the jitter contributed by each flip-flop adds up. The summed jitter of the preceding flip-flops in the clock divider and the shift register may then appear in the output clock signal, rendering the clock signal unsuitable for high speed applications. Yet, based on the recognition that the first clock signal can have a sufficiently small jitter, the invention may be implemented to overcome this prejudice.

The first clock signal is processed in a clock divider, the frequency of which is a fraction of the frequency of the first clock signal. Instead of using a PLL or a DLL architecture to produce a phase-shifted clock signal with an optimum phase relationship to the data to be transmitted, the invention may be implemented to make use of a shift register which is appropriately coupled to the first and the second clock. Each flip-flop of the shift register is clocked by the first clock signal and generates at its output a phase-shifted version of the second clock signal being delayed with respect to the second clock signal by one clock cycle of the first clock for each flip-flop. The so-produced phase-shifted clock signals are fed to a multiplexer, which is adapted to select one phase-shifted clock signal to be used for data transmission of the buffered data. Dependent on the respective requirements for a specific data transmission, an optimum clock signal can be selected. Since the memory buffer according to the described embodiment does not need PLLs or DLLs, power consumption and heat generation is considerably reduced with regard to conventional solutions. The chip area consumed by the shift register is much smaller than the area required by a PLL or DLL.

The electronic device, and in particular the shift register, implemented in accordance with the invention as described, may preferably be adapted to receive, to process and to output differential signals. Accordingly, the first clock signal may be a differential clock signal and the flip-flops of the shift register are preferably adapted to be clocked by the differential first clock signal. Further, the second clock signal may be a differential clock signal and the plurality of flip-flops of the shift register may be adapted to process the second clock signal as a differential data signal. A first group of the flip-flops of the shift register may be coupled to operate in response to a rising edge of the first clock signal, and a second group of the flip-flops of the shift register may be coupled to operate in response to a falling edge of the first clock signal, by simply interchanging the differential first clock signals at the clock inputs of the second group of flip-flops. An inverter, which would introduce unwanted phase shift, is not required. Further, according to this aspect of the implementation of the invention, only half a period of the fast clock signal is used for generating the phase-shifted derivatives of the second clock signal, which reduces granularity to half the clock period of the first clock signal (i.e., to ½ UI, where UI is a unit interval). By using differential flip-flops, any additional unwanted phase shift or skew due to inverters (or other additional gates) to produce inverted clock signals is avoided. Further, using flip-flops with differential clock and data inputs and differential data outputs allows the phase-shifted output clock signals to be produced using only half the number of flip-flops. If necessary, an electronic device according to the invention may further include clock generating means for recovering the first clock signal from the input data.

According to another aspect of the invention, the electronic device may further include circuitry for generating a third clock signal and a fourth clock signal from the first clock signal, wherein the third clock signal and the fourth clock signal are clock signals that are non-overlapping with respect to each other. Further, an electronic device according to an implementation of the invention may include a special flip-flop, which includes a first master stage for storing a first binary value in response to the third clock signal, a second master stage for storing a second binary value in response to the fourth clock, and a slave stage which is coupled to the first and the second master stages to receive and to store either the first or the second binary value in response to a fifth clock having twice the frequency of the input clock. This aspect of the invention relates to double data rate memory devices (DDR).

Data, which is to be written to the memory devices, is stored in a write FIFO for memory buffer applications. Typically, there are two banks of write FIFOs (for example, one bank for even and another bank for odd clock cycles) which run based on the second clock and an inverted second clock. The even and the odd data stored in the FIFO are re-sampled at twice the core frequency (frequency of the second clock). This usually requires use of a multiplexer, the select line of which is controlled by the core clock and a flip-flop run at twice the frequency. This conventional approach requires an additional clock having twice the clock rate of the core clock. Further, the conventional approach introduces additional latency. The approach according to some embodiments of the invention, in particular a new dual flip-flop architecture, reduces latency by at least six unit intervals (UI)—a unit interval being the length of one clock period of the first clock signal. This advantage is achieved by the newly provided architecture of the flip-flop. Accordingly, two master stages are clocked by two non-overlapping clock signals, such that single bit values are clocked into the two master stages in an alternating manner. A clock having twice the frequency of the input clock is used to clock the data from a selected one of the master stages to the single slave stage which is coupled to both master stages.

The first clock signal is source centered with respect to the data signals. Data signals in the context of the invention include command and address signals, as well as strobe signals or the like. The internal core clock of the memory buffer is preferably one of the shifted clock signals generated by the shift register. The multiplexer is preferably implemented as a tri-state solution comprising a plurality of tri-state buffers. The tri-state buffers are implemented to introduce the same phase shift relative to the respective clock signals. This is typically done by matching the layouts and wire lengths of the interconnections of the tri-state buffers. All clock signals are routed to the interface via a global clock tree with minimum skew and insertion delay, as well as balanced buffers which do not introduce duty cycle distortion. One of the shifted clock signals may be used as a core clock for generating the data as, for example, command and address signals or strobe signals.

The invention also provides a system for digital data processing. The system includes at least a DIMM board with (e.g., DDR) memory modules and an electronic device for generating clock signals and buffering data. The electronic device may be configured as set out above and include a shift register to derive a plurality of clock signals from a second clock by use of first clock, wherein the first clock has a clock frequency which is an integer multiple of the second clock. The relationship between the frequencies of the first and the second clocks may also include fractions of the first clock including, preferably, half a period of the first clock. This can be done by using, for example, rising and falling edges of the first clock.

In another aspect, the invention also provides a method for buffering data and generating clock signals for a plurality of memory modules on a DIMM board. The method according to the invention includes buffering input data for the memory modules, dividing the first clock signal (e.g., by a positive integer) to receive a second clock signal, and deriving a plurality of clock signals from the second clock signal by sequentially shifting the second signal using, e.g., the rising and/or falling edges of the first clock signal.

DETAILED DESCRIPTION OF THE DRAWINGS

Example embodiments of the invention are described below with reference to accompanying drawings, wherein:

<figref idref="DRAWINGS">FIG. 1</figref> shows a simplified block diagram of an embodiment of the invention;

FIG. 2 show a simplified block diagram of the clocking circuit of FIG. 1;

FIG. <b>2</b>3 shows a simplified schematic and a timing diagram of a shift register according to an embodiment of the invention;

FIG. <b>3</b>4 shows a simplified schematic of a differential shift register according to an embodiment of the invention;

<figref idref="DRAWINGS">FIG. 4</figref> shows a schematicFIGS. 5 and 6 show diagrams of a conventional double data rate generatorgenerators;

FIG. <b>5</b>7 shows a top level block diagram of a flip-flop according to the invention;

FIG. <b>6</b>8 shows a detailed schematic of a flip-flop according to the invention; and

FIG. <b>7</b>9 shows a clock signal selection circuit according to the invention; and

FIG. 10 shows a DIMM according to the invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

FIG.FIGS. <b>1</b>shows aand 2 show simplified block diagramdiagrams of an example implementation of an interface integrated circuit (IC) 100 in accordance with an embodiment of the invention. The interface circuit 100 generally comprises a clocking circuit 102, a data buffer 104, and an (optional) logic circuit 106. A data input receives data from a memory controller or the like (not shown). The input data D-IN applied at data input terminal has a bus width of N<b>2</b>. A clock input CLK receives a first clock signal CLK<b>1</b> in the form of a high speed clock. The input data D-IN comprises all kinds of data, address information and control information to be exchanged with memory modules or ICs 902-1 to 902-8 that are secured on a DIMM board or circuit board 906 and are in communication with an interface IC or module 100 (as shown in FIG. 10). The firstclock signal CLK<b>1</b> is divided by a clock divider 202 in block DIV-SHclocking circuit 102 to derive a secondclock signal CLK<b>20</b> (not shown in <figref idref="DRAWINGS">FIG. 1</figref>) having a lower frequency. The frequency of the firstclock signal CLK<b>1</b> will typically be an integer multiple of the frequency of the second clock signal CLK<b>20</b>. Block DIV-SHClocking circuit 102 also includes an internal shift register 204 (which may be similar to those described below in connection with FIGS. <b>2</b> and <b>3</b>3 and 4). The shift register 204 provides a plurality of phase-shifted derivatives of the second clock signal, a selected one of which may be chosen in response to applied selection signals SEL of bus width N<b>1</b>by way of multiplexer 206 (an example of which can be seen in greater detail in FIG. 9). Clock signals CLKXY and CLK-OUT have the specific phase of one (or more in the case of a bus) of the phase-shifted derivatives of clock signal CLK<b>20</b>, determined according to the applied selection signals SEL.

Clock signal CLKXY is used as a core clock. Signal CLKXY has the same frequency as CLK<b>20</b> and a specific phase relationship with respect to clock signals CLK<b>20</b> and CLK<b>1</b>. The phase of signal CLKXY is selected by one or more of the selection signals SEL. Also, the phase-shifted clock signals at the output pins CLK_OUT of bus width M are selected by selection signals SEL. The block designated by DIGLLogic circuit 106 represents an intermediate logic circuit that can include various additional digital logic, buffers or combinatorial logic which may be coupled between the input D-IN and an output buffer BUF<b>2</b>104. The bus width for data, command and address signals will vary according to the specific architecture of a particular implementation. Thus, the reference numbers N<b>1</b>, N<b>2</b>, N<b>3</b>, N<b>4</b> and M represent different possible bus width combinations.

FIG. <b>2</b>3 shows in more detail an example implementation of a shift register 204-1 of the type implemented in block DIV-SHclocking circuit 102. The second clock signal CLK<b>20</b> is fed as an input signal to the data input D of a first flip-flop FF<b>1</b>302-1. The first clock signal CLK<b>1</b>, with a frequency that is an integer multiple of the frequency of the second clock signal CLK20, is fed to the clock inputs of the flip-flops 302-1 to 302-4. The flip-flops FF<b>1</b>, FF<b>2</b>, FF<b>3</b> and FF<b>4</b>302-1 to 302-4 are coupled in typical shift register configuration, with the output Q of each preceding flip-flop (e.g., Q of FF<b>1</b>flip-flop 302-1) coupled to the data input D of each following flip-flop (e.g., D of FF<b>2</b>flip-flop 302-2). In this way, a number of phase-shifted clock signals CLK<b>21</b>, CLK<b>22</b>, CLK<b>23</b> and CLK<b>24</b> are produced, each being shifted by one clock cycle with respect to a preceding clock signal.

FIG. <b>3</b>4 shows a simplified schematic of a differential shift register 204-2 implementation according to an example embodiment of the invention. The differential shift register comprises six flip-flops FF<b>1</b> to FF<b>6</b>402-1 to 402-6. All flip-flops 402-1 to 402-6 receive differential clock signals CLK<b>1</b> and CLK<b>1</b>Z, where signal CLK<b>1</b>Z is the inverted version of signal CLK<b>1</b>. (A “Z” used at the end of the reference legend of a signal indicates the inverted form of the signal without the “Z”). The frequency of differential clock signals CLK<b>20</b>, CLK<b>20</b>Z is substantially smaller than the frequency of CLK<b>1</b>, CLK<b>1</b>Z. In the present embodiment, the frequency of signal CLK<b>1</b> may, e.g., be six times the frequency of signal CLK<b>20</b>. Signal CLK<b>20</b> can be derived from signal CLK<b>1</b> in known ways using a clock divider 202. The circuit shown in FIG. <b>3</b>4 serves to provide twelve derivative clock signals CLK<b>21</b>-to CLK<b>32</b> of the slower clock signal CLK<b>20</b>. Flip-flops FF<b>1</b>, FF<b>2</b> and FF<b>3</b>402-1 to 402-3 are clocked by the rising edge of signal CLK<b>1</b>, whereas FF<b>4</b>, FF<b>5</b> and FF<b>6</b>flip-flops 402-4 to 402-6 are clocked by the falling edge of signal CLK<b>1</b> (i.e., the rising edge of CLK<b>1</b>Z). This is achieved by simply interchanging the differential clock signals CLK<b>1</b>, CLK<b>1</b>Z at the clock inputs of the two groups of flips-flops. An additional inverter is not needed. Therefore, e.g., for DDR applications, using differential clock signals, such as signals CLK<b>1</b> and CLK<b>1</b>Z, in a fully differential approach without an inverter is particularly useful. The propagation delay of even a single inverter (or any other single gate) would introduce additional and unwanted phase shift in the range of several percent of the period of the clock signals. Because the rising and falling edges of the fast signal CLK<b>1</b> are used, the derivativederivative signals CLK<b>21</b>-CLK<b>32</b> are shifted with respect to each other by half the period of signal CLK<b>1</b> (½ UI). So, the granularity of the phase shifter is reduced to ½ UI of the fast clock signal CLK<b>1</b>.

Preferably, signal CLK<b>20</b> may be inverted before being fed to the input of the phase shifter 204-2 shown in FIG. <b>3</b>4. This may be helpful to compensate for the delays (including setup and hold times and propagation delays, etc.) of the flip-flops. The phase shifter 204-2 shown in FIG. <b>3</b>4 may preferably be used in the DIV-SH stageclocking circuit 102 shown in <figref idref="DRAWINGS">FIG. 1</figref>. The phase shifter 204-2 may be adapted to accommodate different numbers of phase-shifted clock derivatives, as needed.

<figref idref="DRAWINGS">FIG. 4</figref> shows a simplified schematic FIGS. 5 and 6 show diagrams of a configuration used in prior art electronic devices for double data rate data output. In the memory buffer (similar to buffer 104), the data to be written to the memory devices (i.e., memory devices 902-1 to 902-8) is to be stored in a write FIFOfirst-in-first-out (FIFO) for the different memory buffer applications. There are typically two banks 502 and 504 of write first-in first-out (FIFO)FIFO buffers FF<b>03</b> and FFE<b>3</b>602 and 604, which run from the core clock CLKO and the inverted core clock CLKE. The data stored in FF<b>03</b> and FFE<b>3</b>buffers 602 and 604 is alternately fed by multiplexer MUX606 to the output pin (or pins) D_DDR by a core clock CLKR having twice the frequency of the clock signals CLKO and CLKE used for the FIFOs. Therefore, the approach shown in <figref idref="DRAWINGS">FIG. 4</figref>FIGS. 5 and 6 requires an additional clock at twice the frequency of the core clock rate and adds latency.

FIG. <b>5</b>7 shows a simplified block diagram of an example flip-flop 700 according to an aspect of the invention for the data buffer 104 that can be used to form a write FIFO circuit. As with the conventional approach shown in FIG. 4, two complementary clock signals CLK_EVEN and CLK_ODD are fed to the flip-flop FFD700. Further, corresponding data signals D_EVEN and D_ODD are supplied to the flip-flop 700. In the example implementation according to the invention, the flip-flop 700 (or additional circuitry) generates two non-overlapping clock signals CLK<b>3</b> and CLK<b>4</b> as illustrated by the waveforms below the flip-flop, and the data D_EVEN and D_ODD is source centered with respect to either signals CLK<b>3</b> or CLK<b>4</b>.

FIG. <b>6</b>8 shows a more detailed schematic of the flip-flop 700 of FIG. <b>5</b>7. The first master stage 704-1 includes two transmission gates T<b>1</b> and T<b>3</b>712-1 and 712-2 being clocked by respective clock signals CKT<b>1</b>, CKT<b>1</b>Z, where signal CKT<b>1</b>Z is the inverted clock with respect to signal CKT<b>1</b>. Further, the first master stage 704-1 includes inverters INV<b>1</b>inverter 708-1 and clocked inverter INV<b>1</b>Cor tri-state inverter 710-1. The second master stage 704-2 includes the two transmission gates T<b>0</b>, T<b>2</b>712-4 and 712-3 and inverter INV<b>2</b>708-2, as well as clocked inverter INV<b>2</b>C710-2. The slave stage 706 includes inverters INV<b>3</b>inverter 708-3 and clocked inverter INV<b>3</b>C710-3. The slave stage 706 is coupled to the outputs of both master stages 704-1 and 704-2 via transmission gates T<b>3</b> and T<b>2</b>712-2 and 712-3. The master stages 704-1 and 704-2 receive respective data signals D<b>1</b> and D<b>0</b>, one being the even, the other being the odd data as explained with respect to FIG. <b>5</b>7. Accordingly, the first master stage 704-1 stores the data received via input pin D<b>1</b> and the second master stage 704-2 stores the data received via input pin D<b>0</b>. The clock signals CKT<b>1</b>, CKT<b>1</b>Z, CKT<b>0</b>, CKT<b>0</b>Z may be derived in known ways from the third and the fourth clock signals CLK<b>3</b> and CLK<b>4</b> shown in FIG. <b>5</b>7 using control circuit 702. Further, an inverted versionsignal ZCLRZ of the clock signal CLRZ (which can function as a select signal similar to signal CLKR of FIG. 4) is produced by inverter INV<b>4</b>708-6. Inverters INV<b>5</b>-INV<b>8</b>708-4, 708-5, 708-7 and 708-8 are used for clock signals CKT<b>1</b>, CKT<b>1</b>Z, CKT<b>0</b>, CKT<b>0</b>Z.

With respect to the prior art circuit shown in <figref idref="DRAWINGS">FIG. 4</figref>FIGS. 5 and 6, the flip-flop implementation700 according to the invention saves a considerable amount of chip area. Each of the flip-flops shown in <figref idref="DRAWINGS">FIG. 5</figref>700 includes at least a master and a slave stage. The invention provides the same, or even a better functionality in terms of speed and power dissipation, and saves the multiplexer, the control logic and signals for the multiplexer and a slave stage.

FIG. <b>7</b>9 shows an example of a multiplexer 206 that employs tri-state bufferbuffers or inverters 802-1 to 802-5 according to the invention. The clock signals CLK<b>20</b>, CLK<b>21</b>, CLK<b>22</b>, CLK<b>23</b> and CLK<b>24</b> are supplied, respectively, to a number of tri-state buffers 802-1 to 802-5, each having a corresponding selection input SEL<b>20</b>, SEL<b>21</b>, SEL<b>22</b>, SEL<b>23</b> and SEL<b>24</b>. The output signal CLK_OUT is selected from the phase-shifted clock input signals CLK<b>20</b>-to CLK<b>24</b> in response to the applied selection signals. The unselected tri-state buffers of the clock signals which are not selected(i.e., 802-1) can be set in a high impedance state. The tri-state buffermultiplexer 206 may preferably be used in the DIV-SH block of <figref idref="DRAWINGS">FIG. 1</figref>clocking circuit 102. The tri-state buffer may be adapted to any specific number of phase-shifted derivatives of the clock signals.

Those skilled in the art to which the invention relates will appreciate that the described implementations are merely representative examples, and that many other implementations are possible within the scope of the claimed invention.