Stacked microelectronic assemblies with central contacts

CROSS REFERENCE TO RELATED APPLICATIONS

0001This application claims the benefit of the filing date of U.S. Provisional Patent Application No. 60/519,130 filed Nov. 12, 2003, the disclosure of which is hereby incorporated herein by reference.

BACKGROUND OF THE INVENTION

0002The present invention relates to stacked microelectronic assemblies and methods of making such assemblies, to methods of forming such assemblies and to components useful in such assemblies.

0003Semiconductor chips are commonly provided as individual, prepackaged units. A standard chip has a flat, rectangular body with a large front face having contacts connected to the internal circuitry of the chip. Each individual chip typically is mounted in a package which, in turn, is mounted on a circuit panel such as a printed circuit board and which connects the contacts of the chip to conductors of the circuit panel. In many conventional designs, the chip package occupies an area of the circuit panel considerably larger than the area of the chip itself. As used in this disclosure with reference to a flat chip having a front face, the “area of the chip” should be understood as referring to the area of the front face. In “flip chip” designs, the front face of the chip confronts the face of the circuit panel and the contacts on the chip are bonded directly to the circuit panel by solder balls or other connecting elements. The “flip chip” design provides a relatively compact arrangement; each chip occupies an area of the circuit panel equal to or slightly larger than the area of the chip's front face. However, this approach suffers from cost and reliability problems. As disclosed, for example, in certain embodiments of commonly-assigned U.S. Pat. Nos. 5,148,265; 5,148,266; and 5,679,977 the disclosures of which are incorporated herein by reference.

0004Certain innovative mounting techniques offer compactness approaching or equal to that of conventional flip-chip bonding without the reliability and testing problems commonly encountered in that approach. Packages which can accommodate a single chip in an area of the circuit panel equal to or slightly larger than the area of the chip itself are commonly referred to as “chip-sized packages.”

0005Besides minimizing the planar area of the circuit panel occupied by microelectronic assembly, it is also desirable to produce a chip package that presents a low, overall height or dimension perpendicular to the plane of the circuit panel. Such thin microelectronic packages allow for placement of a circuit panel having the packages mounted therein in close proximity to neighboring structures, thus producing the overall size of the product incorporating the circuit panel. Various proposals have been advanced for providing plural chips in a single package or module. In the conventional “multi-chip module”, the chips are mounted side-by-side on a single package substrate, which in turn can be mounted to the circuit panel. This approach offers only limited reduction in the aggregate area of the circuit panel occupied by the chips. The aggregate area is still greater than the total surface area of the individual chips in the module.

0006It has also been proposed to package plural chips in a “stack” arrangement i.e., an arrangement where plural chips are placed one on top of another. In a stacked arrangement, several chips can be mounted in an area of the circuit panel that is less than the total area of the chips. Certain stacked chip arrangements are disclosed, for example, in certain embodiments of the aforementioned U.S. Pat. Nos. 5,679,977 and 5,148,265 patents, and U.S. Pat. No. 5,347,159, the disclosure of which is incorporated herein by reference. U.S. Pat. No. 4,941,033, also incorporated herein by reference, discloses an arrangement in which chips are stacked on top of another and interconnected with one another by conductors on so-called “wiring films” associated with the chips.

0007Despite these efforts in the art, further improvements would be desirable in the case of multi-chip packages for chips having contacts located substantially in central regions of the chips. Certain semiconductor chips, such as some memory chips, are commonly made with the contacts in one or two rows located substantially along a central axis of the chip.

SUMMARY OF THE INVENTION

0008One aspect of the present invention provides microelectronic assemblies including at least two microelectronic elementelements having central contacts. A first microelectronic element faces downward and underlies a portion of the second microelectronic element. In the preferred embodiments, according to this aspect of the invention, the first and second microelectronic elements are provided with contacts located on front surfaces on the microelectronic elements. The contacts are disposed on a central region of the microelectronic elements. One or both of the microelectronic elements are electrically connected to terminals on the dielectric elements. Apertures may be included with the dielectric elements wherein the apertures underlie central regions of the microelectronic elements so that the dielectric element does not obstruct the contacts on the microelectronic elements. In certain, more preferred embodiments, terminals on the dielectric element are mobile relative to the first and second microelectronic elementelements. In certain, more preferred embodiments, a spacer may be provided so as to underlie a second portion of the second microelectronic element. The spacer layer is placed on an opposing side of the second microelectronic element as compared to the first microelectronic element with the central region of the second microelectronic element being located between the spacer and the first microelectronic element. An adhesive layer may be used to connect the spacer layer or the first microelectronic element or both to the second microelectronic element.

0009A stacked assembly, according to a further aspect of the present invention, includes a first microelectronic element, a second microelectronic element and a third microelectronic element. Each microelectronic element has contacts disposed on its front surface about a central region of the element. The second microelectronic element overlies a portion of the first microelectronic element and the third microelectronic element; however, the central region of the second microelectronic element is unencumbered by either of the two. The first microelectronic element and the second microelectronic element may have substantially similar structures. As with the previous embodiment of the present invention, an adhesive layer may be provided so as to connect the first and/or third microelectronic elements to the second microelectronic element. A dielectric element may be provided so as to underlie all of the microelectronic elements; however, apertures in the dielectric element are provided underlying central regions of the microelectronic elements so as to not encumber contacts disposed on these elements. As with the first embodiment of the present invention, wire leads connect the microelectronic elements to conductive features located on the dielectric element. In either of the embodiments, wire bonds connecting contacts on the microelectronic elements to conductive elements on the dielectric element may also take the form of wire leads, frangible leads, strip-like leads or the like.

0010A stacked assembly, according to even still a further aspect of the present invention, may include a first microelectronic element and a second microelectronic element. Both microelectronic elements having contacts disposed along their central regions may be directly connected to a circuit board or other microelectronic element via a mass of conductive material. Examples of this massive conductive material include solder, solder-core ball mass, a spring with solder fill, lands solder or the like. As is consistent with the stacked assemblies of the present invention, the second microelectronic element overlies at least a portion of the first microelectronic element. A spacer layer may be provided so as to underline a portion of the second microelectronic element opposite the first microelectronic element. Furthermore, the spacer layer may take the form of a third microelectronic element also being directly connected to a circuit board or the like.

0011In yet a still further aspect of the present invention, underlying microelectronic elements, such as the first microelectronic element and the third microelectronic element of any of the four described assemblies, may include bond ribbons. Bond ribbons may be used for connecting contacts disposed on the front surface of the microelectronic elements to terminals on the front surface of a dielectric element. Bond ribbons may be connected to the contacts of the underlying microelectronic elements and may be deformed to a vertical extensive position by moving the microelectronic elements and the dielectric element away from one another.

0012As with all embodiments of the present invention, an encapsulant material may be provided so as to cover and protect components of the microelectronic elements.

BRIEF DESCRIPTION OF THE DRAWINGS

0013<figref idref="DRAWINGS">FIG. 1</figref> is a diagrammatic sectional elevational view of the stacked assembly according to a first embodiment of the present invention;

0014<figref idref="DRAWINGS">FIG. 2</figref> is a bottom view of the stacked assembly according to a first embodiment of the present invention;

0015<figref idref="DRAWINGS">FIG. 3</figref> is a view similar to <figref idref="DRAWINGS">FIG. 1</figref> but depicting another embodiment of the present invention;

0016<figref idref="DRAWINGS">FIG. 4</figref> is a side view similar to <figref idref="DRAWINGS">FIG. 1</figref> but depicting another embodiment of the present invention;

0017<figref idref="DRAWINGS">FIG. 5</figref> is a block diagram side view depicting a basic design concept of the present invention; and

0018<figref idref="DRAWINGS">FIGS. 6</figref>, <b>7</b>, and <b>8</b> are similar to <figref idref="DRAWINGS">FIG. 1</figref> but depicting further embodiments of the present invention.

DETAILED DESCRIPTION

0019As shown in <figref idref="DRAWINGS">FIG. 1</figref>, a stacked microelectronic assembly <b>10</b> according to one embodiment of the present invention includes a first microelectronic element <b>12</b> and a second microelectronic element <b>14</b>. Microelectronic element <b>12</b> has a front surface <b>16</b> and a back surface <b>18</b> opposite the front surface <b>16</b>. Microelectronic element <b>12</b> further includes central region <b>13</b> and first and second end regions <b>15</b> and <b>17</b>, adjacent to central region <b>13</b>. Electrical contacts <b>20</b> are exposed on front surface <b>16</b>. As used in this disclosure, a statement that a conductive feature such as a terminal, contact, bonding pad or the like is “exposed on” a surface or structure means that it is accessible to be electrically connected with another conductive element which approaches the surface. The conductive feature may be flush with the specified surface, may project outwardly from such surface, or may be recessed relative to such surface.

0020Contacts <b>20</b> on the first microelectronic element <b>12</b> are exposed within central region <b>13</b> of front surface <b>16</b>. For example, contacts <b>20</b> may be formed as one or two parallel rows adjacent to the center of surface <b>16</b>. Microelectronic element <b>14</b> is arranged similarly to microelectronic element <b>12</b>, in that it has a front surface <b>22</b>, a back surface <b>24</b> opposite the front surface and electrical contacts <b>26</b> are exposed on the front surface <b>22</b>. Microelectronic element <b>14</b> also includes a central region <b>19</b> and first and second end regions <b>21</b> and <b>23</b> adjacent to central region <b>19</b>. In the first embodiment of the invention, as shown in <figref idref="DRAWINGS">FIG. 1</figref>, each microelectronic element <b>12</b> and <b>14</b> is a conventional semiconductor chip. Similarly, contacts <b>26</b> of second microelectronic element <b>14</b> are disposed within central region <b>19</b> of front surface <b>22</b> and may also be formed as one or two parallel rows adjacent the center of front surface <b>22</b>.

0021The front surface <b>16</b> of the first microelectronic element faces downwardly. Second microelectronic element <b>14</b> overlies first microelectronic element <b>12</b> with the front surface <b>22</b> of the second microelectronic element also facing downwardly. Front surface <b>22</b> of second microelectronic element <b>14</b> and back surface <b>18</b> of first microelectronic element <b>12</b> confront each other in a “front-to-back” configuration. With regard to the present disclosure, terms such as “downwardly” or “upwardly” are used to describe directions that are opposed to each other without regard to any gravitational frame of reference. Similarly, terms such as “over” and “under”, or “above” and “below” are used to describe the relative position to elements or assembly within the frame of reference of the assembly itself.

0022Second end region <b>23</b> of microelectronic element <b>14</b> overlies first end region <b>15</b> of microelectronic element <b>12</b>. The actual percentage of microelectronic element <b>14</b> which overlies microelectronic element <b>12</b> is not important but what is important is that the portion of front surface <b>22</b> of microelectronic element <b>14</b> which has disposed within in it contacts <b>26</b>, i.e. central region <b>19</b>, does not overlie microelectronic element <b>12</b>. Thus specific dimensions of central region <b>19</b> and first and second end regions <b>21</b> and <b>23</b> may fluctuate depending on where and how many contacts <b>26</b> are disposed on front surface <b>22</b>. Furthermore, a sufficient area of front surface <b>22</b> should overlie microelectronic element <b>12</b> so as to support microelectronic element <b>14</b>.

0023The assembly also includes a dielectric element <b>30</b> having a first surface <b>32</b> and a second surface <b>34</b> with electrically conductive terminals <b>36</b> exposed on second surface <b>34</b>. Dielectric element <b>30</b> includes aperture <b>33</b> located substantially under central region <b>13</b> of microelectronic element <b>12</b> so as not to obstruct contacts <b>20</b>. Microelectronic element <b>12</b> is disposed over first surface <b>32</b> of dielectric element <b>30</b> in a downwardly-facing orientation with front surface <b>16</b> confronting upwardly-facing first surface <b>32</b>. Preferably, dielectric element <b>30</b> comprises a layer of flexible material, such as a layer of polyimide, BT resin or other dielectric material of the type commonly utilized for making tape automated bonding (“TAB”) tapes, or a relatively rigid, board-like material such as a thick layer of fiber-reinforced epoxy as, for example, an Fr-4 or Fr-5 board and a layer of a die attach adhesive <b>31</b> defining the first surface <b>32</b>. Dielectric element <b>30</b> also includes additional conductive features including bond pads <b>40</b> exposed on second surface <b>34</b> and conductive traces <b>42</b> connecting bond pads <b>40</b> to terminals <b>36</b>.

0024As shown in <figref idref="DRAWINGS">FIGS. 1 and 2</figref>, leads <b>50</b> are in the form of wire bonds, and are used to connect contacts <b>20</b> of first microelectronic element <b>12</b> to some of the bond pads <b>40</b>. Other leads in the form of wire bonds <b>70</b> are used to connect contacts <b>26</b> of second microelectronic element <b>14</b> to other bond pads <b>40</b>. The dielectric element may further include a solder-mask layer <b>52</b> defining the second surface <b>34</b>, with apertures or holes at bond pads <b>40</b>. Preferably, at least some of the wire bonds <b>50</b>, <b>70</b> are connected through bond pads <b>40</b> and traces <b>42</b> to at least some of the terminals <b>36</b>.

0025Most preferably, all of the conductive features on the dielectric element are formed from a single layer of metal. This avoids the need for precise registration between multiple layers of metallic features and formation of interconnections between such layers during manufacture of the dielectric element. Additional metallic features (not shown) such as conductive planes for use as ground planes or power distribution planes may be provided.

0026An adhesive layer <b>60</b> may connect microelectronic elements <b>12</b> and <b>14</b>. Adhesive layer <b>60</b> may be a die-attach adhesive, and may be comprised of low elastic modulus material such as a silicone elastomer. However, where the two microelectronic elements are conventional semiconductor chips formed from the same material, they will tend to expand and contract in unison in response to temperature changes and, accordingly, a relatively rigid attachment as, for example, a thin layer of a high elastic modulus adhesive or solder can be employed.

0027As illustrated in <figref idref="DRAWINGS">FIG. 1</figref>, at least some of the terminals <b>36</b> are disposed beneath front surface <b>16</b> of microelectronic element <b>12</b>. At least some of the terminals <b>36</b> are movable with respect to the first electronic element <b>12</b> and hence with respect to at least some of contacts <b>20</b>.

0028Assembly <b>10</b> may further include an encapsulant <b>80</b> that covers leads <b>50</b>, <b>70</b> and protects the microelectronic elements <b>12</b>, <b>14</b>. The encapsulant may also be provided between the front surfaces <b>16</b>, <b>22</b> and the first surface <b>32</b>, thoroughly surrounding leads <b>50</b>, <b>70</b>, and may fill open spaces between microelectronic elements <b>12</b> and <b>14</b>. Preferred encapsulants comprise flexibilized epoxies or silicone elastomers.

0029Assembly <b>10</b> may further include a plurality of joining units, such as eutectic solder balls <b>81</b>, as shown in <figref idref="DRAWINGS">FIG. 1</figref>. Solder balls <b>81</b> are attached to terminals <b>36</b> and hence are electrically interconnected to at least some of the bond pads <b>40</b>, leads <b>50</b> and <b>70</b> and contacts <b>20</b> and <b>26</b>. Other types of joining units such as solid-core solid balls or masses or balls of a diffusion-bonding or eutectic bonding alloy, masses of conductive polymer composition, or the like may be employed. In use, the assembly is mounted on a circuit panel such as circuit board <b>95</b> having contact pads <b>94</b>. The second surface <b>34</b> of the dielectric element <b>30</b> faces downwardly towards the circuit board, and solder balls <b>81</b> are bonded to the contact pads of the circuit board, thus connecting the contact pads to the microelectronic elements. The contact pads on the circuit board are connected by traces on or in the circuit board to the other elements of an electrical circuit which must co-act with microelectronic elements <b>12</b> and <b>14</b>. During the bonding operation, and during operation of the completed circuit board and circuit, differential thermal expansion and contraction of the circuit board and chips may occur. This may be caused by the difference between the coefficient of expansion of the microelectronic elements and circuit board; by difference in temperature between the microelectronic elements and the circuit board; or by combinations of these factors. Such differential thermal expansion causes some or all of the contact pads <b>95</b> to move relative to the microelectronic element and contacts <b>20</b> and <b>26</b>. Desirably, movement of terminals <b>36</b> relative to microelectronic elements relieves some or all of the stress which would otherwise be imposed on solder balls <b>81</b> by relative movement of the terminals and contact pads. To enhance moveability of terminals <b>36</b> relative to the microelectronic elements, dielectric element <b>30</b> may include a compliant layer. For example, die attach adhesive <b>31</b> may be a compliant die attach adhesive. Additionally, movement of terminals allows for easier testability. This is due to the fact that if either terminals <b>36</b> or contact pads located on a tester are not in exact planer alignment, terminals <b>36</b> are sufficiently flexible so as to be able to align most terminals with a corresponding contact pad. In other words, movement of terminals <b>36</b> enhance the engageability of a test fixture to the microelectronic assembly.

0030Preferred combinations of the features described above allow the manufacture of a two-chip center stack assembly having a thickness of less than 1.2 mm above the terminals <b>36</b>. More preferably, such a thickness will be 0.7 mm (700 microns) or less.

0031In preferred embodiments of the present invention, joining units or solder balls <b>81</b> have a height of about 300 microns or less; more preferably, about 200 microns or less, and most preferably about 100 microns or less. Thus the overall height of the assembly above the circuit panel after assembly, including the height of the joining units, most preferably is about 1.5 mm or less, and most preferably about 1.3 mm or less. Joining units having such low heights, also know as “fine pitch” joining units, may be used to beneficially affect the assemblies wherein the terminals are moveable with respect to the microelectronic elements and relative to the contacts on the microelectronic elements. As discussed above, this moveability relieves the mechanical strain or deformation generated by differential thermal expansion of the microelectronic elements. Some of the deformation may also be relieved by flexure of the joining units connecting the assembly to a circuit panel, such as a printed circuit board. Larger joining units can flex to a greater extent than smaller ones and, therefore, relieve a greater amount of deformation without failure due to fatigue of the joining units. In preferred embodiments of the present invention, the movement of the terminals relative to microelectronic elements relieves a significant portion of such deformation, allowing the use of relatively small joining units while still maintaining acceptable levels of reliability. However, moveability is not essential in all embodiments.

0032An alternate embodiment of the present invention is shown in <figref idref="DRAWINGS">FIG. 3</figref>. Microelectronic assembly <b>100</b> is similar to microelectronic element assembly <b>10</b> but also includes a spacer layer <b>164</b> disposed beneath first end region <b>121</b> of second microelectronic element <b>114</b> and may overlay a portion of dielectric element <b>130</b>. Also, dielectric element <b>130</b> includes a second aperture aligned with the central region of the second microelectronic element. Spacer layer <b>164</b> is designed to balance and support microelectronic element <b>114</b> in conjunction with microelectronic element <b>112</b>. Desirably, spacer layer <b>164</b> is made of a compliant material that allows movement of dielectric element <b>130</b>, and hence movement of terminals <b>136</b>, relative to contacts <b>120</b> and <b>126</b>. Preferred materials for such compliant layers include epoxies and silicones, with flexibilized epoxies and silicone elastomers being particularly preferred. The leads <b>150</b>, <b>170</b> are flexible to permit such movement.

0033Encapsulant <b>180</b> may be provided so as to protect and seal assembly <b>100</b>, similar to assembly <b>10</b>. In addition, in embodiments that do not include a separate spacer layer <b>164</b>, the encapsulant may also be provided between the front surfaces <b>116</b>, <b>122</b> and the first surface <b>132</b>, thoroughly surrounding leads <b>150</b>, <b>170</b>, and may fill open spaces between microelectronic elements <b>112</b> and <b>114</b>.

0034It is preferred, although not necessary to the invention, that microelectronic elements <b>112</b> and <b>114</b> are attached to each other by means such as adhesive layer <b>160</b>. It is also preferred that microelectronic element <b>114</b> and spacer layer <b>164</b> are attached to each other by adhesive layer <b>160</b>.

0035In a third embodiment shown in <figref idref="DRAWINGS">FIG. 4</figref>, assembly <b>200</b> includes a third microelectronic element <b>202</b>, along with first and second microelectronic elements <b>212</b>, <b>214</b>. Third microelectronic element <b>202</b> includes front surface <b>203</b>, rear surface <b>204</b>, central region <b>205</b> and first and second end regions <b>206</b> and <b>207</b>. Electrical contacts <b>208</b> are disposed on front surface <b>203</b>. Assembly <b>200</b> may be substantially similar to assembly <b>100</b> discussed above with reference to <figref idref="DRAWINGS">FIG. 3</figref>. The one significant difference is that microelectronic element <b>202</b> replaces spacer layer <b>164</b> underlying microelectronic element <b>214</b>. Specifically, second end region <b>207</b> of microelectronic element <b>202</b> underlies first end region <b>221</b> of microelectronic element <b>214</b>. Consistent with the first embodiment of the present invention, the percentage of front surface <b>222</b> overlying microelectronic element <b>202</b> may fluctuate depending on the number of contacts <b>226</b> located on front surface <b>222</b> of microelectronic element <b>214</b>. In other words central region <b>219</b> of microelectronic element <b>214</b> must not overlie second end region <b>207</b> of microelectronic element <b>202</b>. However, the amount of front surface <b>222</b> of microelectronic element <b>214</b> overlying second end region <b>207</b> of microelectronic element <b>202</b> should be sufficient to support microelectronic element <b>214</b> in conjunction with microelectronic element <b>212</b>.

0036Similar to microelectronic <b>12</b> of <figref idref="DRAWINGS">FIG. 1</figref>, contacts <b>208</b> disposed on front surface <b>203</b> of microelectronic element <b>202</b> have wire bonds <b>250</b> in the form of leads for connecting contacts <b>208</b> to bond pads <b>240</b> of dielectric element <b>230</b>. Dielectric element <b>230</b> may include solder mass layer <b>252</b> defining second surface <b>234</b> of dielectric element <b>230</b> with apertures or holes at bond pads <b>240</b>. Dielectric element <b>230</b> can be seen as just a larger version of dielectric element <b>30</b> of assembly <b>10</b>. Apertures <b>233</b> are provided in dielectric element <b>230</b> so that dielectric element <b>230</b> does not obstruct leads <b>250</b> or <b>270</b>. The apertures are aligned with the central regions of each microelectronic element. Traces <b>242</b> connect the various conductive features to each other, as discussed in conjunction with the first embodiment of the present invention. Similarly, at least some of the leads <b>250</b> and <b>270</b> associated with microelectronic elements <b>202</b>, <b>212</b> and <b>214</b> are connected to at least some of the terminals <b>236</b>, whereas at least some bond pads <b>240</b> are also connected to at least some of the terminals <b>236</b>. Some or all of the bonds pads <b>240</b> may be connected with some or all of the leads <b>250</b> and <b>270</b>. Assembly <b>200</b> may further include an encapsulant <b>280</b> that covers the leads <b>250</b>, and <b>270</b> and protects the microelectronic element <b>212</b>, <b>214</b> and <b>202</b>. Encapsulant <b>280</b> is similar to encapsulant <b>80</b> and can be employed for similar purposes.

0037The assembly <b>200</b> can be thought of as a brick wall having an A-B-A configuration wherein A designates a lower tier element such as first microelectronic element <b>212</b> or third microelectronic element <b>202</b>, and B designates an upper tier microelectronic element such as second microelectronic element <b>214</b>, and with the contact-bearing central regions arranged in the order indicated. Each upper tier element B overlies a portion of at least one lower tier element A and A′ so as to form the structure shown in <figref idref="DRAWINGS">FIG. 4</figref>.

0038As shown in <figref idref="DRAWINGS">FIG. 5</figref>, a third embodiment of the invention makes use of the A-B-A configuration by continuing the structure horizontally outwards. <figref idref="DRAWINGS">FIG. 5</figref> is a skeletal depiction of a B-A-B-A-B configuration. The structure may have a configuration of A-B-A-B-A or A-B-A-B or B-A-B-A-B, or any other combination of the two where a structure A and a structure B are adjacent to one another. These structures could be extended out indefinitely until a required amount of microelectronics elements are met. Additionally, structures that follow varying designs such as having a plurality of A structures adjacent to one another without an overlying B structure may be employed.

0039In an alternate embodiment of the present invention as shown in <figref idref="DRAWINGS">FIG. 6</figref>, assembly <b>300</b> includes microelectronic elements denoted by the structure A altered so as to include a substantially continuous dielectric element <b>330</b> underlying at least one microelectronic element denoted A. For this discussion microelectronic element <b>312</b> will represent microelectronic elements having a structure equal to A. Contacts <b>320</b> are electrically connected to bond ribbons leads <b>390</b>. The bond ribbons may be of the type described in U.S. Pat. No. 5,518,964, the disclosure of which is incorporated by reference herein. As disclosed in certain embodiments of the '964 patent, the bond ribbons may be initially formed in place on the first surface of the dielectric element, and may initially extend in the plane of such surface. The bond ribbons may be connected to the contacts <b>320</b> of the first microelectronic element <b>312</b> and may be deformed to the vertical-extensive position depicted in <figref idref="DRAWINGS">FIG. 6</figref> by moving the first microelectronic element <b>312</b> and the dielectric element <b>330</b> away from one another after bonding the ribbons to the contacts of the first microelectronic element. Related bond ribbon configurations and methods of forming bond ribbons embodiments are discussed in U.S. Pat. Nos. 6,329,607; 6,228,686; 6,191,368; 5,976,913; and 5,859,472, the disclosures of which are also incorporated by reference herein.

0040In a further alternate embodiment as shown in <figref idref="DRAWINGS">FIG. 7</figref>, assembly <b>400</b> includes first microelectronic element <b>412</b> and second microelectronic element <b>414</b>. The microelectronic elements in assembly <b>400</b> may be substantially similar to the first and second microelectronic elements employed with assembly <b>10</b> of <figref idref="DRAWINGS">FIG. 1</figref>. However, assembly <b>400</b> differs from the previous assemblies in that the dielectric layer has not been included in the assembly. Additionally, masses of conductive material, preferably solder balls <b>481</b>, are employed for conductively connecting contacts <b>420</b> of first microelectronic element <b>412</b> to the circuit board. Similar masses <b>483</b> connect contacts <b>426</b> of second microelectronic element <b>414</b> directly to contacts <b>494</b> of circuit board <b>495</b>. In the mounted condition illustrated in <figref idref="DRAWINGS">FIG. 7</figref>, the masses <b>481</b> associated with the contacts <b>420</b> of the first microelectronic element have a lesser height than masses <b>483</b> associated with the second microelectronic element. Additionally, the conductive material may be comprised of other material as, for example, polymeric conductive materials, solid core solder balls, solder filled springs, solder land or the like. A combination of options may also be employed. As with all the previous embodiments, an adhesive layer (not shown) may connect microelectronic elements <b>412</b> and <b>414</b>. Additionally, an encapsulant (also not shown) as with all embodiments of the present invention may be included with assembly <b>400</b>. Although the elimination of the dielectric layer has been described with specific reference to assembly <b>400</b>, the dielectric layer may be also eliminated from other embodiments described herein. Additionally, conductively connecting contacts on microelectronic elements directly to contacts on a circuit board, as shown in <figref idref="DRAWINGS">FIG. 7</figref>, may be incorporated with other embodiments described within the present application.

0041The embodiment shown in <figref idref="DRAWINGS">FIG. 7</figref> may be assembled using various methods. For example, microelectronic element <b>412</b> may be preassembled to microelectronic element <b>414</b>. The entire assembly may then be surface mounted to circuit board <b>495</b> using solder balls <b>481</b> with standard surface mount techniques known in the art. Additionally, microelectronic element <b>412</b> may be surface mounted to circuit board <b>495</b> first and in a next step, microelectronic element <b>414</b> is surface mounted to the circuit board.

0042<figref idref="DRAWINGS">FIG. 8</figref> shows assembly <b>500</b> employing alternate conducting leads connecting contacts <b>520</b> and <b>526</b> to other conductive features of the assembly. Assembly <b>500</b> may include any or all of the features previously described in this reference herein in conjunction with other embodiments of the present invention. The one significant modification to assembly <b>500</b> is that strip-like leads <b>550</b> formed integrally with traces <b>542</b> are used to connect contacts <b>520</b> and <b>526</b> to conductive features of the microelectronic elements. The construction of such strip-like leads is described, for example, in commonly assigned U.S. Pat. No. 5,915,752, which is hereby incorporated by reference herein. As shown in <figref idref="DRAWINGS">FIG. 8</figref>, assembly <b>500</b> may include a spacer layer <b>564</b> underlying second microelectronic element <b>514</b>. As with all embodiments of the present invention, spacer layer <b>564</b> may be made of a compliant material or additionally, spacer layer <b>564</b> may be comprised of a small microelectronic element. In the case where spacer layer <b>564</b> is a small microelectronic element, the small microelectronic element may either not extend horizontally past second microelectronic element <b>514</b> or only extend slightly past the edge of microelectronic element <b>514</b>. Various adhesive layers and encapsulants may be included with assembly <b>500</b>, as described throughout this disclosure.

0043Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.