Writing system and method for phase change memory

CROSS REFERENCE TO RELATED APPLICATIONS

0001This application claims priority of Taiwan Patent Application No. 96142224, filed on Nov. 8, 2007 the entirety of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

00021. Field of the Invention

0003The invention relates to a writing system and method for a phase change memory.

00042. Description of the Related Art

0005With the growth in the use of portable electronic devices, demand for non-volatile memory has increased. Among the various kinds of non-volatile memory, phase change memory is the most competitive next generation non-volatile memory due to its higher speed, lower power consumption, higher capacity, reliability, easier process integration and lower cost.

0006The operation of a phase change memory is mainly achieved by inputting two current pulses with different current magnitudes to the phase change memory to switch the phase change memory between an amorphous state and crystalline state. According to Ohm-Joule's Law, when the current is input to the phase change memory, the phase change memory is heated. The phase change memory may thus be crystallized or melted based on different currents. Based on the described illustration, the logic state of the phase change memory can be switched by inputting different currents, enabling data storage. <figref idref="DRAWINGS">FIG. 1</figref> is a schematic diagram showing the writing current pulse and the reading current pulse of the phase change memory. When a RESET operation is applied to the phase change memory, a reset current I_RESETwith high amplitude and short pulse width is applied, the phase change memory is thus melted because the temperature of the phase change memory exceeds the melting temperature of the phase change material of the phase change memory, T_m. When the temperature of the phase change memory decreases, the state of the phase change memory is transformed to the amorphous state due to the insufficient cool down period. Thus, the phase change memory has high resistance. When a SET operation is applied to the phase change memory, a set current I_SETwith lower amplitude and longer pulse width is applied. The phase change memory is heated by the set current I_SET, and the temperature of the phase change memory is held substantially between the melting temperature T_mand a crystallizing temperature T_cof the phase change material used by the phase change memory. During the SET operation, the melted phase change memory has sufficient time for crystallizing and the phase change memory thus has a low resistance.

0007As described, the phase change memory respectively stores data with logic state 1 and 0 by the RESET operation and the SET operation. When reading the phase change memory, a read current I_READthe amplitude of which is less than the set current I_SET, is applied to the phase change memory to determine the logic state of the data stored in the phase change memory based on the sensed resistance.

BRIEF SUMMARY OF THE INVENTION

0008An embodiment of the writing system for a phase change memory based on the present application is disclosed. The writing system comprises a first phase change memory (PCM) cell, a second PCM cell, a first writing circuit and a verifying circuit. The first writing circuit executes a writing procedure, receives and writes a first data to the first PCM cell. The verifying circuit executes a verifying procedure and the circuit further comprises a processing unit and a second writing circuit. The processing unit reads and compares the data stored in the second PCM cell with a second data. The second writing circuit writes the second data to the second PCM cell when the data stored in the second PCM cell and the second data are not matched.

0009An embodiment of the invention provides a writing method for a phase change memory and the method is implemented by a first writing circuit and a verifying circuit. The method comprises performing a writing procedure to a first phase change memory (PCM) cell in a first cycle; performing a verifying procedure to a second PCM cell in the first cycle; and if the verifying result of the second PCM cell is matched, the verifying circuit outputs a current adjustment signal to the first writing circuit to adjust a first writing current output by the first writing circuit.

0010A detailed description is given in the following embodiments with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

0011The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

0012<figref idref="DRAWINGS">FIG. 1</figref> is a schematic diagram showing the writing current pulse and the reading current pulse of the phase change memory.

0013<figref idref="DRAWINGS">FIG. 2</figref> is a current-resistance characteristic curve diagram of a phase change memory.

0014<figref idref="DRAWINGS">FIG. 3</figref> is a schematic diagram of the control circuit for the phase change memory according to an embodiment of the invention.

0015<figref idref="DRAWINGS">FIG. 4</figref> is a flowchart of the writing procedure and the verifying procedure according to an embodiment of the invention.

0016<figref idref="DRAWINGS">FIG. 5</figref> is a timing diagram of a conventional writing procedure and verifying procedure for the phase change memory and the present innovative writing procedure and verifying procedure for the phase change memory.

0017<figref idref="DRAWINGS">FIG. 6</figref> is a schematic diagram of an embodiment of the writing system for the phase change memory according to the invention.

0018<figref idref="DRAWINGS">FIG. 7</figref> is a circuit diagram of a writing circuit and the auxiliary writing circuit according to an embodiment of the invention.

0019<figref idref="DRAWINGS">FIG. 8</figref> is a schematic diagram of a writing system for the phase change memory according to another embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

0020The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

0021<figref idref="DRAWINGS">FIG. 2</figref> is a current-resistance characteristic curve diagram of a phase change memory. Curve <b>21</b> is a current-resistance characteristic curve of a normal phase change memory. When the phase change memory receives the set current I_SET, the resistance of the phase change memory is substantially R_SET, and when the phase change memory receives the reset current I_RESET, the resistance of the phase change memory is substantially R_RESET. If the access number of the phase change memory increases, the current-resistance characteristic curve may drift, such as the curve <b>22</b>. Take the curve <b>22</b> for example, when the phase change memory receives the set current I_SET, the resistance of the phase change memory is still substantially R_SET, but when the phase change memory receives the reset current I_RESET, the resistance of the phase change memory is not R_RESET. Thus, the phase change memory can be normally accessed. In this situation, higher set current I_SETand reset current I_RESETare required to keep the phase change memory operating normally.

0022In another embodiment, the set current I_SETcannot maintain the resistance of the phase change memory R_SETdue to the process of the phase change memory. In this situation, a smaller set current I_SETand reset current I_RESETare required to keep the phase change memory operating normally.

0023<figref idref="DRAWINGS">FIG. 3</figref> is a schematic diagram of the control circuit for the phase change memory according to an embodiment of the invention. According to the architecture of the control circuit in <figref idref="DRAWINGS">FIG. 3</figref>, a read/write splitting structure is applied to increase the performance of the phase change memory. The reading and verifying circuit <b>31</b> comprises a reading circuit <b>34</b> and a verifying circuit <b>35</b> to verify the phase change memory cell matrix <b>33</b>. When the writing circuit <b>32</b> writes to the bit line <b>37</b> of the phase change memory cell matrix <b>33</b>, the reading and verifying circuit <b>31</b> verifies the PCM cell coupled to the bit line <b>36</b>. The reading circuit <b>34</b> reads and transmits the data stored in the PCM cell coupled to the bit line <b>36</b> to the verifying circuit <b>35</b>. The verifying circuit <b>35</b> compares the data from the reading circuit <b>34</b> with a reference data. When the data read by the reading circuit <b>34</b> is the same as the reference data, the PCM cell matrix <b>33</b> can be normally accessed. If the data read by the reading circuit <b>34</b> is not the same as the reference data, a control signal is output to the writing circuit <b>32</b> to adjust the magnitude of the output current thereof.

0024Typically, to increase the write speed of the phase change memory, the writing current is more than usual; thus, the W/L ratio of the transistor is also larger than usual to carry the larger writing current. For example, when the writing circuit <b>32</b> writes to the PCM cells coupled to the bit line <b>37</b>, the control signal S<b>1</b> turns the transistor T<b>1</b> on and the writing current can be transmitted to the PCM cell matrix <b>33</b> via the transistor T<b>1</b>. Similarly, the operation of the transistors T<b>2</b> and Tn is the same as the operation of the transistor T<b>1</b>. When the reading circuit <b>34</b> reads the PCM cells coupled to the bit line <b>34</b>, the control signal X<b>1</b> turns the transistor Y<b>1</b> on and the reading current can be transmitted to the PCM cell matrix <b>33</b> via the transistor Y<b>1</b>. Similarly, the operation of the transistors Y<b>2</b> and Yn is the same as the operation of the transistor Y<b>1</b>.

0025Typically, when reading the phase change memory, a reading current with smaller magnitude is usually applied, however, the small current cannot easily drive the transistor with larger W/L ratio. Therefore, although the write speed increases, the read speed decreases. The performance of the phase change memory still cannot improve significantly. In the present innovative embodiment, the switches coupled to the writing circuit <b>32</b> and the reading circuit <b>34</b> are implemented by different transistors with different W/L ratios. To increase the write speed, the switch coupled to the writing circuit <b>32</b> is implemented by a transistor with larger W/L ratio, such as the transistor T<b>1</b>, to carry a larger current. To increase the read speed, the switch coupled to the reading circuit <b>34</b> is implemented by a transistor with smaller W/L ratio, such as the transistor X<b>1</b>, to carry a smaller current.

0026<figref idref="DRAWINGS">FIG. 4</figref> is a flowchart of the writing procedure and the verifying procedure according to an embodiment of the invention. In step S<b>41</b>, a writing procedure is first applied to the (N−1)th PCM cell, and the procedure jumps to both the step S<b>42</b> and step S<b>43</b>. In step S<b>42</b>, another writing procedure is applied to the Nth PCM cell. At the same time, in step S<b>43</b>, a verifying procedure is applied to the (N−1)th PCM cell. In step S<b>44</b>, a read current is applied to read the data stored in the (N−1)th PCM cell, and a reference data is then compared with the data stored in the (N−1)th PCM cell. The reference data is the data which was originally written to the (N−1)th PCM cell. In step S<b>45</b>, a comparison circuit compares the data stored in the (N−1)th PCM cell with the reference data. If the data stored in the (N−1)th PCM cell is the same as the reference data, the procedure jumps to step S<b>47</b>S49. If the data stored in the (N−1)th PCM cell is not the same as the reference data, the procedure jumps to step S<b>46</b>. In step S<b>46</b>, the writing current is adjusted based on the comparison result generated in step S<b>45</b> and when the comparison result in the step S<b>45</b> is yes, the adjusted writing current is applied to write the (N+1)th PCM cell in step S<b>49</b> for executing a writing procedure to the (N+1)th PCM cell in step S<b>48</b>. In this embodiment, the steps S<b>42</b> to S<b>46</b> are implemented during the same cycle. When the step S<b>48</b> is executed, a verifying procedure is also applied to the Nth PCM cell.

0027In this embodiment, after the writing current is adjusted in step S<b>46</b>, the procedure jumps to step S<b>47</b> to apply a writing procedure to the (N−1)th PCM cell. In this embodiment, the writing current is adjusted based on the comparison result generated in step S<b>45</b>. In another embodiment the writing procedure in the step S<b>47</b> and step S<b>48</b> are implemented by different writing circuit. When the writing procedure is applied to the (N−1)th PCM cell, a verifying procedure is also applied to the Nth PCM cell.

0028<figref idref="DRAWINGS">FIG. 5</figref> is a timing diagram of a conventional writing procedure and verifying procedure for the phase change memory and the present innovative writing procedure and verifying procedure for the phase change memory. Timing diagram <b>51</b> shows the timing diagram of a conventional writing procedure and verifying procedure for the phase change memory. The conventional verifying procedure is executed after the writing procedure. If the verifying procedure passes, another writing procedure for the next PCM cell is executed. If the verifying procedure fails, the writing procedure is re-executed for the PCM cell. Timing diagram is timing diagram of the present innovative writing procedure and verifying procedure for the phase change memory. In this embodiment, the writing procedure and the verifying procedure can be implemented by different processing unit. Therefore, the processing time can be significantly reduced. In this embodiment, the processing unit can be implemented by software or hardware.

0029<figref idref="DRAWINGS">FIG. 6</figref> is a schematic diagram of an embodiment of the writing system for the phase change memory according to the invention. The first writing circuit <b>62</b> receives and writes a reference data to the phase change memory <b>63</b>. The verifying unit <b>61</b> comprises a processing unit <b>64</b> and a second writing circuit <b>66</b>. The reading circuit <b>65</b> outputs a read current to the phase change memory <b>63</b> to read the data stored in the phase change memory <b>63</b>. The processing unit <b>64</b> compares the reference data and the data read from the phase change memory <b>63</b> read by the reading circuit <b>65</b>. If the reference data is the same as the data read from the phase change memory <b>63</b>, a verify signal is transmitted to the first writing circuit <b>62</b> to maintain the magnitude of the writing current of the first writing circuit <b>62</b>. If the reference data is not the same as the data read from the phase change memory <b>63</b>, a control signal is transmitted to the first writing circuit <b>62</b> and the second writing circuit <b>66</b> to adjust the magnitude of the writing current.

0030The second writing circuit <b>66</b> receives the control signal and re-writes the reference data to the phase change memory <b>63</b> by the adjusted current. In this embodiment, when the verifying unit <b>61</b> verifies the (N−1)th PCM cell, the first writing circuit <b>62</b> writes to the Nth PCM cell. In one embodiment, if the writing procedure executed by the first writing circuit <b>62</b> is not finished and the first writing circuit <b>62</b> receives the control signal, the first writing circuit <b>62</b> interrupts the writing procedure and re-writes the reference data to the PCM cell by the adjusted writing current. In another embodiment, when the verifying unit <b>61</b> verifies that the data written to the (N−1)th PCM cell is wrong and the writing procedure executed by the first writing circuit <b>62</b> is finished, the first writing circuit <b>62</b> adjusts the magnitude of the writing current and executes a writing procedure to the (N+1)th PCM cell by the adjusted writing current. In another embodiment, the first writing circuit <b>62</b> and the second writing circuit <b>64</b> further respectively comprise an auxiliary writing circuit to adjust the magnitude of the writing current from the first writing circuit <b>62</b> and the second writing circuit <b>64</b> based on the control signal.

0031<figref idref="DRAWINGS">FIG. 7</figref> is a circuit diagram of a writing circuit and the auxiliary writing circuit according to an embodiment of the invention. The writing circuit <b>72</b> outputs the writing current I based on the reference current I_resoutput by a reference current source <b>71</b>. The auxiliary driving <b>73</b> utilizes the current mirror and the different W/L ratios of transistors T<b>1</b>, T<b>2</b>, T<b>3</b>, T<b>4</b>, T<b>5</b> and T<b>6</b> to output different auxiliary currents with different magnitudes. The auxiliary driving circuit <b>73</b> outputs the auxiliary current based on the control signal S<b>1</b>, S<b>2</b> and S<b>3</b>. In this embodiment, the auxiliary currents output by the auxiliary driving circuit <b>73</b> can be output after addition. Those skilled in the art can modify the auxiliary driving circuit <b>73</b> to let the auxiliary currents output by the auxiliary driving circuit <b>73</b> to be output after subtraction.

0032<figref idref="DRAWINGS">FIG. 8</figref> is a schematic diagram of a writing system for the phase change memory according to another embodiment of the invention. The first writing circuit <b>82</b> receives and writes the data to the phase change memory <b>83</b>. The verifying unit <b>81</b> verifies whether the data stored in the phase change memory <b>83</b> is correct based on a reference data. In this embodiment, when the verifying unit <b>81</b> verifies the (N−1)th PCM cell, the first writing circuit <b>82</b> writes the Nth PCM cell.

0033The verifying unit <b>81</b> comprises a detection and comparison circuit <b>84</b>, a current adjustment circuit <b>85</b> and a second writing circuit <b>87</b>. The reading circuit <b>86</b> reads the phase change memory <b>83</b> by a reading current and transmits the read data to the detection and comparison circuit <b>84</b>. The detection and comparison circuit <b>84</b> compares the data from the reading <b>86</b> and a reference data. If the two data are matched, a verify signal is transmitted to the first writing <b>82</b> to maintain the magnitude of the writing current of the first writing circuit <b>82</b>. If the reference data is not the same as the data read from the phase change memory <b>83</b>, a control signal is transmitted to the first writing circuit <b>82</b> and the second writing circuit <b>87</b> to adjust the magnitude of the writing current. When the operation after writing Nth PCM cell is to read the (N+1)th PCM cell, the Nth PCM cell still can be verified.

0034The second writing circuit <b>87</b> receives the control signal and re-writes the reference data to the phase change memory <b>83</b> by the adjusted current. In this embodiment, when the verifying unit <b>81</b> verifies the (N−1)th PCM cell, the first writing circuit <b>82</b> writes to the Nth PCM cell. In one embodiment, if the writing procedure executed by the first writing circuit <b>82</b> is not finished and the first writing circuit <b>82</b> receives the control signal, the first writing circuit <b>82</b> interrupts the writing procedure and re-writes the reference data to the PCM cell by the adjusted writing current. In another embodiment, when the verifying unit <b>81</b> verifies that the data written to the (N−1)th PCM cell is wrong and the writing procedure executed by the first writing circuit <b>82</b> is finished, the first writing circuit <b>82</b> adjusts the magnitude of the writing current and executes a writing procedure to the (N+1)th PCM cell by the adjusted writing current. In another embodiment, the first writing circuit <b>82</b> and the second writing circuit <b>87</b> further respectively comprise an auxiliary writing circuit to adjust the magnitude of the writing current from the first writing circuit <b>82</b> and the second writing circuit <b>87</b> based on the control signal.

0035While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.