Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask

CLAIM TO DOMESTIC PRIORITY

0001The present non-provisional application is a reissue application of U.S. Pat. No. 8,026,128, which claims the benefit of priority of U.S. Provisional Application Ser. No. 61/141,791, filed Dec. 31, 2008. The present nonprovisional application, and further is a continuation-in-part of U.S. application Ser. No. 12/062,293, now U.S. Pat. No. 7,700,407, filed Apr. 3, 2008, and which is a division of U.S. application Ser. No. 10/985,654, now U.S. Pat. No. 7,368,817, filed Nov. 10, 2004, entitled “Bump-on-Lead Flip Chip Interconnection” by Rajendra D. PensePendse, which claims the benefit of U.S. Provisional Application No. 60/533,918, filed Dec. 31, 2003, and U.S. Provisional Application No. 60/518,864, filed Nov. 10, 2003.

FIELD OF THE INVENTION

0002The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of providing self-confinement of conductive bump material during reflow without use of a solder mask.

BACKGROUND OF THE INVENTION

0003Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).

0004Semiconductor devices perform a wide range of functions such as high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.

0005Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.

0006A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.

0007Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.

0008One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller die size may be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.

0009<figref idref="DRAWINGS">FIG. 1</figref> illustrates a portion of flip chip type semiconductor device <b>10</b> with interconnect <b>12</b> metallurgically and electrically connected between bump pad <b>14</b> and trace line <b>20</b> using solder mask <b>15</b>. A circular solder mask or registration opening (SRO) <b>16</b> is formed over substrate <b>18</b> to expose trace line <b>20</b>, as shown in <figref idref="DRAWINGS">FIG. 2</figref>. Trace line <b>20</b> is a straight conductor with optional bump pad for mating to interconnect <b>12</b>. SRO <b>16</b> confines the conductive bump material on the bump pad of trace line <b>20</b> during reflow and prevents the molten bump material from leeching onto the trace lines, which can cause electrical shorts to adjacent structures. SRO <b>16</b> is made larger than the trace line or bump pad. SRO <b>16</b> is typically circular in shape and made as small as possible to reduce the pitch of trace line <b>20</b> and increase routing density.

0010In typical design rules, the minimum escape pitch of trace line <b>20</b> is limited by the fact that SRO <b>16</b> must be at least as large as the base diameter (D) of interconnect <b>12</b> plus a solder mask registration tolerance (SRT). In addition, a minimum ligament (L) of solder mask material is needed between adjacent openings by virtue of the limits of the solder mask application process. More specifically, the minimum escape pitch is defined as P=D+2*SRT+L. In one embodiment, D is 100 micrometers (μm), SRT is 10 μm, and L is 60 μm, hence, the minimum escape pitch is 100+2*10+60=180 μm.

0011<figref idref="DRAWINGS">FIGS. 3a and 3b</figref> show a top view and cross-sectional view of another conventional arrangement with trace line <b>30</b> routed between traces lines <b>32</b> and <b>34</b> and bumps <b>36</b> and <b>38</b> on substrate <b>40</b>. Bumps <b>36</b> and <b>38</b> electrically connect semiconductor die <b>42</b> to substrate <b>40</b>. Solder mask <b>44</b> overlays bump pads <b>46</b> and <b>48</b>. The minimum escape pitch of trace line <b>30</b> is defined by P=D/2+SRT+L+W/2, where D is bump base diameter, SRT is solder mask registration tolerance, W is trace line width, and L is the ligament separation between SRO and adjacent structures. In one embodiment, D is 100 μm, SRT is 10 μm, W is 30 μm, and L is 60 μm. The minimum escape pitch of trace lines <b>30</b>-<b>34</b> is 100/2+10+60+30/2=135 μm. As the demand for high routing density increases, a smaller escape pitch is needed.

SUMMARY OF THE INVENTION

0012A need exists to minimize escape pitch of trace lines for higher routing density. Accordingly, in one embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a semiconductor die having a die bump pad, providing a substrate having a trace line with substrate bump pad, depositing conductive bump material on the substrate bump pad or die bump pad, mounting the semiconductor die over the substrate so that the conductive bump material is disposed between the die bump pad and substrate bump pad, and reflowing the conductive bump material without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The conductive bump material is self-confined within a footprint of the die bump pad or substrate bump pad during reflow.

0013In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a first semiconductor structure having a first bump pad, providing a second semiconductor structure having a second bump pad, depositing conductive bump material between the first and second bump pads, and reflowing the conductive bump material without a solder mask around the first and second bump pads to form an interconnect. The conductive bump material is self-confined within the first and second bump pads during reflow.

0014In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of depositing conductive bump material over a first bump pad, and reflowing the conductive bump material without a solder mask. The conductive bump material is self-confined within the first bump pad during reflow.

0015In another embodiment, the present invention is a semiconductor device comprising a semiconductor die having a first bump pad and substrate having a second bump pad. An interconnect is formed between the first and second bump pads by reflowing conductive bump material without a solder mask. The conductive bump material is self-confined within the first and second bump pads.

BRIEF DESCRIPTION OF THE DRAWINGS

0016<figref idref="DRAWINGS">FIG. 1</figref> illustrates a cross-sectional view of a conventional interconnect formed between a semiconductor die and trace line on a substrate;

0017<figref idref="DRAWINGS">FIG. 2</figref> illustrates a top view of the conventional interconnect formed over the trace line through a solder mask opening;

0018<figref idref="DRAWINGS">FIGS. 3a-3b</figref> illustrate conventional arrangement of trace lines between interconnects reflowed using a solder mask;

0019<figref idref="DRAWINGS">FIG. 4</figref> illustrates a PCB with different types of packages mounted to its surface;

0020<figref idref="DRAWINGS">FIGS. 5a-5d</figref> illustrate further detail of the representative semiconductor packages mounted to the PCB;

0021<figref idref="DRAWINGS">FIGS. 6a-6b</figref> is a semiconductor device with interconnects reflowed on trace lines without a solder mask;

0022<figref idref="DRAWINGS">FIGS. 7a-7b</figref> show further detail of the bump pad along the trace line;

0023<figref idref="DRAWINGS">FIG. 8</figref> shows a composite interconnect with non-fusible base and fusible cap; and

0024<figref idref="DRAWINGS">FIGS. 9a-9b</figref> illustrate an alternate embodiment of the semiconductor device with interconnects reflowed on trace lines without a solder mask.

DETAILED DESCRIPTION OF THE DRAWINGS

0025The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings.

0026Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, resistors, and transformers, create a relationship between voltage and current necessary to perform electrical circuit functions.

0027Passive and active components are formed over the surface of the semiconductor wafer by a series of process steps including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process modifies the electrical conductivity of semiconductor material in active devices, transforming the semiconductor material into an insulator, conductor, or dynamically changing the semiconductor material conductivity in response to an electric field or base current. Transistors contain regions of varying types and degrees of doping arranged as necessary to enable the transistor to promote or restrict the flow of electrical current upon the application of the electric field or base current.

0028Active and passive components are formed by layers of materials with different electrical properties. The layers can be formed by a variety of deposition techniques determined in part by the type of material being deposited. For example, thin film deposition may involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes. Each layer is generally patterned to form portions of active components, passive components, or electrical connections between components.

0029The layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned. A pattern is transferred from a photomask to the photoresist using light. The portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. The remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.

0030Depositing a thin film of material over an existing pattern can exaggerate the underlying pattern and create a non-uniformly flat surface. A uniformly flat surface is required to produce smaller and more densely packed active and passive components. Planarization can be used to remove material from the surface of the wafer and produce a uniformly flat surface. Planarization involves polishing the surface of the wafer with a polishing pad. An abrasive material and corrosive chemical are added to the surface of the wafer during polishing. The combined mechanical action of the abrasive and corrosive action of the chemical removes any irregular topography, resulting in a uniformly flat surface.

0031Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and environmental isolation. To singulate the die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with solder bumps, stud bumps, conductive paste, or wirebonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.

0032<figref idref="DRAWINGS">FIG. 4</figref> illustrates electronic device <b>50</b> having a chip carrier substrate or PCB <b>52</b> with a plurality of semiconductor packages mounted on its surface. Electronic device <b>50</b> may have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown in <figref idref="DRAWINGS">FIG. 4</figref> for purposes of illustration.

0033Electronic device <b>50</b> may be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device <b>50</b> may be a sub-component of a larger system. For example, electronic device <b>50</b> may be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASICs), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components.

0034In <figref idref="DRAWINGS">FIG. 4</figref>, PCB <b>52</b> provides a general substrate for structural support and electrical interconnect of the semiconductor packages mounted on the PCB. Conductive signal traces <b>54</b> are formed over a surface or within layers of PCB <b>52</b> using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces <b>54</b> provide for electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces <b>54</b> also provide power and ground connections to each of the semiconductor packages.

0035In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate carrier. Second level packaging involves mechanically and electrically attaching the intermediate carrier to the PCB. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to the PCB.

0036For the purpose of illustration, several types of first level packaging, including wire bond package <b>56</b> and flip chip <b>58</b>, are shown on PCB <b>52</b>. Additionally, several types of second level packaging, including ball grid array (BGA) <b>60</b>, bump chip carrier (BCC) <b>62</b>, dual in-line package (DIP) <b>64</b>, land grid array (LGA) <b>66</b>, multi-chip module (MCM) <b>68</b>, quad flat non-leaded package (QFN) <b>70</b>, and quad flat package <b>72</b>, are shown mounted on PCB <b>52</b>. Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB <b>52</b>. In some embodiments, electronic device <b>50</b> includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using cheaper components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.

0037<figref idref="DRAWINGS">FIGS. 5a-5d</figref> show exemplary semiconductor packages. <figref idref="DRAWINGS">FIG. 5a</figref> illustrates further detail of DIP <b>64</b> mounted on PCB <b>52</b>. Semiconductor die <b>74</b> includes an active region containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and are electrically interconnected according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active region of semiconductor die <b>74</b>. Contact pads <b>76</b> are one or more layers of conductive material, such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and are electrically connected to the circuit elements formed within semiconductor die <b>74</b>. During assembly of DIP <b>64</b>, semiconductor die <b>74</b> is mounted to an intermediate carrier <b>78</b> using a gold-silicon eutectic layer or adhesive material such as thermal epoxy. The package body includes an insulative packaging material such as polymer or ceramic. Conductor leads <b>80</b> and wire bonds <b>82</b> provide electrical interconnect between semiconductor die <b>74</b> and PCB <b>52</b>. Encapsulant <b>84</b> is deposited over the package for environmental protection by preventing moisture and particles from entering the package and contaminating die <b>74</b> or wire bonds <b>82</b>.

0038<figref idref="DRAWINGS">FIG. 5b</figref> illustrates further detail of BCC <b>62</b> mounted on PCB <b>52</b>. Semiconductor die <b>88</b> is mounted over carrier <b>90</b> using an underfill or epoxy-resin adhesive material <b>92</b>. Wire bonds <b>94</b> provide first level packing interconnect between contact pads <b>96</b> and <b>98</b>. Molding compound or encapsulant <b>100</b> is deposited over semiconductor die <b>88</b> and wire bonds <b>94</b> to provide physical support and electrical isolation for the device. Contact pads <b>102</b> are formed over a surface of PCB <b>52</b> using a suitable metal deposition such electrolytic plating or electroless plating to prevent oxidation. Contact pads <b>102</b> are electrically connected to one or more conductive signal traces <b>54</b> in PCB <b>52</b>. Bumps <b>104</b> are formed between contact pads <b>98</b> of BCC <b>62</b> and contact pads <b>102</b> of PCB <b>52</b>.

0039Flip chip semiconductor packages and wafer level packages (WLP) are commonly used with integrated circuits (ICs) demanding high speed, high density, and greater pin count. In <figref idref="DRAWINGS">FIG. 5c</figref>, semiconductor die <b>58</b> is mounted face down to intermediate carrier <b>106</b> with a flip chip style first level packaging. Active region <b>108</b> of semiconductor die <b>58</b> contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements within active region <b>108</b>. Semiconductor die <b>58</b> is electrically and mechanically connected to carrier <b>106</b> through interconnects <b>110</b>.

0040BGA <b>60</b> is electrically and mechanically connected to PCB <b>52</b> with a BGA style second level packaging using interconnects <b>112</b>. Semiconductor die <b>58</b> is electrically connected to conductive signal traces <b>54</b> in PCB <b>52</b> through interconnects <b>110</b>, signal lines <b>114</b>, and interconnects <b>112</b>. A molding compound or encapsulant <b>116</b> is deposited over semiconductor die <b>58</b> and carrier <b>106</b> to provide physical support and electrical isolation for the device. The flip chip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die <b>58</b> to conduction tracks on PCB <b>52</b> in order to reduce signal propagation distance, lower capacitance, and improve overall circuit performance.

0041In another embodiment, active area <b>108</b> of semiconductor die <b>58</b> is directly mounted facedown to PCB <b>115</b>, i.e., without an intermediate carrier, as shown in <figref idref="DRAWINGS">FIG. 5d</figref>. Bump pads <b>111</b> are formed on active area <b>108</b> using an evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Bump pads <b>111</b> connect to the active and passive circuits by conduction tracks in active area <b>108</b>. Bump pads <b>111</b> can be Al, Sn, Ni, Au, Ag, or Cu. An electrically conductive bump material is deposited over bump pads <b>111</b> using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), Bi, Cu, solder, and combinations thereof, with an optional flux material. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to die bump pads <b>160</b> using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps <b>117</b>. In some applications, bumps <b>117</b> are reflowed a second time to improve electrical contact to bump pads <b>111</b>. The flip chip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die <b>58</b> to conduction tracks on PCB <b>115</b> in order to reduce signal propagation, lower capacitance, and achieve overall better circuit performance.

0042<figref idref="DRAWINGS">FIGS. 6a and 6b</figref> illustrate a top view and cross-sectional view of a portion of flip chip type semiconductor die <b>120</b> with die bump pad <b>122</b>. Trace line <b>124</b> is a straight conductor with integrated bump pad <b>126</b> formed on substrate or PCB <b>130</b>. <figref idref="DRAWINGS">FIGS. 7a and 7b</figref> show further detail of substrate bump pad <b>126</b> along trace line <b>124</b>. The substrate bump pad <b>126</b> can be rounded as shown in <figref idref="DRAWINGS">FIG. 7a</figref>, or rectangular as shown in <figref idref="DRAWINGS">FIG. 7b</figref>. The sides of substrate bump pad <b>126</b> may be co-linear with trace line <b>124</b>.

0043An electrically conductive bump material is deposited over die bump pad <b>122</b> or substrate bump pad <b>126</b> using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to die bump pad <b>122</b> and substrate bump pad <b>126</b> using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form interconnect <b>132</b>. In some applications, interconnect <b>132</b> is reflowed a second time to improve electrical contact between die bump pad <b>122</b> and substrate bump pad <b>126</b>. The bump material around the narrow substrate bump pad <b>126</b> maintains die placement during reflow. Although interconnect <b>132</b> is shown connected to trace line <b>124</b> as a bump-on-lead (BOL), the interconnect can also be formed over a bump pad on substrate <b>130</b> having an area on the same order or greater than die bump pad <b>122</b>. An optional underfill material <b>138</b> is deposited between semiconductor die <b>120</b> and substrate <b>130</b>.

0044In high routing density applications, it is desirable to minimize escape pitch of trace lines <b>124</b>. The escape pitch between trace lines <b>124</b> can be reduced by eliminating the solder mask for reflow containment, i.e., by reflowing the bump material without a solder mask. Solder mask <b>140</b> may be formed over a portion of substrate <b>130</b>. However, solder mask <b>140</b> is not formed over substrate bump pad <b>126</b> of trace line <b>124</b> for reflow containment. That is, the portion of trace line <b>124</b> designed to mate with the bump material is devoid of any SRO of solder mask <b>140</b>. Since no SRO is formed around die bump pad <b>122</b> or substrate bump pad <b>126</b>, trace lines <b>124</b> can be formed with a finer pitch, i.e., trace lines <b>124</b> can be disposed closer together or to nearby structures. Without solder mask <b>140</b>, the pitch between trace lines <b>124</b> is given as P=D+PLT+W/2, wherein D is the base diameter of interconnect <b>132</b>, PLT is die placement tolerance, and W is the width of the trace line <b>124</b>. In one embodiment, given a bump base diameter of 100 μm, PLT of 10 μm, and trace line width of 30 μm, the minimum escape pitch of trace line <b>124</b> is 125 μm. The solder mask-less bump formation eliminates the need to account for the ligament spacing of solder mask material between adjacent openings, SRT, and minimum resolvable SRO, as found in the prior art.

0045When the bump material is reflowed without a solder mask to metallurgically and electrically connect die bump pad <b>122</b> to substrate bump pad <b>126</b>, the wetting and surface tension causes the bump material to maintain self-confinement and be retained within the space between die bump pad <b>122</b> and substrate bump pad <b>126</b> and portion of substrate <b>130</b> immediately adjacent to trace line <b>124</b> substantially within the footprint of the bump pads.

0046To achieve the desired self-confinement property, the bump material can be immersed in a flux solution prior to placement on die bump pad <b>122</b> or substrate bump pad <b>126</b> to selectively render the region contacted by the bump material more wettable than the surrounding area of trace line <b>124</b>. The molten bump material remains confined substantially within the area defined by the bump pads due to the wettable properties of the flux solution. The bump material does not run-out to the less wettable areas. A thin oxide layer or other insulating layer can be formed over areas where bump material is not intended to make the area less wettable. Hence, solder mask <b>140</b> is not needed around die bump pad <b>122</b> or substrate bump pad <b>126</b>.

0047In another embodiment, a composite interconnect <b>144</b> is formed between die bump pad <b>122</b> and substrate bump pad <b>126</b> to achieve the desired self-confinement of the bump material. Composite interconnect <b>144</b> includes a non-fusible base <b>146</b> made of Cu, Au, Sn, Ni, and Pb, and a fusible cap <b>148</b> made of solder, Sn, or indium, as shown in <figref idref="DRAWINGS">FIG. 8</figref>. The volume of fusible bump material in relation to the non-fusible base material is selected to ensure self-confinement by virtue of surface tension forces. During reflow, the fusible base material is self-confined around the non-fusible base material. The fusible bump material around the non-fusible base also maintains die placement during reflow. In general, the height of composite interconnect <b>144</b> is the same or less than the diameter of the bump. In some cases, the height of composite interconnect <b>144</b> is greater than the diameter of the interconnect. In one embodiment, given a bump base diameter of 100 μm, the non-fusible base <b>146</b> is about 45 μm in height and the fusible cap <b>148</b> is about 35 μm in height. The molten bump material remains confined substantially within the area defined by the bump pads because the volume of bump material deposited to form composite bump <b>144</b>, including non-fusible base <b>146</b> and fusible cap <b>148</b>, is selected so that the resulting surface tension is sufficient to retain the bump material substantially within the footprint of the bump pads and prevent run-out to unintended adjacent or nearby areas. Hence, solder mask <b>140</b> is not needed around die bump pad <b>122</b> or substrate bump pad <b>126</b>, which reduces trace line pitch and increases routing density.

0048<figref idref="DRAWINGS">FIGS. 9a and 9b</figref> illustrate a top view and cross-sectional view of another embodiment with flip chip type semiconductor die <b>150</b> having die bump pad <b>152</b>. Trace line <b>154</b> is a straight conductor with integrated bump pad <b>156</b> formed on substrate or PCB <b>160</b>, similar to <figref idref="DRAWINGS">FIGS. 7a and 7b</figref>. In this embodiment, bump pads <b>156</b> are arranged in multiple or offset rows. Accordingly, alternate trace lines <b>154</b> include an elbow for routing to bump pads <b>156</b>.

0049An electrically conductive bump material is deposited over die bump pad <b>152</b> or substrate bump pad <b>156</b> using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to die bump pad <b>152</b> and substrate bump pad <b>156</b> using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form interconnect <b>162</b>. In some applications, interconnect <b>162</b> is reflowed a second time to improve electrical contact between die bump pad <b>152</b> and substrate bump pad <b>156</b>. The bump material around the narrow substrate bump pad <b>156</b> maintains die placement during reflow. Although interconnect <b>162</b> is shown connected to trace line <b>154</b> as BOL, the bump material can also be reflowed over a bump pad on substrate <b>160</b> having an area on the same order or greater than die bump pad <b>152</b>. An optional underfill material <b>168</b> is deposited between semiconductor die <b>150</b> and substrate <b>160</b>.

0050In high routing density applications, it is desirable to minimize escape pitch. In order to reduce the pitch between trace lines <b>154</b>, the bump material is reflowed without a solder mask. The escape pitch between trace lines <b>154</b> can be reduced by eliminating the solder mask for solder reflow containment, i.e., by reflowing the bump material without a solder mask. Solder mask <b>170</b> may be formed over a portion of substrate <b>160</b>. However, solder mask <b>170</b> is not formed over substrate bump pad <b>156</b> of trace line <b>154</b> for solder reflow containment. That is, the portion of trace line <b>154</b> designed to mate with the bump material is devoid of an SRO of solder mask <b>170</b>. Since no SRO is formed around die bump pad <b>152</b> or substrate bump pad <b>156</b>, trace lines <b>154</b> can be formed with a finer pitch, i.e., trace lines <b>154</b> can be disposed closer to adjacent structures.

0051Without solder mask <b>170</b>, the pitch between trace lines <b>154</b> is given as P=D/2+PLT+W/2, wherein D is the base diameter of bump <b>162</b>, PLT is die placement tolerance, and W is the width of the trace line <b>154</b>. In one embodiment, given a bump diameter of 100 μm, PLT of 10 μm, and trace line width of 30 μm, the minimum escape pitch of trace line <b>154</b> is 75 μm. The solder mask-less bump formation eliminates the need to account for the ligament spacing of solder mask material between adjacent openings, SRT, and minimum resolvable SRO, as found in the prior art.

0052When the bump material is reflowed without a solder mask to metallurgically and electrically connect die bump pad <b>152</b> of semiconductor die <b>150</b> to substrate bump pad <b>156</b> of trace line <b>154</b>, the wetting and surface tension causes the bump to maintain self-confinement and be retained within the space between die bump pad <b>152</b> and substrate bump pad <b>156</b> and portion of substrate <b>160</b> immediately adjacent to trace line <b>154</b> substantially within the footprint of the bump pads.

0053To achieve the desired self-confinement property, the bump material can be immersed in a flux solution prior to placement on die bump pad <b>152</b> or substrate bump pad <b>156</b> to selectively render the region contacted by the bump material more wettable than the surrounding area of trace line <b>154</b>. The molten bump material remains confined substantially within the area defined by the bump pads due to the wettable properties of the flux solution. The bump material does not run-out to the less wettable areas. A thin oxide layer or other insulating layer can be formed over areas where bump material is not intended to make the area less wettable. Hence, solder mask <b>170</b> is not needed around die bump pad <b>152</b> or substrate bump pad <b>156</b>.

0054In another embodiment, a composite interconnect is formed between die bump pad <b>152</b> and substrate bump pad <b>156</b> to achieve the desired self-confinement of the bump material. The composite interconnect includes a non-fusible base made of Cu, Au, Sn, Ni, or Pb, and a fusible cap made of solder, Sn, or indium, similar to <figref idref="DRAWINGS">FIG. 8</figref>. The height or volume of fusible bump material in relation to the non-fusible base material is selected to ensure self-confinement by virtue of surface tension forces. During reflow, the fusible base material is self-confined around the non-fusible base material. The fusible bump material around the non-fusible base also maintains die placement during reflow. In general the height of the composite interconnect is the same or less than the diameter of the bump. In some cases, the height of the composite interconnect is greater than the diameter of the interconnect. In one embodiment, given a bump base diameter of 100 μm, the non-fusible base is about 45 μm in height and the fusible cap is about 35 μm in height. The molten bump material remains confined substantially within the area defined by the bump pads because the volume of bump material deposited to form the composite bump, including non-fusible base and fusible cap, is selected so that the resulting surface tension is sufficient to retain the bump material substantially within the footprint of the bump pads and prevent run-out to unintended adjacent or nearby areas. Hence, solder mask <b>170</b> is not needed around die bump pad <b>152</b> or substrate bump pad <b>156</b>, which reduces trace line pitch and increases routing density.

0055While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.