Thin film transistor panel for liquid crystal display

CROSS REFERENCE TO PRIOR APPLICATIONS

0001This application is a continuation of application Ser. No. 10/750,890, filed Jan. 5, 2004, which claims priority to and the benefit of Korean Patent Application No. 10-2003-0000266 filed on Jan. 3, 2003 now U.S. Pat. No. 6,936,845, which are all hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

0002(a) Field of the Invention

0003The present invention relates to a thin film transistor array panel, and in particular, to a thin film transistor array panel for a liquid crystal display.

0004(b) Description of the Related Art

0005A typical liquid crystal display (“LCD”) includes an upper panel provided with a common electrode and an array of color filters, a lower panel provided with a plurality of thin film transistors (“TFTs) and a plurality of pixel electrodes, and a liquid crystal layer is interposed therebetween. The pixel electrodes and the common electrode are applied with electric voltages and the voltage difference therebetween causes electric field. The variation of the electric field changes the orientations of liquid crystal molecules in the liquid crystal layer and thus the transmittance of light passing through the liquid crystal layer. As a result, the LCD displays desired images by adjusting the voltage difference between the pixel electrodes and the common electrode.

0006The LCD has a major disadvantage of its narrow viewing angle, and several techniques for increasing the viewing angle have been developed. Among these techniques, the provision of a plurality of cutouts or a plurality of projections on the pixel electrodes and the common electrode opposite each other along with the vertical alignment of the liquid crystal molecules with respect to the upper and the lower panels is promising.

0007The cutouts provided both at the pixel electrodes and the common electrode give wide viewing angle by generating fringe field to adjust the tilt directions of the liquid crystal molecules.

0008The provision of the projections both on the pixel electrode and the common electrode distorts the electric field to adjust the tilt directions of the liquid crystal molecules.

0009The fringe field for adjusting the tilt directions of the liquid crystal molecules to form a plurality of domains is also obtained by providing the cutouts at the pixel electrodes on the lower panel and the projections on the common electrode on the upper panel.

0010Among these techniques for widening the viewing angle, the provision of the cutouts has problems that an additional mask for patterning the common electrode is required, an overcoat is required for preventing the effect of the pigments of the color filters on the liquid crystal material, and severe disclination is generated near the edges of the patterned electrode. The provision of the projections also has a problem that the manufacturing method is complicated since it is required an additional process step for forming the projections or a modification of a process step. Moreover, the aperture ratio is reduced due to the projections and the cutouts.

SUMMARY OF THE INVENTION

0011A thin film transistor array panel is provided, which includes: an insulating substrate; a first signal wire formed on the insulating substrate; a second signal wire formed on the insulating substrate and intersecting the first signal wire in an insulating manner; first and second pixel electrodes formed in a pixel area defined by the intersections of the first and the second signal wires and including a plurality of subareas partitioned by cutouts; a direction control electrode formed in the pixel area and including a portion overlapping at least one of the cutouts; and a first thin film transistor connected to the direction control electrode, the first signal wire, and the second signal wire.

0012The thin film transistor array panel may further include: a second thin film transistor connected to the first pixel electrode, the first signal wire, and the second signal wire.

0013The thin film transistor array panel may further include: a third thin film transistor connected to the first pixel electrode, the first signal wire, and the second signal wire.

0014Preferably, the first signal wire includes first and second signal lines, the second signal wire includes third and fourth signal lines, the second thin film transistor is connected to the first signal line, the third signal line, and the first pixel electrode, the third thin film transistor is connected to the second signal line, the third signal line, and the first pixel electrode, and the first thin film transistor is connected to the second signal line, the fourth signal line, and the direction control electrode.

0015The thin film transistor array panel may further include a third signal wire intersecting the second signal wire in an insulating manner.

0016Preferably, the first signal wire includes first and second signal lines, the second signal wire includes third and fourth signal lines, the second thin film transistor is connected to the first signal line, the third signal line, and the first pixel electrode, the third thin film transistor is connected to the second signal line, the third signal line, and the first pixel electrode, and the first thin film transistor is connected to the second signal line, the third signal wire, and the direction control electrode.

0017Preferably, the first signal wire includes first and second signal lines, the second signal wire includes third and fourth signal lines, the second thin film transistor is connected to the first signal line, the third signal line, and the first pixel electrode, the third thin film transistor is connected to the second signal line, the third signal wire, and the first pixel electrode, and the first thin film transistor is connected to the second signal line, the fourth signal line, and the direction control electrode.

0018The thin film transistor array panel may further include a coupling electrode connected to the first pixel electrode and overlapping at least one of the cutouts of the second pixel electrode, wherein the direction control electrode includes a portion overlapping one of the cutouts of the first pixel electrode and does not overlap the cutouts of the second pixel electrode.

0019The direction control electrode preferably overlaps the cutouts of the first and the second pixel electrodes.

0020The cutouts of the second pixel electrode may include a transverse cutout bisecting the second pixel electrode into upper and lower halves and a plurality of first oblique cutouts having inversion symmetry with respect to the transverse cutout, and the cutouts of the first pixel electrode may include a plurality of second oblique cutouts having inversion symmetry with respect to the transverse cutout.

0021The first and the second pixel electrodes preferably have inversion symmetry with respect to the transverse cutout.

0022The thin film transistor array panel may further include a third signal wire intersecting the second signal wire in an insulating manner and including an electrode disposed between the first pixel electrode and the second pixel electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

0023The present invention will become more apparent by describing embodiments thereof in detail with reference to the accompanying drawings in which:

0024<figref idref="DRAWINGS">FIG. 1</figref> is a layout view of an LCD an embodiment of the present invention;

0025<figref idref="DRAWINGS">FIG. 2</figref> is a sectional view of the LCD shown in <figref idref="DRAWINGS">FIG. 1</figref> taken along the line II-II′;

0026<figref idref="DRAWINGS">FIG. 3</figref> is a sectional view of the LCD shown in <figref idref="DRAWINGS">FIG. 1</figref> taken along the lines III-III′-III″;

0027<figref idref="DRAWINGS">FIG. 4</figref> is an equivalent circuit diagram of an LCD shown in <figref idref="DRAWINGS">FIGS. 1-3</figref>;

0028<figref idref="DRAWINGS">FIG. 5</figref> is a layout view of an LCD according to another embodiment of the present invention;

0029<figref idref="DRAWINGS">FIG. 6</figref> is a layout view of an LCD according to another embodiment of the present invention;

0030<figref idref="DRAWINGS">FIG. 7</figref> is a sectional view of the LCD shown in <figref idref="DRAWINGS">FIG. 6</figref> taken along the line VII-VII′;

0031<figref idref="DRAWINGS">FIG. 8</figref> is an equivalent circuit diagram of the LCD shown in <figref idref="DRAWINGS">FIGS. 6 and 7</figref>;

0032<figref idref="DRAWINGS">FIGS. 9 and 10</figref> are equivalent circuit diagrams of LCDs according to embodiments of the present invention;

0033<figref idref="DRAWINGS">FIG. 11</figref> is a layout view of an LCD according to another embodiment of the present invention;

0034<figref idref="DRAWINGS">FIG. 12</figref> is an equivalent circuit diagram of the LCD shown in <figref idref="DRAWINGS">FIG. 11</figref>;

0035<figref idref="DRAWINGS">FIG. 13</figref> is a layout view of an LCD according to another embodiment of the present invention;

0036<figref idref="DRAWINGS">FIG. 14</figref> is an equivalent circuit diagram of the LCD shown in <figref idref="DRAWINGS">FIG. 13</figref>;

0037<figref idref="DRAWINGS">FIGS. 15 and 16</figref> are equivalent circuit diagrams of LCDs according to embodiments of the present invention;

0038<figref idref="DRAWINGS">FIG. 17</figref> is a layout view of an LCD according to another embodiment of the present invention; and

0039<figref idref="DRAWINGS">FIG. 18</figref> is an equivalent circuit diagram of the LCD shown in <figref idref="DRAWINGS">FIG. 11</figref>.

DETAILED DESCRIPTION OF EMBODIMENTS

0040The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the inventions invention are shown. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

0041In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numerals refer to like elements throughout. It will be understood that when an element such as a layer, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

0042Then, liquid crystal displays according to embodiments of this invention will be described in detail with reference to the accompanying drawings.

0043<figref idref="DRAWINGS">FIG. 1</figref> is a layout view of an LCD an embodiment of the present invention, <figref idref="DRAWINGS">FIG. 2</figref> is a sectional view of the LCD shown in <figref idref="DRAWINGS">FIG. 1</figref> taken along the line II-II′, <figref idref="DRAWINGS">FIG. 3</figref> is a sectional view of the LCD shown in <figref idref="DRAWINGS">FIG. 1</figref> taken along the lines III-III′-III″, and <figref idref="DRAWINGS">FIG. 4</figref> is an equivalent circuit diagram of an LCD shown in <figref idref="DRAWINGS">FIGS. 1-3</figref>.

0044An LCD according to an embodiment of the present invention includes a plurality of gate lines <b>121</b> transmitting gate signals, a plurality of data lines <b>171</b> transmitting data voltages, and a plurality of pixels connected to the gate lines <b>121</b> and the data lines <b>171</b>. As shown in <figref idref="DRAWINGS">FIG. 4</figref>, each pixel includes a plurality of capacitors Clca, Clcb, Cdcea, Cdceb and Cst and a transistor. The transistor has a gate connected to a gate line <b>121</b>, a source connected to a data line <b>171</b>, and a drain connected to the capacitors Cdcea, Cdceb and Cst connected in parallel. The capacitors Cdcea and Clca are connected in series and the capacitors Cdceb and Clcb are connected in series. The capacitors Clca, Clcb and Cst are connected to a predetermined voltage such as the common voltage Vcom.

0045In structural view, the LCD includes a TFT array panel, a color filter array panel facing the TFT array panel and separated by a predetermined gap, and a liquid crystal layer filled in the predetermined gap, as shown in <figref idref="DRAWINGS">FIGS. 1-3</figref>.

0046Referring to <figref idref="DRAWINGS">FIGS. 1-3</figref>, the TFT array panel includes a plurality of gate lines <b>121</b> transmitting scanning signals, a plurality of data lines <b>171</b> transmitting data signals as well as a plurality of pairs of storage electrode lines <b>131</b>a and <b>131</b>b transmitting a predetermined voltage such as the common voltage Vcom. The gate lines <b>121</b> and the data lines <b>171</b> intersect each other to define a plurality of pixel areas.

0047Each pixel area is provided with a pair of pixel electrodes (PEs) <b>190</b>a and <b>190</b>b, a direction control electrode (DCE) <b>178</b>, and a DCE TFT connected to one of the gate lines <b>121</b>, one of the data lines <b>171</b>, and the DCE <b>178</b>.

0048The color filter array panel includes a plurality of color filters <b>230</b> and a common electrode <b>270</b> supplied with the common voltage Vcom.

0049The PEs <b>190</b>a and <b>190</b>b and the common electrode <b>270</b> along with the liquid crystal layer interposed therebetween form a pair of liquid crystal (LC) capacitors indicated by Clca and Clcb shown in <figref idref="DRAWINGS">FIG. 4</figref>. The PEs <b>190</b>a and <b>190</b>b and the storage electrode lines <b>131</b>a and <b>131</b>b along with an insulator disposed therebetween form a storage capacitor represented by Cst. The DCE <b>178</b> and the PEs <b>190</b>a and <b>190</b>b are capacitively coupled to form a pair of DCE capacitors represented by Cdcea and Cdceb.

0050The PEs <b>190</b>a and <b>190</b>b are floating and supplied with a coupling voltage obtained by the coupling with the DCE <b>178</b>.

0051The reference numerals for the above-described capacitors are also used for indicating the capacitances of the capacitors in this specification.

0052The PEs <b>190</b>a and <b>190</b>b have a plurality of cutouts <b>191</b>, <b>192</b>a, <b>192</b>b, <b>193</b>a, <b>193</b>b, <b>194</b>a, <b>194</b>b, <b>195</b>a and <b>195</b>b overlapping the DCE <b>178</b> such that an electric field generated by the DCE <b>178</b> goes out through the cutouts <b>191</b>, <b>192</b>a, <b>192</b>b, <b>193</b>a, <b>193</b>b, <b>194</b>a, <b>194</b>b, <b>195</b>a and <b>195</b>b. The electric field generated by the DCE <b>178</b> pre-tilts liquid crystal molecules in the liquid crystal layer. (The term “cutout” in this specification includes gaps <b>191</b>, <b>193</b>a and <b>193</b>b between separated portions of the PE <b>190</b>a and between the separated PEs <b>190</b>a and <b>190</b>b if there is no particular mention.) The pretilted liquid crystal molecules are rapidly tilted without dispersion upon the application of the electric field generated by the PEs <b>190</b>a and <b>190</b>b.

0053In order to obtain the pretilt of the liquid crystal molecules using the electric field generated by the DCE <b>178</b>, a voltage of the DCE <b>178</b> relative to a voltage of the common electrode <b>270</b> (referred to as a “DCE voltage” hereinafter) is larger than a voltage of the PEs <b>190</b>a and <b>190</b>b relative to a voltage of the common electrode <b>270</b> (referred to as a “pixel voltages” hereinafter) by a predetermined value.

0054The LCD according to an embodiment of the present invention easily satisfies this requirement by applying the coupling voltage to the floating PEs <b>190</b>a and <b>190</b>b.

0055Since the DCE voltage Vdce is substantially equal to a data voltage Vd, pixel voltages Va and Vb of the PEs <b>190</b>a and <b>190</b>b are obtained from the voltage distribution law as follows: <br />Va=Vd×Cdcea/(Cdcea+Clca); and<br />Vb=Vd×Cdecb/(Cdecb+Clcb).

0056Accordingly, the DCE voltage Vdce is always higher larger than the pixel voltages Va and Vb.

0057In the meantime, when a pixel area includes two sub-areas with somewhat different electric fields, a lateral visibility is improved by the mutual compensation in the two subareas.

0058If the pixel voltage Va of the PE <b>190</b>a is intended to be higher than the pixel voltage Vb of the PE <b>190</b>b, the capacitances Cdcea, Clca, Cdceb and Clcb are determined to satisfy a relation, <br />Cdcea/(Cdcea+Clca)>Cdceb/(Cdceb+Clcb).

0059The capacitances are adjusted by overlapping areas between the PEs <b>190</b>a and <b>190</b>b and the DCE <b>178</b>.

0060Now, the LCD according to this embodiment is described more in detail with reference to <figref idref="DRAWINGS">FIGS. 1 to 3</figref>.

0061The TFT array panel is now described in detail.

0062A plurality of gate lines <b>121</b> are formed on an insulating substrate <b>110</b> and a plurality of data lines <b>171</b> are formed thereon. The gate lines <b>121</b> and the data lines <b>171</b> are insulated from each other and intersect each other to define a plurality of pixel areas.

0063Each pixel area is provided with a pair of PEs <b>190</b>a and <b>190</b>b, a DCE <b>178</b>, and a DCE TFT.

0064The DCE TFT for switching voltages to be applied to the DCE <b>178</b> has three terminals, a gate electrode <b>123</b>c connected to a gate line <b>121</b>, a source electrode <b>173</b>c connected to a data line <b>171</b>, and a drain electrode <b>175</b>c connected to the DCE <b>178</b>. The DCE <b>178</b> is applied with a direction-controlling voltage for controlling the pre-tilts of the liquid crystal molecules to generate a direction-controlling electric field between the DCE <b>178</b> and the common electrode <b>270</b>. The DCE <b>178</b> is formed in a step for forming the data lines <b>171</b>. The PEs <b>190</b>a and <b>190</b>b are floating rather than being connected to the gate lines <b>121</b> or the data lines <b>171</b>, and they overlap the DCE <b>178</b> to be capacitively coupled.

0065The layered structure of the TFT array panel will be described in detail.

0066A plurality of gate lines <b>121</b> and a plurality of pairs of first and second storage electrode lines <b>131</b>a and <b>131</b>b are formed on an insulating substrate <b>110</b>.

0067Each gate line <b>121</b> extends substantially in a transverse direction and it includes a plurality of pairs of branches forming gate electrodes <b>123</b>c and an expanded end portion <b>125</b> for signal reception from an external device.

0068Each storage electrode line <b>131</b>a or <b>131</b>b extends substantially in the transverse direction although it has some curves. Each pair of storage electrode lines <b>131</b>a and <b>131</b>b include a plurality of sets of branches forming first fourth storage electrodes <b>133</b>a, <b>133</b>b, <b>134</b>a and <b>134</b>a. The first and the second storage electrodes <b>133</b>a and <b>133</b>b are branched from the first and the second storage electrode lines <b>131</b>a and <b>13</b>b in a longitudinal direction, respectively. The third and the fourth storage electrodes <b>134</b>a and <b>134</b>b are branched from the first and the second storage electrode lines <b>131</b>a and <b>131</b>b in the longitudinal direction and they are curved to extend in oblique directions. The first storage electrode lines <b>131</b>a and the second storage electrode lines <b>131</b>b have inversion symmetry.

0069The gate lines <b>121</b> and the storage electrode lines <b>131</b>a and <b>131</b>b are preferably made of Al, Cr or their alloys, Mo or Mo alloy. If necessary, the gate lines <b>121</b> and the storage electrode lines <b>131</b>a and <b>131</b>b include a first layer preferably made of Cr or Mo alloys having excellent physical and chemical characteristics and a second layer preferably made of Al or Ag alloys having low resistivity.

0070A gate insulating layer <b>140</b> is formed on the gate lines <b>121</b> and the storage electrode lines <b>131</b>a and <b>131</b>b.

0071A semiconductor layer <b>151</b> and <b>154</b>c preferably made of amorphous silicon is formed on the gate insulating layer <b>140</b>. The semiconductor layer <b>151</b> and <b>154</b>c includes a plurality of channel semiconductors <b>154</b>c forming channels of TFTs and a plurality of data-line semiconductors <b>151</b> located under the data lines <b>171</b>.

0072An ohmic contact layer <b>161</b>, <b>163</b>c and <b>165</b>c preferably made of silicide or n+ hydrogenated amorphous silicon heavily doped with n type impurity is formed on the semiconductor layer <b>151</b> and <b>154</b>c.

0073A plurality of data lines <b>171</b> including a plurality of source electrodes <b>173</b>c, a plurality of drain electrodes <b>175</b>c, and a plurality of DCEs <b>178</b> and <b>178</b>a-<b>178</b>c are formed on the ohmic contact layer <b>161</b>, <b>163</b>c and <b>165</b>c and the gate insulating layer <b>140</b>.

0074The data lines <b>171</b> extend in the longitudinal direction and intersect the gate lines <b>121</b> to define a plurality of pixels. The source electrodes <b>173</b>c and the drain electrodes <b>175</b>c are disposed on respective portions <b>163</b>c and <b>165</b>c opposite each other. Each data line <b>171</b> includes an expanded end portion <b>179</b> for receiving data voltages from an external device.

0075The DCEs <b>178</b> and <b>178</b>a-<b>178</b>c are located in the pixel areas defined by the intersections of the gate lines <b>121</b> and the data lines <b>171</b>. Each DCE <b>178</b> and <b>178</b>a-<b>178</b>c includes a stem <b>178</b> having a “V” shape with a chamfered bottom, a plurality of branches <b>178</b>d and <b>178</b>e having a chevron shape <b>178</b>a, <b>178</b>b and <b>178</b>c.

0076The data lines <b>171</b>, the drain electrodes <b>175</b>c, and the DCEs <b>178</b> and <b>178</b>a-<b>178</b>c are preferably made of Al, Cr or their alloys, Mo or Mo alloy. If necessary, the data lines <b>171</b>, the drain electrodes <b>175</b>c, and the DCEs <b>178</b> and <b>178</b>a-<b>178</b>c include a first layer preferably made of Cr or Mo alloys having excellent physical and chemical characteristics and a second layer preferably made of Al or Ag alloys having low resistivity.

0077A passivation layer <b>180</b> preferably made of silicon nitride or organic insulator is formed on the data lines <b>171</b>, the drain electrodes <b>175</b>c, and the DCEs <b>178</b> and <b>178</b>a-<b>178</b>c.

0078The passivation layer <b>180</b> and the gate insulating layer <b>140</b> are provided with a plurality of contact holes <b>183</b> exposing the end portions <b>125</b> of the gate lines <b>121</b> and a plurality of contact holes <b>184</b> exposing the end portions <b>179</b> of the data lines <b>171</b>.

0079A plurality of first and second PEs <b>190</b>a and <b>190</b>b and a plurality of contact assistants <b>95</b> and <b>97</b> are formed on the passivation layer <b>180</b>.

0080The first PE <b>190</b>a has a pair of oblique cutouts <b>192</b>a and <b>192</b>b, and the second PE <b>190</b>a has two pairs of oblique cutouts <b>194</b>a, <b>194</b>b, <b>195</b>a and <b>195</b>b. The oblique cutouts <b>192</b>a, <b>192</b>b, <b>194</b>a, <b>194</b>b, <b>195</b>a and <b>195</b>b have inversion symmetry with respect to an imaginary line bisecting the PEs <b>190</b>a and <b>190</b>b into upper and lower halves. The cutouts <b>192</b>a, <b>192</b>b, <b>194</b>a, <b>194</b>b, <b>195</b>a and <b>195</b>b overlap the DCE <b>178</b> and <b>178</b>a-<b>178</b>c.

0081The first and the second PEs <b>190</b>a and <b>190</b>b also have inversion symmetry with respect to an imaginary line bisecting the PEs <b>190</b>a and <b>190</b>b into upper and lower halves.

0082A linear gap between the first PE <b>190</b>a and the second PE <b>190</b>b includes a pair of oblique portions <b>193</b>a and <b>193</b>b and a longitudinal portion disposed between the oblique portions <b>193</b>a and <b>193</b>b. The longitudinal portion is shorter than the oblique portions <b>193</b>a and <b>193</b>b.

0083The second PE <b>190</b>b includes two partitions separated from each other by a cutout <b>191</b> parallel to the gate lines <b>121</b>. Since the partitions of the second PE <b>190</b>b have inversion symmetry, they have substantially the same potential although they are separated from each other.

0084The contact assistants <b>95</b> and <b>97</b> are connected to the exposed end portions <b>125</b> of the gate lines <b>121</b> and the exposed end portions <b>179</b> of the data lines <b>171</b> through the contact holes <b>183</b> and <b>184</b>, respectively.

0085The PEs <b>190</b> and the contact assistants <b>95</b> and <b>97</b> are preferably formed of IZO or ITO.

0086To summarize, each PE <b>190</b> has the plurality of cutouts <b>191</b>, <b>192</b>a, <b>192</b>b, <b>193</b>a, <b>193</b>b, <b>194</b>a, <b>194</b>b, <b>195</b>a and <b>195</b>b and some cutouts <b>191</b>, <b>192</b>a, <b>192</b>b, <b>194</b>a and <b>194</b>b overlap the DCE <b>178</b> and <b>178</b>a-<b>178</b>c. The DCE <b>178</b> and <b>178</b>a-<b>178</b>c and the cutouts <b>191</b>, <b>192</b>a, <b>192</b>b, <b>194</b>a and <b>194</b>b are aligned such that the DCE <b>178</b> and <b>178</b>a-<b>178</b>c is exposed through the cutouts <b>191</b>, <b>192</b>a, <b>192</b>b, <b>194</b>a and <b>194</b>b to be seen in front view.

0087The cutouts <b>191</b>, <b>192</b>a, <b>192</b>b, <b>193</b>a, <b>193</b>b, <b>194</b>a, <b>194</b>b, <b>195</b>a and <b>195</b>b partition the pixel area into a plurality of subareas, and liquid crystal regions located on the subareas are called domains. The domains disposed opposite each other with respect to a cutout have different tilt directions and they are classified into four groups based on the tilt directions.

0088According to another embodiment of the present invention, the DCEs <b>178</b> and <b>178</b>a-<b>178</b>c include substantially the same layer as the gate lines <b>121</b>. Portions of the passivation layer <b>180</b> located on the DCEs <b>178</b> and <b>178</b>a-<b>178</b>c may be removed to form a plurality of openings.

0089The upper panel will no be described in detail.

0090A black matrix <b>220</b> for preventing light leakage, a plurality of red, green and blue color filters <b>230</b>, and a common electrode <b>270</b> preferably made of a transparent conductor such as ITO or IZO are formed on a substrate <b>210</b> preferably made of transparent insulating material such glass.

0091A plurality of liquid crystal molecules contained in the liquid crystal layer is aligned such that their director is perpendicular to the lower and the upper substrates <b>110</b> and <b>210</b> in absence of electric field. The liquid crystal layer has negative dielectric anisotropy.

0092The TFT array panel and the color filter panel are aligned such that the PEs <b>190</b>a and <b>190</b>b match and overlap the color filters <b>230</b>. In this way, a pixel region is divided into a plurality of domains by the cutouts <b>191</b>, <b>192</b>a, <b>192</b>b, <b>193</b>a, <b>193</b>b, <b>194</b>a, <b>194</b>b, <b>195</b>a and <b>195</b>b. The alignment of the liquid crystal layer in each domain is stabilized by the DCE <b>178</b> and <b>178</b>a-<b>178</b>c.

0093In addition, the lateral visibility is improved by applying different voltages to the two pixel electrodes <b>190</b>a and <b>190</b>b.

0094This embodiment illustrates the liquid crystal layer having negative dielectric anisotropy and homeotropic alignment with respect to the substrates <b>110</b> and <b>210</b>. However, the liquid crystal layer may have positive dielectric anisotropy and homogeneous alignment with respect to the substrates <b>110</b> and <b>210</b>.

0095A TFT array panel according to another embodiment of the present invention may be manufactured using four photo-etching steps. In this case, a semiconductor layer may have substantially the same planar shape as data lines, source electrode, drain electrodes, DCEs, and underlying ohmic contacts, which is resulted from the patterning using a single photoresist.

0096In the above-described LCD, the domain partitioning is made by the cutouts of the PEs, and the domain stability is reinforced by the DCE and the storage electrode. Therefore, the domain partitioning depends upon the cutout arrangement of the PE, the DCE, and the storage electrodes, and the domain stability is also largely influenced by the arrangement.

0097An exemplary TFT array panel for an LCD according to another embodiment of the present invention is described in detail with reference to <figref idref="DRAWINGS">FIG. 5</figref>.

0098<figref idref="DRAWINGS">FIG. 5</figref> is a layout view of an LCD according to another embodiment of the present invention.

0099As shown in <figref idref="DRAWINGS">FIG. 5</figref>, an LCD according to this embodiment includes a plurality of first and second PEs <b>190</b>a and <b>190</b>b like the LCD shown in <figref idref="DRAWINGS">FIG. 2</figref>. Each of the second PEs <b>190</b>b includes two partitions and a connection connecting the two partitions.

0100Other structures of the TFT panel shown in <figref idref="DRAWINGS">FIG. 6</figref> are similar to those shown in <figref idref="DRAWINGS">FIGS. 1-3</figref>.

0101An exemplary TFT array panel for an LCD according to another embodiment of the present invention is described in detail with reference to <figref idref="DRAWINGS">FIGS. 6-8</figref>.

0102<figref idref="DRAWINGS">FIG. 6</figref> is a layout view of an LCD according to another embodiment of the present invention, <figref idref="DRAWINGS">FIG. 7</figref> is a sectional view of the LCD shown in <figref idref="DRAWINGS">FIG. 6</figref> taken along the line VII-VII′, and <figref idref="DRAWINGS">FIG. 8</figref> is an equivalent circuit diagram of the LCD shown in <figref idref="DRAWINGS">FIGS. 6 and 7</figref>.

0103Referring to <figref idref="DRAWINGS">FIGS. 6-8</figref>, an LCD according to this embodiment also includes a plurality of gate lines <b>121</b>, a plurality of data lines <b>171</b>, and a plurality of pixels connected to the gate lines <b>121</b> and the data lines <b>171</b>. Each pixel includes a pair of LC capacitors Clca and Clcb, DCE capacitors Cdcea and Cdc, a storage capacitor Cst, a coupling capacitor Cpp, and three TFTs T<b>1</b>, T<b>2</b> and T<b>3</b>. The transistor T<b>1</b> has a gate connected to a gate line, a source connected to a data line <b>171</b>, and a drain connected to the capacitors Clca, Cdcea, Cpp and Cst connected in parallel, while the transistor T<b>3</b> has a gate connected to a previous gate line, a source connected to the data line, and a drain connected to the capacitors Cdcea and Cdc connected in parallel. The transistor T<b>2</b> has a gate connected to the previous gate line, a source connected to a previous data line, and a drain connected to the capacitors Clca, Cdcea, Cpp and Cst. The capacitor Clcb is connected between the capacitor Cpp and a predetermined voltage such as the common voltage Vcom, the capacitors Clca and Cdc are connected in common to a predetermined voltage such as the common voltage Vcom, and the capacitor Cst is connected to a predetermined voltage such as the common voltage Vcom.

0104In structural view, the LCD according to this embodiment also includes a TFT array panel, a color filter array panel facing the TFT array panel and separated with a predetermined gap, and a liquid crystal layer filled in the predetermined gap, as shown in <figref idref="DRAWINGS">FIGS. 6 and 7</figref>.

0105Referring to <figref idref="DRAWINGS">FIGS. 1-3</figref>, the TFT array panel includes a plurality of gate lines <b>121</b> transmitting scanning signals, a plurality of data lines <b>171</b> transmitting data signals as well as a plurality of pairs of storage electrode lines <b>131</b>a and <b>131</b>b transmitting a predetermined voltage such as the common voltage Vcom. The gate lines <b>121</b> and the data lines <b>171</b> intersect each other to define a plurality of pixel areas.

0106Each pixel area is provided with first and second PEs <b>190</b>a and <b>190</b>b, a coupling electrode <b>176</b>, a DCE <b>178</b>, first and second PE TFTs (indicated by the reference numerals T<b>1</b> and T<b>3</b> in <figref idref="DRAWINGS">FIG. 8</figref>) for the PEs <b>190</b>a and <b>190</b>b, and a DCE TFT (indicated by the reference T<b>2</b> in <figref idref="DRAWINGS">FIG. 8</figref>) for the DCE <b>178</b>. The first PE TFT T<b>1</b> includes a gate electrode <b>121</b>a connected to a gate line <b>121</b>, a source electrode <b>173</b>ab connected to a data line <b>171</b>, and a drain electrode <b>175</b>a connected to the first PE <b>190</b>a, while the second PE TFT T<b>3</b> includes a gate electrode <b>123</b>b connected to a previous gate line <b>121</b>, a source electrode <b>173</b>ab connected to the data line <b>171</b>, and a drain electrode <b>175</b>b connected to the first PE <b>190</b>a. The DCE TFT T<b>2</b> includes a gate electrode <b>123</b>c connected to the previous gate line <b>121</b>, a source electrode <b>173</b>c connected to a previous data line, and a drain electrode <b>175</b>c connected to the DCE <b>178</b>.

0107The color filter array panel includes a plurality of color filters <b>230</b> and a common electrode <b>270</b> supplied with the common voltage Vcom.

0108The first and the second PEs <b>190</b>a and <b>190</b>b and the common electrode <b>270</b> along with the liquid crystal layer interposed therebetween form a pair of liquid crystal (LC) capacitors indicated by Clca and Clcb shown in <figref idref="DRAWINGS">FIG. 8</figref>. The first and the second PEs <b>190</b>a and <b>190</b>b and the storage electrode lines <b>131</b>a and <b>131</b>b along with an insulator disposed therebetween form a storage capacitor represented by Cst. The DCE <b>178</b> and the first PE <b>190</b>a are capacitively coupled to form a DCE capacitor represented by Cdcea, and the DCE <b>178</b> and the common electrode <b>270</b> are capacitively coupled to for a DCE capacitor Cdc. The first PE <b>190</b>a and the second PE <b>190</b>b are capacitively coupled through the coupling capacitor <b>176</b> to form a coupling capacitor Cpp.

0109The PEs <b>190</b>a and <b>190</b>b have a plurality of cutouts <b>191</b>, <b>192</b>a, <b>192</b>b, <b>193</b>a, <b>193</b>b, <b>194</b>a, <b>194</b>b, <b>195</b>a and <b>195</b>b overlapping the DCE <b>178</b> and the coupling electrode <b>176</b> such that electric fields generated by the DCE <b>178</b> and the coupling electrode <b>176</b> go out through the cutouts <b>191</b>, <b>192</b>a, <b>192</b>b, <b>193</b>a, <b>193</b>b, <b>194</b>a, <b>194</b>b, <b>195</b>a and <b>195</b>b. The electric fields generated by the DCE <b>178</b> and the coupling electrode <b>176</b> pre-tilt liquid crystal molecules in the liquid crystal layer. The pretilted liquid crystal molecules are rapidly tilted without dispersion upon the application of the electric field generated by the first and the second PEs <b>190</b>a and <b>190</b>b.

0110The lateral visibility is improved by applying somewhat different voltages to the first and the second PEs <b>190</b>a and <b>190</b>b.

0111It is assumed that the LCD having the above-described structure is subject to a dot inversion. Referring to <figref idref="DRAWINGS">FIG. 8</figref>, a gate-on voltage applied to a previous gate line turns on the transistors T<b>2</b> and T<b>3</b> such that the DCE <b>178</b> is charged with a data voltage having a positive polarity with respect to the common voltage Vcom, while the first PE <b>190</b>a is charged with a data voltage having a negative polarity. Accordingly, the initial voltage charged in the DCE capacitor Cdcea is equal to the voltage difference between the positive data voltage and the negative data voltage. When the gate-on voltage is applied to a relevant gate line, the transistor T<b>1</b> is turned on to apply a positive data voltage to the first PE <b>190</b>a and the transistors T<b>2</b> and T<b>3</b> are turned off to float the DCE <b>178</b>. Accordingly, the voltage Vdce of the DCE <b>178</b> increases as the voltage Va of the first PE <b>190</b>a increases.

0112Accordingly, the DCE voltage Vdce is always higher than the pixel voltage Va of the first PE <b>190</b>a by an amount of (Vdce−Va), thereby obtaining pre-tilt angles of the liquid crystal molecules.

0113The voltage Vdce of the DCE <b>178</b> is given by: <br />Vdce=Vd1+[−C3×Vd1+(C2+C3)Vd2+C2×Vd3]/(C2+C3),<br /> where <br />C1=Clac+Cst+(Cpp×Clcb)/(Cpp+Clcb),<br />C<b>2</b>=Cdcea, and<br />C<b>3</b>=Cdc.

0114Here, the parasitic capacitance between the gate electrode and the drain electrode of the transistors is ignored.

0115The pixel voltage Vb of the second PE <b>190</b>b is calculated from the voltage distribution rule: <br />Vb=Va×Cpp/(Cpp+Clcb).

0116Since Cpp/(Cpp+Clcb) is smaller than 1, the pixel voltage Va is higher than the pixel voltage Vb by a predetermined portion.

0117As described above, two PEs having different voltages in a pixel area compensate to improve the lateral visibility.

0118<figref idref="DRAWINGS">FIGS. 9 and 10</figref> are equivalent circuit diagrams of LCDs according to embodiments of the present invention.

0119As shown in <figref idref="DRAWINGS">FIG. 9</figref>, the source of the DCE transistor T<b>2</b> is grounded or connected to the common voltage Vcom through such as a storage electrode line. Referring to <figref idref="DRAWINGS">FIGS. 6 and 7</figref>, the connection is obtained by providing a contact hole penetrating the gate insulating layer <b>140</b> and the passivation layer <b>180</b> to expose the storage electrode line <b>131</b>a or <b>131</b>b and a contact hole penetrating the passivation layer <b>180</b> to expose the source electrode <b>173</b>c and by forming a connection (not shown) for connecting the source electrode <b>173</b>c to the storage electrode line <b>131</b>a or <b>131</b>b.

0120Assuming the parasitic capacitance between the gate electrode and the drain electrode of the transistors is negligible, the voltage Vdce of the DCE <b>178</b> shown in <figref idref="DRAWINGS">FIG. 9</figref> is given by: <br />Vdce=Vd1+[−C3×Vd1+C2×Vd3]/(C2+C3),<br /> where C<b>1</b>=Clac+Cst+(Cpp×Clcb)/(Cpp+Clcb), C<b>2</b>=Cdcea, and C<b>3</b>=Cdc.

0121As shown in <figref idref="DRAWINGS">FIG. 10</figref>, the source of the second PE transistor T<b>2</b> is grounded or connected to the common voltage Vcom through such as a storage electrode line. Referring to <figref idref="DRAWINGS">FIGS. 6 and 7</figref>, the connection is obtained by providing a contact hole penetrating the gate insulating layer <b>140</b> and the passivation layer <b>180</b> to expose the storage electrode line <b>131</b>a or <b>131</b>b and a contact hole penetrating the passivation layer <b>180</b> to expose the source electrode <b>173</b>ab of the second PE transistor T<b>2</b> and by forming a connection (not shown) for connecting the source electrode <b>173</b>ab to the storage electrode line <b>131</b>a or <b>131</b>b.

0122Assuming the parasitic capacitance between the gate electrode and the drain electrode of the transistors is negligible, the voltage Vdce of the DCE <b>178</b> shown in <figref idref="DRAWINGS">FIG. 10</figref> is given by: <br />Vdce=Vd1+[−C3×Vd1+(C2+C3)Vd2]/(C2+C3)<br /> where C<b>1</b>=Clac+Cst+(Cpp×Clcb)/(Cpp+Clcb), C<b>2</b>=Cdcea, and C<b>3</b>=Cdc.

0123<figref idref="DRAWINGS">FIG. 11</figref> is a layout view of an LCD according to another embodiment of the present invention, and <figref idref="DRAWINGS">FIG. 12</figref> is an equivalent circuit diagram of the LCD shown in <figref idref="DRAWINGS">FIG. 11</figref>.

0124Referring to <figref idref="DRAWINGS">FIGS. 11 and 12</figref>, the second PE TFT T<b>3</b> is omitted.

0125Assuming the parasitic capacitance between the gate electrode and the drain electrode of the transistors is negligible, the voltage Vdce of the DCE <b>178</b> shown in <figref idref="DRAWINGS">FIGS. 11 and 12</figref> is given by: <br />Vdce=(C1+C3)[(2−C3/C2)Vd1+Vd2]/(2C2+C1)<br /> where C<b>1</b>=Clac+Cst+(Cpp×Clcb)/(Cpp+Clcb), C<b>2</b>=Cdcea, and C<b>3</b>=Cdc.

0126As described above, the LCDs shown in <figref idref="DRAWINGS">FIGS. 6-12</figref> include the coupling electrodes <b>176</b> for capacitively coupling the first PE <b>190</b>a and the second PE <b>190</b>b.

0127<figref idref="DRAWINGS">FIG. 13</figref> is a layout view of an LCD according to another embodiment of the present invention, and <figref idref="DRAWINGS">FIG. 14</figref> is an equivalent circuit diagram of the LCD shown in <figref idref="DRAWINGS">FIG. 13</figref>.

0128Referring to <figref idref="DRAWINGS">FIG. 13</figref>, the coupling electrode <b>176</b> shown in <figref idref="DRAWINGS">FIGS. 6-12</figref> is omitted and thus there is not coupling capacitor Cpp shown in <figref idref="DRAWINGS">FIGS. 6-12</figref>. Instead, the DCE <b>178</b> is capacitively coupled with both the first and the second pixel electrodes <b>190</b>a and <b>190</b>b to form a pair of DCE capacitors Cdcea and Cdceb.

0129Accordingly, the capacitors Cdcea, Cdceb and Cdc are connected in parallel to the drain of the DCE TFT T<b>2</b>, and the capacitors Clca, Clcb and Cdc are connected in parallel to the common voltage Vcom. The capacitors Clca, Cdcea and Cst are connected in parallel to the first PE TFT T<b>1</b> and the storage capacitor Cst is connected to a predetermined voltage such as the common voltage Vcom. The DCE capacitor Cdceb and the LC capacitor Clcb are connected in series.

0130The voltage Vdce of the DCE <b>178</b> is given by: <br />Vdce=Vd1+[−C3×Vd1+(C2+C3)Vd2+C2×Vd3]/(C2+C3),<br /> where <br />C1=Clac+Cst,<br />C<b>2</b>=Cdcea, and<br />C3=Cdc+(Cdecb×Clcb)/(Cdceb+Clcb).

0131Here, the parasitic capacitance between the gate electrode and the drain electrode of the transistors is ignored.

0132The pixel voltage Vb of the second PE <b>190</b>b is calculated from the voltage distribution rule: <br />Vb=Vdce×Cdceb/(Cdceb+Clcb)

0133As described above, two PEs having different voltages in a pixel area compensate to improve the lateral visibility.

0134<figref idref="DRAWINGS">FIGS. 15 and 16</figref> are equivalent circuit diagrams of LCDs according to embodiments of the present invention.

0135As shown in <figref idref="DRAWINGS">FIG. 15</figref>, the source of the DCE transistor T<b>2</b> is grounded or connected to the common voltage Vcom through such as a storage electrode line.

0136Assuming the parasitic capacitance between the gate electrode and the drain electrode of the transistors is negligible, the voltage Vdce of the DCE <b>178</b> shown in <figref idref="DRAWINGS">FIG. 15</figref> is given by: <br />Vdce=Vd1+[−C3×Vd1+C2×Vd3]/(C2+C3),<br /> where C<b>1</b>=Clac+Cst, C<b>2</b>=Cdcea, and C<b>3</b>=Cdc+(Cdecb×Clcb)/(Cdceb+Clcb).

0137As shown in <figref idref="DRAWINGS">FIG. 16</figref>, the source of the second PE transistor T<b>2</b> is grounded or connected to the common voltage Vcom through such as a storage electrode line.

0138Assuming the parasitic capacitance between the gate electrode and the drain electrode of the transistors is negligible, the voltage Vdce of the DCE <b>178</b> shown in <figref idref="DRAWINGS">FIG. 16</figref> is given by: <br />Vdce=Vd1+[−C3×Vd1+(C2+C3)Vd2]/(C2+C3)<br /> where C<b>1</b>=Clac+Cst, C<b>2</b>=Cdcea, and C<b>3</b>=Cdc+(Cdecb×Clcb)/(Cdceb+Clcb).

0139<figref idref="DRAWINGS">FIG. 17</figref> is a layout view of an LCD according to another embodiment of the present invention, and <figref idref="DRAWINGS">FIG. 18</figref> is an equivalent circuit diagram of the LCD shown in <figref idref="DRAWINGS">FIG. 11</figref>.

0140Referring to <figref idref="DRAWINGS">FIGS. 17 and 18</figref>, the second PE TFT T<b>3</b> is omitted.

0141Assuming the parasitic capacitance between the gate electrode and the drain electrode of the transistors is negligible, the voltage Vdce of the DCE <b>178</b> shown in <figref idref="DRAWINGS">FIGS. 11 and 12</figref> is given by: <br />Vdce=(C1+C3)[(2−C3/C2)Vd1+Vd2]/(2C2+C1)<br /> where C<b>1</b>=Clac+Cst, C<b>2</b>=Cdcea, and C<b>3</b>=Cdc+(Cdecb×Clcb)/(Cdceb+Clcb).

0142As described above, the DCE stabilizes the domains and the pair of PEs supplied with different voltages improves the lateral visibility.

0143While the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art will appreciate that various modifications and substitutions can be made thereto without departing from the spirit and scope of the present invention as set forth in the appended claims.