Dynamic forward error correction

FIELD OF THE INVENTION

0001The present inventions pertain to the field of error correction in communication systems, including more specifically, forward error correction arrangements.

BACKGROUND OF THE INVENTION

0002Digital communications systems utilize communication channels over which traffic data is communicated. These channels are typically bandwidth limited, having a finite channel capacity. The channel capacity together with other properties of the channel, such as various forms of noise and interference, will, with statistical certainty, cause, or otherwise result, in the injection of error conditions in the traffic data communicated over the channel. The effects of these error conditions may be particularly evident in wireless communications systems, which utilize generally unpredictable over-the-air communications channels through which remote stations communicate with a central station.

0003A technique for eliminating, or at least reducing, the effects of these error conditions is called Forward Error Correction (FEC). In general, the employment of an FEC technique entails transmitting error detection data and error correction data along with the bearer data. The error detection data and error correction data are typically derived from the bearer data itself by employing an error detection algorithm and error correction algorithm known to the receiver as well as the transmitter, and in the case of a digital wireless communications systems, a remote station and a central station in communication with one another.

0004FEC techniques have been employed in Time Division Multiple Access (TDMA) and Code Division Multiple Access (CDMA) wireless communications systems. For example, TDMA systems typically allow communication between a plurality of remote stations and a central station using the same frequency band and transmitting bearer data between remote stations and the central station during discrete time periods (i.e., each remote station transmits and receives bearer data broken up into bearer data bursts during respective time slots of cyclically repeating time frames).

0005In wireless communication, prior to transmission, the central station or remote station appends or encodes the bearer data with error detection data and error correction data according to a respective error detection algorithm and error correction algorithm. The reciprocal remote station or central station receives each error correctable bearer data packet, automatically corrects any errors in each error correctable bearer data packet (within the limits of the error correction algorithm) by processing the error correctable bearer data packet according to the error correction algorithm, and detects any residual errors in each corrected bearer data packet by processing the corrected bearer data packet according to the error detection algorithm.

0006The use of an FEC technique to eliminate or reduce the effects of transmission errors, however, does not come without a cost to the communications system. The transmission bandwidth available to a user transmitting in a particular time slot in known systems is reduced by the overhead required to transmit the error correction data. The transmission of error correction data with each error correctable bearer data packet can require 100% or more overhead in some instances. This increase in overhead typically results in either a longer time slot or a reduction in the bandwidth available for the traffic data (for a fixed transmission bit rate). In addition, in known wireless communications systems, the Bit Error Rate (BER) of the traffic data communicated between a central station and a remote station depends on dynamically varying conditions, such as, the relative distance between the remote station and the central station, interference, environmental conditions, traffic data transmission rate, etc.

0007As a result, the BER of bearer data transmitted between the central station and a remote station varies with each particular remote station and with time with respect to each remote station making it difficult to systematically select an FEC error correction algorithm that optimizes both the transmission overhead and error protection capability. To provide high quality communication between the central station and any given remote station during any given time period, the error correction algorithm is generally selected based on the worst-case BER, and is thus overly robust in most situations, resulting in undesirably high overhead and reduced overall data throughput for the system.

0008There thus is a need for a communications system that employs an FEC arrangement that among other things, maximizes the amount of bearer data transmitted between the central station and any given remote station at any given time, while still providing an acceptable error rate.

SUMMARY OF THE INVENTION

0009The present inventions comprise a novel method of dynamically varying the transmission of error correction data in communications systems.

0010In a preferred method of the present inventions, a first plurality of error correctable bearer data packets is transmitted between a first communications device and a second communications device during a first multi-frame (i.e., a plurality of time frames). An initial error correction algorithm is selected from a plurality of error correction algorithms, which is then employed to generate error correction data. The error correction data is transmitted with the bearer data packets by, such as, e.g., appending or encoding the error correction data thereto, creating the first plurality of error correctable bearer data packets. The plurality of error correction algorithms can comprise any number of different error correction algorithms, which may include no error correction algorithm. Upon receipt of the first plurality of error correctable bearer data packets, errors that are injected into the first plurality of error correctable bearer data packets during the transmission thereof are corrected within the limits of the selected error correction algorithm.

0011The error rate level of the communications channel between the first communications terminal and the second communications terminal is determined during the first multi-frame. The error rate level of the communications channel may be determined by such techniques as, e.g., measuring the number of defective corrected bearer data packets (i.e., block error rate (BLER)) or measuring the number of bit errors in the uncorrected bearer data packets (i.e., bit error rate (BER)). A subsequent error correction algorithm, which may be the same as the initial error correction algorithm, is selected from the plurality of error correction algorithms based in part upon the determined error rate level.

0012A second plurality of error correctable bearer data packets is transmitted between the first communications terminal and the second communications terminal during a second multi-frame. The subsequent selected error correction algorithm is employed to generate error correction data, which is transmitted with the second plurality of error correctable bearer data packets. The second plurality of error correctable bearer data packets are corrected within the limits of the second selected error correction algorithm. The error rate level of the communication channel between the first communications terminal and the second communications terminal is determined during the second multi-frame. A third error correction algorithm, which can be the same as or different from the second selected error correction algorithm, is selected from the plurality of error correction algorithms based in part upon the determined error rate level.

0013The third selected error correction algorithm is employed to correct the third plurality of error correctable bearer data packets transmitted between the first communications terminal and the second communications terminal during the third multi-frame. This error correction algorithm selection and error correctable bearer data packet correction process is repeated during future multi-frames.

BRIEF DESCRIPTION OF THE DRAWINGS

0014<figref idref="DRAWINGS">FIG. 1</figref> is a representative block diagram of a wireless communication system cell showing an FEC dynamic central station communicating with a plurality of FEC dynamic remote stations;

0015<figref idref="DRAWINGS">FIG. 2</figref> depicts TDMA/FDD formatted downlink time frames and uplink time frames divided into a plurality of time slots;

0016<figref idref="DRAWINGS">FIG. 3</figref> depicts TDMA/TDD formatted downlink/uplink time frames divided into a plurality of time slots;

0017<figref idref="DRAWINGS">FIG. 4A</figref> is a representative block diagram of the FEC dynamic central station and one of the FEC dynamic remote stations;

0018<figref idref="DRAWINGS">FIG. 4B</figref> is a representative block diagram of an alternative embodiment of the FEC dynamic central station and one of the FEC dynamic remote stations;

0019<figref idref="DRAWINGS">FIG. 5A</figref> is a representative block diagram of an FEC dynamic remote station processor;

0020<figref idref="DRAWINGS">FIG. 5B</figref> is a representative block diagram of an alternative embodiment of an FEC dynamic remote station processor;

0021<figref idref="DRAWINGS">FIG. 6</figref> is a representative block diagram of an FEC dynamic central station processor;

0022<figref idref="DRAWINGS">FIG. 7</figref> depicts TDMA formatted multi-frames divided into a plurality of time frames;

0023<figref idref="DRAWINGS">FIG. 8</figref> depicts the arrangement of <figref idref="DRAWINGS">FIGS. 8A and 8B</figref>;

0024<figref idref="DRAWINGS">FIGS. 8A and 8B</figref> are flow diagram illustrating a protocol for dynamically selecting an error correction algorithm;

0025<figref idref="DRAWINGS">FIG. 9</figref> depicts the arrangement of <figref idref="DRAWINGS">FIGS. 9A and 9B</figref>; and

0026<figref idref="DRAWINGS">FIGS. 9A and 9B</figref> are flow diagram illustrating an alternative protocol for dynamically selecting an error correction algorithm.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

0027<figref idref="DRAWINGS">FIG. 1</figref> depicts a TDMA wireless communication system <b>100</b> arranged to operate in accordance with a preferred embodiment of the present inventions. An FEC dynamic central station <b>104</b> is depicted as communicating with respective FEC dynamic remote stations <b>106</b> within a cell <b>102</b>. The cell <b>102</b> can be a macro-cell, micro-cell, wireless local loop, or any network in which multiple communication devices can communicate with one another. The FEC dynamic central station <b>104</b> can be a base station, base station controller, mobile switching center, or any communication device that can communicate with multiple remote stations. The FEC dynamic remote stations <b>106</b> can be any combination of remote terminals (e.g., mobile handsets, wireless modems, wired communication terminals (R<b>54</b>), or wireless local loop terminals).

0028The FEC dynamic central station <b>104</b> and respective FEC dynamic remote stations <b>106</b> communicate in a Time Division Multiple Access/Frequency Division Duplex (TDMA/FDD) format. That is, respective communications between the FEC dynamic central station <b>104</b> and each of the FEC dynamic remote stations <b>106</b> are time isolated, and the downlink communication between the FEC dynamic central station <b>104</b> and a particular FEC dynamic remote station <b>106</b> is frequency isolated from the uplink communication between the FEC dynamic central station <b>104</b> and that particular FEC dynamic remote station <b>106</b>. The FEC dynamic central station <b>104</b> transmits data to the FEC dynamic remote stations <b>106</b> over a single downlink frequency, such as, 1960 MHZ, and the FEC dynamic remote stations <b>106</b> transmit data to the FEC dynamic central station <b>104</b> over a single uplink frequency, such as, 1880 MHZ.

0029As shown in <figref idref="DRAWINGS">FIG. 2</figref>, the downlink frequency is divided into cyclically repeating downlink time frames <b>108</b>(<b>1</b>), and the uplink frequency is divided into cyclically repeating uplink time frames <b>108</b>(<b>2</b>). The time frames <b>108</b>(<b>1</b>)/(<b>2</b>) are further divided into respective sets of time slots <b>110</b>(<b>1</b>)/(<b>2</b>). The uplink time frames <b>108</b>(<b>2</b>) are synchronized with the downlink time frames <b>108</b>(<b>1</b>).

0030The FEC dynamic remote stations <b>106</b> are respectively assigned time slots <b>110</b>(<b>1</b>) in the downlink time frames <b>108</b>(<b>1</b>) during which they receive downlink error correctable bearer data packets from the FEC dynamic central station <b>104</b> (in this case, time slots D<b>1</b>, D<b>3</b>, D<b>5</b>, and D<b>6</b> for respective FEC dynamic remote stations <b>1</b>-<b>4</b>). As such, the FEC dynamic central station <b>104</b> is assigned the same time slots <b>110</b>(<b>1</b>) during which it transmits downlink error correctable bearer data packets to the respective FEC dynamic remote stations <b>106</b>. The FEC dynamic remote stations <b>106</b> are respectively assigned time slots <b>110</b>(<b>2</b>) in the uplink time frames <b>108</b>(<b>2</b>) during which they transmit uplink error correctable bearer data packets to the FEC dynamic central station <b>104</b> (in this case, time slots U<b>4</b>, U<b>6</b>, U<b>8</b>, and U<b>1</b> for respective FEC dynamic remote stations <b>1</b>-<b>4</b>). As such, the FEC dynamic central station <b>104</b> is assigned the same respective time slots <b>110</b> during which it receives uplink error correctable bearer data packets from the respective FEC dynamic remote stations <b>106</b>. As can be seen, several time slots of delay, and in this case three, are induced between corresponding downlink time slots <b>110</b>(<b>1</b>) and uplink time slots <b>110</b>(<b>2</b>) to obviate the need for installing additional equipment in the FEC dynamic remote stations <b>106</b>. Depending on the particular protocol of the system, the empty time slots <b>110</b>(<b>1</b>)/(<b>2</b>) are used as idle time slots for anticipated usage by other FEC dynamic remote stations <b>106</b>, or alternatively, to support various other functions, such as transmission of control data between the FEC dynamic central station <b>104</b> and the FEC dynamic remote stations <b>106</b> or transmission of broadcast data from the FEC dynamic central station <b>104</b>.

0031Alternatively, the wireless communications system <b>100</b> is configured in a TDMA/TDD format, wherein a single frequency is utilized for both downlink and uplink transmission of bearer data, and the downlink communication between the FEC dynamic central station <b>104</b> and a particular FEC dynamic remote station <b>106</b> is time isolated from the uplink communication between the FEC dynamic central station <b>104</b> and that particular FEC dynamic remote station <b>106</b>. As shown in <figref idref="DRAWINGS">FIG. 3</figref>, the downlink/uplink frequency is divided into cyclically repeating time frames <b>108</b>(<b>3</b>), which are further divided into time slots <b>110</b>(<b>3</b>). Half of the time slots <b>110</b>(<b>3</b>) are dedicated to downlink transmissions of data, and half of the time slots <b>110</b>(<b>3</b>) are dedicated to uplink transmissions of data. It should be noted, however, that number of time slots <b>110</b>(<b>3</b>) dedicated to the respective downlink and uplink transmissions can be unbalanced. Each FEC dynamic remote station <b>106</b> is assigned a pair of time slots <b>110</b>(<b>3</b>) during which it can respectively receive downlink error correctable bearer data packets from the FEC dynamic central station <b>104</b> and transmit uplink error correctable bearer data packets to the FEC dynamic central station <b>104</b> (in this case, time slots (D<b>1</b>,U<b>1</b>), (D<b>2</b>,U<b>2</b>), (D<b>3</b>,U<b>3</b>), and (D<b>4</b>,U<b>4</b>) for respective FEC dynamic remote stations <b>1</b>-<b>4</b>). As such, the FEC dynamic central station <b>104</b> transmits downlink error correctable bearer data packets to the respective FEC dynamic remote stations <b>106</b> and receives uplink error correctable bearer data packets from the respective FEC dynamic remote stations <b>106</b> during the same pairs of time slots <b>110</b>(<b>3</b>).

0032Although <figref idref="DRAWINGS">FIG. 1</figref> depicts only four FEC dynamic remote stations <b>106</b> in communication with the FEC dynamic central station <b>104</b> over a single frequency pair (TDMA/FDD) or single frequency (TDMA/TDD), in reality, the FEC dynamic central station <b>104</b> simultaneously communicates with many other FEC dynamic remote stations <b>106</b> over a broad range of frequencies or frequency pairs.

0033<figref idref="DRAWINGS">FIG. 4A</figref> depicts a block diagram of the FEC dynamic central station <b>104</b> and one of the FEC dynamic remote stations <b>106</b> of the wireless communications system <b>100</b> in communication with each other. The FEC dynamic central station <b>104</b> and the FEC dynamic remote station <b>106</b> utilize a reciprocal adaptive FEC arrangement to ensure proper and efficient communication between the FEC dynamic central station <b>104</b> and the FEC dynamic remote station <b>106</b>.

0034The FEC dynamic remote station <b>106</b> transmits uplink error correctable bearer data packets to the FEC dynamic central station <b>104</b> in accordance with the TDMA/FDD or TDMA/TDD arrangement as respectively depicted in <figref idref="DRAWINGS">FIGS. 2 and 3</figref>. The FEC dynamic remote station <b>106</b> comprises a processor <b>112</b> that orchestrates the timing of the error correctable uplink bearer data transmissions. The uplink error correctable bearer data packets comprise uplink traffic data originating from an input/output device <b>114</b> electrically coupled to the FEC dynamic remote station <b>106</b>. The input/output device <b>114</b> is typically a voice encoder/decoder or data source/sink, such as, e.g., a personal computer (PC). The processor <b>112</b> is electrically coupled to and performs handshaking operations with the input/output device <b>114</b> during which uplink traffic data is transferred from the input/output device <b>114</b>. The amount of uplink traffic data transferred from the input/output device <b>114</b> to form a single uplink bearer data packet can be varied by the processor <b>112</b>. The input/output device <b>114</b> is electrically coupled and transfers uplink bearer data packets to an error detection encoder <b>116</b>.

0035The processor <b>112</b> is also electrically coupled and transfers uplink control data (such as, e.g., status data informing the FEC dynamic central station <b>104</b>), to the error detection encoder <b>116</b>. The error detection encoder <b>116</b> appends the uplink bearer data packet with the uplink control data. The error detection encoder <b>116</b> also generates error detection data according to a cyclical redundancy check (CRC) algorithm and appends the uplink bearer data packet with the error detection data. The error detection encoder <b>116</b> can, however, employ other types of error detection algorithms without straying from the principles taught by this invention.

0036The error detection encoder <b>116</b> is electrically coupled to an error correction encoder <b>118</b>, which appends error correction data onto the uplink bearer data packet according to an error correction algorithm, and in this case a Hamming error correction algorithm, to form an uplink error correctable bearer data packet. In alternative embodiments, a single error correction/error detection encoder comprises the error correction encoder <b>118</b> and error detection encoder <b>116</b>.

0037The error correction encoder <b>118</b> is dynamic in that it is configured to employ, on-command, no error correction algorithm, thus generating no error correction data; a low-level Hamming error correction algorithm, which generates error correction data requiring 20% overhead to transmit for each uplink error correctable bearer data packet; or a high-level Hamming error correction algorithm, which generates error correction data requiring 100% overhead to transmit for each uplink error correctable bearer data packet. The overhead percentage is defined as the amount of error correction data relative to the amount of traffic data in an error correctable bearer data packet. As described further below, the processor <b>112</b> dynamically selects the particular error correction algorithm to be employed by the error correction encoder <b>118</b>. In alternative embodiments, the particular type and amount of error correction algorithms available to the error correction encoder <b>118</b> vary from those described above. For instance, eleven error correction algorithms, whether of the Hamming type or otherwise, can be employed, with the overhead of the error correction algorithms varying by 10% between a range of 0% and 100%. In further alternative embodiments, an error correction algorithm can be variable, so that, rather than selecting an error correction algorithm, the overhead of the error correction algorithm is varied.

0038The error correction encoder <b>118</b> is electrically coupled to a modulator <b>120</b>, which modulates the uplink error correctable bearer data packet onto a carrier frequency. The modulator <b>120</b> is electrically coupled to transmitter <b>122</b>, which amplifies and filters the uplink error correctable bearer data packet. The transmitter is electrically coupled to an antenna <b>124</b>, which transmits the uplink error correctable bearer data packet over-the-air to the FEC dynamic central station <b>104</b>.

0039The FEC dynamic remote station <b>106</b> also receives downlink error correctable bearer data packets from the FEC dynamic central station <b>104</b> in accordance with the TDMA/FDD or TDMA/TDD arrangement respectively depicted in <figref idref="DRAWINGS">FIGS. 2 and 3</figref>. As with the uplink bearer data transmissions, the FEC dynamic remote station processor <b>112</b> orchestrates the timing of the downlink bearer data reception. The downlink error correctable bearer data packets comprise downlink traffic data originating from an input/output device <b>114</b>′ electrically coupled to the FEC dynamic central station <b>104</b>. The input/output device <b>114</b>′ on the FEC dynamic central station <b>104</b> side of the wireless communications system <b>100</b> is typically an interface to a communications network, such as, e.g., a Public Switched Telephone Network (PSTN), or a data network, such as, e.g., the internet.

0040The antenna <b>124</b> receives a downlink error correctable bearer data packet over-the-air from the FEC dynamic central station <b>104</b>. The antenna <b>124</b> is electrically coupled to the receiver <b>126</b>, which selects the downlink error correctable bearer data packet channel. The receiver <b>126</b> is electrically coupled to a demodulator <b>128</b>, which extracts the downlink error correctable bearer data packet from the radio frequency carrier.

0041The demodulator <b>128</b> is electrically coupled to an error correction decoder <b>130</b>, which processes and corrects the downlink error correctable bearer data packet according to an error correction algorithm, and in this case, a Hamming error correction algorithm. Like the error correction encoder <b>118</b>, the error correction decoder <b>130</b> is dynamic in that it is configured to operate in a manner consistent with the encoder algorithm applied to the current error correctable bearer data packet. As described further below, the processor <b>112</b> dynamically selects the particular error correction algorithm to be employed by the error correction decoder <b>130</b>. In alternative embodiments, the particular type and amount of error correction algorithms available to the error correction decoder <b>130</b> vary from those described above.

0042The error correction decoder <b>130</b> can only correct the downlink error correctable bearer data packet within the limits of the particular error correction algorithm employed. Although the error correction decoder <b>130</b> attempts to correct the downlink error correctable bearer data packet, it is possible that the error correction decoder <b>130</b> can output a corrected downlink error correctable bearer data packet with a residual error.

0043The error correction decoder <b>130</b> is electrically coupled and transfers the corrected downlink error correctable bearer data packet to an error detection decoder <b>132</b>, which processes and detects any residual errors in the corrected downlink error correctable bearer data packets according to an error detection algorithm, such as a CRC error detection algorithm. The error detection decoder <b>132</b> can, however, employ other types of error detection algorithms without straying from the principles taught by this invention. In alternative embodiments, a single error correction/error detection decoder comprises the error correction decoder <b>130</b> and error detection decoder <b>132</b>.

0044The error detection decoder <b>132</b> separates the downlink control data from the corrected downlink bearer data packet, and may provide an indication that the corrected bearer data packet still has an error, initiating a bearer data packet retransmission. The error detection decoder <b>132</b> is electrically coupled and transfers the downlink bearer data packet to the input/output device <b>114</b> as downlink traffic data. The error detection decoder <b>132</b> is also electrically coupled and transfers the control data to the processor <b>112</b>. The processor <b>112</b> is electrically coupled to and performs handshaking operations with the input/output device <b>114</b> during which downlink traffic data is transferred to the input/output device <b>114</b>. The amount of downlink traffic data transferred to the input/output device <b>114</b> can be varied by the processor <b>112</b>.

0045The FEC dynamic remote station processor <b>112</b> not only controls the timing of the transmission and reception functions of the FEC dynamic remote station <b>106</b>, but is also internally configured and arranged with the input/output device <b>114</b>, error correction encoder <b>118</b>, error correction decoder <b>130</b>, and error detection decoder <b>132</b> to orchestrate the reciprocal dynamic FEC arrangement of the present invention.

0046As shown in <figref idref="DRAWINGS">FIG. 5A</figref>, the FEC dynamic remote station processor <b>112</b> comprises a Central Processing Unit (CPU) <b>134</b>, which performs the processing functions in the FEC dynamic remote station <b>106</b>. The processor <b>112</b> further comprises instructions that allow the FEC dynamic remote station <b>106</b> to dynamically generate uplink error correctable bearer data packets and dynamically correct downlink error correctable bearer data packets in accordance with the present inventions. These instructions preferably take the form of a computer software program embedded in memory, such as, e.g., a ROM chip, or fixed logic, such as, e.g., an ASIC, which can be either on-board or separate from the CPU <b>134</b>. The FEC dynamic remote station processor <b>112</b> further comprises various memory locations for the storage of status data concerning the FEC arrangement employed by the wireless communications system <b>100</b>. For the purposes of illustration, these memory locations are depicted in <figref idref="DRAWINGS">FIG. 5A</figref> as registers. It should be understood, however, that any memory storage vehicle that allows for the storage and access of data can be employed.

0047The FEC dynamic remote station processor <b>112</b> tracks the respective error correction algorithms that are employed by the error correction encoder <b>118</b> and error correction decoder <b>130</b>. The processor <b>112</b> comprises an uplink algorithm specification register <b>136</b>, which stores a data value (A) indicating the type and level of the error correction algorithm that is employed by the FEC dynamic remote station <b>106</b> to append the current uplink error correctable bearer data packet with error correction data. The data value (A) stored in the uplink algorithm specification register <b>136</b> is either equal to “0” indicating no error correction algorithm, “1” indicating the low-level error correction algorithm, or “2” indicating the high-level error correction algorithm. Again, the present invention is not to be limited to these particular error correction algorithms and can include other types of error correction algorithms without departing from the principles taught by this invention. As shown in <figref idref="DRAWINGS">FIG. 4A</figref>, the processor <b>112</b> is electrically coupled to the error correction encoder <b>118</b>, so that the processor <b>112</b> can, after accessing the uplink algorithm specification register <b>136</b>, transmit a control signal to the error correction encoder <b>118</b>, specifying the particular error correction algorithm to be employed by the error correction encoder <b>118</b> when appending the current uplink error correctable bearer data packet with error correction data.

0048The FEC dynamic remote station processor <b>112</b> comprises a downlink algorithm specification register <b>138</b>, which stores a data value (B) indicating the type and level of the error correction algorithm employed by the FEC dynamic remote station <b>106</b> to correct the current downlink error correctable bearer data packet with error correction data. The data value (B) stored in the downlink algorithm specification register <b>138</b> is equal to either “0” indicating no error correction algorithm, “1” indicating the low-level error correction algorithm, or “2” indicating the high-level error correction algorithm. As shown in <figref idref="DRAWINGS">FIG. 4A</figref>, the processor <b>112</b> is electrically coupled to the error correction decoder <b>130</b>, so that the processor <b>112</b> can, after the CPU <b>134</b> accesses the downlink algorithm specification register <b>138</b>, transmit a control signal to the error correction decoder <b>130</b> specifying the particular error correction algorithm to be employed by the error correction decoder <b>130</b> when correcting the current downlink error correctable bearer data packet.

0049As shown in <figref idref="DRAWINGS">FIG. 7</figref>, cyclically repeating time frames <b>108</b> are grouped into cyclically repeating multi-frames <b>156</b>. The time frames <b>108</b> commonly represent the TDMA/FDD formatted downlink time frames <b>108</b>(<b>1</b>) and uplink time frames <b>108</b>(<b>2</b>) shown in <figref idref="DRAWINGS">FIG. 2</figref> and the TDMA/TDD formatted downlink/uplink time frames <b>108</b>(<b>3</b>) shown in <figref idref="DRAWINGS">FIG. 3</figref>. The multi-frames <b>156</b> commonly represent downlink multi-frames <b>156</b>(<b>1</b>) and uplink time frames <b>156</b>(<b>2</b>) respectively comprising the TDMA/FDD formatted downlink time frames <b>108</b>(<b>1</b>) and uplink time frames <b>108</b>(<b>2</b>), and the downlink/uplink multi-frames <b>156</b>(<b>3</b>) comprising the TDMA/TDD formatted downlink/uplink time frames <b>108</b>(<b>3</b>). The number of time frames <b>108</b> in each multi-frame <b>156</b> is dictated by the particular time frame <b>108</b> during which the FEC dynamic remote station processor <b>112</b> selects an error correction algorithm. That is, the processor <b>112</b> only selects an error correction algorithm during a particular time frame <b>108</b> considered as the last time frame <b>108</b> of the multi-frame <b>156</b>, which may not have a fixed number of time frames <b>108</b>.

0050The processor <b>112</b> comprises a time frame incremental register <b>140</b>, which stores a data value (i) indicating the number of time frames <b>108</b> that have passed in the current multi-frame <b>156</b>. As shown in <figref idref="DRAWINGS">FIG. 4A</figref>, the error detection decoder <b>132</b> is electrically coupled to the processor <b>112</b>, so that the error detection decoder <b>132</b> can send a control signal to the processor <b>112</b> indicating receipt of a downlink error correctable bearer data packet. For each control signal sent from the error detection decoder <b>132</b> indicating that a downlink error correctable bearer data packet has been received by the FEC dynamic remote station <b>106</b>, the data value (i) in the time frame incremental register <b>140</b> is incremented by one. The processor <b>112</b> comprises a multi-frame register <b>142</b>, which stores a data value (L) indicating the time frame <b>108</b> of the current multi-frame <b>156</b> during which the processor <b>112</b> selects the error correction algorithm. The data value (L) is set by specifying the number of time frames <b>108</b> in the current multi-frame <b>156</b>.

0051The CPU <b>134</b> compares the data value (i) in the time frame incremental register <b>140</b> with the data value (L) in the multi-frame register <b>142</b> to determine whether the current time frame <b>108</b> is the last time frame <b>108</b> in the current multi-frame <b>156</b>, and thus whether the error correction algorithm should be currently selected. For instance, if the data value (L) is set to 100, the current multi-frame <b>156</b> includes 100 time frames <b>108</b>. The CPU <b>134</b> selects the error correction algorithm if the data value (i) equals 100, indicating the 100th and last time frame <b>108</b> of the current set of 100 time frames <b>108</b>.

0052The FEC dynamic remote station processor <b>112</b> determines an error rate level of the communication channel between the FEC dynamic remote station <b>106</b> and the FEC dynamic central station <b>104</b>, and more particularly an actual block error rate (BLER) level of the downlink error correctable bearer data packets transmitted during the current multi-frame <b>156</b>. It should be noted that for purposes of this specification, the current BLER level refers to the current BLER or any estimations thereof. The processor <b>112</b> comprises a BLER incremental register <b>144</b> that stores a data value (j) equal to the number of corrected downlink bearer data packets in which at least one residual error, i.e., a defective corrected downlink bearer data packet, exists. The current BLER level can be determined from the data value (j). The error detection decoder <b>132</b> is electrically coupled to the processor <b>112</b>, so that the error detection decoder <b>132</b> can send to the processor <b>112</b> a control signal indicating the presence of a defective corrected downlink bearer data packet. For each control signal sent from the error detection decoder <b>132</b> indicating the presence of a defective corrected downlink bearer data packet, the data value (j) in BLER incremental register <b>144</b> is incremented by one.

0053As previously stated, during the last time frame <b>108</b> of the current multi-frame <b>156</b>, the FEC dynamic remote station processor <b>112</b> selects one of the three error correction algorithms to be employed by the error correction encoder <b>118</b>′ of the FEC dynamic central station <b>104</b> and the error correction decoder <b>130</b> of the FEC dynamic remote station <b>106</b> during the next multi-frame <b>156</b>. The processor <b>112</b> comprises a minimum BLER threshold set register <b>146</b> and a maximum BLER threshold set register <b>148</b>, which respectively store data values (M) and (N) indicating the minimum tolerable BLER level, the triggering of which would indicate that the current error correction algorithm is too robust, and the maximum tolerable BLER level, the triggering of which would indicate that the current error correction algorithm is not robust enough. Thus, data value (M) is set by specifying a minimum BLER threshold level equal to a current BLER level that will trigger selection of the next lower error correction algorithm. Similarly, data value (N) is set by specifying a minimum BLER threshold level equal to a current BLER level that will trigger selection of the next higher error correction algorithm. Because the data value (N) represents a higher threshold than does the data value (M), the data value (N) is greater than the data value (M).

0054The CPU <b>134</b> respectively compares the data value (j) in the BLER incremental register <b>144</b> with the data value (M) in the minimum BLER threshold set register <b>146</b> and the data value (N) in the maximum BLER threshold set register <b>148</b> to determine which error correction algorithm is selected. For instance, if the data value (M) is set to 5, and the data value (N) is set to 15, the CPU <b>134</b> selects the next lower error correction algorithm if the data value (j) is less than 5. In this case, if the high-level error correction algorithm is currently being used, the CPU <b>134</b> selects the low-level error correction algorithm, and if the low-level error correction algorithm or no error correction algorithm is currently being used, the CPU <b>134</b> selects no error correction algorithm. If the data value (j) is equal to or greater than 5 and equal to or less than 15, the CPU <b>134</b> selects the current error correction algorithm. If the data value (j) is greater than 15, the CPU <b>134</b> selects the next higher error correction algorithm. In this case, if the low-level error correction algorithm or the high-level error correction algorithm is currently being used, the CPU <b>134</b> selects the high-level error correction algorithm, and if no error correction algorithm is currently being used, the CPU <b>134</b> selects the low-level error correction algorithm.

0055In this manner, the CPU <b>134</b> maintains the number of defective corrected downlink bearer data packets between a minimum and a maximum threshold, resulting in the employment of an error correction algorithm that maintains the current BLER level at a tolerable level while at the same time not creating excessive overhead. It should be noted that the selection of the error correction algorithm is relative in that the error correction algorithm selected is based on the error correction algorithm currently employed.

0056During dynamic communication conditions, wherein the quality of the communications channel may vary widely over time, the data value (L) in the multi-frame register <b>142</b> is set to a relatively low value, so that the wireless communications system <b>100</b> can quickly compensate for the dynamic communication conditions. During stable communication conditions when the quality of the communications channel varies little over time, the data value (L) in the multi-frame register <b>142</b> is set to a relatively high value, so that the wireless communications system <b>100</b> does not unnecessarily use CPU processing time.

0057The processor <b>112</b> determines the dynamic communication conditions and occasionally adjusts the number of time frames <b>108</b> in a given multi-frame <b>156</b> by adjusting the data value (L) in the multi-frame register <b>142</b>. The processor <b>112</b> comprises a dynamic incremental register <b>150</b>, which stores a data value (k) indicating the number of consecutive times the CPU <b>134</b> has selected the same error correction algorithm. If the CPU <b>134</b> selects the same error correction algorithm in the last time frame <b>108</b> of the current multi-frame <b>156</b> as that selected by the CPU <b>134</b> in the last time frame <b>108</b> of the previous multi-frame <b>156</b>, the CPU <b>134</b> increments the data value (k) in the dynamic incremental register by one.

0058The processor <b>112</b> comprises a low stability threshold set register <b>152</b> and a high stability threshold set register <b>154</b>, which respectively store a data value (P) indicating a low stability threshold, and a data value (Q) indicating a high stability threshold. The data value (P) is set by specifying a low stability threshold value equal to the number of consecutive selections of the same error correction algorithm on which selection of either decreasing or maintaining the number of time frames <b>108</b> in the next multi-frame <b>156</b> (i.e., data value (L)) is based. The data value (Q) is set by specifying a high stability threshold value equal to the number of consecutive selections of the same error correction algorithm on which selection of either maintaining or increasing the number of time frames <b>108</b> in the next multi-frame <b>156</b> is based. Because data value (Q) represents a higher threshold than does the data value (P), the data value (Q) is greater than the data value (P).

0059If a different error correction algorithm is selected, the CPU <b>134</b> compares the data value (k) with the data value (P) in the low stability threshold set register <b>152</b> to determine whether the data value (L) in the multi-frame register <b>142</b> should be decreased or maintained. In this case, the data value (k) need not be compared to the data value (Q) in the high stability threshold set register <b>154</b>, since the necessity to increase the data value (L) would only be triggered by a highly stable communication channel.

0060If the same error correction algorithm is selected, the CPU <b>134</b> compares the data value (k) with the data value (Q) in the high stability threshold set register <b>152</b> to determine whether the data value (L) in the multi-frame register <b>142</b> should be increased or maintained. In this case, the data value (k) need not be compared to the data value (P) in the low stability threshold set register <b>154</b>, since the necessity to decrease the data value (L) would only be triggered by a highly dynamic communication channel.

0061Thus, by way of non-limiting example, if the data value (P) is set to 10, the data value (Q) is set to 30, the data value (L) is decreased if the data value (k) is less than 10 upon selection of a different error correction algorithm, increased if the data value (k) is greater to or equal to 30 upon selection of the same error correction algorithm, and maintained in all other cases.

0062Alternatively, rather than varying the data value (L) in the multi-frame register <b>142</b> based on the number of consecutive times selection of the same error correction algorithm occurs, as described above, variance of the data value (L) can be based on the ratio of the number of times selection of an error correction algorithm was changed or not changed over a set number of multi-frames.

0063Referring to <figref idref="DRAWINGS">FIG. 4B</figref>, an alternative embodiment of an FEC dynamic remote station <b>206</b> is described. In this embodiment, rather than determining a current BLER level based on the number of defective corrected downlink bearer data packets received by the error detection decoder <b>132</b> as previously described, a current bit error rate (BER) level is determined by measuring the number of bit errors in the downlink bearer data packets received by the error correction decoder <b>130</b>. It should be noted that for purposes of this specification, the current BER level refers to the actual BER or any estimations thereof. The FEC dynamic remote station <b>206</b> is similar to the FEC dynamic remote station <b>106</b>, with the exception that the error correction decoder <b>130</b> is electrically coupled to a processor <b>212</b> to transfer a control signal thereto indicating the number of bit errors that exist in an uncorrected downlink bearer data packet. In such a case, the error detection encoder <b>116</b> and/or error detection decoder <b>132</b> is not required for purposes of obtaining the current BLER level, although in some cases, may be required for purposes of indicating to the FEC dynamic remote station <b>206</b> or base station <b>104</b> (via an ARQ signal) that a defective corrected bearer data packet (i.e., contains a residual error) has been received as described above.

0064As depicted in <figref idref="DRAWINGS">FIG. 5B</figref>, the processor <b>212</b> is similar to the processor <b>112</b>, with the exception that, instead of the BLER incremental register <b>144</b>, minimum BLER threshold set register <b>146</b> and maximum BLER threshold set register <b>148</b>, the processor <b>212</b> includes a BER incremental register <b>244</b>, first-level BER threshold set register <b>246</b> and a second-level BER threshold set register <b>248</b>. The BER incremental register <b>244</b> stores a data value (p) equal to the number of bit errors received by the FEC dynamic remote station <b>204</b>. The current BER level can be determined from data value (p). For each control signal sent from the error correction decoder <b>130</b> indicating the number of bit errors in an uncorrected downlink bearer data block, the data value (p) in the BER incremental register <b>244</b> is incremented by that number.

0065The first-level BER threshold set register <b>246</b> stores a data value (R) indicating the BER threshold level between selection of no error correction algorithm and the low-level error correction algorithm. The second-level BER threshold set register <b>248</b> stores a data value (S) indicating the BER threshold level between selection of the low-level error correction algorithm and the high-level error correction algorithm. Thus, data value (R) and data value (S) are set by defining three ranges of bit error values that will respectively result in the selection of no error correction algorithm, the low-level error correction algorithm, and the high-level error correction algorithm.

0066The CPU <b>234</b> respectively compares the data value (p) in the BER incremental register <b>244</b> with the data value (R) in the first-level BER threshold set register <b>246</b> and the data value (S) in the second-level BER threshold level to determine which error correction algorithm is selected. For instance, if the data value (R) is set to 20, and the data value (S) is set to 50, the CPU <b>234</b> selects no error correction algorithm if the data value (p) is less then 20, the low level error correction algorithm if the data value (p) is equal to or greater than 20 and less than 50, and the high-level error correction algorithm if the data value (p) is equal to or greater than 50.

0067It should be noted that the number of threshold levels will equal the number of error correction algorithms less one. Thus, if eleven error correction algorithms can be selected, ten threshold levels will be needed to define eleven ranges of detective bit values.

0068It should also be noted that by measuring the number of defective bits received by the error correction decoder <b>130</b>, the current BER level can be more accurately obtained. That is, this alternative method takes into account multiple bit errors in each downlink bearer data packet, as well as bit errors that would otherwise not be detected because of correction. Furthermore, because the current BER level is not based on the detection of errors after correction, absolute selection of an error correction algorithm can be accomplished. That is, selection of an error correction algorithm is not based on the error correction algorithm currently employed, facilitating a more flexible error correction algorithm selection process. Thus, the high-level error correction algorithm can be selected even if the error correction algorithm currently used is no error correction algorithm, and vice versa.

0069The processor <b>112</b> comprises other registers, such as registers that store information concerning the time slots <b>110</b> during which the FEC dynamic remote station <b>106</b> respectively transmits uplink error correctable bearer data packets and receives downlink error correctable bearer data packets, as well as information relating to the FEC dynamic remote stations <b>106</b> in current communication with the FEC dynamic central station <b>104</b>. For purposes of simplicity and ease of illustration, however, discussion of these registers is omitted.

0070Preferably, the FEC dynamic remote station <b>106</b> includes any combination of digitizing, source coding and decoding, interleaving and de-interleaving, burst formatting, or ciphering and de-ciphering functions. For the purposes of simplicity and ease of illustration, however, these functions are not illustrated and described.

0071Because the dynamic FEC arrangement employed by the wireless communications system <b>100</b> is reciprocal, the componentry of the FEC dynamic central station <b>104</b> is similar to that of the FEC dynamic remote station <b>106</b>. That is, as shown in <figref idref="DRAWINGS">FIG. 4A</figref>, the FEC dynamic central station <b>104</b>, like the FEC dynamic remote station <b>106</b>, comprises an error detection encoder <b>116</b>′, error correction encoder <b>118</b>′, modulator <b>120</b>′, transmitter <b>122</b>′, and antenna <b>124</b>′, which are all configured and arranged with each other and with the processor <b>112</b>′ and input/output device <b>114</b>′ to facilitate the transmission of error correctable bearer data packets to the FEC dynamic remote station <b>106</b>. Likewise, the FEC dynamic central station <b>104</b> further comprises a receiver <b>126</b>′, demodulator <b>128</b>′, error correction decoder <b>130</b>′, and error detection decoder <b>132</b>′, which are all configured and arranged with each other and with the processor <b>112</b>′, antenna <b>124</b>′ and input/output device <b>114</b>′ to facilitate the reception of error correctable bearer data packets transmitted by the FEC dynamic remote station <b>106</b>.

0072As shown in <figref idref="DRAWINGS">FIG. 6</figref>, the FEC dynamic central station processor <b>112</b>′, like the FEC dynamic remote station processor <b>112</b>, comprises a CPU <b>134</b>′, which performs all of the processing functions in the FEC dynamic central station <b>104</b>. The processor <b>112</b>′ further comprises instructions that allow the FEC dynamic remote station <b>106</b> to dynamically generate downlink error correctable bearer data packets and dynamically correct uplink error correctable bearer data packets. These instructions are in the form of registers, and in particular a downlink algorithm specification register <b>136</b>′, which stores a data value (A′); uplink algorithm specification register <b>138</b>′, which stores a data value (B′); time frame incremental register <b>140</b>′, which stores a data value (i′); multi-frame register <b>142</b>′, which stores a data value (L′); BLER incremental register <b>144</b>′, which stores a data value (j′); minimum BLER threshold set register <b>146</b>′, which stores a data value (M′), maximum BLER threshold set register <b>148</b>′, which stores a data value (N′); dynamic incremental register <b>150</b>′, which stores a data value (k′); low stability threshold set register <b>152</b>′, which stores a data value (P); and high stability threshold set register <b>154</b>′, which stores a data value (Q)

0073It should be noted that the processor <b>112</b>′ provides for the measurement of current BLER levels. Quite similarly, but not shown, an FEC dynamic central station processor can be employed for providing the measurement of current BER levels, much like the FEC dynamic remote station processor <b>212</b>.

0074It should be further noted that, for purposes of simplicity in describing the principles of this invention, only the componentry in the FEC dynamic central station <b>104</b> is necessary to communicate with various FEC dynamic remote stations <b>106</b> over a single pair of downlink and uplink frequencies (TDMA/FDD) or a single downlink/uplink frequency pair (TDMA/TDD) is depicted in <figref idref="DRAWINGS">FIGS. 4A</figref>, <b>4</b>B and <b>6</b>. In reality, the FEC dynamic central station <b>104</b> communicates with a multitude of FEC dynamic remote stations <b>106</b> over a range of downlink and uplink frequency pairs or downlink/uplink frequencies and includes other components not employed in the FEC dynamic remote station <b>104</b>, such as a multiplexer and demultiplexer. Furthermore, the FEC dynamic central station processor <b>112</b>′ includes a number of register sets equal to the system capacity of the wireless communications system <b>100</b>, i.e., the number of FEC dynamic remote stations <b>106</b> that the FEC dynamic central station <b>104</b> is able to communicate with.

0075It should also be noted that the FEC arrangement employed by the FEC dynamic central station <b>104</b> is independent from the FEC arrangement employed by the FEC dynamic remote station <b>106</b>, and thus, the error correction algorithm selected by the FEC dynamic central station <b>104</b> processor <b>112</b>′ to append downlink error correctable bearer data packets with error correction data does not necessarily correspond to the error correction algorithm selected by the FEC dynamic remote station processor <b>112</b> to append uplink error correctable bearer data packets with error correction data. Also, the present inventions are not limited to those wireless communications systems that employ a bilateral dynamic FEC arrangement as just described, but can also include wireless communications systems that employ a unilateral or asymmetric dynamic FEC arrangement.

0076The following is a description of the operation of the wireless communications system <b>100</b>. During the initial handshaking operation between the FEC dynamic central station <b>104</b> and the FEC dynamic remote station <b>106</b>, data concerning the initial particulars of the FEC arrangement of the wireless communications system <b>100</b>, as well as initiation data, such as identification data, time slot allocation data, and frequency allocation data is communicated between the FEC dynamic central station <b>104</b> and the FEC dynamic remote station <b>106</b>.

0077If the wireless communications system <b>100</b> employs a TDMA/FDD format, the downlink and uplink frequencies are different, and the FEC dynamic remote station <b>106</b> transmits and receives error correctable bearer data packets during staggered time slots <b>110</b>(<b>1</b>) and <b>110</b>(<b>2</b>) of respective independent time frames <b>108</b>(<b>1</b>) and <b>108</b>(<b>2</b>), as depicted in <figref idref="DRAWINGS">FIG. 2</figref>. If the wireless communications system <b>100</b> employs a TDMA/TDD format, the downlink and uplink frequencies are the same, and the FEC dynamic remote station <b>106</b> transmits and receives error correctable bearer data packets during different time slots <b>110</b>(<b>3</b>) of the single time frame <b>108</b>(<b>3</b>), as depicted in <figref idref="DRAWINGS">FIG. 3</figref>. Frequency and time slot assignment is orchestrated by the FEC dynamic central station <b>104</b>.

0078After the initial handshaking operations between the FEC dynamic central station <b>104</b> and the FEC dynamic remote station <b>106</b>, the registers of the FEC dynamic central station processor <b>112</b>′ and the FEC dynamic remote station processor <b>112</b> are initialized, and downlink error correctable bearer data packets and uplink error correctable bearer data packets are alternately transmitted between the FEC dynamic central station <b>104</b> and the FEC dynamic remote station <b>106</b>.

0079With respect to the TDMA/FDD formatted system <b>100</b>, the FEC dynamic central station <b>104</b> appends downlink error correctable bearer data packets with error correction data according to a selected error correction algorithm and respectively transmits these error correctable bearer data packets to the FEC dynamic remote station <b>106</b> in the respective downlink time frames <b>108</b>(<b>1</b>) of a downlink multi-frame <b>156</b>(<b>1</b>). The FEC dynamic remote station <b>106</b> corrects the error correctable bearer data packets according to the selected error correction algorithm and determines a current BER level of the downlink communication channel between the FEC dynamic central station <b>104</b> and the FEC dynamic remote station <b>106</b> during the last downlink time frame <b>108</b>(<b>1</b>) of the downlink multi-frame <b>156</b>(<b>1</b>) based on the bearer data received over the entire downlink multi-frame <b>156</b>(<b>1</b>). The FEC dynamic remote station <b>106</b> selects, based on the current BER level, an error correction algorithm to be employed by the FEC dynamic central station <b>104</b> and the FEC dynamic remote station <b>106</b> to respectively append and correct the downlink error correctable bearer data packets transmitted during the respective downlink time frames <b>108</b>(<b>1</b>) of the next downlink multi-frame <b>156</b>(<b>1</b>).

0080Likewise, the FEC dynamic remote station <b>106</b> appends uplink error correctable bearer data packets with error correction data according to a selected error correction algorithm and respectively transmits these error correctable bearer data packets to the FEC dynamic central station <b>104</b> in the respective uplink time frames <b>108</b>(<b>2</b>) of an uplink multi-frame <b>156</b>(<b>2</b>). The FEC dynamic central station <b>104</b> corrects the error correctable bearer data packets according to the selected error correction algorithm and determines a current BER level of the uplink communications channel between the FEC dynamic central station <b>104</b> and the FEC dynamic remote station <b>106</b> during the last uplink time frame <b>108</b>(<b>2</b>) of the uplink multi-frame <b>156</b>(<b>2</b>) based on the bearer data received over the entire uplink multi-frame <b>156</b>(<b>2</b>). The FEC dynamic central station <b>104</b> selects, based on the current BER level, an error correction algorithm to be employed by the FEC dynamic remote station <b>106</b> and the FEC dynamic central station <b>104</b> to respectively append and correct the uplink error correctable bearer data packets transmitted during the respective uplink time frames <b>108</b>(<b>2</b>) of the next uplink multi-frame <b>156</b>(<b>2</b>).

0081Referring to <figref idref="DRAWINGS">FIGS. 4-8</figref>, and more specifically to <figref idref="DRAWINGS">FIG. 8</figref>, the FEC dynamic central station processor <b>112</b>′ and the FEC dynamic remote station processor <b>112</b> perform various steps in effecting the downlink transmission of consecutive error correctable bearer data packets during the respective downlink time frames <b>108</b>(<b>1</b>) of each downlink multi-frame <b>156</b>(<b>1</b>) according to the dynamic FEC arrangement of the present invention.

0082At step <b>158</b>, the data registers of the FEC dynamic central station processor <b>112</b>′ and FEC dynamic remote station processor <b>112</b> are initialized. The data value (A′) in the downlink algorithm specification register <b>136</b>′ of the FEC dynamic central station processor <b>112</b>′ and the data value (B) in the downlink algorithm specification register <b>138</b> of the FEC dynamic remote station processor <b>112</b> are initially both set to “0”, “1”, or “2” to specify the particular error correction algorithm initially and respectively employed by the FEC dynamic central station <b>104</b> to generate error correction data and the FEC dynamic remote station <b>106</b> to process and correct the first downlink error correctable bearer data packet. The initial data values (A′) and (B) will depend on the particular system requirements.

0083The data values (i), (j), and (k) in the respective time frame incremental register <b>140</b>, BLER incremental register <b>144</b>, and dynamic incremental register <b>150</b> of the FEC dynamic remote station processor <b>112</b> are initialized to “0”. The data value (L) in the multi-frame register <b>142</b> is initialized to set the number of time frames <b>108</b> in the first multi-frame <b>156</b>. The data value (M) in the minimum BLER threshold set register <b>146</b> and the data value (N) in the maximum BLER threshold set register <b>148</b> are initialized to respectively set the minimum BLER threshold level and the maximum BLER threshold level. The data value (P) in the low stability threshold set register <b>152</b> and the data value (Q) in the high stability threshold set register <b>154</b> are initialized to respectively set the low stability threshold and the high stability threshold. The initial data values (L), (M), (N), (P), and (Q) will vary with the particulars of the wireless communications system <b>100</b> and are set accordingly.

0084At steps <b>160</b> to <b>176</b>, the FEC dynamic central station processor <b>112</b>′ and the FEC dynamic remote station processor <b>112</b> respectively configure the error correction encoder ′<b>118</b> and the error detection decoder <b>132</b> according to the current error correction algorithm, coordinate the transmission, reception, and correction of respective downlink error correctable bearer data packets during the current multi-frame <b>156</b>, and select an error correction algorithm to be employed during the next multi-frame <b>156</b>.

0085At step <b>160</b>, the FEC dynamic central station processor <b>112</b>′ configures the error correction encoder <b>118</b>′, so that it employs the particular error correction algorithm specified in the downlink algorithm specification register <b>136</b>′ to generate the error correction data that is to be appended to the current downlink error correctable bearer data packet.The CPU <b>134</b>′ accesses the downlink algorithm specification register <b>136</b>′ to obtain the current data value (A′). If the data value (A′) equals “0”, the processor <b>112</b>′ sends a control signal to the error correction encoder <b>118</b>′ indicating that no error correction algorithm be employed. If the data value (A′) equals “1”, the processor <b>112</b>′ sends a control signal to the error correction encoder <b>118</b>′ indicating that the low-level error correction algorithm be employed. If the data value (A′) equals any value but “0” or “1”, the processor <b>112</b>′ sends a control signal to the error correction encoder <b>118</b>′ indicating that the high-level error correction algorithm be employed.

0086At step <b>162</b>, the FEC dynamic remote station processor <b>112</b> configures the error correction decoder <b>130</b>, so that it employs the particular error correction algorithm specified in the downlink algorithm specification register <b>138</b> to process and correct the current downlink error correctable bearer data packet. The CPU <b>134</b> accesses the downlink algorithm specification register <b>138</b> to obtain the current data value (B). If the data value (B) equals “0”, the processor <b>112</b> sends a control signal to the error correction decoder <b>130</b> indicating that no error correction algorithm should be employed. If the data value (B) equals “1”, the processor <b>112</b> sends a control signal to the error correction decoder <b>130</b> indicating that the low-level error correction algorithm should be employed. If the data value (B) equals any value but “0” or “1”, the processor <b>112</b> sends a control signal to the error correction decoder <b>130</b> indicating that the high-level error correction algorithm should be employed. It should be noted that the data value (A′) in the downlink algorithm specification register <b>136</b>′ of the FEC dynamic central station processor <b>112</b>′ is equal to the data value (B) in the downlink algorithm specification register <b>138</b> of the FEC dynamic remote station processor <b>112</b>, since the error correction encoder <b>118</b>′ of the FEC dynamic central station <b>104</b> and the error correction decoder <b>130</b> of the FEC dynamic remote station <b>106</b> employ the same error correction algorithm to respectively generate error correction data and correct the downlink error correctable bearer data packet.

0087At step <b>164</b>, the FEC dynamic central station processor <b>112</b>′ directs the FEC dynamic central station <b>104</b> to transmit a downlink error correctable bearer data packet during a time slot <b>110</b>(<b>1</b>) of the current downlink time frame <b>108</b>(<b>1</b>) which the FEC dynamic remote station <b>106</b> is designated to receive an error correctable downlink bearer data packet (shown as time slot <b>3</b> in <figref idref="DRAWINGS">FIG. 7</figref>).

0088If an Automatic Retry Request (ARQ) signal transmitted by the FEC dynamic remote station <b>106</b> indicating the receipt of a previously transmitted defective corrected bearer data packet, as described further below, was not received by the FEC dynamic central station <b>104</b>, the FEC dynamic central station processor <b>112</b>′ directs the input/output device <b>114</b>′ electrically coupled to the FEC dynamic central station <b>104</b> to transfer downlink traffic data to the error detection encoder <b>116</b>′ as a downlink bearer data packet. The amount of downlink traffic data transferred to the error detection encoder <b>116</b>′ will depend on the particular error correction algorithm employed by the error correction encoder <b>118</b>′. That is, the processor <b>112</b>′ directs the input/output device <b>114</b>′ to increase the amount of downlink traffic data transferred as error correction data overhead decreases. Contrariwise, the processor <b>112</b>′ directs the input/output device <b>114</b>′ to decrease the amount of downlink traffic data transferred as the error correction data overhead increases. The processor <b>112</b>′ then transfers downlink control data to the error detection encoder <b>116</b>′ where it is appended to the downlink bearer data packet. The error detection encoder <b>116</b>′ generates error detection data according to the CRC error detection algorithm and appends the downlink bearer data packet with the generated error detection data. The error detection encoder <b>116</b>′ then transfers the downlink bearer data packet to the error correction encoder <b>118</b>′. The error correction encoder <b>118</b>′ then encodes the downlink bearer data packet with error correction data according to the error correction algorithm specified by the processor <b>112</b>′ to form an error correctable downlink bearer data packet.

0089If an ARQ signal was received, the FEC dynamic central station processor <b>112</b>′ directs the input/output device <b>114</b>′ to not transfer downlink traffic data to the error correction encoder <b>118</b>′. Instead, the previous downlink error correctable bearer data packet stored in the error correction encoder is re-transmitted as the current downlink error correctable bearer data packet.

0090The downlink error correctable bearer data packet is then transferred to the modulator <b>120</b>′ and transmitter <b>112</b>′, where it is respectively modulated with a downlink carrier frequency, and amplified and filtered. The downlink error correctable bearer data packet is then transferred to the antenna <b>124</b>′, where it is transmitted over-the-air to the antenna <b>124</b> of the FEC dynamic remote station <b>106</b>.

0091At step <b>166</b>, the FEC dynamic remote station processor <b>112</b> directs the FEC dynamic remote station <b>106</b> to receive the downlink error correctable bearer data packet transmitted over-the-air from the FEC dynamic central station <b>104</b> during the downlink time slot <b>110</b>(<b>1</b>) of the current downlink time frame <b>108</b>(<b>1</b>). The downlink error correctable bearer data packet is received by the antenna <b>124</b>, and transferred to the receiver <b>126</b> and the demodulator <b>128</b>, where it is respectively filtered and demodulated from the carrier frequency. The downlink error correctable bearer data packet is then transferred to the error correction decoder <b>130</b>. The error correction decoder <b>130</b> then processes and corrects, within the limits of the error correction algorithm specified by the processor <b>112</b>, the downlink error correctable bearer data packet to generate a corrected downlink bearer data packet. The corrected downlink bearer data packet is then transferred to the error detection decoder <b>132</b>, where it is processed to determine the existence of any residual errors.

0092At step <b>168</b>, the FEC dynamic remote station processor <b>112</b> remedies any residual errors in the corrected bearer data packet. If the error detection decoder <b>132</b> does not sense a residual error in the corrected downlink bearer data packet, the error detection decoder <b>132</b> sends a control signal to the processor <b>112</b> indicating that the error detection decoder <b>132</b> currently possesses a valid downlink bearer data packet. The downlink control data is then separated from the corrected downlink bearer data packet. The valid downlink bearer data packet is transferred to the input/output device <b>114</b> electrically coupled to the FEC dynamic remote station <b>106</b> as downlink traffic data. The downlink control data originating from the FEC dynamic central station <b>104</b> is transferred to the processor <b>112</b>, where it is accordingly processed. In response to no residual errors in the corrected downlink bearer data packet, the CPU <b>134</b> increments by one the data value (i) in the time frame incremental register <b>140</b>.

0093If the error detection decoder <b>132</b> senses at least one residual error in the corrected downlink bearer data packet, the error detection decoder <b>132</b> sends a control signal to the processor <b>112</b> indicating that the error detection decoder <b>132</b> currently possesses a defective corrected downlink bearer data packet.

0094If the input/output device <b>114</b> is not delay-sensitive, such as, e.g., a PC, the defective corrected downlink bearer data packet is not transferred to the input/output device <b>114</b>. Instead, the FEC dynamic remote station processor <b>112</b> directs the FEC dynamic remote station <b>106</b> to transmit an ARQ control signal during the next available control time slot.

0095If the input/output device <b>114</b> is delay-sensitive, such as, e.g., a voice encoder/decoder, the downlink control data is separated from the corrected downlink bearer data packet. The defective corrected downlink bearer data packet is transferred to the input/output device <b>114</b> electrically coupled to the FEC dynamic remote station <b>106</b> as downlink traffic data. The processor <b>112</b>, however, will send a control signal to the input/output device <b>114</b> indicating the existence of defective downlink traffic data. The input/output device <b>114</b> then processes the downlink traffic data accordingly. The downlink control data originating from the FEC dynamic central station <b>104</b> is transferred to the processor <b>112</b>, where it is accordingly processed. In response to an indicated defective corrected bearer data packet, the CPU <b>134</b> increments by one, both the data value (i) in the time frame incremental register <b>140</b> and the data value (j) in the BLER incremental register <b>144</b>.

0096At step <b>170</b>, the FEC dynamic remote station processor <b>112</b> determines whether the current downlink time frame <b>108</b>(<b>1</b>) is the last time frame in the current downlink multi-frame <b>156</b>(<b>1</b>). That is, the FEC dynamic remote station processor <b>112</b> determines whether the next error correction algorithm should currently be selected. The CPU <b>134</b> accesses the time frame incremental register <b>140</b> to obtain the data value (i), and thus, the current downlink time frame <b>108</b>(<b>1</b>). The CPU <b>134</b> also accesses the multi-frame register <b>144</b> to obtain the data value (L), and thus the number of downlink time frames <b>108</b>(<b>1</b>) in the current multi-frame <b>156</b>(<b>1</b>). The CPU <b>134</b> compares the data value (i) with the data value (L). If the data value (i) does not equal the data value (L), the wireless communications system <b>100</b> goes to step <b>164</b> whereat the FEC dynamic central station processor <b>112</b>′ directs the FEC dynamic central station <b>104</b> to transmit the next downlink error correctable bearer data packet during the next downlink time frame <b>108</b>(<b>1</b>) of the current downlink multi-frame <b>156</b>(<b>1</b>).

0097If the data value (i) equals the data value (L), the FEC dynamic remote station processor <b>106</b> selects, at step <b>172</b>, the particular error correction algorithm to be employed by the error correction encoder <b>118</b>′ of the FEC dynamic central station <b>104</b> and the error correction decoder <b>130</b> of the FEC dynamic remote station <b>106</b> to respectively generate error correction data and correct the error correctable bearer data packets transmitted during the downlink time frames <b>108</b>(<b>1</b>) of the next downlink multi-frame <b>156</b>(<b>1</b>).

0098At step <b>172</b>, if the current BLER level does not trigger the minimum BLER threshold or the maximum BLER threshold, the current error correction algorithm employed is selected. If the current BLER level triggers the minimum BLER threshold, the next lower error correction algorithm is selected. If the current BLER level triggers the maximum BLER threshold, the next higher error correction algorithm is selected.

0099In this manner, the CPU <b>134</b> determines a current BLER level by accessing the BLER incremental register <b>144</b> to obtain the current data value (j), and determines a minimum BLER threshold level by accessing the minimum BLER threshold set register <b>146</b> to obtain the current data value (M). The CPU <b>134</b> compares the data value (j) to the data value (M). If the data value (j) is less than the data value (M), the CPU <b>134</b> accesses the downlink algorithm specification register <b>138</b> to obtain the current data value (B), and thus the current error correction algorithm. If the current data value (B) is less than or equal to “1”, the CPU <b>134</b> selects the data value (B) as “0”, indicating no error correction algorithm should be selected. If the current value (B) is greater than “1”, the CPU <b>34</b> selects the data value (B) as 1, indicating that the low-level error correction algorithm should be selected.

0100If the data value (j) is greater than or equal to the data value (M), the CPU <b>134</b> determines the maximum BLER threshold by accessing the maximum BLER threshold set register <b>148</b> to obtain the current data value (N). The CPU <b>134</b> compares the data value (j) to the data value (N). If the data value (j) is greater than the data value (N), the CPU <b>134</b> accesses the downlink algorithm specification register <b>138</b> to obtain the current data value (B), and thus the current error correction algorithm. If the current data value (B) equals “0”, the CPU <b>134</b> selects the data value (B) as “1”, indicating the low-level error correction algorithm. If the current data value (B) does not equal “0”, the CPU <b>134</b> selects the data value (B) as “2”, indicating the high-level error correction algorithm.

0101If the data value (j) is not greater than the data value (N), the CPU <b>134</b> does not select a value for the data value (B), indicating that the current error correction algorithm should be maintained. The CPU <b>134</b> then increments the data value (k) in the dynamic incremental register <b>150</b> indicating that a new error correction algorithm has not been selected, i.e., the currently selected data value (B) is equal to the previously selected data value (B). As will be described in further detail below, the data value (B) is not reset until approved by the central station <b>104</b>.

0102Subsequent to proposed selection of the error correction algorithm, the CPU <b>134</b> resets the data value (i) in the time frame incremental register <b>140</b> to “0” and the data value (j) in the BLER incremental register <b>144</b> to “0”, so that they are initialized for the next multi-frame <b>156</b>.

0103At step <b>174</b>, the FEC dynamic remote station processor <b>112</b> determines whether the data value (L) in the multi-frame register <b>142</b>, and thus the number of downlink time frames <b>108</b>(<b>1</b>) in the next downlink multi-frame <b>156</b>(<b>1</b>), should be changed with respect to the stability of the communication channel quality.

0104If the data value (k) in the dynamic incremental register <b>150</b> at step <b>172</b> was not incremented indicating a change in the selection of the error correction algorithm, the FEC dynamic remote station processor <b>212</b> determines whether the number of downlink time frames <b>108</b>(<b>1</b>) in the next downlink multi-frame <b>156</b>(<b>1</b>) should be decreased or maintained. The CPU <b>134</b> determines the number of consecutive times the same error correction algorithm has been selected by accessing the dynamic incremental register <b>150</b> to obtain the data value (k). The CPU <b>134</b> also determines the low stability threshold value by accessing the low stability threshold set register <b>152</b> to obtain the data value (P). The CPU <b>134</b> compares the data value (k) with the data value (P). If the data value (k) is less than the data value (P), the CPU <b>134</b> decrements the data value (L) in the multi-frame register <b>142</b> by a particular number, decreasing the number of time frames <b>108</b> in the next multi-frame <b>156</b>. If the data value (k) is not less than the data value (P), the CPU <b>134</b> does not change the data value (L) in the multi-frame register <b>142</b>, maintaining the number of time frames <b>108</b> in the next multi-frame <b>156</b>. Whether the data value (L) is decremented or maintained,. the CPU <b>134</b> resets the data value (k) to “0”, so that the stability of the communication channel quality can be redetermined.

0105If the data value (k) in the dynamic incremental register <b>150</b> at step <b>172</b> has been incremented indicating no change in the error correction algorithm, the FEC dynamic remote station processor <b>212</b> determines whether the number of downlink time frames <b>108</b>(<b>1</b>) in the next downlink multi-frame <b>156</b>(<b>1</b>) should be increased or maintained. The CPU <b>134</b> determines the number of consecutive times the same error correction algorithm has been selected by accessing the dynamic incremental register <b>150</b> to obtain the current data value (k). The CPU <b>134</b> also determines the high stability threshold value by accessing the high stability threshold set register <b>154</b> to obtain the data value (Q). The CPU <b>134</b> compares the data value (k) to the data value (Q). If the data value (k) is equal to or greater than the data value (Q), the CPU <b>134</b> increments the data value (L) in the multi-frame register <b>142</b> by a particular number, increasing the number of time frames <b>108</b> in the next multi-frame <b>156</b>. The CPU <b>134</b> resets the data value (k) to “0”, so that the stability of the communication channel quality can be redetermined. If the data value (k) is less than the data value (Q), the CPU <b>134</b> does not change the data value (L), maintaining the number of downlink time frames <b>108</b>(<b>1</b>) in the next downlink multi-frame <b>156</b>(<b>1</b>) to its current value. The CPU <b>134</b> does not reset the data value (k), so that the current number of consecutive times the same error correction algorithm has been selected is taken into account during the next determination of the stability of the communication channel quality.

0106At step <b>176</b>, the FEC dynamic remote station <b>106</b> transmits uplink control data to the FEC dynamic central station <b>104</b> during the next available control time slot. The uplink control data indicates the error correction algorithm selected by the FEC dynamic remote station <b>106</b>, the next downlink time frame <b>108</b>(<b>1</b>) during which the FEC dynamic remote station <b>106</b> selects an error correction algorithm, and if applicable, an ARQ signal indicating the receipt of a defective corrected downlink bearer data packet as described above.

0107The FEC dynamic central station <b>104</b> receives the uplink error correctable bearer data packet from the FEC dynamic remote station <b>106</b> and processes the uplink control data. The FEC dynamic central station <b>104</b> transmits downlink control data to the FEC dynamic remote station <b>106</b> during the next available downlink control time slot. The downlink control data indicates whether the error correction algorithm selection is approved or denied. If the FEC dynamic central station processor <b>112</b>′ determines that the selected error correction algorithm should be employed, the downlink control data indicates approval of the selected error correction algorithm. On the other hand, if the FEC dynamic central station processor <b>112</b>′ determines that the selected error correction algorithm should not be employed, such as, if the selected error correction algorithm is not compatible with the wireless communication system <b>100</b> or the available overhead or central station does not support the error correction algorithm, the downlink control data indicates denial of the selected error correction algorithm.

0108The FEC dynamic remote station <b>106</b> receives the downlink control data, and accordingly either resets the data value (B) of the downlink algorithm specification register <b>138</b> to the selected data value (B) if the selected error correction algorithm was approved by the FEC dynamic central station processor <b>212</b>′, or does not reset the data value (B) of the downlink algorithm specification register <b>138</b> to the selected data value (B), if the selected error correction algorithm was denied by the FEC dynamic central station processor <b>212</b>′.

0109The FEC dynamic central station processor <b>112</b>′, in turn, resets the data value (A′) in the downlink algorithm specification register <b>136</b>′ equal to the data value (B).

0110Rather than synchronizing the error correction algorithm used by the central station <b>104</b> and remote station <b>106</b> to respectively encode and process a downlink bearer data packet by sending a confirmation or denial signal during a dedicated control time slot as described above with respect to step <b>176</b>, synchronization of the error correction algorithm can be accomplished by encoding each downlink bearer data packet with a highly protected code word indicating the error correction algorithm that was employed to encode the particular downlink bearer data packet with error correction data. During processing of the downlink bearer data packet, the remote station <b>106</b> can decode the code word to determine the error correction algorithm to be employed to process the downlink bearer data packet. More alternatively, the remote station <b>106</b> can process the downlink bearer data packet with all available error correction algorithms, and use the best corrected bearer data packet.

0111After synchronization of the error correction algorithm, the wireless communications system <b>100</b> then returns to steps <b>160</b> and <b>162</b> where the error correction encoder <b>118</b>′ of the FEC dynamic central station <b>104</b> and the error correction decoder <b>118</b> of the FEC dynamic remote station <b>106</b> are configured to employ the particular error correction algorithm as specified by the data value (A′) and data value (B).

0112If an error correction algorithm was selected at step <b>172</b>, and thus, the data value (i) in the time frame incremental register <b>140</b> was reset to “0”, the next downlink error correctable bearer data packet transmitted by the FEC dynamic central station <b>104</b> and received by the FEC dynamic remote station <b>106</b> will occur during the first time frame <b>108</b> of the next multi-frame <b>156</b>. Contrariwise, if an error correction algorithm was not selected at step <b>172</b>, and thus, the data value (i) in the time frame incremental register <b>140</b> was not reset to “0”, the next downlink error correctable bearer data packet transmitted by the FEC dynamic central station <b>104</b> and received by the FEC dynamic remote station <b>106</b> will occur during the next downlink time frame <b>108</b>(<b>1</b>) of the current downlink multi-frame <b>156</b>(<b>1</b>).

0113The steps performed by the FEC dynamic central station processor <b>112</b>′ and the FEC dynamic remote station processor <b>112</b>, in effecting the uplink transmission of consecutive error correctable bearer data packets according to the dynamic FEC arrangement of the present invention, are reciprocal to and independent of those described above, with respect to the downlink transmission of consecutive error correctable bearer data packets. For purposes of simplicity and terseness, these steps will not be described.

0114If the current BER level, rather than the current BLER is obtained, steps <b>258</b>, <b>266</b>, <b>268</b> and <b>272</b> (<figref idref="DRAWINGS">FIG. 9</figref>) are performed in place of steps <b>158</b>, <b>166</b>, <b>168</b> and <b>172</b>. Step <b>258</b> is similar to step <b>158</b> with the exception that, rather than initializing the minimum-level BLER threshold set register <b>146</b> and the maximum-level BLER threshold set register <b>148</b>, the data value (R) in the first-level BER threshold set register <b>246</b> and the data value (S) in the second level BLER threshold set register <b>248</b> are initialized to respectively set the first-level BER threshold level and the second-level BER threshold level.

0115Step <b>266</b> is similar to step <b>166</b> with the exception that the error correction decoder <b>130</b>, rather than the error detection decoder <b>132</b>, is employed to measure the current BER level rather than the current BLER level. That is, prior to correcting a downlink bearer data packet, the error correction decoder <b>130</b> measures the bit errors in the downlink bearer data packet and sends a corresponding control signal to the processor indicating the existence and number of bit errors in the downlink bearer data packet.

0116Step <b>268</b> is similar to step <b>168</b> with the exception that the total number of errors in each uncorrected downlink bearer data packet are tracked (i.e., the current BER is measured), rather than the existence of a defective corrected downlink bearer data packet (i.e., the current BLER is measured). That is, if the error correction decoder <b>130</b> receives a downlink bearer data packet with no bit errors, the error correction decoder <b>130</b> sends a control signal to the processor <b>112</b> indicating that the error correction decoder <b>130</b> possesses a downlink bearer data packet with no bit errors. If the error correction decoder <b>130</b> receives a downlink bearer data packet with at least one error, the error correction decoder <b>130</b> sends a control signal to the processor <b>112</b> indicating the existence and number of bit errors in the downlink bearer data packet. The CPU <b>234</b> increments the data value (p) in the BER incremental register <b>244</b> by the number of bit errors detected. The downlink bearer data packet is then corrected and processed as described above.

0117Step <b>272</b> is similar to step <b>172</b>, with the exception that absolute selection, rather than relative selection, of the error correction algorithm is performed. If the current BER level falls within the range below the first-level threshold, no error correction algorithm is selected. If the current BER level falls within the range between the first-level threshold and the second-level threshold, the low-level error correction algorithm is selected. If the current BER level falls within the range above the second-level threshold, the high-level error correction algorithm is selected.

0118Thus, the CPU <b>234</b> determines a current BER level by accessing the BER incremental register <b>244</b> to obtain the current data value (p), and determines a first-level BER threshold level by accessing the first-level BER threshold set register <b>246</b> to obtain the current data value (R) and a second-level BER threshold level by accessing the second-level BER threshold set register <b>248</b> to obtain the current data value (S). The CPU <b>234</b> compares the data value (p) to the data values (R) and (S). If the data value (p) is less than the data value (R), the CPU <b>234</b> selects the data value (B) as “0”, indicating that the no error correction algorithm should be selected. If the data value (p) is equal to or greater than the data value (S), the CPU <b>234</b> selects the data value (B) as “2”, indicating that the high-level error correction algorithm should be selected. In all other cases, the CPU <b>234</b> selects the data value (B) as “1”, indicating that the low-level error correction algorithm should be selected. If data value (B) has changed, the CPU <b>234</b> does not increment the data value (k). If data value (B) has not changed, the CPU <b>234</b> increments by one the data value (k).

0119Subsequent to the proposed selection of the error correction algorithm, the CPU <b>234</b> resets the data value (i) in the time frame incremental register <b>140</b> to “0” and the data value (p) in the BER incremental register <b>244</b> to “0”, so that they are initialized for the next multi-frame <b>156</b>.

0120Operation of the wireless communications system <b>100</b> in the TDMA/TDD format is similar to that described above with respect to the TDMA/FDD format, with the exception that the reciprocal error correctable bearer data packet transmissions between the FEC dynamic central station <b>104</b> and the FEC dynamic remote station <b>106</b> occur during the same downlink/uplink time frame <b>108</b>(<b>3</b>), i.e., same frequency.

0121The present inventions are not limited to the wireless communication system disclosed above and may include other types of wireless communications systems, such as, e.g., satellite based communications systems, or other types of wire-based systems, such as, e.g., LAN systems or fiber optic networks.

0122The present inventions can be used in an out-of-band FEC system, wherein error correction data is transmitted and received in out-of-band time slots, as described in further detail in copending application Ser. No. 09/314,580 filed concurrently herewith, which is fully and expressly incorporated herein by reference.

0123Thus, an improved apparatus and method for improving the data throughput of a communications system is disclosed. While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications are possible without departing from the inventive concepts herein.

0124The invention, therefore is not to be restricted except in the spirit of the appended claims.