Method and apparatus for scaling up and down a video image

0001This is one of five reissue applications of U.S. Pat. No. 5,874,937. The first reissue is application Ser. No. 10/224,477 filed Aug. 21, 2002. The second reissue is application Ser. No. 11/905,507, filed Oct. 1, 2007. The third is application Ser. No. 12/222,127, filed Aug. 1, 2008. The fourth is application Ser. No. 12/801,725, filed Jun. 22, 2010. The fifth is this application, filed Jul. 12, 2011. This application also is a continuation of Reissue application Ser. No. 12/801,725 filed Jun. 22, 2010 now U.S. Pat. No. Re. 42,656, which is a continuation of Reissue application Ser. No. 12/222,127 filed Aug. 1, 2008 now U.S. Pat. No. Re. 41,522, which is a continuation of Reissue application Ser. No. 11/905,507 filed Oct. 1, 2007 now abandoned, which is a continuation of Reissue application Ser. No. 10/224,477 filed Aug. 21, 2002 now abandoned.

BACKGROUND OF THE INVENTION

00021. Field of the Invention

0003The present invention relates to a method of and an apparatus for scaling up and down an input video image and displaying the resultant video image on a display device.

00042. Description of the Related Art

0005In some cases, it is required to display video images generated by a computer on another display device, such as a liquid-crystal projector. In such a case, the computer should generate video signals according to the resolution of the display device. In the description of this specification, the term “resolution” implies both a number of dots (that is, a number of pixels) in a horizontal direction of a video image and a number of lines (that is, a number of scanning lines) in a vertical direction. The number of dots in the horizontal direction is referred to as the horizontal resolution, whereas the number of lines in the vertical direction is referred to as the vertical resolution.

0006The resolution and the number of tones of a video image generated by a computer are restricted by the capacity of a video RAM (VRAM) in the computer. The number of tones is reduced for a display with a greater resolution (that is, a larger screen size), and increased for a display with a smaller resolution. When the display device has a significantly large screen size, it may be impossible to make the resolution of a video signal generated by the computer coincident with the resolution of the display device. The similar problem arises when a video image generated by a device other than the computer (for example, a television image) is displayed on a display device other than a television receiver.

SUMMARY OF THE INVENTION

0007Accordingly, an object of the present invention is to convert any resolution of an input video image to a resolution of a display device and display the video image with the converted resolution.

0008The present invention is directed to a video image scaling apparatus for scaling up or down an input video image and displaying the scaled video image on a display device. The apparatus comprises: resolution determination means for analyzing an input video signal to determine a resolution of the input video signal; and scaling means for expanding or contracting a video image expressed by the input video signal so that the resolution of the video signal is made equal to a resolution of the display device.

0009Since the resolution of a display device is known, a ratio of the resolution of the input video signal to the resolution of the display device can be obtained if the resolution of the input video signal is determined. Expansion or contraction of a video image by the ratio will make the resolution of a video signal equal to the resolution of the display device.

0010In a preferred embodiment of the present invention, the resolution determination means comprises: resolution storage means for storing relations between the resolution of the input video signal and frequencies of synchronizing signals of the input video signal; frequency determination means for determining frequencies of the synchronizing signals of the input video signal; and means for reading out a resolution corresponding to the frequencies of the synchronizing signals from the resolution storage means.

0011When the relations between the resolutions of a video signal and frequencies of synchronizing signals are stored in the resolution storage means, the resolution can be readily determined according to the frequencies of the synchronizing signals.

0012In accordance with an aspect of the present invention, the apparatus further comprises: means for displaying a sign indicating that a resolution is unknown when the frequencies of the synchronizing signals of the input video image are not stored in the resolution storage means; and resolution setting means for setting a value of the unknown resolution of the input video signal and registering a relation between the resolution and the frequencies of the synchronizing signals of the input video signal in the resolution storage means.

0013This aspect allows to convert the resolution of an input image signal even if the input video signal has synchronizing signals of unknown frequencies.

0014The scaling means comprises: a first buffer memory for temporarily storing the input video signal; a frame memory in which a video signal read out of the first buffer memory is written; a second buffer memory for temporarily storing a video signal read out of the frame memory; and memory control means for giving a write address to the frame memory while successively reading out video signals from the first buffer memory to write the video signal read out of the first buffer memory into the frame memory, and for giving a read address to the frame memory to read out the video signal from the frame memory and transfer the video signal to the second buffer memory, and wherein the memory control means comprises: means for expanding or contracting a video image read out of the frame memory by adjusting the read address given to the frame memory.

0015The present invention is also directed to a method of scaling up or down an input video image and displaying the scaled video image on a display device. The method comprises the steps of: (a) analyzing an input video signal to determine a resolution of the input video signal; and (b) expanding or contracting a video image expressed by the input video signal so that the resolution of the video signal is made equal to a resolution of the display device.

0016These and other objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

0017<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram illustrating the structure of a liquid-crystal projector as a first embodiment according to the present invention;

0018<figref idref="DRAWINGS">FIG. 2</figref> schematically illustrates functions of a video scaler <b>36</b>;

0019<figref idref="DRAWINGS">FIG. 3</figref> is a block diagram illustrating the internal structure of the video scaler <b>36</b>;

0020<figref idref="DRAWINGS">FIG. 4</figref> shows the contents of a resolution determination table;

0021<figref idref="DRAWINGS">FIG. 5</figref> shows a wave form of a composite video signal;

0022<figref idref="DRAWINGS">FIG. 6</figref> is a block diagram illustrating the internal structure of a scaling unit <b>70</b>;

0023<figref idref="DRAWINGS">FIG. 7</figref> is a timing chart showing a process of generating vertical addresses;

0024<figref idref="DRAWINGS">FIGS. 8A and 8B</figref> show a concrete procedure of expanding a video image;

0025<figref idref="DRAWINGS">FIG. 9</figref> is a timing chart showing a process of generating horizontal addresses;

0026<figref idref="DRAWINGS">FIG. 10</figref> is a block diagram illustrating the internal structure of a latch error elimination circuit <b>150</b>;

0027<figref idref="DRAWINGS">FIG. 11</figref> is a block diagram illustrating the structure of a down converter as a second embodiment according to the present invention; and

0028<figref idref="DRAWINGS">FIGS. 12A</figref>, <b>12</b>B<b>1</b>, <b>12</b>B<b>2</b>, and <b>12</b>B<b>3</b> show a process of expanding and contracting a video image by multiplying read addresses by a predetermined coefficient K.

DESCRIPTION OF THE PREFERRED EMBODIMENT

0029<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram illustrating the structure of a liquid-crystal projector as a first embodiment according to the present invention. The liquid-crystal projector projects video images generated by a personal computer <b>100</b> on a large-size screen (not shown). The liquid-crystal projector includes a CPU <b>20</b>, a main memory <b>22</b>, an input panel <b>24</b> functioning as input means, an A-D converter <b>32</b>, a frame memory <b>34</b>, a video scaler <b>36</b>, LCD drivers <b>38</b>, LCD panels (liquid-crystal panels) <b>40</b>, and a light source <b>42</b>. The frame memory <b>34</b> includes three memory planes for storing R, G, and B signals, respectively. The LCD drivers <b>38</b> and the LCD panels are also provided for the R, G, and B signals.

0030The CPU <b>20</b> functions as a frequency determination unit <b>26</b> for determining a frequency of a synchronizing signal SYNC given by the personal computer <b>100</b> and as a resolution determination unit <b>28</b> for determining a resolution corresponding to the frequency of the synchronizing signal SYNC. The CPU <b>20</b> executes computer program codes stored in the main memory <b>22</b> to implement these functions.

0031The A-D converter <b>32</b> converts an analog video signal VPC generated by the personal computer <b>100</b> to a digital video signal DPC and transmits the digital video signal DPC to the video scaler <b>36</b>. The video scaler <b>36</b> receives the digital video signal DPC as well as the synchronizing signal SYNC output from the personal computer <b>100</b>. In the description of this specification, the term “video signals” may represent video signals in a narrow sense that do not include synchronizing signals, and also those in a broad sense that include synchronizing signals.

0032The video scaler <b>36</b> writes the input digital video signal DPC into the frame memory <b>34</b> while reading out a video signal from the frame memory <b>34</b> and supplying the video signal to the LCD driver <b>38</b>. In the course of writing or reading procedure, the video scaler <b>36</b> expands or contracts a video image, so as to make the resolution of the video signal coincident with a standard resolution of the LCD panel <b>40</b>. The LCD driver <b>38</b> reproduces a video images that is transmitted from the video scaler <b>36</b> on the LCD panel <b>40</b>. The video images reproduced on the LCD panels <b>40</b> are finally projected as a color image on the screen by means of an optical system including the light source <b>42</b>.

0033<figref idref="DRAWINGS">FIG. 2</figref> schematically illustrates the functions of the video scaler <b>36</b>. As shown in the left half of <figref idref="DRAWINGS">FIG. 2</figref>, video images generated by the personal computer <b>100</b> may have a variety of resolutions (for example, 640 dots by 400 lines, 640 dots by 480 lines, 800 dots by 600 lines, 1,024 dots by 768 lines, and 1,600 dots by 1,200 lines). The standard resolution of the LCD panel <b>40</b> is, on the other hand, fixed to a predetermined value. In the example of <figref idref="DRAWINGS">FIG. 2</figref>, the standard resolution is 800 dots by 600 lines. The video scaler <b>36</b> accordingly expands or contracts the input video signal VPC in order to generate a video signal having the standard resolution of the LCD panel <b>40</b>. When the video signal VPC generated by the personal computer <b>100</b> is input into the liquid-crystal projector of this embodiment, a video image expressed by the video signal VPC will be reproduced on the whole screen of the LCD panels <b>40</b>. This means that the resolution in the liquid-crystal projector is independent of the resolution of the input video signal VPC. Accordingly, a video image originally generated by the personal computer <b>100</b> can be reproduced on the LCD panel <b>40</b> to cover its whole display area regardless of the resolution and the number of tones of the image which are determined by the personal computer <b>100</b>.

0034<figref idref="DRAWINGS">FIG. 3</figref> is a block diagram illustrating the internal structure of the video scaler <b>36</b>. The video scaler <b>36</b> includes a first color conversion unit <b>50</b>, a write synchronizing signal generator <b>52</b>, an input FIFO buffer <b>54</b>, a DRAM controller <b>56</b>, an address controller <b>58</b>, a CPU access controller <b>60</b>, two output FIFO buffers <b>61</b> and <b>62</b>, a filter unit <b>64</b>, a second color conversion unit <b>66</b>, and a read synchronizing signal generator <b>68</b>. As shown in <figref idref="DRAWINGS">FIG. 3</figref>, the frame memory <b>34</b> is constructed as a dynamic RAM in this embodiment. The DRAM controller <b>56</b> is a circuit for controlling a process of writing video signals into the frame memory <b>34</b> and a process of reading out video signals from the frame memory <b>34</b>.

0035The digital video signal DPC output from the A-D converter <b>32</b> shown in <figref idref="DRAWINGS">FIG. 1</figref> is given to the first color conversion unit <b>50</b>, which carries out a color conversion to RGB signals, if necessary. By way of example, when the input digital video signal DPC is an YCrCb signal, the first color conversion unit <b>50</b> converts the YCrCb signal to an RGB signal.

0036The synchronizing signal SYNC generated by the personal computer <b>100</b> includes a horizontal synchronizing signal HSYNC<b>1</b> and a vertical synchronizing signal VSYNC<b>1</b>. The write synchronizing signal generator <b>52</b> has an internal PLL circuit (not shown), which multiplies the frequency of either the horizontal synchronizing signal HSYNC<b>1</b> or the vertical synchronizing signal VSYNC<b>1</b> by N₀to generate a dot clock signal DCK<b>1</b>. The dot clock signal DCK<b>1</b> indicates an update timing of a dot position in the horizontal direction. The dot clock signal DCK<b>1</b> as well as the horizontal synchronizing signal HSYNC<b>1</b> and the vertical synchronizing signal VSYNC<b>1</b> are supplied to the address controller <b>58</b>.

0037The video signal converted by the first color conversion unit <b>50</b> is temporarily stored in the FIFO buffer <b>54</b> and written into the frame memory <b>34</b> by the DRAM controller <b>56</b>. The FIFO buffer <b>54</b> works to adjust the timing of the writing operation. The writing operation into the frame memory <b>34</b> is carried out synchronously with the write synchronizing signals (DCK<b>1</b>, HSYNC<b>1</b>, and VSYNC<b>1</b>) output from the write synchronizing signal generator <b>52</b>. Each dot position (or horizontal address) is updated synchronously with the dot clock signal DCK<b>1</b>, while each scanning line position (vertical address) is updated synchronously with the horizontal synchronizing signal HSYNC<b>1</b>. Each frame or each field is updated synchronously with the vertical synchronizing signal VSYNC<b>1</b>. The DRAM controller <b>56</b> also reads out video signals stored in the frame memory <b>34</b> and writes the input video signals alternately into the two FIFO buffers <b>61</b> and <b>62</b>. The reading-out operation from the frame memory <b>34</b> is carried out synchronously with read synchronizing signals (DCK<b>2</b>, HSYNC<b>2</b>, and VSYNC<b>2</b>) generated by the read synchronizing signal generator <b>68</b>. The read synchronizing signals (DCK<b>2</b>, HSYNC<b>2</b>, and VSYNC<b>2</b>) are also supplied to the LCD driver <b>38</b> to be used as display synchronizing signals for the LCD panel <b>40</b>. The address controller <b>58</b> is a circuit for generating a write address and a read address and supplying the write and read addresses to the DRAM controller <b>56</b>. The address controller <b>58</b> further includes a scaling unit <b>70</b> for expanding or contracting (or scaling up or down) a video image.

0038One line of video signals read out from the frame memory <b>34</b> are written alternately into the two output FIFO buffers <b>61</b> and <b>62</b>. In the mean time, video signals are read out from the buffer which is not under the writing operation, to be supplied to the filter unit <b>64</b>. The filter unit <b>64</b> is a circuit for carrying out a variety of filtering processes, such as γ correction (conversion of input/output tones) and left-to-right and top-to-bottom inversions of video images. The filtered video signal undergoes the color conversion in the second color conversion unit <b>66</b>, if necessary, to be converted to an output video signal DOUT. The output video signal DOUT is then supplied to the LCD driver <b>38</b> (see <figref idref="DRAWINGS">FIG. 1</figref>).

0039The CPU <b>20</b> shown in <figref idref="DRAWINGS">FIG. 1</figref> has access to the respective elements in the video scaler <b>36</b> via the CPU access controller <b>60</b> shown in <figref idref="DRAWINGS">FIG. 3</figref>. In measuring the frequency of the synchronizing signal SYNC corresponding to the input video signal VPC, the CPU <b>20</b> receives the signals output from the write synchronizing signal generator <b>52</b> via the CPU access controller <b>60</b>. The CPU <b>20</b> first functions as the frequency determination unit <b>26</b> (see <figref idref="DRAWINGS">FIG. 1</figref>) to measure the frequencies of the horizontal synchronizing signal HSYNC<b>1</b> and the vertical synchronizing signal VSYNC<b>1</b>, which are supplied to the write synchronizing signal generator <b>52</b>. The CPU <b>20</b> then functions as the resolution determination unit <b>28</b> to determine the resolution of the input video image VPC based on the measured frequencies.

0040<figref idref="DRAWINGS">FIG. 4</figref> shows a resolution determination table indicating relations between the resolutions and the frequencies of the synchronizing signals. The relations between the various resolutions (the number of dots by the number of lines) and the frequencies of the horizontal synchronizing signal and the vertical synchronizing signal are registered in the resolution determination table, which is stored in the main memory <b>22</b>. The frequency of an operation clock of the CPU <b>20</b> is at least tens of MHz while the frequency of the horizontal synchronizing signal is tens of kHz, and the frequency of the vertical synchronizing signal several is tens of Hz. The CPU <b>20</b> can thus execute the computer program codes to implement the function of the frequency determination unit <b>26</b> to measure these frequencies with a sufficiently high accuracy. In accordance with a concrete procedure, the CPU <b>20</b> carries out the counting-up operation at a regular interval and obtains a count between edges (such as falling edges) of the horizontal synchronizing signal HSYNC<b>1</b>. The CPU <b>20</b> then calculates the frequency of the horizontal synchronizing signal HSYNC<b>1</b> from the count. The frequency of the vertical synchronizing signal VSYNC<b>1</b> can be determined in a similar manner. After determining the frequencies of the synchronizing signals HSYNC<b>1</b> and VSYNC<b>1</b>, the resolution determination unit <b>28</b> determines the corresponding resolution by referring to the resolution determination table (<figref idref="DRAWINGS">FIG. 4</figref>).

0041As shown in <figref idref="DRAWINGS">FIG. 4</figref>, plural combinations of the frequencies of synchronizing signals may correspond to an identical resolution. It is accordingly desirable to register relations between the resolutions and the frequencies used in a number of commercially available apparatuses as many as possible into the resolution determination table. There is, however, still a possibility of receiving a video signal having a frequency not registered in the resolution determination table. In such a case, the CPU <b>20</b> shown in <figref idref="DRAWINGS">FIG. 1</figref> may make a display on the LCD panel <b>40</b> (or on a display unit of the input panel <b>24</b>), showing that the frequency of the input video signal VPC has not yet been registered. The user then sets the resolution (the number of dots by the number of lines) of the input video signal VPC with the input panel <b>24</b>, thereby registering the relation between the frequency and the resolution into the resolution determination table. In order to realize this process, it is desirable to store the resolution determination table in a write-enable memory, such as a RAM or a flash memory.

0042The resolution of the input video signal VPC may be determined on the basis of not only the frequencies of the horizontal synchronizing signal and the vertical synchronizing signal but on period widths H_Hand H_Vof the horizontal and vertical synchronizing signals and on the kind of interlacing. <figref idref="DRAWINGS">FIG. 5</figref> shows the period widths H_Hand H_Vof the horizontal synchronizing signal and the vertical synchronizing signal. For convenience of illustration, <figref idref="DRAWINGS">FIG. 5</figref> shows a wave form of a composite video signal. Determination of the resolution of the input video signal based on the frequencies of the synchronizing signals as well as their period widths H_Hand H_Vand the state of interlacing can effectively reduce the possible errors that may be made in the determination.

0043The horizontal resolution and the vertical resolution determined by the resolution determination unit <b>28</b> are given to the address controller <b>58</b> via the CPU access controller <b>60</b> (see <figref idref="DRAWINGS">FIG. 3</figref>). The scaling unit <b>70</b> in the address controller <b>58</b> carries out expansion or contraction of a video image as described before along with <figref idref="DRAWINGS">FIG. 2</figref>, in order to convert the horizontal and vertical resolutions to the standard resolutions of the LCD panel <b>40</b>.

0044<figref idref="DRAWINGS">FIG. 6</figref> is a block diagram illustrating the internal structure of the scaling unit <b>70</b>. The scaling unit <b>70</b> includes a PLL circuit <b>142</b>, a frequency divider <b>144</b>, a horizontal address generator <b>146</b>, a vertical address generator <b>148</b>, a 3-state buffer <b>160</b>, and an inverter <b>162</b>. A data latch <b>164</b> shown in <figref idref="DRAWINGS">FIG. 6</figref> is a circuit included in the DRAM controller <b>56</b>. The horizontal address generator <b>146</b> includes a latch error elimination circuit <b>150</b>, a first counter <b>152</b>, and a first latch <b>154</b>. The vertical address generator <b>148</b> includes a second counter <b>156</b> and a second latch <b>158</b>.

0045The PLL circuit <b>142</b> receives the horizontal synchronizing signal HSYNC<b>2</b>, which is generated for the reading-out operation, and generates a second dot clock signal DCKX having the frequency of N times the frequency of HSYNC<b>2</b>. The frequency divider <b>144</b> receives the dot clock signal DCK<b>2</b>, which is also generated for the reading operation, and divides the frequency of DCK<b>2</b> by M to generate a line increment signal LINCX. The preset values N and M in the PLL circuit and the frequency divider <b>144</b> are used to convert the resolution of the input video signal VPC to the resolution of the LCD panel <b>40</b>, and are respectively determined by the CPU <b>20</b>. A concrete process of determining the preset values N and M will be described later.

0046<figref idref="DRAWINGS">FIG. 7</figref> is a timing chart showing operation of the vertical address generator <b>148</b>. After being reset by the vertical synchronizing signal VSYNC<b>2</b> for the reading operation (FIG. <b>7</b>(a)), the second counter <b>156</b> counts the number of pulses in the line increment signal LINCX. A count HC on the second counter <b>156</b> (<figref idref="DRAWINGS">FIG. 7(d)</figref>) is latched at a rising edge of the horizontal synchronizing signal HSYNC<b>2</b> and given as a vertical address VADD to the 3-state buffer <b>160</b>. In the example of <figref idref="DRAWINGS">FIG. 7(e)</figref>, the vertical address VADD is updated as 0, 1, 1, 2, . . .

0047<figref idref="DRAWINGS">FIGS. 8A and 8B</figref> show a concrete process of expanding a video image. <figref idref="DRAWINGS">FIG. 8A</figref> shows video data stored in the frame memory <b>34</b>, and <figref idref="DRAWINGS">FIG. 8B</figref> shows expanded video data. Numerals written in the tables represent the values of video data. In the timing chart of <figref idref="DRAWINGS">FIG. 7(e)</figref>, video data are read out from the frame memory <b>34</b> such that: a video image on a scanning line of VADD=0 is read out once, a video image on a scanning line of VADD=1 twice, a video image on a scanning line of VADD=2 twice, and the like. The video image thus read out is accordingly expanded in the vertical direction as shown in <figref idref="DRAWINGS">FIG. 8B</figref>. A vertical magnification MV<b>2</b> is given as a ratio of a frequency fHSYNC<b>2</b> of the horizontal synchronizing signal HSYNC<b>2</b> to a frequency fLINCX of the line increment signal LINCX. The video image can be expanded by an arbitrary magnification in the vertical direction by adjusting the preset value M in the frequency divider <b>144</b> (<figref idref="DRAWINGS">FIG. 6</figref>). The video image will be contracted in the vertical direction when the value of the magnification MV<b>2</b> is less than 1.

0048<figref idref="DRAWINGS">FIG. 9</figref> is a timing chart showing an operation of the horizontal address generator <b>146</b>. The latch error elimination circuit <b>150</b> (<figref idref="DRAWINGS">FIG. 6</figref>) generates a third dot clock signal DCKXX (<figref idref="DRAWINGS">FIG. 9(e)</figref>) from the first and the second dot clock signals DCK<b>2</b> and DCKX (<figref idref="DRAWINGS">FIGS. 9(b) and 9(d)</figref>).

0049<figref idref="DRAWINGS">FIG. 10</figref> is a block diagram illustrating the internal structure of the latch error elimination circuit <b>150</b>. The latch error elimination circuit <b>150</b> includes a delay circuit <b>170</b>, an exclusive NOR (EXNOR) circuit <b>172</b>, and a D-type flip-flop <b>174</b>. An output signal DKFF of the EXNOR circuit <b>172</b> is an inversion of an exclusive OR of the first dot clock signal DCK<b>2</b> and a signal obtained by delaying the dot clock signal DCK<b>2</b> by a predetermined time period. The signal DKFF thus represents timings of rises and falls of the first dot clock signal DCK<b>2</b> as shown in <figref idref="DRAWINGS">FIG. 9(c)</figref>.

0050The output signal DKFF of the EXNOR circuit <b>172</b> is supplied to a clock input terminal of the flip-flop <b>174</b>, while the second dot clock signal DCKX is given to a D-input terminal of the flip-flop <b>174</b>. The third dot clock signal DCKXX output from the flip-flop <b>174</b> thus represents the level of the second dot clock signal DCKX at a rising edge of the output signal DKFF of the EXNOR circuit <b>172</b> as shown in <figref idref="DRAWINGS">FIG. 9(e)</figref>. The third dot clock signal DCKXX has the frequency identical with that of the second dot clock signal DCKX. The output signal DKFF of the EXNOR circuit <b>172</b> rises after a predetermined delay time from an edge of the first dot clock signal DCK<b>2</b>, and the timing of the level change of the third dot clock signal DCKXX is delayed by the predetermined delay time from the edge of the first dot clock signal DCK<b>2</b> accordingly. The latch error elimination circuit <b>150</b> generates the third dot clock signal DCKXX, in order to prevent the value of a horizontal address latched by the first latch <b>154</b> from being unstable as discussed later in detail.

0051After being reset by the pulse of the horizontal synchronizing signal HSYNC<b>2</b>, the first counter <b>152</b> of the horizontal address generator <b>146</b> (<figref idref="DRAWINGS">FIG. 6</figref>) counts up the number of pulses of the third dot clock signal DCKXX generated by the latch error elimination circuit <b>150</b> and supplies a count DC (<figref idref="DRAWINGS">FIG. 9(f)</figref>) to the first latch <b>154</b>. Since the third dot clock signal DCKXX and the second dot clock signal DCKX have identical frequencies as mentioned above, the count DC of the first counter <b>152</b> practically indicates the number of pulses of the second dot clock signal DCKX. The first latch <b>154</b> latches the count DC synchronously with the first dot clock signal DCK<b>2</b>, and gives the latched count as a horizontal address HADD (<figref idref="DRAWINGS">FIG. 9(g)</figref>) to the 3-state buffer <b>160</b>. The horizontal address HADD accordingly represents the number of pulses of the second dot clock signal DCKX and is updated at every rising edge of the first dot clock signal DCK<b>2</b>. The value of the horizontal address HADD can be updated in a predetermined manner by adjusting a frequency fDCK<b>2</b> of the first dot clock signal DCK<b>2</b> and a frequency fDCKX of the second dot clock signal DCKX. In the example of <figref idref="DRAWINGS">FIG. 9(g)</figref>, the value of the horizontal address HADD is varied as 0,0,1, . . .

0052The tables of <figref idref="DRAWINGS">FIGS. 8A and 8B</figref> discussed above show a process of expanding a video image according to the horizontal address HADD in <figref idref="DRAWINGS">FIG. 9(g)</figref>. The timing chart shown in <figref idref="DRAWINGS">FIG. 9</figref> corresponds to timings of generating addresses in the horizontal direction on an upper-most scanning line having the vertical address of VADD=0. The horizontal address HADD is updated as 0,0,1 . . . as shown in <figref idref="DRAWINGS">FIG. 9(g)</figref>. Video data of the respective pixels existing on this scanning line are successively read out from the frame memory <b>34</b> o that the video data of the pixel having the horizontal address HADD=0 is read out twice, the video data of the pixel having the horizontal address HADD=1 is read out once, and the like.

0053As discussed above, the horizontal address HADD depends upon the relation between the frequencies of the two dot clock signals DCK<b>2</b> and DCKX. A video image can thus be expanded or contracted in the horizontal direction by adjusting the frequencies of these dot clock signals DCK<b>2</b> and DCKX. A magnification MH<b>2</b> of a video image in the horizontal direction is given as the ratio of the frequency fDCK<b>2</b> of the first dot clock signal DCK<b>2</b> to the frequency fDCKX of the second dot clock signal DCKX as shown in the bottom of <figref idref="DRAWINGS">FIG. 8</figref>. A video image can accordingly be expanded or contracted by an arbitrary magnification in the horizontal direction by adjusting the preset value N in the PLL circuit <b>142</b>.

0054The reason why the latch error elimination circuit <b>150</b> is used to generate the signal DCKXX is as follows. As shown in <figref idref="DRAWINGS">FIG. 9(f)</figref>, the count DC on the first counter <b>152</b> is varied synchronously with each rising edge of the third dot clock signal DCKXX (<figref idref="DRAWINGS">FIG. 9(e)</figref>) after the horizontal synchronizing signal HSYNC<b>2</b> (<figref idref="DRAWINGS">FIG. 9(a)</figref>) is returned to the high level. As discussed previously, an edge of the third dot clock signal DCKXX is delayed by a predetermined time period from an edge of the first dot clock signal DCK<b>2</b>. The latch timing in the first latch <b>154</b> thus does not overlap the timing of variation in count DC, so that the value of the horizontal address HADD is made stable.

0055As discussed above, the magnification MH<b>2</b> in the horizontal direction and the magnification MV<b>2</b> in the vertical direction can be set independently as shown in the bottom of <figref idref="DRAWINGS">FIG. 8</figref>, by adjusting the preset value N of the PLL circuit <b>142</b> and the preset value M of the frequency divider <b>144</b> shown in <figref idref="DRAWINGS">FIG. 6</figref>. A video image can be reproduced on the whole screen of the LCD panel <b>40</b> by setting the magnification MH<b>2</b> in the horizontal direction equal to the ratio of [the horizontal resolution of the LCD panel <b>40</b>] to [the horizontal resolution of the input video signal VPC] and by setting the magnification MV<b>2</b> in the vertical direction equal to the ratio of [the vertical resolution of the LCD panel <b>40</b>] to [the vertical resolution of the input video signal VPC].

0056<figref idref="DRAWINGS">FIG. 11</figref> is a block diagram illustrating the structure of a down-converter as a second embodiment according to the present invention. The down-converter has a video signal selection unit <b>200</b> in addition to the input unit of the liquid-crystal projector shown in <figref idref="DRAWINGS">FIG. 1</figref>. The down-converter further includes a video encoder <b>202</b> in place of the LCD driver <b>38</b>, and a variety of output devices (such as a television receiver <b>204</b>, a video player <b>206</b>, and a CD-RAM <b>208</b>) in place of the LCD panel <b>40</b> and the light source <b>42</b>.

0057The video signal selection unit <b>200</b> receives two television signals STV<b>1</b> and STV<b>2</b> as well as video signals (VPC, SYNC) generated by a personal computer, and selects one of the received signals. The television signals STV<b>1</b> and STV<b>2</b> are composite video signals including synchronizing signals. When the video signal selection unit <b>200</b> selects a composite video signal, a decoder (not shown) in the video signal selection unit <b>200</b> generates component video signals VIN and a synchronizing signal SYNC from the selected composite video signal.

0058The video encoder <b>202</b> generates a composite video signals from a digital video signal DOUT and the reading-out synchronizing signals (DCK<b>2</b>, HSYNC<b>2</b>, and VSYNC<b>2</b>) output from the video scaler <b>36</b>. The composite video signal thus generated is supplied to the television receiver <b>204</b> and the video player <b>206</b>. In order to write a video image into the CD-RAM <b>208</b> (write-enable compact disk unit), the video encoder <b>202</b> does not generate a composite video signal but directly supplies the digital video signal DOUT and the reading-out synchronizing signals to the CD-RAM <b>208</b>. The video scaler <b>36</b> can change the resolution of a video image to a desired resolution as discussed previously. When the user specifies a desired resolution, the video scaler <b>36</b> can output video images with the desired resolution corresponding to the various output devices. The apparatus of <figref idref="DRAWINGS">FIG. 11</figref> is called down-converter because it can convert a variety of input video signals down to a variety of output video signals.

0059The present invention is not restricted to the above embodiments or applications. There may be many modifications, changes, and alterations without departing from the scope and spirit of the main characteristics of the inventions follows.

0060(1) The functions of the frequency determination unit <b>26</b> and the resolution determination unit <b>28</b> (see <figref idref="DRAWINGS">FIG. 1</figref>) realized by the computer program codes in the above embodiments may be realized by hardware circuits.

0061(2) In the above embodiments, image expansion and contraction are carried out when video images are read out from the frame memory <b>34</b>. The image expansion and contraction may, however, be executed when video images are written into the frame memory <b>34</b>.

0062(3) Any technique other than the frequency control discussed above may be applied to the image expansion and contraction. For example, they can be attained by multiplying the read address or the write address by a predetermined coefficient to change the addresses so that the image is expanded or contracted according to the changed addresses. FIGS. <b>12</b>A and <b>12</b>B<b>1</b>-<b>12</b>B<b>3</b> show a process of expanding and contracting a video image by multiplying read address by a predetermined coefficient K. <figref idref="DRAWINGS">FIG. 12A</figref> shows a video image stored in the frame memory <b>34</b>, whereas FIGS. <b>12</b>B<b>1</b> through <b>12</b>B<b>3</b> show expanded or contracted video images. In the drawing, Di,j represents video data written at an address (i,j) in the frame memory <b>34</b>.

0063In the example of FIGS. <b>12</b>A and <b>12</b>B<b>1</b>-<b>12</b>B<b>3</b>, it is assumed that a memory resolution is defined by Mx (dots) by My (lines) and a display resolution Nx (dots) by Ny (lines). The coefficients K(Kx,Ky) by which the addresses are multiplied are given as follows: <br />Kx=Mx/Nx  (1a)<br />Ky=My/Ny  (1b)

0064A read address (XADD,YADD) used for reading out video data from the frame memory <b>34</b> is converted to a new read address (XADD,YADD) by the following equations: <br />XADD=INT(Kx×XADD)  (2a)<br />YADD=INT(Ky×YADD)  (2b)<br /> wherein the operator INT( )represents an operation of taking an integral portion of the value in parentheses.

0065FIG. <b>12</b>B<b>1</b> shows an example of the displayed image when the coefficients Kx and Ky are greater than 1.0 (for example, Kx=Ky=2.0). When the original horizontal address XADD is increased one by one, such as 0,1,2, . . . , the converted horizontal address XADD is varied as 0,2,4, . . . according to Equation (2a) given above. The vertical address YADD is converted in the same manner. Video data are read out from the frame memory <b>34</b> according to the converted read addresses XADD and YADD, so that a contracted video image is displayed as shown in FIG. <b>12</b>B<b>1</b>. The horizontal magnification and the vertical magnification in this contracting process are respectively equal to 1/Kx and 1/Ky.

0066When the coefficients Kx and Ky are equal to 1.0, a video image in the frame memory <b>34</b> is displayed without any expansion or contraction as shown in FIG. <b>12</b>B<b>2</b>.

0067FIG. <b>12</b>B<b>3</b> shows an example of the displayed image when the coefficients Kx and Ky are smaller than 1.0 (for example, Kx=Ky=0.7). When the original horizontal address XADD is increased one by one as 0,1,2,3, . . . , the converted horizontal address XADD is varied as 0,0,1,2, . . . The vertical address YADD is converted in the same manner. Video data are read out from the frame memory <b>34</b> according to the converted read addresses XADD and YADD, so that an expanded video image is displayed as shown in FIG. <b>12</b>B<b>3</b>.

0068It is possible to set arbitrary values to Kx and Ky independently.

0069(4) When a high-speed read/write memory, such as a synchronous DRAM, is used for the frame memory <b>34</b>, high-speed reading and writing of video signals can be carried out.

0070Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.