Method for fabricating a semiconductor storage device having an increased dielectric film area

0001This application is a divisional of U.S. patent application Ser. No. 09/059,590 filed Apr. 4, 1998 now U.S. Pat. No. 6,288,423.

BACKGROUND OF THE INVENTION

00021. Field of the Invention

0003The present invention relates to a semiconductor device including a memory cell having a composite gate structure or a semiconductor device including a stacked memory cell capacitor and a method of fabricating the same.

00042. Description of the Related Art

0005Conventionally, several improvements have been made to improve the write and erase characteristics of a memory cell of an EEPROM or the like having a floating gate structure or a memory cell capacitor.

0006As an example, in prior art disclosed in Japanese Patent Laid-Open No. 5-110107, at least a portion of a polysilicon film as a floating gate electrode is formed by CVD under conditions by which a larger number of fine undulations are formed on the surface of the floating gate electrode, and an insulating interlayer and a control gate electrode are formed along the undulations on the surface of the floating gate electrode.

0007These fine undulations increase the capacitance between the floating gate electrode and a control gate electrode. When voltage drop in which the voltage applied to the control gate electrode decreases occurs, these undulations efficiently act on the floating gate electrode to improve the write and erase characteristics.

0008Also, in prior art disclosed in Japanese Patent Laid-Open No. 5-55605, a recess is formed in substantially the center of a floating gate electrode to increase the capacitance between the floating gate electrode and a control gate electrode. Consequently, an effect similar to the effect of the above prior art is achieved.

0009The capacitance of a memory cell capacitor can also be increased by forming undulations on the surface of a lower electrode.

0010For example, Japanese Patent Laid-Open No. 5-243515 has described a method of increasing the charge storage amount by forming a rectangular or cylindrical trench in a lower electrode of a stacked memory cell capacitor.

0011Unfortunately, the above-mentioned prior arts have the following problems.

0012First, in the prior art disclosed in Japanese Patent Laid-Open No. 5-110107, the fine undulations on the floating gate electrode are formed under specific conditions by CVD. Therefore, the fabrication steps are complicated to set the CVD conditions. Additionally, since these undulations are very fine, the effect of increasing the capacitance is not satisfactory.

0013In the prior art disclosed in Japanese Patent Laid-Open No. 5-55605, the recess is formed in substantially the center of the floating gate electrode after a polysilicon film serving as the floating gate electrode is formed. Therefore, it is unavoidable to complicate the fabrication steps and increase the number of the fabrication steps. Also, the end point of etching for forming the recess is difficult to determine. Accordingly, the recess may sometimes extend through the polysilicon film to separate the floating gate electrode.

0014In the prior art of a capacitor disclosed in Japanese Patent Laid-Open No. 5-243515, the trench is formed by etching after stacked polysilicon serving as the lower electrode is formed. Accordingly, the fabrication steps are complicated and the number of the fabrication steps is increased. Furthermore, the end point of the etching cannot be easily determined.

SUMMARY OF THE INVENTION

0015It is an object of the present invention to provide a semiconductor device which includes a composite gate structure memory cell or a stacked memory cell capacitor, effectively increases the capacitance of the floating gate electrode or the memory cell capacitor, and has high reliability, and a simple method of fabricating this semiconductor device.

0016A semiconductor device of the present invention is a semiconductor device including an element active region defined by forming an element isolation structure on a semiconductor substrate, comprising an island-like charge storage film formed across the element isolation structure and the element active region so as to be formed on the element active region through an insulating film, the charge storage film having a recess in a surface on the element active region and a hole formed on the element isolation structure to reach the element isolation structure, a dielectric film so formed as to cover the surface of the charge storage film including inner surfaces of the hole, and a conductive film formed on the dielectric film and capacitively coupled with the charge storage film.

0017Another aspect of the semiconductor device of the present invention is a semiconductor device including an element active region defined by forming an element isolation structure on a semiconductor substrate, comprising an island-like charge storage film formed across the element isolation structure and the element active region so as to be formed on the element active region through an insulating film, the charge storage film having a recess in a surface on the element active region and a hole formed on the element isolation structure to reach the element isolation structure, and a conductive film formed on the charge storage film.

0018Still another aspect of the semiconductor device of the present invention is a semiconductor device including an element active region defined by forming an element isolation structure on a semiconductor substrate and having a transistor constituted by a gate electrode and a pair of impurity diffusion layers in the element active region, comprising an insulating interlayer formed on the semiconductor substrate including the transistor, a first hole formed in the insulating interlayer and having a surface layer of the impurity diffusion layer as a bottom surface, an island-like charge storage film electrically connected to one of the impurity diffusion layers through the first hole, a second hole formed in the charge storage film and having a surface layer of the insulating interlayer as a bottom surface, a dielectric film so formed as to cover a surface of the charge storage film including inner surfaces of the second hole, and a conductive film formed on the dielectric film and capacitively coupled with the charge storage film, wherein the charge storage film, the dielectric film, and the conductive film constitute a capacitor.

0019Still another aspect of the semiconductor device of the present invention is a semiconductor device including an element active region defined by forming an element isolation structure on a semiconductor substrate, comprising an insulating film formed on the semiconductor substrate in the element active region, and a charge storage film patterned on the insulating film, wherein the charge storage film is formed across the element isolation structure and has a hole on the element isolation structure, and at least a portion of a bottom surface of the hole reaches a surface layer of the element isolation structure.

0020Still another aspect of the semiconductor device of the present invention is a semiconductor device including a plurality of element isolation regions defined by forming an element isolation structure on a semiconductor substrate, comprising an island-like charge storage film formed across the element isolation structure and the element active regions and having a recess, a dielectric film so formed as to cover a surface of the charge storage film, and a conductive film formed on the dielectric film and capacitively coupled with the charge storage film, wherein the charge storage film is formed in each of the element active regions, and an upper surface of each of the charge storage films is planarized by CMP and flush with an upper surface of an adjacent charge storage film.

0021A method of fabricating a semiconductor device according to the present invention comprises the first step of defining an element active region by forming an element isolation structure on a semiconductor substrate, the second step of forming an insulating film on the semiconductor substrate in the element active region, the third step of forming a first conductive film on an entire surface of the semiconductor substrate including the insulating film and the element isolation structure, the fourth step of forming a mask pattern having first and second openings on the first conductive film, the fifth step of etching the first conductive film until the element isolation structure is exposed in the first opening by using the mask pattern as a mask, thereby dividing the first conductive film, and simultaneously forming a recess in the second opening having the first conductive film on a bottom of the recess, the sixth step of forming a dielectric film so as to cover a surface of the first conductive film, and the seventh step of forming a second conductive film on the dielectric film opposite the first conductive film and separated by the dielectric film.

0022Another aspect of the method of fabricating a semiconductor device according to the present invention comprises the first step of defining an element active region by forming an element isolation structure on a semiconductor substrate, the second step of forming a gate insulating film and a gate electrode in the element active region, the third step of doping an impurity into the second substrate to form a pair of impurity diffusion layers in surface regions of the semiconductor substrate on two sides of the gate electrode, the fourth step of forming a first conductive film electrically connected to one of the impurity diffusion layers, the fifth step of forming a mask pattern having at least first and second openings on the first conductive film, the sixth step of etching the first conductive film by using the mask pattern as a mask, thereby dividing the first conductive film in the first opening, and simultaneously forming a recess in the second opening where the first conductive film is on a bottom of the recess, the seventh step of forming a dielectric film so as to cover a surface of the first conductive film, and the eighth step of forming a second conductive film on the dielectric film opposite the second conductive film and separated by the dielectric film.

0023Still another aspect of the method of fabricating a semiconductor device according to the present invention comprises the first step of forming a first conductive film in an insulating film region on a semiconductor substrate, the second step of forming a mask pattern having two types of openings on the first conductive film, the third step of etching the first conductive film by using the mask pattern as a mask, thereby dividing the first conductive film conforming to a shape of one of the openings, and simultaneously forming at least one recess in a surface of the divided first conductive film conforming to a shape of the other opening, the fourth step of forming an insulating film so as to cover a surface of the first conductive film, and the fifth step of forming a second conductive film so as to cover a surface of the insulating film and opposing the second conductive film to the first conductive film through the insulating film.

0024Still another aspect of the method of fabricating a semiconductor device according to the present invention comprises the first step of defining an element active region by forming an element isolation structure on a semiconductor substrate, the second step of forming an insulating film on the semiconductor substrate in the element active region, the third step of forming a first conductive film on an entire surface including the insulating film and the element isolation structure, the fourth step of forming a mask pattern having at least first and second openings on the first conductive film, the fifth step of etching the first conductive film until the element isolation structure is exposed in the first and second openings by using the mask pattern as a mask, thereby dividing the first conductive film below the first opening, and simultaneously forming a hole extending through the first conductive film below the second opening, the sixth step of forming a dielectric film so as to cover the first conductive film, and the seventh step of forming a second conductive film on the dielectric film opposite the first conductive film and separated by the dielectric film.

0025Still another aspect of the method of fabricating a semiconductor device according to the present invention comprises the first step of defining an element active region by forming an element isolation structure on a semiconductor substrate, the second step of forming a gate oxide film and a gate electrode on the semiconductor substrate in the element active region, the third step of doping an impurity into the semiconductor substrate in the element active region to form a pair of impurity diffusion layers in surface regions of the semiconductor substrate on two sides of the gate electrode, the fourth step of forming a first conductive film electrically connected to one of the impurity diffusion layers, the fifth step of forming a mask pattern having at least first and second openings on the first conductive film, the sixth step of etching the first conductive film by using the mask pattern as a mask, thereby dividing the first conductive film below the first opening, and simultaneously forming a hole extending through the first conductive film below the second opening, the seventh step of forming a dielectric film so as to cover a surface of the first conductive film, and the eighth step of forming a second conductive film so as to cover the dielectric film and opposing the second conductive film to the first conductive film through the dielectric film.

0026In the semiconductor device of the present invention, a recess or a hole is formed in the charge storage film. Therefore, the area of the dielectric film can be increased to increase the charge storage amount. Especially when a hole is formed, the charge storage film and the conductive film can be opposite to each other and separated by the dielectric film within the range from the lower surface to the upper surface of the hole. Consequently, the charge storage amount can be effectively increased.

0027In the method of fabricating a semiconductor device of the present invention, the first conductive film (charge storage film) is divided by etching along the first opening in a mask pattern. At the same time, a recess or hole can be formed by self-alignment along the second opening in the mask pattern.

0028By setting the width of the first opening to be twice or more the width of the second opening, it is possible to decrease the etching rate in the second opening by a micro-loading effect and reliably form the recess without dividing the first conductive film.

0029Also, when the first conductive film is formed across the step between the element isolation structure and the element active region, the first conductive film is etched after its surface is planarized by polishing. Accordingly, even when etching is performed until the element isolation structure is exposed along the first opening, a recess can be formed without dividing the first conductive film in the second opening formed above the element active region.

0030When a hole is to be formed in the first conductive film, the first conductive film is etched until the underlying stacked film is exposed in the first and second openings. Consequently, it is possible to divide the first conductive film along the first opening and form a hole along the second opening.

0031The present invention can provide a semiconductor device which includes a composite gate structure memory cell or a stacked memory cell capacitor and in which the capacitance of the floating gate or the memory cell capacitor is effectively increased, and a method of stably and reliably fabricating this semiconductor device.

0032Accordingly, the present invention contributes to further development of these semiconductor devices.

BRIEF DESCRIPTION OF THE DRAWINGS

0033<figref idref="DRAWINGS">FIGS. 1A</figref> to <b>1</b>G are schematic sectional views showing a method of fabricating an EEPROM according to the first embodiment in order of steps;

0034<figref idref="DRAWINGS">FIGS. 2A</figref> to <b>2</b>J are schematic sectional views showing the method of fabricating the EEPROM according to the first embodiment in order of steps;

0035<figref idref="DRAWINGS">FIG. 3</figref> is a schematic plan view showing the EEPROM according to the first embodiment;

0036<figref idref="DRAWINGS">FIGS. 4A</figref> to <b>4</b>C are schematic sectional views showing a method of fabricating an EEPROM according to a modification of the first embodiment in order of steps;

0037<figref idref="DRAWINGS">FIG. 5</figref> is a schematic plan view showing the EEPROM according to the modification of the first embodiment shown in <figref idref="DRAWINGS">FIGS. 4A</figref> to <b>4</b>C;

0038<figref idref="DRAWINGS">FIGS. 6A</figref> to <b>6</b>C are schematic views showing a method of fabricating an EEPROM according to another modification of the first embodiment in order of steps;

0039<figref idref="DRAWINGS">FIG. 7</figref> is a schematic view showing the EEPROM according to the modification of the first embodiment shown in <figref idref="DRAWINGS">FIGS. 6A</figref> to <b>6</b>C;

0040<figref idref="DRAWINGS">FIGS. 8A</figref> to <b>8</b>D are schematic sectional views showing a method of fabricating an EEPROM according to the second embodiment in order of steps;

0041<figref idref="DRAWINGS">FIG. 9</figref> is a schematic plan view showing the EEPROM according to the second embodiment;

0042<figref idref="DRAWINGS">FIGS. 10A</figref> to <b>10</b>K are schematic sectional views showing a method of fabricating a stacked capacitor cell structure DRAM according to the third embodiment in order of steps;

0043<figref idref="DRAWINGS">FIG. 11</figref> is a schematic plan view showing the stacked capacitor cell structure DRAM according to the third embodiment;

0044<figref idref="DRAWINGS">FIGS. 12A</figref> to <b>12</b>E are schematic sectional views showing a method of fabricating a stacked capacitor cell structure DRAM according to a modification of the third embodiment in order of steps;

0045<figref idref="DRAWINGS">FIG. 13</figref> is a schematic plan view showing the stacked capacitor cell structure DRAM according to the modification of the third embodiment shown in <figref idref="DRAWINGS">FIGS. 12A</figref> to <b>12</b>E;

0046<figref idref="DRAWINGS">FIGS. 14A</figref> to <b>14</b>E are schematic sectional views showing a method of fabricating a stacked capacitor cell structure DRAM according to another modification of the third embodiment in order of steps;

0047<figref idref="DRAWINGS">FIG. 15</figref> is a schematic plan view showing the stacked capacitor cell structure DRAM according to the modification of the third embodiment shown in <figref idref="DRAWINGS">FIGS. 14A</figref> to <b>14</b>E;

0048<figref idref="DRAWINGS">FIG. 16</figref> is a schematic plan view showing the EEPROM according to the first embodiment; and

0049<figref idref="DRAWINGS">FIG. 17</figref> is a flow chart showing a read method of the EEPROM according to the first embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

0050The arrangement of a memory cell of an EEPROM according to the first embodiment of the present invention and a method of fabricating the same will be described below. <figref idref="DRAWINGS">FIGS. 1A</figref> to <b>1</b>G and <b>2</b>A to <b>2</b>J are side sectional views showing the fabrication steps of the EEPROM memory cell according to the first embodiment. <figref idref="DRAWINGS">FIG. 3</figref> is a schematic plan view showing a memory cell region of the EEPROM. A section I—I in <figref idref="DRAWINGS">FIG. 3</figref> corresponds to <figref idref="DRAWINGS">FIGS. 1A</figref> to <b>1</b>G; and a section II—II, to <figref idref="DRAWINGS">FIGS. 2A</figref> to <b>2</b>J.

0051First, the surface of a p-type silicon semiconductor substrate <b>1</b> is selectively oxidized by a so-called LOCOS process to form a field oxide film <b>2</b>. Consequently, element isolation is achieved on the p-type silicon semiconductor substrate <b>1</b> to define element formation regions <b>3</b>.

0052Subsequently, the element formation regions on the p-type silicon semiconductor substrate <b>1</b> are thermally oxidized to form a tunnel oxide film <b>4</b> having a thickness of about 100 Å, thereby obtaining the state shown in <figref idref="DRAWINGS">FIGS. 1A and 2A</figref>. Thereafter, a polysilicon film <b>5</b> having a thickness of about 5,000 Å is formed on the entire surface of the field oxide film <b>2</b> and the tunnel oxide film <b>4</b> by adding a dopant gas by low-pressure CVD. Alternatively, an undoped polysilicon film <b>5</b> may be formed and given conductivity by ion-implanting an impurity such as arsenic. This state is shown in FIG. <b>2</b>B.

0053Next, a photoresist <b>6</b> is formed on the polysilicon film <b>5</b> by photolithography. In this photolithography, as shown in <figref idref="DRAWINGS">FIG. 1B</figref>, a photoresist opening <b>7</b> is formed by forming an opening about 0.6 μm wide in a region for isolating floating gate electrodes <b>9</b> to be formed later. Also, photoresist openings <b>8</b> are formed by forming openings about 0.25 μm wide in regions corresponding to substantially the center of the width of the tunnel oxide film <b>4</b>.

0054By using the photoresist <b>6</b> as a mask, the polysilicon film <b>5</b> is selectively removed by dry etching until the surface of the field oxide film <b>2</b> below the photoresist opening <b>7</b> is exposed. Since the width of the photoresist openings <b>8</b> is smaller than the half width of the photoresist opening <b>7</b>, the supply of the etchant is reduced by a microloading effect when the polysilicon film <b>5</b> exposed in the photoresist openings <b>8</b> is etched. As a consequence, the etching rate is decreased in these portions.

0055That is, the progress in etching the polysilicon film <b>5</b> exposed in the photoresist opening <b>7</b> is faster than the progress in etching the polysilicon film <b>5</b> exposed in the photoresist openings <b>8</b>. Accordingly, the polysilicon film <b>5</b> exposed in the photoresist opening <b>7</b> is removed first, and the underlying field oxide film <b>2</b> is exposed.

0056The dry etching is stopped when the field oxide film <b>2</b> is exposed in the photoresist opening <b>7</b>. Consequently, the polysilicon film <b>5</b> is separated in the position of the photoresist opening <b>7</b>, forming the floating gate electrodes <b>9</b>. In the positions of the photoresist openings <b>8</b>, the polysilicon film <b>5</b> remains on the bottom surfaces to form recesses <b>20</b> on the floating gate electrodes <b>9</b>. This state is shown in <figref idref="DRAWINGS">FIGS. 1C and 2C</figref>.

0057Subsequently, as shown in <figref idref="DRAWINGS">FIGS. 1D and 2D</figref>, a silicon oxide film about 50 Å thick, a silicon nitride film about 40 Å thick, and a silicon oxide film about 50 Å thick are deposited in this order on the entire surface by LPCVD, thereby forming a dielectric film <b>10</b> made from an ONO film.

0058As shown in <figref idref="DRAWINGS">FIGS. 1E and 2E</figref>, a polysilicon film <b>11</b> having a thickness of about 1,500 Å is formed on the dielectric film <b>10</b> by CVD and patterned together with the floating gate electrodes <b>9</b> and the dielectric film <b>10</b>, thereby completing composite gate electrodes <b>12</b>. This state is shown in <figref idref="DRAWINGS">FIGS. 1E and 2F</figref>. The floating gate electrodes <b>9</b> have the function of a charge storage film which stores electric charge in accordance with the voltage applied to the polysilicon film <b>11</b>.

0059By using the composite gate electrodes <b>12</b> as masks, arsenic is ion-implanted into the surface region of the p-type silicon semiconductor substrate <b>1</b> to form a source region <b>13</b> and a drain region <b>14</b> as n-type impurity diffusion layers. Appropriate ion-implantation conditions are an acceleration energy of about 70 kev and a dose of about 5×10¹⁵/cm². Thereafter, annealing is performed at 900° C. for about 30 min to activate the implanted arsenic, obtaining the state shown in FIG. <b>2</b>G.

0060Next, as shown in <figref idref="DRAWINGS">FIG. 2H</figref>, a BPSG film <b>15</b> as an insulating interlayer is deposited on the entire surface by CVD, and the surface is planarized by reflow. Thereafter, contact holes <b>16</b>, <b>17</b>, and <b>18</b> are formed in the BPSG film <b>15</b> to expose portions of the source region <b>13</b>, the polysilicon film <b>11</b>, and the drain region <b>14</b>, respectively. The result is the state shown in FIG. <b>2</b>I.

0061After an aluminum alloy film <b>19</b> is deposited by sputtering to bury the contact holes <b>16</b>, <b>17</b>, and <b>18</b>, a wiring pattern is formed by photolithography and subsequent dry etching to complete a memory cell of an EEPROM as shown in <figref idref="DRAWINGS">FIGS. 1F</figref>, <b>2</b>J, and <b>3</b>.

0062Note that the element formation regions <b>3</b> defined in the first step can also be defined by a method other than LOCOS. When the regions are to be defined by a so-called field shield structure, a shield gate oxide film is first formed on the p-type semiconductor substrate <b>1</b>, and a thin polysilicon film and a CVD oxide film are formed in this order on top of the shield gate oxide film.

0063Subsequently, patterning is performed to remove the above stacked structure except for portions serving as the element isolation regions. Thereafter, a CVD oxide film is formed, and anisotropic etching is performed to leave this CVD oxide film only on the side walls of the patterned stacked structure described above, thereby forming the element isolation regions. <figref idref="DRAWINGS">FIG. 1G</figref> shows a memory cell of an EEPROM having a field shield element isolation structure thus formed. In <figref idref="DRAWINGS">FIG. 1G</figref>, a thin polysilicon film <b>24</b> covered with a CVD oxide film <b>23</b> is equivalent to a shield plate electrode.

0064It is also possible to define element active regions by a trench element isolation structure formed by burying an insulating film in a trench formed in a semiconductor substrate.

0065In the first embodiment as described above, in separating the adjacent floating gate electrodes <b>9</b> of a memory cell of an EEPROM, the width of the photoresist openings <b>8</b> is made smaller than the half width of the photoresist opening <b>7</b>. Consequently, even when the polysilicon film <b>5</b> exposed in the photoresist opening <b>7</b> is etched away to expose the underlying field oxide film <b>2</b>, the polysilicon film <b>5</b> is left behind on the bottom surfaces of the photoresist openings <b>8</b> by the microloading effect, forming the recesses <b>20</b> in these portions.

0066Since etching is stopped when the field oxide film <b>2</b> is exposed, the bottom surfaces of the recesses <b>20</b> are reliably positioned above the surface of the field oxide film <b>2</b> by the microloading effect. This prevents the polysilicon film <b>5</b> from being divided by the recesses <b>20</b>. Accordingly, the floating gate electrodes <b>9</b> having the recesses <b>20</b> can be stably formed.

0067Also, the recesses <b>20</b> are formed by self-alignment at the same time the floating gate electrodes <b>9</b> are separated. Therefore, the recesses <b>20</b> can be formed without increasing the number of fabrication steps.

0068In the composite gate electrode <b>12</b> including the floating gate electrode <b>9</b> having the recess <b>20</b>, the dielectric film <b>10</b> made from an ONO film, and the polysilicon film <b>11</b>, the capacitance of the dielectric film <b>10</b> is increased by the recess <b>20</b>. As a consequence, the write and erase characteristics of the memory cell can be improved.

Modifications

0069A modification of the first embodiment will be described below. <figref idref="DRAWINGS">FIGS. 4A</figref> to <b>4</b>C are side sectional views showing the steps in fabricating a memory cell of an EEPROM according to this modification. <figref idref="DRAWINGS">FIG. 5</figref> is a schematic plan view showing a memory cell region of this EEPROM. A section I—I in <figref idref="DRAWINGS">FIG. 5</figref> corresponds to <figref idref="DRAWINGS">FIGS. 4A</figref> to <b>4</b>C. The same reference numerals as in the EEPROM of the first embodiment denote the same parts, and a detailed description thereof will be omitted.

0070<figref idref="DRAWINGS">FIG. 4A</figref> corresponds to the step shown in <figref idref="DRAWINGS">FIG. 1B</figref> of the first embodiment. In this modification, the steps up to the state shown in <figref idref="DRAWINGS">FIG. 4A</figref> are the same as in the first embodiment. As shown in <figref idref="DRAWINGS">FIG. 4A</figref>, the number of openings in the photoresist <b>6</b> formed on the polysilicon film <b>5</b> is larger than in the first embodiment.

0071That is, as shown in <figref idref="DRAWINGS">FIG. 4A</figref>, substantially cylindrical photoresist openings <b>21</b> are formed between the photoresist openings <b>7</b> and the photoresist opening <b>8</b> in this modification.

0072By using this photoresist <b>6</b> as a mask, the polysilicon film <b>5</b> is selectively removed by dry etching. The etching is performed until the underlying field oxide film <b>2</b> is exposed in the photoresist opening <b>8</b> and the photoresist openings <b>21</b>. Consequently, as shown in <figref idref="DRAWINGS">FIG. 4B</figref>, substantially cylindrical openings <b>22</b> are formed, and the recesses <b>20</b> are formed in the photoresist openings <b>7</b>.

0073Thereafter, as in the first embodiment, the dielectric film <b>10</b> made from an ONO film is formed on the entire surface. The polysilicon film <b>11</b> is then formed by CVD and patterned to form the composite gate electrodes <b>12</b>.

0074As in the first embodiment, arsenic is ion-implanted to form the source and drain regions <b>13</b> and <b>14</b> (not shown), the BPSG film <b>15</b> is deposited and subjected to reflow, the contact holes <b>16</b>, <b>17</b>, and <b>18</b> are formed, and the aluminum alloy film <b>19</b> is deposited and patterned to complete a memory cell of an EEPROM as shown in <figref idref="DRAWINGS">FIGS. 4C and 5</figref>.

0075In the memory cell of the EEPROM according to the modification with the above arrangement, the substantially cylindrical openings <b>22</b> are additionally formed on the floating gate electrodes <b>9</b>. Accordingly, the capacitance of the dielectric film <b>10</b> can be further increased compared to the first embodiment. As a consequence, the write and erase characteristics of the memory cell can be further improved.

0076Note that the etching rate controlled by the microloading effect can be increased or decreased by properly changing the diameter of the photoresist openings <b>21</b> in the above modification. For example, the diameter may be made smaller than in the above modification to set the same etching rate as the photoresist openings <b>7</b>, and the polysilicon film <b>5</b> may be removed to the extent to which the underlying field oxide film <b>2</b> is not exposed.

0077If this is the case, in the step shown in <figref idref="DRAWINGS">FIG. 4A</figref>, substantially cylindrical photoresist openings <b>26</b> having a smaller diameter are formed between the photoresist openings <b>7</b> and <b>8</b> as shown in FIG. <b>6</b>A.

0078By using this photoresist <b>6</b> as a mask, the polysilicon film <b>5</b> is selectively removed by dry etching. In this etching, the polysilicon film <b>5</b> exposed in the photoresist openings <b>26</b> is also removed to form substantially cylindrical recesses <b>25</b> as shown in FIG. <b>6</b>B.

0079After the dielectric film <b>10</b> made from an ONO film is formed on the entire surface, the polysilicon film <b>11</b> is formed by CVD and patterned to form the composite gate electrodes <b>12</b>.

0080Thereafter, arsenic is ion-implanted to form the source and drain regions <b>13</b> and <b>14</b>, the BPSG film <b>15</b> is deposited on the entire surface and subjected to reflow, the contact holes <b>16</b>, <b>17</b>, and <b>18</b> are formed, and the aluminum alloy film <b>19</b> is deposited and patterned to complete a memory cell of an EEPROM as shown in FIG. <b>6</b>C and the schematic plan view of FIG. <b>7</b>.

0081As described above, even when the recesses <b>25</b> are formed by giving the microloading effect to the photoresist openings <b>26</b> by decreasing the diameter of the photoresist openings <b>26</b>, the capacitance of the dielectric film <b>10</b> can be increased compared to the first embodiment. Consequently, the write and erase characteristics of the memory cell can be improved.

Second Embodiment

0082The arrangement of an EEPROM according to the second embodiment of the present invention and a method of fabricating the same will be described below. <figref idref="DRAWINGS">FIGS. 8A</figref> to <b>8</b>D are side sectional views showing the steps in fabricating a memory cell of the EEPROM according to the second embodiment. <figref idref="DRAWINGS">FIG. 9</figref> is a schematic plan view showing a memory cell region of this EEPROM. A section I—I in <figref idref="DRAWINGS">FIG. 9</figref> corresponds to <figref idref="DRAWINGS">FIGS. 8A</figref> to <b>8</b>D. The same reference numerals as in the EEPROM of the first embodiment denote the same parts, and a detailed description thereof will be omitted.

0083This second embodiment differs from the first embodiment in that after a polysilicon film <b>5</b> is formed, the surface of the polysilicon film <b>5</b> is planarized by chemical mechanical polishing (CMP) before the step of forming a photoresist <b>6</b>.

0084<figref idref="DRAWINGS">FIG. 8A</figref> is a view corresponding to the step shown in <figref idref="DRAWINGS">FIG. 2B</figref> of the first embodiment. Referring to <figref idref="DRAWINGS">FIG. 8A</figref>, the polysilicon film <b>5</b> having a thickness of about 1,000 Å is formed by LPCVD on a field oxide film <b>2</b> and a gate oxide film <b>4</b>. The steps up to the state shown in <figref idref="DRAWINGS">FIG. 8A</figref> are the same as in the first embodiment.

0085Thereafter, as shown in <figref idref="DRAWINGS">FIG. 8B</figref>, the surface of the polysilicon film <b>5</b> is planarized by chemical mechanical polishing (CMP).

0086As shown in <figref idref="DRAWINGS">FIG. 8C</figref>, the photoresist <b>6</b> is formed on the polysilicon film <b>5</b>. In the formation of this photoresist <b>6</b>, a photoresist opening <b>7</b> is formed by forming an opening about 0.6 μm wide in a region for isolating floating gate electrodes <b>9</b> to be formed later. Also, photoresist openings <b>8</b> are formed by forming openings about 0.6 μm wide in portions above regions corresponding to the centers of the floating gate electrodes <b>9</b>.

0087The polysilicon film <b>5</b> is dry-etched by using the photoresist <b>6</b> as a mask, and the etching is stopped when the field oxide film <b>2</b> is exposed in the photoresist opening <b>7</b>. The surface of the polysilicon film <b>5</b> is previously planarized by chemical mechanical polishing described above. Therefore, when etching is stopped at the time the field oxide film <b>2</b> is exposed, the tunnel oxide film <b>4</b> is not exposed and recesses <b>20</b> are formed in the photoresist openings <b>8</b> due to the step between the surfaces of the field oxide film <b>2</b> and the tunnel oxide film <b>4</b>.

0088Accordingly, the recesses <b>20</b> can be formed with high controllability at the same time the floating gate electrodes <b>9</b> are isolated. This state is shown in <figref idref="DRAWINGS">FIGS. 8D and 9</figref>.

0089Thereafter, as in the first embodiment, a dielectric film <b>10</b> made from an ONO film (not shown) is formed, a polysilicon film <b>11</b> is formed by CVD, and these films are patterned to form composite gate electrodes <b>12</b>.

0090Following the same procedure as in the first embodiment, arsenic is ion-implanted into the p-type semiconductor substrate, a BPSG film <b>15</b> (not shown) is formed, and reflow is performed. Finally, contact holes <b>16</b>, <b>17</b>, and <b>18</b> are formed, and an aluminum alloy film <b>19</b> is formed and patterned to complete a memory cell of an EEPROM.

0091In the second embodiment as described above, the surface of the polysilicon film <b>5</b> is planarized before the photoresist <b>6</b> is formed. Therefore, even when etching is performed until the field oxide film <b>2</b> is exposed in the photoresist opening <b>7</b>, the recesses <b>20</b> can be reliably formed in the photoresist openings <b>8</b> without exposing the underlying tunnel oxide film <b>4</b>.

0092By sufficiently increasing the height of the step between the surface of the tunnel oxide film <b>4</b> and the surface of the field oxide film <b>2</b>, the recesses <b>20</b> can be formed by leaving the polysilicon film <b>5</b> behind on the bottom surfaces with higher controllability.

0093Also, in the second embodiment, the recesses <b>20</b> can also be formed by self-alignment when the floating gate electrodes <b>9</b> are isolated.

0094Furthermore, the photoresist <b>6</b> is formed on the planarized polysilicon film <b>5</b> and patterned by lithography. Therefore, the widths of the photoresist openings <b>7</b> and <b>8</b> can be set with high controllability during lithography.

0095In the above first and second embodiments, a nonvolatile memory such as an EEPROM or an EPROM using the floating gate electrodes <b>9</b> made from polysilicon as a charge storage film is described. However, a stacked film of a silicon oxide film, a silicon nitride film, and a silicon oxide film may be used as a charge storage film, and the present invention may be applied to an MONOS type nonvolatile memory including this charge storage film, a control gate, a source, and a drain. The present invention may also be applied to an MNOS type nonvolatile memory including a charge storage film made from a stacked film of a silicon oxide film and a silicon nitride film, a control gate, a source, and a drain. When a charge storage film is made from an insulating film as described above, the dielectric film <b>10</b> need not be formed. If this is the case, electric charge is stored in the interface of the silicon oxide film or the silicon nitride film.

0096<figref idref="DRAWINGS">FIG. 16</figref> is a schematic plan view showing an embodiment in which the source region <b>13</b> is formed by a diffusion layer commonly to the unit memory cells, and the gate electrode <b>22</b> of the access transister is formed commonly to the unit memory cells, over the first and second embodiments above described.

0097Furthermore, if storage information is binary data, the EEPROM can also be constituted as a so-called multi-valued memory by setting a predetermined value of two bits or more as a storage state. That is, if the storage state is n bits (2n values, n is an integer of 2 or more), it is only necessary to set 2n different threshold voltages. For example, if the storage state is two bits (four values), four different reference voltages (threshold voltages) are used in a one-to-one correspondence with storage states “00”, “01”, “10”, and “11”. In a read, one storage state of each memory cell of the EEPROM is specified from the four threshold voltages by a predetermined determining operation. If the storage state is three bits (eight values), eight different reference voltages (threshold voltages) are used in a one-to-one correspondence with storage states “000”, “001”, “010”, “011”, “100”, “101”, “110”, and “111”. In a read, one storage state of each memory cell of the EEPROM is specified from the eight threshold voltages by a predetermined determining operation. In addition to the various effects described earlier, this multi-valued EEPROM greatly increases the storage density of each memory cell. Therefore, the EEPROM can well meet demands for a higher integration degree and a finer structure. If storage information is not binary data but information constituted by 0, 1, and 2, it is also possible to use “0”, “1”, and “2”, or “00”, “01”, “02”, “10”, “11”, “12”, “20”, “21”, and “22” as storage states. The storage state is expressed by three values in the former case and nine values in the latter case. This multi-valued structure is also applicable to a DRAM (to be described later) and other various semiconductor memories as well as to the EEPROM.

0098A method of writing storage information when the EEPROM described above is a multi-valued memory capable of storing 2-bit information in each memory cell will be described below. First, to write storage information “11”, the drain region <b>14</b> of a memory cell is connected to the ground potential, the source region <b>13</b> is opened, and a voltage of about 22 V is applied to the polysilicon film <b>11</b>. Consequently, electrons are injected from the drain region <b>14</b> into the floating gate electrode <b>9</b> through the tunnel oxide film <b>4</b>, and the threshold voltage (V_T) goes positive. Accordingly, the threshold voltage of the memory cell rises to about 4 V. This storage state is “11”.

0099To write data “10”, the drain region <b>14</b> of the memory cell is connected to the ground potential, the source region <b>13</b> is opened, and a voltage of about 20 V is applied to the polysilicon film <b>11</b>. Consequently, electrons are injected from the drain region <b>14</b> into the floating gate electrode <b>9</b> through the tunnel oxide film <b>4</b>, and the threshold voltage of the memory cell changes to about 3 V. This storage state is “10”.

0100To write data “01”, the drain region <b>14</b> of the memory cell is connected to the ground potential, the source region <b>13</b> is opened, and a voltage of about 18 V is applied to the polysilicon film <b>11</b>. Consequently, electrons are injected from the drain region <b>14</b> into the floating gate .electrode <b>9</b>.through the tunnel oxide film <b>4</b>, and the threshold voltage of the memory cell changes to about 2 V. This storage state is “01”.

0101To write data “00”, the drain region <b>14</b> of the memory cell is connected to the ground potential, the source region <b>13</b> is opened, and a voltage of about 10 V is applied to the polysilicon film <b>11</b>. Consequently, the electrons injected into the floating gate electrode <b>9</b> are cleared from the drain region <b>14</b>, and the threshold voltage of the memory cell changes to about 1 V. This storage state is “00”.

0102Individual steps of a read method when the EEPROM described above is a multi-valued memory capable of storing 2-bit information in each memory cell will be described below with reference to FIG. <b>17</b>. First, whether the upper bit of storage information stored in a memory cell is “0” or “1” is checked. To this end, a voltage of about 5 V is applied to the source region <b>13</b> and the drain region <b>14</b> and the polysilicon film <b>11</b> (step S<b>1</b>). The drain current is detected by a sense amplifier, and the threshold voltage V_Tis compared with the threshold voltage of a comparative transistor Tr<b>1</b> (step S<b>2</b>). If the threshold voltage V_Tis larger than the threshold voltage of the transistor Tr<b>1</b>, it is determined that the upper bit is “1”. If the current of the transistor Tr<b>1</b> is smaller, it is determined that the upper bit is “0”.

0103If the threshold voltage V_Tis larger than the threshold voltage of the transistor Tr<b>1</b>, a similar read is performed by using a transistor Tr<b>2</b>, and the current flowing through the memory cell is compared with the current flowing through the transistor Tr<b>2</b> (step S<b>3</b>). If the threshold voltage V_Tis smaller than the threshold voltage of the transistor Tr<b>1</b>, a similar read is performed by using a transistor Tr<b>3</b> (step S<b>4</b>).

0104If the threshold voltage V_Tis larger than the threshold voltage of the transistor Tr<b>2</b> in the read performed in step S<b>3</b>, it is determined that the storage information stored in the memory cell is “11” (step S<b>5</b>), and the information is read out from the memory cell on the other hand, if the threshold voltage V_Tis smaller than the threshold voltage of the transistor Tr<b>2</b> in step S<b>3</b>, it is determined that the storage information stored in the memory cell is “10” (step S<b>6</b>), and the information is read out from the memory cell.

0105If the threshold voltage of the memory cell is larger than the threshold voltage of the transistor Tr<b>3</b> in step S<b>4</b>, it is determined that the storage information stored in the memory cell is “01” (step S<b>7</b>), and the information is read out from the memory cell. If the threshold voltage V_Tis smaller than the threshold voltage of the transistor Tr<b>3</b> in step S<b>4</b>, it is determined that the storage information stored in the memory cell is “00” (step S<b>8</b>), and the information is read out from the memory cell.

Third Embodiment

0106The arrangement of a stacked capacitor cell structure DRAM according to the third embodiment of the present invention and a method of fabricating the same will be described below. <figref idref="DRAWINGS">FIGS. 10A</figref> to <b>10</b>K are side sectional views showing the steps in fabricating two adjacent DRAM memory cells in the third embodiment. <figref idref="DRAWINGS">FIG. 11</figref> is a schematic plan view showing these DRAM memory cell regions. A section I—I in <figref idref="DRAWINGS">FIG. 11</figref> corresponds to <figref idref="DRAWINGS">FIGS. 10A</figref> to <b>10</b>K.

0107First, as shown in <figref idref="DRAWINGS">FIG. 10A</figref>, the surface of a p-type silicon semiconductor substrate <b>31</b> is selectively oxidized by a so-called LOCOS process to form a field oxide film <b>32</b>. Consequently, element isolation is achieved on the p-type silicon semiconductor substrate <b>31</b> to define two element formation regions <b>32</b>.

0108Subsequently, the surface of the element formation regions <b>32</b> is thermally oxidized to form a gate oxide film <b>34</b> having a thickness of about 130 Å. Thereafter, a polysilicon film <b>35</b> is formed on the entire surface by CVD.

0109The gate oxide film <b>34</b> and the polysilicon film <b>35</b> are then patterned by photolithography and subsequent dry etching, thereby forming gate electrodes <b>36</b>. This state is shown in FIG. <b>10</b>B.

0110By using the gate electrodes <b>36</b> as masks, arsenic is ion-implanted to form source regions <b>37</b> and drain regions <b>38</b> as n-type impurity diffusion layers. Annealing is then performed to activate the arsenic ions. Appropriate ion-implantation conditions are an acceleration energy of about 70 kev and a dose of about 5×10¹⁵/cm². Appropriate annealing conditions are a temperature of 900° C. and an annealing time of about 30 min. Consequently, n-type MOS transistors are formed on the p-type silicon substrate <b>31</b> as shown in FIG. <b>10</b>C.

0111Next, as shown in <figref idref="DRAWINGS">FIG. 10D</figref>, a BPSG film <b>39</b> as an insulating interlayer is formed on the entire surface of the p-type silicon semiconductor substrate <b>31</b> by CVD, and the surface is planarized by reflow.

0112As shown in <figref idref="DRAWINGS">FIG. 10E</figref>, holes <b>40</b> for exposing portions of the source regions <b>27</b> are formed in the BPSG film <b>39</b>. Thereafter, a polysilicon film <b>41</b> is formed in the holes <b>40</b> and on the BPSG film <b>39</b> by adding a dopant gas by low-pressure CVD. Alternatively, an undoped polysilicon film <b>41</b> may be formed on the BPSG film <b>39</b> and given conductivity by ion-implanting an impurity such as arsenic. This state is shown in FIG. <b>10</b>F.

0113Subsequently, a photoresist <b>42</b> is formed on the polysilicon film <b>41</b> by photolithography. In this photolithography, as shown in <figref idref="DRAWINGS">FIG. 10G</figref>, a photoresist opening <b>43</b> is formed by forming an opening about 0.6 μm wide in a region for isolating lower electrodes <b>48</b> of adjacent stacked capacitor cells to be formed later. Also, photoresist openings <b>44</b> are formed by forming openings about 0.25 μm wide in regions near the centers of the lower electrodes <b>48</b> to be formed.

0114By using the photoresist <b>42</b> as a mask, the polysilicon film <b>41</b> is selectively removed by dry etching. Since the width of the photoresist openings <b>44</b> is smaller than the half width of the photoresist opening <b>43</b>, the supply of the etchant is reduced by a microloading effect when the polysilicon film <b>41</b> exposed in the photoresist openings <b>44</b> is etched. As a consequence, the etching rate is decreased in these portions.

0115That is, the progress in etching polysilicon film <b>41</b> exposed in the photoresist opening <b>43</b> is faster than the progress in etching the polysilicon film <b>41</b> exposed in the photoresist openings <b>44</b>. Accordingly, the polysilicon film <b>41</b> exposed in the photoresist opening <b>43</b> is removed first, and the underlying BPSG film <b>39</b> is exposed.

0116This dry etching is stopped when the BPSG film <b>39</b> is exposed in the photoresist opening <b>43</b>. Consequently, the polysilicon film <b>41</b> is separated in the position of the photoresist opening <b>43</b>, forming the lower electrodes <b>48</b> of the stacked capacitor cells. In the positions of the photoresist openings <b>44</b>, the polysilicon film <b>41</b> remains on the bottom surfaces to form recesses <b>49</b> in the lower electrodes <b>48</b>. This state is shown in FIG. <b>10</b>H.

0117Next, a silicon nitride film about 30 Å thick is deposited on the entire surface by LPCVD and oxidized in an oxygen atmosphere at about 850° C., thereby forming a dielectric film <b>45</b> made from an ONO film.

0118A polysilicon film <b>46</b> having a thickness of about 1,500 Å and serving as an upper electrode of the stacked capacitor cells is formed on the dielectric film <b>45</b> by CVD and patterned together with the dielectric film <b>45</b>, thereby completing a stacked capacitor cell structure including the lower electrodes <b>48</b>, the dielectric film <b>45</b>, and the polysilicon film <b>46</b> as an upper electrode as shown in FIG. <b>10</b>I. In this structure, the lower electrodes <b>48</b> achieve the function of charge storage films which capacitively couple with the polysilicon film <b>46</b> through the dielectric film <b>45</b>.

0119Subsequently, as shown in <figref idref="DRAWINGS">FIG. 10J</figref>, a BPSG film <b>50</b> is formed on the entire surface and subjected to reflow, and contact holes <b>47</b> are formed to expose portions of the drain regions <b>38</b>. Thereafter, an aluminum alloy film <b>51</b> as a bit line is filled in the contact holes <b>47</b> and deposited on the BPSG film by sputtering. Finally, the aluminum alloy film <b>51</b> is patterned to complete a stacked capacitor cell structure DRAM as shown in <figref idref="DRAWINGS">FIGS. 10K and 11</figref>.

0120In the third embodiment as described above, in separating the adjacent lower electrodes <b>48</b> in the stacked capacitor cell structure DRAM, the width of the photoresist openings <b>44</b> is made smaller than the half width of the photoresist opening <b>43</b>. Consequently, even when the polysilicon film <b>41</b> exposed in the photoresist opening <b>43</b> is etched away until the underlying BPSG film <b>39</b> is exposed, the polysilicon film <b>41</b> is left behind on the bottom surfaces of the photoresist openings <b>44</b> by the microloading effect, forming the recesses <b>49</b> in these portions.

0121Since etching is stopped when the BPSG film <b>39</b> is exposed, the bottom surfaces of the recesses <b>49</b> are reliably positioned above the surface of the BPSG film <b>39</b> by the microloading effect. This prevents the polysilicon film <b>41</b> from being separated by the recesses <b>20</b>. Accordingly, the lower electrodes <b>48</b> having the recesses <b>49</b> can be stably formed.

0122Also, the recesses <b>49</b> are formed by self-alignment at the same time the lower electrodes <b>48</b> are isolated. Therefore, the recesses <b>49</b> can be formed without increasing the number of fabrication steps.

0123In each stacked capacitor cell including the lower electrode <b>48</b> having the recess <b>49</b>, the dielectric film <b>45</b> made from the ONO film, and the polysilicon film <b>46</b> as the upper electrode, the capacitance of the dielectric film <b>45</b> is increased by the recess <b>49</b>. As a consequence, the write and erase characteristics of the memory cell can be improved.

Modifications

0124A modification of the third embodiment will be described below. <figref idref="DRAWINGS">FIGS. 12A</figref> to <b>12</b>E are side sectional views showing the steps in fabricating two adjacent DRAM memory cell capacitors according to this modification. <figref idref="DRAWINGS">FIG. 13</figref> is a schematic plan view showing the memory cell capacitors. A section I—I in <figref idref="DRAWINGS">FIG. 13</figref> corresponds to <figref idref="DRAWINGS">FIGS. 12A</figref> to <b>12</b>E. The same reference numerals as in the DRAM of the third embodiment denote the same parts, and a detailed description thereof will be omitted.

0125<figref idref="DRAWINGS">FIG. 12A</figref> corresponds to the step shown in <figref idref="DRAWINGS">FIG. 10G</figref> of the third embodiment. In this modification, the steps up to the state shown in <figref idref="DRAWINGS">FIG. 12A</figref> are the same as in the third embodiment. As shown in <figref idref="DRAWINGS">FIG. 12A</figref>, the number of openings in the photoresist <b>42</b> formed on the polysilicon film <b>41</b> is larger than in the third embodiment.

0126That is, following the same procedure as in the third embodiment, the photoresist opening <b>43</b> is formed by forming an opening about 0.6 μm wide in a region for isolating the lower electrodes <b>48</b> of adjacent stacked capacitor cells to be described later. Also, the photoresist openings <b>44</b> are formed by forming openings about 0.25 μm wide in regions near the centers of the lower electrodes <b>48</b> to be formed. In this modification, substantially cylindrical photoresist openings <b>53</b> are formed between the photoresist openings <b>43</b> and <b>44</b>.

0127By using the photoresist <b>42</b> as a mask, the polysilicon film <b>41</b> is selectively removed by dry etching. Since the width of the photoresist openings <b>44</b> is made smaller than the half width of the photoresist openings <b>43</b> and <b>53</b>, the supply of the etchant is reduced by a microloading effect when the polysilicon film <b>41</b> exposed in the photoresist openings <b>44</b> is etched. As a consequence, the etching rate is decreased in these portions.

0128That is, the progress in etching the polysilicon film <b>41</b> exposed in the photoresist openings <b>43</b> and <b>53</b> is faster than the progress in etching the polysilicon film <b>41</b> exposed in the photoresist openings <b>44</b>. Accordingly, the polysilicon film <b>41</b> exposed in the photoresist openings <b>43</b> and <b>53</b> is removed first, and the underlying BPSG film <b>39</b> is exposed.

0129This dry etching is stopped when the BPSG film <b>39</b> is exposed in the photoresist openings <b>43</b> and <b>53</b>. Consequently, the polysilicon film <b>41</b> is separated in the position of the photoresist opening <b>43</b>, forming the lower electrodes <b>48</b> of the stacked capacitor cells. In the photoresist openings <b>53</b>, the underlying BPSG film is exposed to form substantially cylindrical openings <b>54</b> in the lower electrodes <b>48</b>. Also, in the positions of the photoresist openings <b>44</b>, the polysilicon film <b>41</b> remains on the bottom surfaces to form recesses <b>49</b> in the lower electrodes <b>48</b>. This state is shown in FIG. <b>12</b>B.

0130Subsequently, a silicon nitride film about 30 Å thick is deposited on the entire surface by LPCVD and oxidized in an oxygen atmosphere at about 850° C., thereby forming the dielectric film <b>45</b> made from an ONO film.

0131The polysilicon film <b>46</b> having a thickness of about 1,500 Å and serving as an upper electrode of the stacked capacitor cells is formed on the dielectric film <b>45</b> by CVD and patterned together with the dielectric film <b>45</b>, thereby completing a stacked capacitor cell structure including the lower electrodes <b>48</b>, the dielectric film <b>45</b>, and the polysilicon film <b>46</b> as an upper electrode as shown in FIG. <b>12</b>C.

0132Subsequently, as shown in <figref idref="DRAWINGS">FIG. 12D</figref>, the BPSG film <b>50</b> is formed on the entire surface and subjected to reflow, and the contact holes <b>47</b> are formed to expose portions of the drain regions <b>38</b>. Thereafter, the aluminum alloy film <b>51</b> as a bit line is filled in the contact holes <b>47</b> and deposited on the BPSG film by sputtering. Finally, the aluminum alloy film <b>51</b> is patterned to complete a stacked capacitor cell structure DRAM as shown in <figref idref="DRAWINGS">FIGS. 12E and 13</figref>.

0133In this modification, the capacitance of the dielectric film <b>45</b> made from an ONO film can be further increased by the substantially cylindrical openings <b>54</b> compared to the third embodiment. As a consequence, the capacitive coupling ratio can be increased.

0134Note that the etching rate controlled by the microloading effect can be increased or decreased by properly changing the diameter of the photoresist openings <b>53</b> in the above modification. For example, the diameter may be made smaller than in the above modification to set the same etching rate as the photoresist openings <b>44</b>, and the polysilicon film <b>41</b> may be removed to the extent to which the underlying field oxide film <b>39</b> is not exposed.

0135If this is the case, in the step shown in <figref idref="DRAWINGS">FIG. 12A</figref>, substantially cylindrical photoresist openings <b>55</b> having a smaller diameter are formed between the photoresist openings <b>43</b> and <b>44</b> as shown in FIG. <b>14</b>A.

0136By using a photoresist <b>42</b> as a mask, the polysilicon film <b>41</b> is selectively removed by dry etching. Since the width of the photoresist openings <b>44</b> and <b>55</b> is made smaller than the half width of the photoresist opening <b>43</b>, the supply of the etchant is reduced by the microloading effect when the polysilicon film <b>41</b> exposed in the photoresist openings <b>44</b> and <b>55</b> is etched. As a consequence, the etching rate is decreased in these portions.

0137That is, the progress in etching the polysilicon film <b>41</b> exposed in the photoresist opening <b>43</b> is faster than the progress in etching the polysilicon film <b>41</b> exposed in the photoresist openings <b>44</b> and <b>55</b>. Accordingly, the polysilicon film <b>41</b> exposed in the photoresist opening <b>43</b> is removed first, and the underlying BPSG film <b>39</b> is exposed.

0138This dry etching is stopped when the BPSG film <b>39</b> is exposed in the photoresist opening <b>43</b>. Consequently, the polysilicon film <b>41</b> is separated in the position of the photoresist opening <b>43</b>, forming lower electrodes <b>48</b> of stacked capacitor cells. In the positions of the photoresist openings <b>44</b>, the polysilicon film <b>41</b> remains on the bottom surfaces to form recesses <b>49</b> in the lower electrodes <b>48</b>. Also, in the positions of the photoresist openings <b>55</b>, the polysilicon film <b>41</b> remains on the bottom surfaces to form substantially cylindrical recesses <b>56</b> in the lower electrodes <b>48</b>. This state is shown in FIG. <b>14</b>B.

0139Subsequently, a silicon nitride film about 30 Å thick is deposited on the entire surface by LPCVD and oxidized in an oxygen atmosphere at about 850° C., thereby forming the dielectric film <b>45</b> made from an ONO film.

0140The polysilicon film <b>46</b> having a thickness of about 1,500 Å and serving as an upper electrode of the stacked capacitor cells is formed on the dielectric film <b>45</b> by CVD and patterned together with the dielectric film <b>45</b>, thereby completing a stacked capacitor cell structure including the lower electrodes <b>48</b>, the dielectric film <b>45</b>, and the polysilicon film <b>46</b> as an upper electrode as shown in FIG. <b>14</b>C.

0141Subsequently, as shown in <figref idref="DRAWINGS">FIG. 14D</figref>, the BPSG film <b>50</b> is formed on the entire surface and subjected to reflow, and the contact holes <b>47</b> are formed to expose portions of the drain regions <b>38</b>. Thereafter, the aluminum alloy film <b>51</b> as a bit line is filled in the contact holes <b>47</b> and deposited on the BPSG film by sputtering. Finally, the aluminum alloy film <b>51</b> is patterned to complete a stacked capacitor cell structure DRAM as shown in <figref idref="DRAWINGS">FIGS. 14E and 15</figref>.

0142Note that in the third embodiment, a photoresist <b>6</b> may also be formed after the surface of a polysilicon film <b>5</b> is planarized as in the second embodiment. If this is the case, recesses can be formed in lower electrodes of capacitors without using the microloading effect as in the second embodiment. Additionally, since photolithography is performed by forming the photoresist <b>6</b> on the planarized polysilicon film <b>5</b>, the widths of the photoresist openings <b>43</b> and <b>44</b> can be set with higher controllability.

0143In the second and third embodiments, an element isolation structure can be formed by a field shield structure or a trench element isolation structure.

0144In the first to third embodiments, a silicon oxide film or an ONO film is used as a dielectric film. However, a dielectric film is not restricted to these films. For example, a ferroelectric film may also be used.

0145If a ferroelectric film is used, the polysilicon film <b>5</b>, <b>11</b> can be replaced with a film made of platinum, a titanium compound, a tungsten compound or a ruthenium compound. It may also be formed of a double layer structure in which a conductive film made of, for example, poly-silicon is provided under a platinum film.

0146Any material having a ferroelectric characteristic can be used as a material of the above-mentioned ferroelectric film. For example, PZT(lead zirconate titanate), PLZT(lead lanthanum zirconate titanate), barium titanate, palladium titanate, barium strontium titanate and bismuth titanate can be used as the material of the ferroelectric film. A dielectric film made of, for example, tantalic oxides or Ta₂O₅BSTO, which has a high dielectric constant of more than 50, can be used instead of the ferroelectric film.

0147The third embodiment described above may also be applied to a multi-value DRAM having three or more values. For example, methods of read and write to multi-value DRAMs are described in Japanese Patent Laid-Open No. 60-239994.

0148Furthermore, an insulating film including a silicon nitride film or an insulating film including a silicon oxide film and a silicon nitride film may be used as a charge storage film.