Arbitrary waveform synthesizer to generate one or more arbitrary waveforms

RELATED APPLICATIONS

This application is a continuation-in-part of U.S. application Ser. No. 10/951,435, filed Sep. <b>27, 2004, now U.S. Pat. No. 7,425,875 </b>which is in turn is a continuation of U.S. application Ser. No. 10/726,163, filed Dec. 2, 2003, now abandoned, which is in turn a continuation of U.S. application Ser. No. 10/131,606 filed Apr. 24, 2002, now U.S. Pat. No. 6,664,832, issued Dec. 16, 2003, which is in turn a continuation of U.S. application Ser. No. 09/607,078 filed Jun. 29, 2000, now U.S. Pat. No. 6,377,094, filed Jun. <b>29, 2000International Application No. PCT/US02/09155, filed Mar. </b>25, 2002.

This application also claims priority to U.S. Provisional Application No. 60/614,459, filed Oct. 1, 2004.

The entirety of each of these prior applications is incorporated herein by reference.

FIELD OF THE INVENTION

This invention relates generally to the field of waveform generation. More specifically, the invention relates to a method and apparatus for generating an arbitrary waveform using an oscillator or more generally delay elements in a delay line circuit that may be part of an oscillator, a phase locked loop circuit or a delay locked loop circuit.

BACKGROUND OF THE INVENTION

There are many instances when it is desirable to inexpensively divide units of time or units of distance into smaller units. For example, in a range detector, the time elapsed between the outgoing signal and the incoming signal may be very short, on the order of nanoseconds, and the use of a standard reference clock to count the time elapsed would yield an inaccurate count resulting in inaccurate distance calculations.

In another example, in laser printers, it is often desirable to provide a transition from white to black (or vice versa) at various distances within a given line cell for high resolution. See U.S. Pat. No. 5,109,283 incorporated herein by this reference. A white-to-black or black-to-white signal, however, clocked at the printer's pixel clock rate of 10 MHz, is not resolved finely enough at the printer's laser diode to accurately control print transitions within a given print cell. Faster clocks are too expensive and/or not available to reference the print transitions at the high temporal resolution (e.g., one nanosecond corresponding to print cell distances on the order of microns) required for high resolution graphic images.

One solution to the above problems is to use a device incorporating a free-running ring oscillator (also referred to interchangeably as a loop oscillator). U.S. Pat. Nos. 5,793,709 and 5,903,522 describe such solutions, and are herein incorporated by this reference. However, as signal requirements for applications in the fields of CD-RW, DVD, communications and radar demand transition edges of higher frequency and precision, limitations are realized. Differences in circuit conductive path lengths and implementation hardware become noticeable. An algebra clock based on the frequency of the reference clock limits the speed of the calculations made by the algebra circuitry. External circuitry calculating the speed of the free-running loop oscillator (“loop”) also limits the speed of the calculations made by the algebra circuitry. Devices using the output may not tolerate a sudden, unpredictable transition in the output signal when a synchronization signal is used.

The present invention addresses these needs.

SUMMARY OF THE INVENTION

It is therefore an object of this invention to compensate for different implementation hardware and unequal path lengths. Another object of this invention is to generate an internal clock for the transition edge calculations based on the output signal being generated, which can be substantially faster than the reference clock. The invention also includes a watchdog for supplying the internal clock should the transition edge calculations become erroneous. Another object of this invention is to internally calculate the average loop speed in order to increase the overall allowable frequency of the calculation. The circuitry also calculates the transition position in the loop based on the average loop speed to improve accuracy. Another object of this invention is to generate an output that seamlessly joins an updated output waveform with a previous output waveform upon an intentional change in the output phase. Applications in the fields of CD-RW, DVD, communications and radar require faster and more precise edge transitions.

This invention relates to a method and apparatus for generating an arbitrary waveform. In one aspect, the invention relates to a waveform generator for generating an arbitrary waveform. The waveform generator includes a free-running ring oscillator, an algebra module, a switching module and an output module. The free-running ring oscillator includes a plurality of delay elements connected in a loop and a plurality of taps disposed between the delay elements, with each tap providing a uniquely phased, oscillating transition signal. The algebra module includes an algebra data input port, a clock input port and an algebra data output port. The algebra module generates a signal at the algebra data output port indicating a first rising edge of the arbitrary waveform in response to a signal received at the algebra data input port. The switching module includes a switch input port in electrical communication with the algebra data output port, a plurality of switch tap input ports in electrical communication with the free-running ring oscillator taps and switch output port. At the switch output port, the switch module provides a first transition signal selected from one of the plurality of free-running ring oscillator taps in response to the signal indicative of a first rising edge received at the switch input port. The output module includes a transition signal input port in electrical communication with the switch output port, a window input port in electrical communication with the algebra data output port and a waveform output port in electrical communication with the clock input port of the algebra module. The output module creates an arbitrary waveform at the waveform output port in response to the first transition signal received at the transition signal input port of the output module and the signal of a first rising edge received at the window input port.

In one embodiment, the arbitrary waveform generator includes a loop averaging module, which includes a reference clock input port and a tap input port, which is electrically connected to the plurality of taps in the free-running ring oscillator. In response to a reference clock signal received at the reference clock input port, the loop averaging module counts the number of tap transitions occurring between edges of the reference clock signal and calculates an average loop speed in response to the count. The loop averaging module can further calculate the instantaneous phase of the ring oscillator in response to the calculated average loop speed and a plurality of captured states of the loop.

In another embodiment, the arbitrary waveform generator includes a fine delay module. The fine delay module includes a signal input port in electrical communication with the switch output port, a selection input port in electrical communication with the algebra data output port of the algebra module and a fine-delay output port in electrical communication with the input port of the output module. The fine delay module delays the propagation of the first transition signal from the switch output port of the switching module to the input port of the output module in response to the signal of a first rising edge received at the selection input port. The selection input port of the output module is in electrical communication with the switch output port of the switching module through the fine delay module.

In another embodiment, the algebra module includes a synchronization input port. In response to signals received at the algebra data input port and the synchronization input port, the algebra module, at the algebra data output port, creates a signal of a first rising edge within the arbitrary waveform. The algebra module then generates a signal of a first rising edge that results in a seamless incorporation of the first rising edge in the arbitrary waveform generator.

In another embodiment, one of the delay elements is an inverting delay element, with each delay element being identically loaded. In another embodiment, at least one delay element includes a test switch module. The test switch module has a test control input port and a test data input port. In response to a signal received at the test control input port, the delay element, at the corresponding tap, creates a signal identical to the signal received at the test data input port.

In another embodiment, the arbitrary waveform generator also includes a compensation module. The compensation module includes a data output port in electrical communication with the algebra module and a compensation input port to receive a signal indicative of a frequency altering parameter of a source of a reference clock. The compensation module estimates a variation in frequency of the reference clock associated with the frequency altering parameter of the source of the reference clock. The compensation module then creates a correction signal at the compensation output port in response to this frequency variation. In another embodiment, the frequency altering parameter is the temperature of the source of the reference clock. In another embodiment, the frequency altering parameter is the age of the source of the reference clock.

In another embodiment, the algebra module is made to create a second signal of the first falling edge within the arbitrary waveform at the algebra data output port in response to a signal received at the algebra input port. In another embodiment, the output module is made to create a catch-up signal of an erroneous signal of a first rising edge received at the window input port. In another embodiment, the arbitrary waveform generator is implemented within a CMOS integrated circuit.

In another embodiment, the arbitrary waveform generator includes an amplifier and a loop-speed compensator circuit. The amplifier feeds forward at least one component of power-supply noise from a power supply coupled to the ring oscillator and the loop-speed compensator circuit is in electrical communication with the amplifier. In one embodiment, the loop-speed compensator circuit is in electrical communication with the loop averaging module to adjust the calculated average loop speed in response to the amplified noise. In another embodiment, the loop-speed compensator circuit is in electrical communication with the algebra module to adjust the calculated average loop speed in response to the amplified noise.

In another embodiment, the arbitrary waveform generator includes a plurality of capacitive elements each of which is in electrical communication with a respective one of a plurality of signal paths. Each capacitive element has a respective predetermined capacitance to create a respective predetermined time delay in the propagation of a transition signal through the respective signal path such that the propagation time for a transition on a first signal path is substantially equal to the propagation time for a transition on a second signal path.

In another embodiment, each capacitive element of the plurality of capacitive elements has a value less than approximately 50 femtofarads. In a further embodiment, each of the plurality of signal paths is in electrical communication with a first capacitive element and a second capacitive element. In a further embodiment, the first and second capacitive elements have different sensitivities to temperature, process and supply voltage.

In another aspect, the invention relates to a method for creating an arbitrary waveform. The method of creating an arbitrary waveform includes generating a continuous sequence of transitions in a loop of delay elements, counting the transitions occurring at one of the delay elements in the loop, determining a desired first rising edge time and a first falling edge time, selecting a first transition in the continuous sequence of transitions in response to the desired first rising edge based on the counted transitions and an internal clock, selecting a second transition in the continuous sequence of transitions in response to the desired first falling edge time based on the counted transitions and an internal clock, generating an output signal using the first and second selected transitions, and generating the internal clock signal based on the output signal.

In one embodiment, the method of generating an output signal includes using each of the transitions of the continuous sequence of transitions to generate the output signal in response to the desired first rising edge time occurring in the past.

In another embodiment, the method includes the calculation of the average rate of transitions at one of the delay elements with respect to an input reference clock.

In another embodiment, the method includes the calculation of the instantaneous phase within the loop of delay elements in response to the calculated average rate of transitions and a plurality of captured states of the loop of delay elements.

In another embodiment, the method includes adding to the selected transition one of a plurality of propagation delays, where the difference between two of the plurality of propagation delays is less than the average propagation time of a transition through a delay element in the loop of delay elements.

In another embodiment, the method includes receiving an external synchronization signal and modifying the selection of the first and second transitions in response to the received synchronization signal. In a further embodiment, the modification process includes adjusting the selection of the first transition so there is a seamless incorporation of the first rising edge in the output signal to create the arbitrary waveform.

In another embodiment, each transition has a polarity. In a further embodiment, generating a continuous sequence of transitions includes inverting the polarity of a transition with a delay element. In a further embodiment, the generation of a continuous sequence of transitions provides an identical load to each of the delay elements.

In another embodiment, the method includes receiving a signal indicative of a frequency altering parameter of a source of a reference clock, determining any variation of the reference clock due to the frequency altering and altering the selection of the first transition in response to the determined variation. In another embodiment, the frequency altering parameter is a temperature of the source of the reference clock. In another embodiment, the frequency altering parameter is an age of the source of the reference clock.

In another embodiment, the method includes the addition of a predetermined time delay to the propagation of a transition through a respective signal path such that the propagation time for a transition through the signal path is substantially equal to the propagation time for a transition through a second signal path.

The waveform generation techniques described herein are applicable for use with delay elements of a delay line circuit that may be part of a free-running oscillator, a phase locked loop (PLL) circuit or a delay locked loop (DLL) circuit. Moreover, in order to generate multiple output waveforms, there may be a plurality of switching modules and a corresponding plurality of output modules. Each corresponding switching module/output module pair is dedicated to producing a corresponding output signal. Other unique applications and control configurations are of the digital waveform generation logic combined with locked loop circuits are also provided.

BRIEF DESCRIPTION OF THE DRAWINGS

<figref idref="DRAWINGS">FIG. 1A</figref> is a high level block diagram of one embodiment of the invention;

<figref idref="DRAWINGS">FIG. 1B</figref> is a timing diagram of the signals from the taps of the free-running loop oscillator shown in <figref idref="DRAWINGS">FIG. 1A</figref>;

<figref idref="DRAWINGS">FIG. 2</figref> is a high level block diagram of one embodiment of the invention depicting additional modules;

<figref idref="DRAWINGS">FIG. 3</figref> is a detailed block diagram of one embodiment of the delay element module shown in <figref idref="DRAWINGS">FIG. 2</figref>;

<figref idref="DRAWINGS">FIG. 4</figref> is a high level block diagram of another embodiment of the invention;

<figref idref="DRAWINGS">FIG. 5</figref> is a detailed block diagram of one embodiment of the algebra module of the invention;

<figref idref="DRAWINGS">FIG. 6</figref> is a detailed block diagram of one embodiment of the period integrator module shown in <figref idref="DRAWINGS">FIG. 5</figref>;

<figref idref="DRAWINGS">FIG. 7</figref> is a detailed block diagram of one embodiment of the loop averaging module shown in <figref idref="DRAWINGS">FIG. 5</figref>;

<figref idref="DRAWINGS">FIG. 8</figref> is a detailed block diagram of one embodiment of the clock domain transfer module shown in <figref idref="DRAWINGS">FIG. 5</figref>;

<figref idref="DRAWINGS">FIG. 9A</figref> is a detailed block diagram of one embodiment of the synchronization module shown in <figref idref="DRAWINGS">FIG. 5</figref>;

<figref idref="DRAWINGS">FIG. 9B</figref> is a detailed block diagram of one embodiment of the sync debouncer module shown in <figref idref="DRAWINGS">FIG. 9A</figref>;

<figref idref="DRAWINGS">FIG. 10A</figref> is a detailed block diagram of one embodiment of the switching module of the invention;

<figref idref="DRAWINGS">FIG. 10B</figref> is a detailed block diagram of one embodiment of the balanced mux module shown in <figref idref="DRAWINGS">FIG. 10A</figref>;

<figref idref="DRAWINGS">FIG. 11</figref> is a detailed block diagram of one embodiment of the fine delay module of the invention;

<figref idref="DRAWINGS">FIG. 12</figref> is a detailed block diagram of one embodiment of the output module of the invention;

<figref idref="DRAWINGS">FIG. 13</figref> is a detailed block diagram of one embodiment of the catch-up module, the windowing module and the edge flip flops shown in <figref idref="DRAWINGS">FIG. 12</figref>;

<figref idref="DRAWINGS">FIG. 14</figref> is a detailed block diagram of one embodiment of the phase combining module shown in <figref idref="DRAWINGS">FIG. 12</figref>;

<figref idref="DRAWINGS">FIG. 15</figref> is a detailed block diagram of one embodiment of the balanced XOR module shown in <figref idref="DRAWINGS">FIG. 14</figref>; and

<figref idref="DRAWINGS">FIGS. 16A</figref>, <b>16</b>B, <b>16</b>C and <b>16</b>D represent a timing diagram of signal propagation through one embodiment of the invention.

<figref idref="DRAWINGS">FIG. 17</figref> is a block diagram of a waveform synthesizer system similar to the one shown in <figref idref="DRAWINGS">FIG. 1</figref>, but comprising a phase locked loop (PLL) or a delay locked loop (DLL) circuit that locks to a locking signal.

<figref idref="DRAWINGS">FIG. 18</figref> is a more detailed block diagram of a phase locked loop circuit useful in the waveform synthesizer system shown in FIG. <b>17</b>.

<figref idref="DRAWINGS">FIG. 19</figref> is a block diagram of a delay locked loop circuit also useful in the waveform synthesizer system shown in FIG. <b>17</b>.

<figref idref="DRAWINGS">FIG. 20</figref> is a block diagram of a waveform generator capable of producing a plurality of output waveforms.

<figref idref="DRAWINGS">FIG. 21</figref> is a block diagram of system in which the digital waveform generation logic internal locks the phase of any one of its output signals to a locking signal.

<figref idref="DRAWINGS">FIG. 22</figref> is a block diagram of a locked loop waveform generation system.

DETAILED DESCRIPTION OF THE DRAWINGS

<figref idref="DRAWINGS">FIG. 1A</figref> depicts, at a high level, an arbitrary waveform generator <b>100</b> used to create an output signal <b>136</b>. The arbitrary waveform generator <b>100</b> includes a free-running loop oscillator <b>104</b>, a switching module <b>112</b>, an algebra module <b>108</b> and an output module <b>114</b>. The loop <b>104</b> is electrically connected to the switching module <b>112</b>, via taps, for transmitting transition edges to the switching module <b>112</b>. The algebra module <b>108</b> receives an external reference clock signal <b>128</b> and an algebra data input signal <b>132</b>. Using these signals <b>128</b>, <b>132</b>, the algebra module <b>108</b> calculates, as described in more detail below, which transition edge is to be selected from the taps to generate the next transition edge of the output signal <b>136</b>. The algebra module <b>108</b> is electrically connected to the switching module <b>112</b> and the output module <b>114</b> for transmitting the calculated transition edge used to generate the output signal <b>136</b>. The switching module <b>112</b> receives the transition edge information from the algebra module <b>108</b> and selects the tap of the loop <b>104</b> that corresponds to the calculated transition edge. The switching module is electrically connected to the output module <b>114</b> for transmitting the transition edge from the selected tap to the output module <b>114</b>. The output module receives the transition edge and provides it as an output signal <b>136</b>.

The free-running loop oscillator <b>104</b> includes an input for an external reset signal <b>140</b>, a series of delay element modules <b>120</b>a, <b>120</b>b, <b>120</b>c, <b>120</b>o, <b>120</b>p (generally <b>120</b>) and at least one inverting element <b>124</b>. This reset signal <b>140</b> has two states, a reset state and a run state. While the signal <b>140</b> is in the reset state, the loop <b>104</b> does not oscillate. When the signal <b>140</b> transitions to the run state, the loop <b>104</b> begins to oscillate. The transition propagates through the first delay element module <b>120</b>a to the input of the next delay element module <b>120</b>b. Shortly after a signal is received at the input of a delay element module <b>120</b>, the signal is output on the corresponding tap.

For example, some time after a transition propagates to the input of delay element module <b>120</b>a, it also appears on tap <b>0</b>. As the transition propagates to the output of the delay element module <b>120</b>a and subsequently to the input of the next delay element module <b>120</b>b, it also appears on tap <b>1</b>. This process is repeated as the transition progresses all the way to the last delay element module <b>120</b>p and tap <b>15</b>. The exemplary embodiment of <figref idref="DRAWINGS">FIG. 1A</figref> depicts 16 taps. The number of taps can vary. The number of taps is chosen by design consideration and, in part, depends on the desired frequency, available implementation hardware and speed of algebra module calculation.

The exemplary embodiment of <figref idref="DRAWINGS">FIG. 1B</figref> depicts the transitions as they appear on the corresponding taps of FIG. <b>1</b>A. As shown in <figref idref="DRAWINGS">FIG. 1B</figref>, there is a delay of approximately 300 picoseconds between each transition on each tap. This delay time represents the time it takes the transition to propagate from the input of the delay element module <b>120</b> to the output of the corresponding tap. This delay time is dependent on the hardware used to implement the design. The embodiment shown was implemented on an ASIC in 0.35 micron process. An ASIC in 0.25 micron process can yield a delay time that is approximately one half the delay time of the ASIC in 0.35 micron process. With a smaller the delay time, the algebra module <b>108</b> calculates a more precise placement of a transition edge in the output signal <b>136</b>. The delay time is chosen by design consideration, depending on the desired frequency, available implementation hardware and speed of algebra module calculation.

In another embodiment, each delay element module <b>120</b> contains an inverting element. The inverting elements cause every other tap to transition in the opposite direction for a single edge propagation around the loop. For example, tap <b>1</b>, tap <b>3</b>, tap <b>5</b>, tap <b>7</b>, tap <b>9</b>, tap <b>11</b>, tap <b>13</b> and tap <b>15</b> each transition from a high state to a low state, instead of from a low state to a high state as shown in FIG. <b>1</b>B. Use of inverting elements result in more consistent propagation times around the loop because the propagation time of a positive transition is different than the propagation time of a negative transition. Also, the inverting elements result in more uniform loading of the power supply.

Referring to <figref idref="DRAWINGS">FIG. 2</figref>, the transition propagates through the series of delay element modules <b>120</b>a to <b>120</b>p. Upon reaching the output of the last delay element module <b>120</b>p, the transition has completed one loop (also referred to as a lap). The exemplary embodiment of the loop <b>108</b> includes an inverting logic element <b>208</b> connected to the output of the last delay element module <b>120</b>p. This inverting logic element <b>208</b> is similar to an inverting logic element <b>404</b> (<figref idref="DRAWINGS">FIG. 3</figref>) included in each delay element module <b>120</b> connected to the output of the preceding delay element module <b>120</b>. This ensures that the output of the last delay element module <b>120</b>p is loaded similarly to the other delay element modules <b>120</b>a to <b>120</b>o so that the time between transitions on each tap is similar. Tolerances of hardware implementation also can determine how equal the delay times can be.

To create the “looping” effect, the propagation of transitions through the series of delay element modules <b>120</b>a, <b>120</b>b, <b>120</b>c, <b>120</b>o, <b>120</b>p must be repeated. To accomplish this, one transition is selected (e.g., from delay element module <b>120</b>o) and sent through an inverting element <b>124</b> back to the input of the first delay element module <b>120</b>a. The number of inverter elements <b>124</b> used depends on whether the delay element module <b>120</b> selected (e.g., delay element module <b>120</b>o) outputs a transition in the opposite direction of the first delay element module <b>120</b>a.

For example, if the first delay element module <b>120</b>a previously transitioned from low to high and the selected transition (e.g., delay element module <b>120</b>o) also transitioned from low to high, there must be one inverter <b>124</b> in the path to cause the transition transmitted to the input of the first delay element module <b>120</b>a to be from high to low. If the embodiment had delay element modules <b>120</b> that included inverter elements and the selected transition was already inverted with respect to the first delay element module <b>120</b>a, two inverter elements <b>124</b>, <b>124</b>′ (not shown) are used in series to ensure that the opposite transition was transmitted to the first delay element <b>120</b>a. The delay element module <b>120</b>o connected to the inverter <b>124</b> is selected so that the propagation time of the transition from the selected delay element module <b>120</b>o to the first delay element module <b>120</b>a, via the inverter element(s) <b>124</b>, is approximately equal to the propagation time of the transition from the selected delay element module <b>120</b>o to the output of the last delay element module <b>120</b>p.

For an illustrative example, each delay element module <b>120</b> includes inverting elements. The propagation time through two inverting elements <b>124</b>, <b>124</b>′ (not shown) equal the propagation time of two delay element modules <b>120</b>. The delay element module <b>120</b>m (not shown) corresponding to tap <b>13</b> is selected. Delay element module <b>120</b>n is the opposite transition of the first delay element module <b>120</b>a, so two inverting elements <b>124</b>, <b>124</b>′ are required to ensure the correct polarity. The timing is also correct so that the time the transition propagates from tap <b>13</b> to tap <b>15</b>, the transition also arrives at the input of the first delay element module <b>120</b>a via the two inverting elements <b>124</b>, <b>124</b>′.

As shown in <figref idref="DRAWINGS">FIG. 2</figref>, the loop <b>104</b> also includes a lap counter module <b>200</b> and a state capture module <b>204</b>. The algebra module <b>108</b> also includes a loop averaging module <b>212</b>. The lap counter module <b>200</b> is electrically connected to the first delay element module <b>120</b>a for receiving transition edges as they propagate through the delay element module <b>120</b>a. The lap counter module <b>200</b> is electrically connected to the state capture module <b>204</b> for transmitting the number of laps stored. The state capture module <b>204</b> receives a reference clock signal <b>128</b>. The state capture module <b>204</b> is electrically connected to each of the taps and the lap counter module <b>200</b> for receiving and storing the states of the loop <b>104</b> taps and lap counter module <b>200</b> at a reference clock signal <b>128</b> transition. The state capture module <b>204</b> is also electrically connected to the algebra module <b>108</b> for transmitting the stored state information <b>220</b>. The loop averaging module <b>212</b> receives the transmitted stored state information <b>220</b> from the state capture module <b>204</b> and calculates the average loop speed used in the algebra module <b>108</b> calculations.

The lap counter <b>200</b> includes two counters. A positive edge counter <b>200</b>a (not shown) counts one each time a positive edge transition (e.g. transition from logic low to high) propagates through the first delay element module <b>120</b>a. A negative edge counter <b>200</b>b (not shown) counts one each time a negative edge transition (e.g. transition from logic high to low) propagates through the first delay element module <b>120</b>a. Thus the negative edge counter <b>200</b>b is 180 degrees out-of-phase with the positive edge counter <b>200</b>a. Two counters <b>200</b>a, <b>200</b>b are used to ensure that even if one counter is being updated, the other modules of the arbitrary waveform generator <b>100</b> have access to a stable and accurate counter to determine the lap number. The size (i.e., number of bits) of each counter can vary and is chosen by design consideration, depending on the desired frequency, available implementation hardware and speed of algebra module calculation. Each counter keeps counting and, upon reaching its maximum value, rolls over to zero and continues counting.

The state capture module <b>204</b> includes a register <b>204</b>a (not shown) that uses the reference clock signal <b>128</b> as its clock. Upon a transition of the reference clock signal <b>128</b> (typically a positive edge transition), the register <b>204</b>a stores (also referred to as captures) the state of the loop <b>104</b>. In one embodiment, the register <b>204</b>a stores a 16 bit data word. In this embodiment, 11 bits are used for the value of the lap counter <b>200</b>. Four bits are used to represent 16 taps. These four bits are used for the state of the taps, representing the last tap that the transition propagated through at the time of the capture. One bit is used to represent the state of the transition (i.e., positive edge or negative edge) as it passed through the first delay element module <b>120</b>a. This bit is needed for determining whether the transition edge selected by the algebra module <b>108</b> is a positive edge or a negative edge and needs to be inverted by the switching module <b>112</b>.

The delay element modules <b>120</b> create the transition edges that are outputted to the taps and captured. One of the delay element modules <b>120</b> is shown in more detail in FIG. <b>3</b>. The delay element module <b>120</b> includes a NAND element <b>404</b>. The two inputs <b>408</b>,<b>412</b> of the NAND element <b>404</b> receive signals from the previous delay element module <b>120</b> output and a logic high signal <b>424</b>, respectively. The logic high signal ensures that the output of the NAND element <b>404</b> is the inverted signal of the input signal <b>408</b> from the output of the previous delay element module <b>120</b>.

For the first delay element module <b>120</b>a (FIG. <b>2</b>), the logic high signal is replaced by the reset signal <b>140</b> and the input signal <b>408</b> is received from the inverting output element <b>124</b>, not a previous delay element <b>120</b>. When the reset signal <b>140</b> is in the reset state, a logic low, the output of the NAND element <b>404</b> is a logic high, regardless of the input signal <b>408</b>. The rest of the delay element modules <b>120</b>b to <b>120</b>p (<figref idref="DRAWINGS">FIG. 2</figref>) of the free running loop oscillator <b>104</b>′ are driven to their corresponding states and the loop <b>104</b> stays in that reset state until the reset signal transitions to the run state, a logic high.

The output <b>412</b> of the NAND element <b>404</b> is sent to the next delay element module <b>120</b>. The output <b>412</b> also is an input to an inverter <b>416</b>. The transition from the inverter output <b>420</b> for one selected delay element module <b>120</b> (e.g., delay element module <b>120</b>o, <figref idref="DRAWINGS">FIG. 2</figref>) is sent to another inverter <b>124</b> (<figref idref="DRAWINGS">FIG. 2</figref>) and then to the first delay element module <b>120</b>a to maintain oscillation of the loop <b>104</b>. For the other delay element modules <b>120</b>a, <b>120</b>b, <b>120</b>c, <b>120</b>p, the output <b>420</b> is not connected. In one embodiment, the inverter <b>416</b> is included in each of the delay element modules <b>120</b>, whether connected or not, for load balancing purposes. As discussed above, keeping the loads of the delay element modules <b>120</b> as similar and equal as possible keeps the propagation times through each delay element module <b>120</b> consistent.

The output <b>412</b> of the NAND element <b>404</b> is connected to a test switch module <b>400</b>. The test switch module <b>400</b> receives a test input signal <b>440</b>. The state of this signal <b>440</b> determines the signal generated by test switch module <b>400</b>. For example, if the test input signal <b>440</b> is in a NOT test state (e.g., logic low), NAND element <b>428</b> outputs a signal having the opposite state of the output <b>412</b> of the NAND element <b>404</b>. The NAND element <b>432</b> outputs a logic high, regardless of the test data input signal <b>444</b>. Thus the NAND element <b>436</b> outputs the opposite state of the output of the NAND element <b>428</b>, which is the same as the state of the output <b>412</b> of the NAND element <b>404</b>. If the test input signal <b>440</b> is in a test state (e.g., logic high), the NAND element <b>428</b> outputs a logic high, regardless of the output <b>412</b> of the NAND element <b>404</b>. The NAND element <b>432</b> outputs the opposite state of the test data input signal <b>444</b>. Thus the NAND element <b>436</b> outputs the opposite state of the output of the NAND element <b>432</b>, which is the same state as the test data input signal <b>444</b>.

An inverting driver <b>448</b> amplifies the output of the NAND element <b>436</b>, which is the output of the test switch module <b>400</b>. The output of the inverting driver <b>448</b> is the tap signal <b>456</b> that is sent to the switching module <b>112</b> (FIG. <b>2</b>). Thus depending on the state of the test input signal <b>440</b>, the output of the inverting driver <b>448</b> is the opposite state of either the output of the NAND element <b>404</b> or the test data input signal <b>444</b>.

For the first delay element module <b>120</b>a, the output of the NAND element <b>436</b> also is an input to an inverting driver <b>452</b>. The output of the inverting driver <b>452</b> is connected to the lap counter module <b>200</b>. The lap counter counts each transition that is output from the inverting driver <b>452</b>. For the other delay element modules <b>120</b>b to <b>120</b>p, the output of the inverting driver <b>452</b> is not connected. In one embodiment, the inverting driver <b>452</b> is included in each of the delay element modules <b>120</b>, whether connected or not connected, for load balancing purposes.

<figref idref="DRAWINGS">FIG. 4</figref> depicts an alternate embodiment of an arbitrary waveform generator <b>100</b>′. The arbitrary waveform generator <b>100</b>′ further includes a fine delay module <b>310</b>, a compensation module <b>320</b>, a free running loop oscillator <b>104</b>′ that includes a state capture module <b>204</b>′ and an algebra module <b>108</b>′ that includes a synchronization module <b>304</b>. The fine delay module <b>310</b> is electrically connected to the switching module <b>112</b> for receiving the transition edge. The fine delay module <b>310</b> adds a differential delay to the transition edge that is smaller than the propagation delay time through a delay element module <b>120</b>. The fine delay module <b>310</b> is electrically connected to the output module <b>114</b> for transmitting the further delayed transition edge to the output module <b>114</b>. The compensation module <b>320</b> receives a compensation input signal <b>324</b>. The compensation module is electrically connected to the algebra module <b>108</b>′ for transmitting an adjustment signal.

In one embodiment, the compensation module <b>320</b> receives a compensation input signal <b>324</b> representing the temperature of the oscillator creating the reference clock input signal <b>128</b> (i.e., the source of the reference clock <b>128</b>). The compensation module <b>320</b> determines the variance of the frequency of the reference clock <b>128</b> based on the compensation input signal <b>324</b>, using a predetermined relationship of temperature to frequency (e.g., a look-up table). The compensation module <b>320</b> outputs the adjustment signal, with the variance information, to the algebra module <b>108</b>′. The variance, in terms of a reference clock <b>128</b> period delta, is algebraically added to the desired output period <b>132</b> to produce an ultra-stable time reference as the output signal <b>136</b> without an oven or a warm up delay.

In another embodiment, crystal aging may also be corrected in a similar manner by utilizing an age indicator signal (e.g., the current date) as the compensation input signal <b>324</b>. The compensation module <b>320</b> determines the variance of the frequency of the reference clock <b>128</b> based on the compensation input signal <b>324</b>, using a predetermined relationship of age to frequency (e.g., a look-up table).

The state capture module <b>204</b>′ receives a synchronization input signal <b>300</b>. The state capture module <b>204</b>′ is electrically connected to each of the taps and the lap counter module <b>200</b> for receiving and storing the states of the loop <b>104</b>′ taps and lap counter module <b>200</b> at a synchronization signal <b>300</b> transition. The state capture module <b>204</b>′ includes a second register <b>204</b>b (not shown) that uses the synchronization signal <b>300</b> as its clock. Upon a transition of the synchronization signal <b>300</b> (typically a positive edge transition), the second register <b>204</b>b stores the state of the loop <b>104</b>′. In one embodiment, the second register <b>204</b>b stores a 16 bit data word, the bits being used as described for the first register <b>204</b>a.

The state capture module <b>204</b>′ is also electrically connected to the algebra module <b>108</b>′ for transmitting the stored state information <b>330</b>. The synchronization module <b>304</b> of the algebra module <b>108</b>′ receives the transmitted stored state information <b>330</b> from the state capture module <b>204</b>′ and calculates the selection of subsequent transition edges so the output signal <b>136</b> is in phase with the synchronization signal <b>300</b>.

<figref idref="DRAWINGS">FIG. 5</figref> depicts the algebra module <b>108</b>′ in more detail. The algebra module <b>108</b>′ calculates the lap and tap that is needed from the loop <b>104</b>′ to create each transition edge of the output signal <b>136</b>. In one embodiment, a four channel algebra module <b>108</b>′ calculates the next two rising edges and the corresponding falling edges of the output signal <b>136</b>. The first rising edge is referred to as the phase <b>0</b> signal, the corresponding falling edge is referred to as the phase <b>1</b> signal, the second rising edge is referred to as the phase <b>2</b> signal and the corresponding falling edge is referred to as the phase <b>3</b> signal. For clarity the figures, except as noted, depict the circuitry for creating the phase <b>0</b> signal. The circuitry for the other three phase signals is similar, unless otherwise noted. By calculating four edges in parallel, the algebra module <b>108</b>′ operates at a faster frequency, thus allowing the output signal <b>136</b> to be a higher frequency. In other embodiments, more or less than four channels are required depending on the required performance.

The algebra module <b>108</b>′ receives the reference clock <b>128</b> and the RISE clock <b>540</b>. The RISE clock <b>540</b> is received from the phase combining module <b>1225</b> (<figref idref="DRAWINGS">FIG. 12</figref>) of the output module <b>114</b>. The RISE clock <b>540</b> is half the frequency of the output signal <b>136</b> and has edges corresponding to the rising edges of the output signal <b>136</b>. The algebra module <b>108</b>′ uses the RISE clock <b>540</b> as the clock for performing calculations and storing data in registers. The algebra module <b>108</b>′ also receives an algebra data input signal <b>132</b>. The algebra data input signal <b>132</b> includes a data word <b>132</b>a that represents a multiplier of the period of the reference clock input signal <b>128</b>, the product of which defines the desired period of the output signal <b>136</b>.

In one embodiment, the data word <b>132</b>a is a 27 bit word, where the first 6 bits represent the integer of the multiplier and the other 21 bits represent the fraction of the multiplier. Using 27 bits allows the user to define the frequency of output signal <b>136</b> to better than 1 ppm precision. For example, for an output signal <b>136</b> that is half the period of the reference clock input <b>128</b> (i.e., twice the frequency), the data word <b>132</b>a is 000000.100000000000000000000. For an output signal <b>136</b> that is one-quarter the period of the reference clock input <b>128</b> (i.e., four times the frequency), the data word <b>132</b>a is 000000.010000000000000000000. In another example, an output signal <b>136</b> that is 2.25 times the period of the reference clock input <b>128</b> (i.e., 0.444444 . . . times the frequency), the data word <b>132</b>a is 000010.010000000000000000000.

The multiplier data word <b>132</b>a is used by the period integrator module <b>500</b> to determine when the next rising edge occurs relative to the reference clock signal <b>128</b>. <figref idref="DRAWINGS">FIG. 6</figref> depicts the period integrator module <b>500</b> in more detail. The multiplier data word <b>132</b>a is input into two components, the times n module <b>600</b> and the adder <b>632</b>′. The multiplier data word <b>132</b>a is used by these components <b>600</b>, <b>632</b>′ to calculate the desired transition for the first rising edge, phase <b>0</b>, and the second rising edge, phase <b>2</b>, respectively, in terms of the reference clock signal <b>128</b>. The times n module <b>600</b> multiplies the multiplier data word <b>132</b>a by a constant in one embodiment, hardwired in the IC. The constant is different for different conditions, as described below. The constants used are determined by design requirements.

In an illustrative example, the chosen constants are two (for normal conditions), six (for catch-up mode) and eleven (for synchronization mode). Under normal conditions, the times n module <b>600</b> multiplies the multiplier data word <b>132</b>a by two because the phase <b>0</b> calculation calculates every other rising edge. “Catch-up”, as described below, is a mode where the algebra module <b>108</b>′ has somehow miscalculated and requests a needed edge that has already occurred. As a result, the catch-up module <b>1205</b> (<figref idref="DRAWINGS">FIG. 12</figref>) causes the RISE clock <b>540</b> to operate much faster until the algebra module <b>108</b>′ can catch-up and request a needed edge that occurs in the future. Thus, a constant greater than the two used under normal conditions is needed to allow for the time to catch-up. For the synchronization mode, there is a latency period occurring after the synchronization signal and before the algebra module <b>108</b>′ places a transition edge. This latency period represents the time the synchronization module <b>304</b> needs to calculate when the transition edge can be placed to yield a “seamless” synchronization. The constant must be precisely and accurately determined to accommodate this latency period.

Under normal conditions or catch-up mode, the output of the times n module <b>600</b> is sent to the adder <b>628</b>. The output is the multiplier data word <b>132</b>a multiplied by the constant for the correct mode, either normal conditions or catch-up mode. The correct mode is determined by the input signal <b>604</b>, received from the catch-up module <b>1205</b>, which indicates whether the arbitrary waveform generator <b>100</b>′ is in catch-up mode or not. For synchronization mode, the output, which is the result of the multiplier data word <b>132</b>a times the constant for the synchronization mode, is sent to the adder <b>624</b>.

The output of the times n module <b>600</b> is added in adder <b>628</b> to the current value stored in register <b>616</b>. The current value stored in register <b>616</b> represents the current phase <b>0</b> edge. Under normal conditions, the output of the adder <b>628</b> is the current phase <b>0</b> edge plus two times the desired period in terms of the reference clock signal <b>128</b>. This represents the next phase <b>0</b> edge, which propagates through the mux <b>608</b> and is clocked into the register <b>616</b> at the next RISE clock signal <b>540</b>. Mux <b>608</b> selects from adder <b>624</b> or adder <b>628</b> based on the switchover signal <b>596</b> received from the synchronization module <b>304</b>. Under normal conditions, the output of adder <b>628</b> is selected. This loop (e.g., adding contents of register <b>616</b> to output of times n module <b>600</b> and storing on next RISE clock <b>540</b>) is repeated to determine the next odd rising edge transition.

The phase <b>2</b> signal determination (and corresponding circuitry) is slightly different. Register <b>616</b> contains the current phase <b>0</b> edge. To calculate the next (e.g., second) rising edge, the output of register <b>616</b> (i.e., the first rising edge) is sent to adder <b>632</b>′ and added with the desired period, in terms of the reference clock <b>128</b> (i.e., the multiplier data word <b>132</b>a). The output of adder <b>632</b>′ represents the value of the second (e.g., even) rising edge. The output of adder <b>632</b>′ is clocked into register <b>620</b>′ on the next inverted clock pulse RISEb <b>540</b>′. The inverted clock RISEb <b>540</b>′ is used to meet stringent timing requirements in the phase <b>2</b> channel for generating edges 180 degrees out of phase with phase <b>0</b>. The multiplier data word <b>132</b>a can be changed at each (e.g., first and/or second and/or third, etc.) rising edge calculation. Thus the period can vary with each rising edge, producing an arbitrary waveform.

Referring back to <figref idref="DRAWINGS">FIG. 5</figref>, the output of the period integrator module <b>500</b> is sent to an adder <b>572</b>. As stated above, the output of the period integrator module <b>500</b> represents the time, in terms of the reference clock <b>128</b>, when the next odd transition edge is needed. Another input to the adder <b>572</b> is the current clock time <b>508</b>. The current clock time <b>508</b> received from the clock domain transfer module <b>212</b> is subtracted from next odd transition edge time to determine the number and fraction of clock pulses <b>128</b> remaining before the placement of the next odd transition edge. As indicated in <figref idref="DRAWINGS">FIG. 6</figref>, the output of the period integrator module <b>500</b> for the next even transition edge is sent to an identical adder <b>572</b>′ (not shown). The circuitry shown in <figref idref="DRAWINGS">FIG. 5</figref> for calculating the next odd transition edge is nearly identical for calculating the next even transition edge. One difference is that all of the registers <b>512</b>′, <b>516</b>′, <b>520</b>′, <b>524</b>′, <b>528</b>′, <b>532</b>′, <b>536</b>′ are clocked by the RISEb clock pulse <b>540</b>′.

The user can shift the phase of the desired edge. This is done by a second data word <b>132</b>b, which is part of the algebra data input signal <b>132</b>. In one embodiment, the second data word <b>132</b>b is a 21 bit signed word, where the first 8 bits represent integer reference clock periods and the other 13 bits represent fractional reference clock periods. The phase of the output signal can be shifted forward (e.g., if positive) or backward (e.g., if negative) by up to one hundred and twenty eight reference clock periods. If in synchronization mode, the phase shift is with respect to the last synchronization input <b>300</b>.

If a phase shift input is requested using the second data word <b>132</b>b, then the phase shift is stored in register <b>532</b> and added to adder <b>572</b>. The output of adder <b>572</b> is the location of the next edge beyond the present muster clock signal <b>508</b>, in units of periods of the reference clock <b>128</b>. The output of adder <b>572</b> is clocked into register <b>520</b> at each RISE clock pulse <b>540</b>. Since this value is in terms of the reference clock <b>128</b>, it must be converted to units of laps and taps of the loop <b>104</b>′ by multiplier <b>576</b>. Multiplier <b>576</b> multiplies the output of register <b>520</b> (i.e., the delta edge placement in terms of reference clock <b>128</b>) by the output of register <b>512</b>, which is the current average loop speed (i.e., taps per reference clock pulse <b>128</b>). The result is the time of the next edge from the present muster clock signal <b>508</b> in terms of laps and taps of the loop <b>104</b>′. The result (i.e., the output of the multiplier <b>576</b>) is clocked into register <b>524</b> at a RISE clock pulse <b>540</b>.

In one embodiment, the multiplier <b>576</b> is a seventeen bit by seventeen bit flash multiplier. Since the output of the adder <b>572</b> is, in one embodiment, 21 bits, a barrel shifter (not shown) is used in series between the adder <b>572</b> and the register <b>520</b>. The barrel shifter shifts up to 4 leading (e.g., MSBs) zeros from the output of the adder <b>572</b>, the actual number of shifted zeros depending on relative loop speed, to reduce the binary representation to seventeen bits.

The output of the register <b>524</b>, which represents the desired edge time by a number of laps and taps, is sent to adder <b>580</b>a and added to the current state of the loop <b>104</b>′ to determine the absolute position of the next edge placement. In one embodiment, the sum can be further phase shifted by adding the value stored in register <b>536</b>. The value stored in register <b>536</b> is received as a third data word <b>132</b>c, part of the algebra data input signal <b>132</b>. Because the phase shifting is in terms of taps instead of the reference clock signal <b>128</b>, propagation delays in the system can be accurately cancelled using the third data word <b>132</b>c input.

The output of adder <b>580</b> is sent to adder <b>584</b> for the addition of a constant <b>550</b>. The constant <b>550</b> is determined by implementation choices. For example, it can be determined by chip layout, chosen to allow maximum setup/hold margins at the edge flip-flops <b>1215</b>,<b>1220</b>. The constant <b>550</b> is based on known propagation delays (e.g., in tap units) to center the selected tap transitions in their windows. Constant <b>550</b> only affects selection of the lap and does not affect the selection of the tap. The output of the adder <b>584</b> is clocked into the register <b>528</b> on the RISE clock pulse <b>540</b>. The value <b>560</b> stored in register <b>528</b> is the value <b>560</b> of the lap and tap that is used to select the next edge transition. The register value <b>560</b> is sent to the switching module <b>112</b>, the fine delay module <b>310</b> and the output module <b>114</b> to select the correct edge transition for the next even rising edge (phase <b>0</b> signal) transition in the output signal <b>136</b>.

The phase <b>2</b> signal circuitry similarly has a register <b>528</b>′ to store the value of the next odd rising edge transition. In one embodiment, the circuitry to create the corresponding even and odd falling edges (phase <b>1</b> signal and phase <b>3</b> signal), consists of an adder (not shown) which adds the contents of register <b>528</b> and <b>528</b>′. The algebra module <b>108</b>′ divides the output of the adder by two to obtain a value corresponding to a time half way between two rising edges. Separate adders create the even and odd falling edges. In another embodiment, a fourth data word <b>132</b>d (not shown) can be used with similar circuitry as depicted in <figref idref="DRAWINGS">FIG. 5</figref> to place a falling edge anywhere between the even and odd rising edges based on the fourth data word <b>132</b>d.

In calculating the placement of the transition edges, the algebra module <b>108</b>′ uses the loop averaging module <b>212</b> and the clock domain transfer module <b>504</b>. <figref idref="DRAWINGS">FIG. 7</figref> depicts the loop averaging module <b>212</b> in more detail. The loop averaging module <b>212</b> receives the reference clock signal <b>128</b> to clock information into its registers <b>700</b>, <b>712</b>, <b>734</b>, <b>750</b>. The loop averaging module <b>212</b> also receives stored state information <b>220</b> from the state capture module <b>204</b>′. As stated above, the stored state information <b>220</b> contains the state of the lap counter <b>200</b> and the last tap that the transition propagated through at the time of the capture on the reference clock <b>128</b> transition. The loop averaging module calculates the average speed of the loop in units of taps per reference clock <b>128</b>. The loop averaging module <b>212</b> also calculates the averaged position of the loop at the latest reference clock pulse <b>128</b>, or in other words, the instantaneous phase of the loop at the latest reference clock pulse <b>128</b>.

The average loop speed portion of the loop averaging module <b>212</b> receives the current stored stated information <b>220</b> at the positive input of a subtraction element <b>704</b>. Register <b>700</b> stores the value of the stored stated information <b>220</b> at the previous reference clock pulse <b>128</b>. The subtraction element <b>704</b> receives the value stored in register <b>700</b> at the negative input. The output of the subtraction element <b>704</b> represents the difference and is the number of taps the transition has propagated through during one reference clock <b>128</b> period. This value is stored in register <b>712</b>. In one embodiment, arithmetic elements <b>716</b>, <b>720</b> and <b>724</b> are used to average the loop speed value stored in register <b>712</b> over sixty-four loop speed values (e.g., decay time constant=64) to obtain an average loop speed. Averaging over sixty-four clock pulses is a design choice to provide loop speed accuracy consistent with overall accuracy of the synthesizer. In other embodiments, the number of reference clock pulses <b>128</b> used for averaging is different.

The average speed is stored in register <b>734</b> and provided to the clock domain transfer module <b>504</b> and the synchronization module <b>304</b>. In one embodiment, mux <b>730</b> is used to switch in the most recent loop speed into register <b>734</b> if the current loop speed varies from the average loop speed by more than eight taps per reference clock pulse <b>128</b>. This allows a sudden change in loop speed to reset the average and minimizes large transients that can occur during start-up. The variance of greater than eight taps is a design choice that can be changed to meet design goals.

In another embodiment not shown, the average loop speed <b>564</b> is further adjusted to compensate for variance in the power supply supplying power to the ring oscillator <b>104</b>. This variance is due to noise at frequencies that are not filtered out by other circuits. An amplifying circuit (not shown) scales the voltage level of the variance to a usable level for the compensating circuit. The compensating circuit (not shown) measures the amplified variance in the power supply voltage (e.g., the noise) and digitizes this variance (e.g., sends the noise signal through an A/D converter). The compensating circuit sends the digital variance signal to the loop averaging module <b>212</b> to adjust the calculated average loop speed <b>564</b>. The variance is a linear dependence (i.e., an increase in voltage increases the loop speed) and so the calculated average loop speed <b>564</b> is adjusted accordingly. The digital variance signal can be scaled as needed, using any of the techniques know in the art. Using more bits in the digital variance signal increases the precision of the compensation. In another embodiment, the compensating circuit sends the digital variance signal to the algebra module <b>108</b> to compensate for the power supply variance.

The averaged position (i.e., instantaneous phase) portion of the loop averaging module <b>212</b> tracks the calculated loop position in fractions of a tap and averages the position over time. A calculated average position is used for increased precision. The averaged loop position portion of the loop averaging module <b>212</b> receives, at the positive input of a subtraction element <b>738</b>, the current stored stated information <b>220</b>. The subtraction element <b>738</b> receives, at the negative input, the calculated averaged loop position, which is the output of the stored contents in register <b>750</b>, the previous calculated averaged loop position added at adder <b>758</b> to the average loop speed stored in register <b>734</b>. The difference, the output of the subtraction element <b>738</b>, is the difference between the actual loop position and the calculated averaged loop position. In one embodiment, arithmetic elements <b>742</b> and <b>746</b> are used to average the difference over thirty-two values to obtain an average difference for the past thirty two reference clock pulses <b>128</b>. A value other than thirty-two can be used. The calculated averaged loop position is stored in register <b>750</b>.

In one embodiment, mux <b>754</b> is also used to switch in the previous loop position, stored in register <b>700</b>, if the most current calculated averaged loop position difference from the actual loop position is greater man eight taps. This allows a sudden change in loop phase to reset the average and minimizes large transients that can occur during start-up. The variance of greater than eight taps is a design choice that can be changed to meet design goals. Depending on the state of mux <b>754</b>, either the output of register <b>750</b> or the output of register <b>700</b> is added in adder <b>758</b> to the average loop speed <b>564</b> to create the calculated averaged loop position <b>568</b>. The calculated averaged loop position <b>568</b> is sent to the clock domain transfer module <b>504</b> and the synchronization module <b>304</b>. The average loop speed signal <b>564</b> and clean_cnt_at_clk signal <b>568</b> carry extra bits of precision than their respective time-constants would justify. This is done to avoid accumulating a DC bias from systematic rounding errors.

The clock domain transfer module <b>504</b> is shown in more detail in FIG. <b>8</b>. The clock domain transfer module <b>504</b> receives the average loop speed <b>564</b> and the calculated averaged loop position <b>568</b> from the loop averaging module <b>212</b>, which is clocked in the reference clock <b>128</b> domain. The clock domain transfer module <b>504</b> transfers the signals in the reference clock <b>128</b> domain to signals in the RISE clock <b>540</b> domain. The clock domain transfer module <b>504</b> provides stable values to the registers <b>512</b>, <b>516</b> (<figref idref="DRAWINGS">FIG. 5</figref>) of the algebra module <b>108</b>′, which are clocked in the RISE clock <b>540</b> domain. The clock domain transfer module <b>504</b> also provides the current clock time <b>508</b>, which starts as a counter <b>640</b> in the reference clock <b>128</b> domain and is sent to adder <b>572</b>, which operates in the RISE clock <b>540</b> domain. In the embodiment shown, the counter <b>640</b> is an eight bit counter and rolls over to zero upon reaching its maximum value. The circuit shown simultaneously corrects these signals to the RISEb (e.g., the phase <b>2</b> circuitry).

From the reference clock signal <b>128</b>, a half_clk signal <b>643</b> is created. Dividing the frequency of the reference clock signal <b>128</b> by two creates the half_clk signal <b>643</b>. The first layer of registers <b>644</b>, <b>648</b>, <b>676</b>, <b>680</b>, <b>690</b>, <b>692</b> are clocked with the reference clock signal <b>128</b>. The first layer of registers <b>644</b>, <b>648</b>, <b>676</b>, <b>680</b>, <b>690</b>, <b>692</b> are used to ensure that the signals <b>508</b>, <b>564</b>, <b>568</b> are captured correctly in the reference clock <b>128</b> domain. The circuits (i.e., propagation path) for each signal <b>508</b>, <b>564</b>, <b>568</b> include a pair of first layer registers <b>644</b> and <b>648</b>, <b>676</b> and <b>680</b>, <b>690</b> and <b>692</b>, respectively. One register of each pair <b>644</b>, <b>676</b>, <b>690</b> is enabled when the half_clk signal <b>643</b> is in a positive state. The other register of the pair <b>648</b>, <b>680</b>, <b>692</b> is enabled when the half_clk signal <b>643</b> is in a negative state. For the calculation of the phase <b>0</b> transition edge, registers <b>652</b>, <b>682</b>, <b>694</b> of the second layer of registers are used. Using the pairs of first layer registers <b>644</b> and <b>648</b>, <b>676</b> and <b>680</b>, <b>690</b> and <b>692</b>, ensures that at least one register of the pair is stable when clocking into the registers <b>652</b>, <b>682</b>, <b>694</b> in the RISE clock <b>540</b> domain. Stability is assured even if a the reference clock signal <b>128</b> transitions during a clocking of the RISE clock <b>540</b> domain registers <b>652</b>, <b>682</b>, <b>694</b>. Each mux <b>660</b>, <b>686</b>, <b>698</b> determines which of the pair of first layer registers <b>644</b> and <b>648</b>, <b>676</b>, and <b>680</b>, <b>690</b> and <b>692</b>, is used as outputs of the clock domain transfer module <b>504</b>. The one used is stable. The mux channel selection is made by the state of the half_clk <b>643</b> stored in register <b>641</b>. This register stores the state of the half_clk signal <b>643</b> at some delayed time after the RISE clock <b>540</b> clocks data into the RISE clock <b>540</b> domain registers <b>652</b>, <b>682</b>, <b>694</b>. Whenever half-clk is transitioning when it is captured, the outputs of registers <b>641</b> and <b>642</b>′ are unpredictable. However, all first tier registers are stable at this time so that the one selected doesn't matter, as long as the same one is selected for master_clk signal <b>508</b> and clean_cnt_at_clk signal <b>568</b>. The delays shown are necessary to guarantee this property.

For the calculation of the phase <b>2</b> (e.g., even transition edge) similar circuitry is used (i.e., registers <b>656</b>′, <b>684</b>′, <b>696</b>′, <b>642</b>′ and muxes <b>664</b>′, <b>688</b>′, <b>699</b>′). One difference is that all of the registers <b>656</b>′, <b>684</b>′, <b>696</b>′, <b>642</b>′ are clocked using the RISEb signal <b>540</b>′. In the embodiment shown, the average loop speed signal <b>564</b> received from the loop averaging module <b>212</b> is twenty one bits. A barrel shifter <b>668</b> and auto range element <b>672</b> are used to shift out up to four leading bits and convert the signal to seventeen bits.

If a synchronization signal is used to determine the phase of the output signal <b>136</b> (i.e., synchronization mode), the synchronization module <b>304</b> is involved in calculating the time of the next edge transition. <figref idref="DRAWINGS">FIG. 9A</figref> depicts the synchronization module <b>304</b> in more detail. The synchronization module <b>304</b> receives a synchronization input <b>300</b>, the average loop speed <b>564</b> and calculated average position <b>568</b> from the loop averaging module <b>212</b>. The synchronization module <b>304</b> receives the stored state information <b>330</b> from the state capture module <b>204</b>′. The stored state information <b>330</b> contains the state of the lap counter <b>200</b> and the last transitioned tap at the time of the capture on the synchronization input <b>300</b> transition. The synchronization module <b>304</b> outputs a start_integrate signal <b>592</b>, which represents the time when a seamless edge transition can be placed. The edge transition is seamless because the synchronization module <b>304</b> determines an exact half-cycle when the newly phased output can replace the old with a minimum “glitch”. The synchronization module <b>304</b> selects this transition edge as the point to switchover to output signal <b>136</b> to one in phase with the synchronization input <b>300</b>. The synchronization module <b>304</b> generates a switchover signal <b>596</b> to indicate to the period integrator module <b>500</b> that the needed edge transition has been calculated by the synchronization module <b>304</b> and should be substituted into the period integrator Module <b>500</b>.

To calculate the seamless edge transition placement, the synchronization module <b>304</b> subtracts the calculated average position <b>568</b> at the time of the preceding reference clock <b>128</b> pulse from the stored state information <b>330</b> using the subtraction element <b>820</b>. The output of the subtraction element <b>820</b> represents the phase shift between the reference clock <b>128</b> and the synchronization input signal <b>300</b>, in units of taps. Three registers <b>808</b>, <b>812</b>, <b>816</b> are used to retain the calculated average position <b>568</b> of the loop <b>104</b>′ at the time of the preceding reference clock <b>128</b> pulse for two additional reference clock <b>128</b> pulses, the time it takes the sync debouncer module <b>800</b> to debounce the synchronization signal <b>300</b>.

The sync debouncer module <b>800</b> is shown in more detail in FIG. <b>9</b>B. The XOR element <b>904</b> is an optional element that allows the user to set the polarity of the synchronization input signal <b>300</b>. The syncpol input is set to the active transition of the synchronization input signal <b>300</b>. In the embodiment shown, the debouncing circuitry is set up for an active rising synchronization input signal <b>300</b>. The XOR element <b>904</b> ensures that the output of the XOR element <b>904</b> is an active rising signal, regardless of the polarity of the synchronization input signal <b>300</b> used. The AND element <b>908</b> allows the user to enable and disable synchronization mode. If sync_enable is disabled (e.g., low state), no synchronization pulse is propagated through the sync debouncer module <b>800</b>.

The sync debouncer module <b>800</b> outputs a sync_buff signal <b>950</b>. The synch_buff signal <b>950</b> is used to clock register <b>832</b> (FIG. <b>9</b>A), which captures the output of the period integrator module <b>500</b>, representing the next two desired transition edges, phase <b>0</b> and phase <b>2</b>, at the time of the synchronization pulse <b>300</b>. Sync-buff provides the snyc input to the state capture module <b>204</b>′. The logic element <b>936</b> makes the sync_buff signal last only from the time the synchronization input <b>300</b> transitions until the first D input to flip flop <b>912</b> changes state. Delay <b>944</b> is added to ensure that the sync input to module <b>204</b>′ precedes the edge at the D flip flop <b>912</b>. The time frame for the sync_buff signal <b>950</b> is narrow to allow the SYNC signals arbitrarily near a ref-clk <b>128</b> edge without error. Once register <b>832</b> has stored the information and the first D flip flop has changed state, the next D flip flop <b>916</b> changes state at the subsequent reference clock <b>128</b> pulse. The AND element <b>924</b> only switches to a high state if the synchronization pulse (i.e., the output of AND element <b>908</b>) is high, the first D flip flop <b>912</b> has changed to a high state and the second and third D flip flops <b>916</b>, <b>920</b> are in a low state. If the output of the AND element <b>924</b> is high at the subsequent reference clock <b>128</b> pulse, the output of the second D flip flop <b>915</b> changes to a high state. This creates a stable (i.e., debounced) synchronization signal <b>900</b> (“SYNCsync”). Any SYNC signal lasting less than two reference clock <b>128</b> pulses will not be seen. The SYNCsync signal <b>900</b> lasts for one period of the reference clock <b>128</b>. NAND elements <b>928</b>, <b>932</b> and the third D flip flop <b>920</b> ensure that at the next clock pulse subsequent to the SYNCsync signal <b>900</b>, the second D flip flop <b>916</b> changes state again. When the second D flip flop <b>916</b> changes state again, the SYNCsync signal <b>900</b> ends.

Referring back to <figref idref="DRAWINGS">FIG. 9A</figref>, the SYNCsync signal <b>900</b> is used to enable register <b>824</b>. Register <b>824</b> stores the output of the subtraction element <b>820</b> at the next reference clock <b>128</b> pulse subsequent to the SYNCsync signal <b>900</b>. The SYNCsync signal <b>900</b> is also used to enable register <b>850</b>, which stores the average loop speed <b>564</b> at the next reference clock <b>128</b> pulse subsequent to the SYNCsync signal <b>900</b>. The ripple divider <b>804</b> divides the stored phase shift information in register <b>824</b>, which is in units of taps, by the average loop speed stored in register <b>850</b>, which is in units of taps per reference clock <b>128</b>. The result represents the difference between the reference clock <b>128</b> and the synchronization input <b>300</b>, now in units of the reference clock <b>128</b>.

The result is sent to a positive input on the summer <b>840</b>. The current clock time <b>508</b>, which is stored in register <b>828</b> is also sent to a positive input of the summer <b>840</b>. A constant three is sent to a negative input of the summer <b>840</b>. This constant represents the latency of three reference clock <b>128</b> pulses for the sync debouncer module <b>800</b> and is thus subtracted. The current (i.e., at time of switchover) phase <b>0</b> edge placement is sent to a positive input of the summer <b>840</b>. Either the phase <b>0</b> edge placement or the phase <b>2</b> edge placement captured in register <b>832</b> is sent to a negative input of the summer <b>840</b>. Mux <b>836</b> selects the signal to be used, based on the state of the FALLb signal at some time period, equal to the delay <b>854</b>. This is asynchronous transfer of data between clock domains, prior to the sync_buff signal <b>950</b>. The selected signal represents the calculated transition edge at the time of the synchronization pulse <b>300</b>. This is subtracted from the current (i.e., at time of switchover) phase <b>0</b> edge transition to compensate for the latency of the synchronization module <b>304</b>. The output <b>592</b> of the summer <b>840</b> is sent to register <b>612</b> (<figref idref="DRAWINGS">FIG. 6</figref>) of the period integrator module <b>500</b> (FIG. <b>6</b>). The output <b>592</b> represents the first seamless edge transition for an output signal <b>136</b> in phase with the synchronization input <b>300</b>, in terms of the reference clock <b>128</b>.

The D flip flops <b>850</b>, <b>854</b>, <b>858</b> are used as a delay to ensure that the ripple divider <b>804</b> has settled before switchover occurs. The D flip flops <b>862</b>, <b>866</b> are used to align the switchover signal with the RISE clock <b>540</b>, which is the clock that the registers in the period integrator module <b>500</b> use. D flip flop <b>866</b> and AND element <b>858</b> ensure that the switchover signal lasts for only one period of the RISE clock <b>540</b>. The switchover signal <b>596</b> is used by the mux <b>608</b> (FIG. <b>6</b>). When active, the mux <b>608</b> selects the output of adder <b>624</b>, which includes the calculated edge transition from the synchronization module <b>304</b>. At the next RISE clock <b>540</b> pulse, the calculated edge transition is clocked into register <b>616</b> (<figref idref="DRAWINGS">FIG. 6</figref>) and the switchover signal becomes NOT active. The mux <b>608</b> then selects from the output of the adder <b>628</b>, which as described above continues to add desired period lengths to the previous transition edge. As described above referring to <figref idref="DRAWINGS">FIG. 5</figref>, the first seamless edge transition for an output signal <b>136</b> in phase with the synchronization input <b>300</b>, in terms of the reference clock <b>128</b>, is output from the period integrator module <b>500</b>. It propagates through adder <b>572</b> and multiplier <b>576</b> where it is converted from reference clock <b>128</b> periods to number of taps. The edge transition calculation then proceeds through adder <b>580</b> and adder <b>584</b>, where it is stored in register <b>528</b> on a RISE clock <b>540</b> pulse. The output <b>560</b> of register <b>528</b>, which represents the edge transition placement in terms of taps and laps, is sent to the switching module <b>112</b>. Switching module <b>112</b> uses this information to select the desired tap of loop <b>104</b>′ to create the next edge transition.

<figref idref="DRAWINGS">FIGS. 10A and 10B</figref> depict the switching module <b>112</b> in more detail. <figref idref="DRAWINGS">FIG. 10A</figref> depicts the configuration of muxes <b>1000</b>, <b>1003</b>, <b>1010</b> used for selecting an edge for the phase <b>0</b> signal. In one embodiment, a sixteen-to-one tap selection module <b>1003</b> is used to select a transition edge from one of sixteen taps of the loop <b>104</b>′. The tap selection module <b>1003</b> is made up of five balanced mux modules <b>1000</b>.

<figref idref="DRAWINGS">FIG. 10B</figref> depicts a balanced mux module <b>1000</b> in more detail. The balanced mux module <b>1000</b> is a four-to-one mux. The balanced mux module <b>1000</b> includes NAND elements <b>1015</b>, <b>1020</b>, <b>1025</b>, <b>10301035</b> and capacitive delay elements <b>1040</b>, <b>1045</b>, <b>1050</b>, <b>1055</b>. In one embodiment, the capacitive delay elements <b>1040</b>, <b>1045</b>, <b>1050</b>, <b>1055</b> are implemented using IC library cells designed for the purpose of creating capacitors in an IC, as is know in the art. The capacitance of the capacitive delay elements <b>1040</b>, <b>1045</b>, <b>1050</b>, <b>1055</b> causes a delay in the signal transition as the signal propagates along the corresponding path. The balanced mux module <b>1000</b> receives an edge select input, which in one embodiment is a two bit signal that defines which of the four inputs are selected. NAND elements <b>1015</b>, <b>1020</b>, <b>1025</b>, <b>1030</b>, <b>1035</b> are used to select and propagate the requested edge to the output.

The NAND <b>1015</b>, <b>1020</b>, <b>1025</b>, <b>1030</b>, <b>1035</b> elements are the same for each of the balanced mux modules <b>1000</b>a, <b>1000</b>b, <b>1000</b>c, <b>1000</b>d, <b>1000</b>e, <b>1000</b>f, <b>1000</b>g, <b>1000</b>h, <b>1000</b>i, <b>1000</b>j, depicted in FIG. <b>10</b>A. However, the capacitive delay elements <b>1040</b>, <b>1045</b>, <b>1050</b>, <b>1055</b> are different for each of the balanced mux modules <b>1000</b>a, <b>1000</b>b, <b>1000</b>c, <b>1000</b>d, <b>1000</b>e, <b>1000</b>f, <b>1000</b>g, <b>1000</b>h, <b>1000</b>i, <b>1000</b>j, depicted in FIG. <b>10</b>A. This is necessary because the value of the capacitive delay elements <b>1040</b>, <b>1045</b>, <b>1050</b>, <b>1055</b> are based on two factors, the values of which are different for each of the balanced mux modules <b>1000</b>a, <b>1000</b>b, <b>1000</b>c, <b>1000</b>d, <b>1000</b>e, <b>1000</b>f, <b>1000</b>g, <b>1000</b>h, <b>1000</b>i, <b>1000</b>j.

The first factor is whether the transition being propagated a is a positive going (i.e., from a low state to a high state) or negative going (i.e., from a high state to a low state) transition. The two types of transitions propagate through the NAND elements <b>1015</b>, <b>1020</b>, <b>1025</b>, <b>1030</b>, <b>1035</b>, and other elements in their path, at different rates. The value of the capacitive delay elements <b>1040</b>, <b>1045</b>, <b>1050</b>, <b>1055</b> compensates for these two different rates. The second factor is that the paths the edges propagate through from the taps to the switching module <b>112</b> and through the switching module <b>112</b> have different lengths. The value of the capacitive delay elements <b>1040</b>, <b>1045</b>, <b>1050</b>, <b>1055</b> compensates for these different path lengths. The value of the capacitive delay elements <b>1040</b>, <b>1045</b>, <b>1050</b>, <b>1055</b> ensures that the time a transition edge propagates from a tap to the output of the switching module <b>112</b> is equivalent, regardless of the polarity of the signal or the path length the signal has to propagate. The value of the capacitive delay elements <b>1040</b>, <b>1045</b>, <b>1050</b>, <b>1055</b> varies, dependent on the layout of the implementing hardware. These capacitors also correct for any irregularities in the loop of delay elements <b>104</b>.

In another embodiment, each first capacitive delay element <b>1040</b>, <b>1045</b>, <b>1050</b>, <b>1055</b> of the balanced mux module <b>1000</b> has a second corresponding capacitive delay element <b>1040</b>a, <b>1045</b>a, <b>1050</b>a, <b>1055</b>a (not shown). Each of the second corresponding capacitive delay elements <b>1040</b>a, <b>1045</b>a, <b>1050</b>a, <b>1055</b>a is in parallel with its associated first capacitive delay element (i.e., <b>1040</b> in parallel with <b>1040</b>a). The set of first capacitive elements <b>1040</b>, <b>1045</b>, <b>1050</b>, <b>1055</b> react similarly to variations in temperature, process and supply voltage. The set of second corresponding capacitive delay elements <b>1040</b>a, <b>1045</b>a, <b>1050</b>a, <b>1055</b>a do not react similarly to variations in temperature, process and supply voltage. This ensures that variations in propagation delay that are not linear with respect to variations in temperature, process and supply voltage can be compensated for with the set of second corresponding capacitive delay elements <b>1040</b>a, <b>1045</b>a, <b>1050</b>a, <b>1055</b>a. The second set corresponding capacitive delay elements <b>1040</b>a, <b>1045</b>a, <b>1050</b>a, <b>1055</b>a are implemented by a different IC process than was used to implement the set of first capacitive delay elements <b>1040</b>, <b>1045</b>, <b>1050</b>, <b>1055</b>. Any of the several methods known in the art can be utilized.

Referring back to <figref idref="DRAWINGS">FIG. 10A</figref>, a first tap selection module <b>1003</b>a is used and calibrated (i.e., selection of values of capacitive delay elements) to receive a rising (i.e., positive going) transition from the taps of the loop <b>104</b>′. A second tap selection module <b>1003</b>b is used and calibrated (i.e., selection of values of capacitive delay elements <b>1040</b>, <b>1045</b>, <b>1050</b>, <b>1055</b>) to receive a falling (i.e., negative going) transition from the taps of the loop <b>104</b>′. If the tap selected is a falling edge, and thus selected by the second tap selection module <b>1003</b>b, it is inverted with inverter <b>1005</b>. Mux <b>1010</b> selects which tap selection module <b>1003</b>a, <b>10003</b>b is used, based on an input received from the algebra module <b>108</b>′. The phase <b>1</b>, phase <b>2</b> and phase <b>3</b> signals each have a similar configuration of muxes to select corresponding edges. The rising edge out of MUX <b>1010</b> is always the active edge.

<figref idref="DRAWINGS">FIG. 11</figref> depicts the fine delay module <b>310</b> in more detail. The purpose of the fine delay module <b>310</b> is to delay the transition edge by a differential amount of time that is smaller than the time between the taps of the loop <b>104</b>′ (e.g., smaller than the 300 picoseconds depicted in FIG. <b>1</b>B). The fine delay module <b>310</b> increases the precision of the placement of the edge transition in the output signal <b>136</b>. The fine delay module <b>310</b> includes NAND elements <b>1105</b>, <b>1110</b>, <b>1115</b>, <b>1120</b>, <b>1125</b>, <b>1130</b>, <b>1135</b>, <b>1140</b> and capacitive delay elements <b>1150</b>, <b>1155</b>, <b>1160</b>, <b>1165</b>, <b>1170</b>, <b>1175</b>. The fine delay module <b>310</b> receives an edge select input, which in one embodiment is a three bit signal that defines which of the eight possible paths are used. NAND elements <b>1105</b>, <b>1110</b>, <b>1115</b>, <b>1120</b>, <b>1125</b>, <b>1130</b>, <b>1135</b>, <b>1140</b> are used to select and propagate the requested edge to the output, routing the edge through one of eight possible paths. The arbitrary waveform generator <b>100</b>′ includes a fine delay module for each of the channels the algebra module <b>108</b>′ has calculated (e.g., phase <b>0</b>, phase <b>1</b>, phase <b>2</b>, and phase <b>3</b>). The edge of interest is always positive-going entering and leaving the fine delay module <b>105</b>.

As described above, the capacitive delay elements <b>1150</b>, <b>1155</b>, <b>1160</b>, <b>1165</b>, <b>1170</b>, <b>1175</b> can be different for each fine delay module <b>310</b>. However in the preferred embodiment the internal layout of the fine delay modules are all identical, resulting in identical capacitance values. Also as described above, each fine delay module can include a set of corresponding second capacitive delay elements <b>1150</b>a, <b>1155</b>a, <b>1160</b>a, <b>1165</b>a, <b>1170</b>a, <b>1175</b>a. In one embodiment, even the fastest path through the fine delay module <b>108</b> is much greater than the delay time between each tap. However, the difference of the delay times between any two of the eight possible paths is less than the delay time between each tap. The large fixed component of delay added by fine delay module is compensated for by part of the constant <b>550</b> (<figref idref="DRAWINGS">FIG. 5</figref>) used by the algebra module <b>108</b>′ and (optionally) by part of the phase compensation input <b>132</b>c in the algebra module <b>108</b>′. The output of the fine delay module <b>310</b> is sent to the output module <b>114</b>.

The output module <b>114</b> is depicted in more detail in FIG. <b>12</b>. The output module includes a pair of edge flip flops <b>1215</b>, <b>1220</b> and a windowing module <b>1210</b>. These three components <b>1215</b>, <b>1220</b>, <b>1210</b> are included for each channel (e.g., phase <b>0</b>, phase <b>1</b>, phase <b>2</b>, and phase <b>3</b>). The output module <b>114</b> also includes a phase, or channel, combining module <b>1225</b>. The outputs of the pair of edge flip flops <b>1215</b>, <b>1220</b> for each channel (e.g., phase <b>0</b>, phase <b>1</b>, phase <b>2</b>, and phase <b>3</b>) are sent to the phase or channel, combining module <b>1225</b>. The phase, or channel, combining module <b>1225</b> combines all of the channel signals (e.g., phase <b>0</b>, phase <b>1</b>, phase <b>2</b>, phase <b>3</b>) into a single output <b>136</b>. If multiple outputs are required, various combinations of channels are combined by respective channel-combining modules <b>1225</b> for each output. The output module <b>114</b> also includes a catch-up module. In one embodiment, the catch-up module only involves the rising edge channels (e.g., phase <b>0</b>, phase <b>2</b>).

The catch-up module <b>1205</b>, the windowing module <b>1210</b> and the pair of edge flip flops <b>1215</b>, <b>1220</b> are depicted in more detail in FIG. <b>13</b>. The phase <b>0</b> edge received from the fine delay module <b>310</b> is used as the clock for both edge JK flip flops <b>1215</b>, <b>1220</b>. The JK inputs of the pair of edge flip flops <b>1215</b>, <b>1220</b> are received from the windowing module <b>1210</b>. In one embodiment, the windowing module <b>1210</b> has two comparators <b>1336</b>, <b>1360</b>. A first comparator <b>1336</b> compares the lap calculated by the algebra module <b>108</b>′ with the in-phase lap counter <b>200</b>a. A second comparator <b>1360</b> compares the lap calculated by the algebra module <b>108</b>′ with the out-of-phase lap counter <b>200</b>b. When the lap calculated by the algebra module <b>108</b>′ is equal to the lap counter <b>200</b>, the window is open. The pair of edge flip flops are set to clock the edge transition input from the fine delay module <b>310</b> by AND element <b>1376</b> or <b>1382</b>. Either window-opening flip flop <b>1340</b> or flip flop <b>1372</b> is used, selected by mux <b>1344</b> based on a single bit calculated in the algebra. A XOR element <b>1348</b>, a flip flop <b>1352</b>, and a NAND element <b>1356</b> are used to reset and close the window after the desired edge transition has successfully clocked the pair of edge flip flops <b>1215</b>, <b>1220</b>. A flip flop <b>1368</b> and an AND element <b>1364</b> are used to create a substitute window when so instructed by algebra signal ph<b>0</b>_win_open. The substitute window is used to allow the waveform synthesizer to operate at high frequencies, for instance at frequencies higher than the free-loop-itself. In that situation, the desired loop is already in progress and it is too late to use the mechanism involving comparators <b>1350</b>, <b>1336</b>. Instead, the substitute window “opens” immediately, save for delays, to allow relevant data to be valid.

The first comparator <b>1336</b> also determines whether the lap calculated by the algebra module <b>108</b>′ is less than the current value of the lap counter <b>200</b>a plus a margin for latency. If it is less, then the algebra module <b>108</b>′ has transmitted an erroneous calculation and the first comparator sends a signal to the catch-up module <b>1205</b>. The catch-up module <b>1205</b> is activated when the algebra module <b>108</b> requests a lap that has occurred in the past (i.e., the lap requested is less than the present lap). The output of the comparator <b>1336</b>, indicating that a past lap is requested, is sent to the flip flop <b>1308</b> of the catch-up module <b>1205</b>. At the next period of the loop <b>104</b>′, that error signal is clocked into flip flop <b>1308</b>. The output of the flip flop <b>1308</b>, labeled ph<b>0</b>_catch is sent to an OR element <b>1312</b>. The phase <b>2</b> signal has a similar catch-up module <b>1205</b>′ (not shown). One difference is that the flip flop element <b>1309</b> and the OR element <b>1310</b> are not included with the phase <b>2</b> catch-up module <b>1205</b>′. Phase <b>1</b> and phase <b>3</b> signals do not have catch-up modules <b>1205</b>. The output of flip flop <b>1308</b>′ (not shown) of the phase <b>2</b> catch-up module <b>1205</b>′ is also input to the OR element <b>1312</b> and input to the flip flop <b>1309</b>. On the RISEb clock <b>540</b>′ pulse subsequent to the change of the output of flip flop <b>1308</b>′, the flip flop <b>1309</b> outputs an active catch-up signal to the OR element <b>1310</b>. The OR element <b>1310</b> outputs an active catch-up signal <b>604</b> to the times n module <b>600</b> of the period integrator module <b>500</b>. As described above, the times n module <b>600</b> uses this signal <b>604</b> to determine whether the arbitrary waveform generator is in catch-up mode and applies the correct multiplier. When in catch-up mode, NAND elements <b>1316</b>, <b>1320</b>, <b>1324</b>, <b>1328</b> and AND element <b>1332</b> are used to create RISE clock <b>540</b> pulses at one-fourth the speed of the free-loop <b>104</b>′, using the set and reset inputs of the pair of edge flip flops <b>1215</b>, <b>1220</b>. As described above, catch-up mode creates a substitute fast clock for algebra module <b>108</b>′ and increases the programmed period until the lap requested is once again in the future. At that time, the catch-up module <b>1205</b> terminates catch-up mode (e.g., changes the catch-up signal <b>604</b> to the NOT active state). When the circuit recovers, it recovers in the correct phase.

Referring to <figref idref="DRAWINGS">FIG. 14</figref>, the phase, or channel, combining module <b>1225</b> of the output module <b>114</b> includes three balanced XOR modules <b>1500</b>a, <b>1500</b>b, <b>1500</b>c and four inverting driver elements <b>1405</b>, <b>1410</b>, <b>1415</b>, <b>1420</b>. The outputs of the first two balanced XOR modules <b>1500</b>a, <b>1500</b>b are sent from the output module <b>114</b> to the algebra module <b>108</b>′ and are used by the algebra module <b>108</b>′ as the clock for calculations, as described above. The outputs are also sent to the third balanced XOR module <b>1500</b>c to create the output signal <b>136</b>. The first balanced XOR module <b>1500</b>a receives the rising edge channel signals (i.e., phase <b>0</b>, phase <b>2</b>). The next balanced XOR module <b>1500</b>b receives the falling edge channel signals (i.e., phase <b>1</b>, phase <b>3</b>). The phase combining module <b>1225</b> is used to combine each of the signals (i.e., phase <b>0</b>, phase <b>1</b>, phase <b>2</b>, and phase <b>3</b>). The phase combining module <b>1225</b> combines in a balanced way so that the propagation delay time from the output of the pair of edge flip flops <b>1215</b>, <b>1220</b> to the output signal <b>136</b> is nearly the same regardless of the signal (i.e., phase <b>0</b>, phase <b>1</b>, phase <b>2</b>, phase <b>3</b>) or signal polarities.

<figref idref="DRAWINGS">FIG. 15</figref> depicts a balanced XOR module <b>1500</b> in more detail. The balanced XOR module <b>1500</b> includes six NAND elements <b>1505</b>, <b>1510</b>, <b>1515</b>, <b>1520</b>, <b>1525</b>, <b>1530</b> and eight inverters <b>1535</b>, <b>1540</b>, <b>1545</b>, <b>1550</b>, <b>1555</b>, <b>1560</b>, <b>1565</b>, <b>1570</b>. The balanced XOR module <b>1500</b> also includes capacitive delay elements <b>1575</b>a, <b>1575</b>b, <b>1575</b>c, <b>1575</b>d, <b>1575</b>e, <b>1575</b>f, <b>1575</b>g, <b>1575</b>h. The capacitive delay elements <b>1575</b>a, <b>1575</b>b, <b>1575</b>c, <b>1575</b>d, <b>1575</b>e, <b>1575</b>f, <b>1575</b>g, <b>1575</b>h are different for each of the balanced XOR modules <b>1500</b>a, <b>1500</b>b, <b>1500</b>c depicted in FIG. <b>14</b>. As described above, the capacitive delay elements <b>1575</b>a, <b>1575</b>b, <b>1575</b>c, <b>1575</b>d, <b>1575</b>e, <b>1575</b>f, <b>1575</b>g, <b>1575</b>h are different to compensate for the different path lengths for each input and whether the inputs handle a rising edge or falling edge transition. Also as described above, each balanced XOR module can include a set of corresponding second capacitive delay elements <b>1575</b>aa, <b>1575</b>ab, <b>1575</b>ac, <b>1575</b>ad, <b>1575</b>ae, <b>1575</b>af, <b>1575</b>ag, <b>1575</b>ah.

As an illustrative example, <figref idref="DRAWINGS">FIG. 16</figref> depicts a timing diagram an arbitrary waveform generator <b>100</b>″ that outputs an output signal <b>136</b>″ that is a square wave with a period of seven nanoseconds (i.e., approximately 143 MHz). The timing diagram depicts an arbitrary waveform generator <b>100</b>″ in which an algebra module <b>108</b>″ contains parallel circuitry for the calculation of two alternating rising edges (i.e., phase <b>0</b> and phase <b>2</b>) and two alternating falling edges ( i.e., phase <b>1</b>, phase <b>3</b>). The timing diagram shows each signal from the input into the switching module <b>112</b>″ to the output of the output module <b>114</b>″.

The block labeled “16:1 MUX” represents the propagation time through the tap selection module (e.g., tap selection module <b>1003</b>a in FIG. <b>10</b>A). The block labeled “sign” represents the propagation time through the mux sign-select (e.g., mux <b>1010</b> in <figref idref="DRAWINGS">FIG. 10A</figref>) that selects between the positive (i.e., rising edge) tap selection module (e.g., <b>1003</b>a in <figref idref="DRAWINGS">FIG. 10A</figref>) or the negative (i.e., falling edge) tap selection module (e.g., <b>1003</b>b in FIG. <b>10</b>A). The block labeled “vernier” represents the propagation time through the fine delay module (e.g., fine delay module <b>310</b> in FIG. <b>14</b>). The double lines on the edge preceding the vernier block represent the variable propagation through a fine delay module <b>310</b>. The block labeled “JK flops” represents the propagation time through the pair of edge flip flops (e.g., edge flip flops <b>1215</b>, <b>1220</b> in FIG. <b>13</b>). The block labeled “XOR” immediately subsequent to the block labeled “JK flops” represents the propagation time through the first balanced XOR module (e.g., balanced XOR module <b>1500</b>a for phase <b>0</b> and phase <b>2</b> signals or balanced XOR module <b>1500</b>b for phase <b>1</b> and phase <b>3</b> signals, as shown in FIG. <b>14</b>). The next block labeled “XOR” immediately subsequent to the block labeled “XOR” represents the propagation time through the next balanced XOR module (e.g., balanced XOR module <b>1500</b>c in FIG. <b>14</b>). The block labeled “clock tree” represents the propagation time through the clock tree (e.g., clock tree shown in FIG. <b>14</b>). The signal labeled “out_clk” represents the output signal <b>136</b>″ output by the arbitrary waveform generator <b>100</b>″.

It should be understood that the principles of the arbitrary waveform synthesizer are applicable for use with other circuits that have a plurality of delay elements. For example, <figref idref="DRAWINGS">FIG. 17</figref> illustrates an arbitrary waveform synthesizer (AWS) <b>5000</b> comprising either a phase locked loop (PLL) circuit or a delay locked loop (DLL) circuit instead of a free-running oscillator. The waveform generation logic <b>2000</b> refers to the combination of the algebra module <b>108</b>, switching module(s) <b>112</b>(<b>1</b>), <b>112</b>(<b>2</b>), etc., and output module(s) <b>114</b>(<b>1</b>), <b>114</b>(<b>2</b>), etc., as well as any of the variations or forms of these modules described in the foregoing. The loop circuit <b>3000</b> in the AWS <b>5000</b> may be locked to one of a variety of signals as shown. The signal to which the loop circuit <b>3000</b> locks is called the “locking signal”. As shown in <figref idref="DRAWINGS">FIG. 17</figref>, the locking signal may be the reference clock signal, an externally supplied signal, or any one of the output clock signals Clk<b>1</b> to Clkn.

<figref idref="DRAWINGS">FIG. 18</figref> shows the AWS <b>5000</b> is shown in more detail with a PLL circuit as the loop circuit. As is known in the art, a PLL circuit comprises, in addition to a delay line circuit <b>3010</b>, a phase/frequency detector (PFD) <b>3020</b> and a filter <b>3030</b>. While not specifically shown in <figref idref="DRAWINGS">FIG. 18</figref>, it should be understood that the delay elements the PLL are tapped by the waveform generation logic <b>2000</b> in the manner described above to generate an arbitrary waveform. The locking signal is supplied to one input of the PFD <b>3020</b> through an optional (/M) divider circuit <b>3050</b>, and the feedback within the PLL circuit may be coupled to the PFD <b>3020</b> through an optional (/N) divider circuit <b>3060</b>. The divider circuits <b>3050</b> and <b>3060</b> are particularly useful when it is desired to lock or sync to a ratio (M:N) of an externally supplied locking signal. The output of the PFD <b>3020</b> is a measure of the difference between the frequency (and/or phase) of the locking signal and the output signal of the delay line circuit <b>3010</b>.

A difference between the PLL and DLL and the free-running oscillator described herein is that these are locked circuits because the output is fed back and compared with the input to lock the output to a desired characteristic. Thus, an arbitrary waveform, e.g., clock signal, may be generated using the techniques described herein with a locked oscillator circuit.

The selection of the locking signal (reference clock signal, output clock signal or externally supplied signal) depends on the desired functionality or effect. Locking the loop circuit to one of the output clock signals Clk<b>1</b> to Clkn has the benefit that spurious spectral content in the output signal becomes more predictable.

An externally supplied locking signal may be useful in the case where it is desired to avoid creating electromagnetic interference (EMI) with some other nearby device. For example, it may be desirable to avoid creating interference at a particular frequency range by locking to an externally supplied signal (or a M:N ratio between it and the loop circuit output). Where an M:N ratio is not sufficient for a particular application, additional circuitry to perform sigma-delta, dithering or fractional-N computations, may be included in the PLL shown in FIG. <b>18</b>.

<figref idref="DRAWINGS">FIG. 19</figref> illustrates a similar configuration to that shown in <figref idref="DRAWINGS">FIG. 18</figref>, except where the locked oscillator circuit <b>3000</b> is a DLL. In this case, there is only a (/M) divider circuit <b>3050</b> between the locking signal and the delay line circuit <b>3010</b>.

Turning to <figref idref="DRAWINGS">FIG. 20</figref>, a waveform generator is shown that generates multiple arbitrary and independent waveforms Clk<b>1</b> to Clkn from a single reference clock signal (e.g., crystal). Some of the clock signals Clk<b>1</b> to Clkn (e.g., a subset of them) may have different frequencies independent of each other. In order to generate multiple independent output waveforms from a single reference signal, there are a plurality of switching modules <b>112</b>(<b>1</b>) to <b>112</b>(N) and a corresponding plurality of output modules <b>114</b>(<b>1</b>) to <b>114</b>(N). All delay element taps go to all switching modules <b>112</b>(<b>1</b>) to <b>112</b>(N). Each corresponding switching module/output module pair <b>112</b>(i)/<b>114</b>(i) is dedicated to a corresponding output clock signal Clk(i). The algebra module <b>108</b> is coupled to each switching module <b>112</b>(i) and output module <b>114</b>(i) as shown in the previous figures. The delay elements are tapped by each switching module <b>112</b>(i). The delay elements may be part of an oscillator such as the free-running oscillator described herein, a PLL or a DLL.

In operation, each switching module/output module pair generates a desired output waveform by building edges of the waveform using the techniques described herein, but which may be independent of the output waveform generated by another switching module/output module pair. That is, each switching module/output module pair operates in parallel so as to substantially simultaneously generate a plurality of output waveforms, all from a single reference clock. The output waveforms may be a plurality of clock signals each at a different desired frequency.

While the foregoing describes that the multiple signals may be independent and at different frequencies, it is not to be limited as such. For example, some of the waveforms (e.g., clock signals Clk<b>1</b> to Clkn) generated by the waveform synthesizer <b>5000</b> may be plesiochronous or mesochronous signals. Plesiochronous signals are two or more signals that are arbitrarily close (but not equal) in frequency to each other (or to some other frequency, such as the reference clock signal frequency) within some defined precision. They are not sourced from the same clock and so, over the long term, will be skewed from each other. Said another way, plesiochronous signals have the same nominal frequency, but are actually at slightly different frequencies. For example, they may be locked to two different 25 MHz crystals. In this sense, the waveform synthesizer <b>5000</b> may be coupled to more than one clock reference, but still generate multiple signals, such as plesiochronous signals. Moreover, the waveform synthesizer <b>5000</b> may produce at least one waveform that is arbitrarily close, but unequal, in frequency to another waveform it produces, or arbitrarily close, but unequal, in frequency to another signal, e.g., the reference clock signal.

Mesochronous signals are signals having a relationship such that their corresponding significant instants occur at the same average rate. The signals are at the same frequency, but have different phases, and the phase of each signal may be arbitrarily selected. Again, the waveform synthesizer <b>500</b> may generate multiple signals some of which having the same frequency, but different phases, and thus are offset from each other in phase.

<figref idref="DRAWINGS">FIG. 21</figref> illustrates another embodiment of the AWS in which the waveform generation logic <b>2000</b> internally locks the phase of any one of the output signals Clk<b>1</b> to Clkn to some external locking signal, or a (M:N) ratio thereof. The delay line circuit <b>3010</b> may be part of a locked loop (PLL or DLL) or part of a free running oscillator. The external locking could be the reference clock signal, or some other externally supplied signal. Thus, in this embodiment, the AWS is used as a “virtual-PLL” whether the delay line circuit is part of a free-running oscillator or part of a locked loop circuit. To this end, there is a (/M) divider circuit <b>4010</b>, a (/N) divider circuit <b>4020</b> and a phase detector (PD) <b>4030</b>. The external locking signal is coupled to one input of the PD <b>4030</b> via the divider circuit <b>4010</b> and one of the output signals Clk<b>1</b> to Clkn is coupled to the other input of the PD <b>4030</b> via the divider circuit <b>4020</b>. The PD <b>4030</b> measures the phase difference between one of the arbitrary waveforms, i.e., one of the output signals Clk<b>1</b> to Clkn, and the external locking signal, and supplies a phase difference measurement signal to the algebra module <b>108</b> (<figref idref="DRAWINGS">FIG. 17</figref>) in the waveform generation logic <b>2000</b>. The algebra module <b>108</b> uses the phase difference measurement signal to computationally adjust the next edge that the edge is locked in phase to the locking signal. Thus, the output signal can be made to very closely and accurately track the phase of the external locking signal.

<figref idref="DRAWINGS">FIG. 22</figref> illustrates a locked loop-AWS in which the waveform generation logic is used to create any locking ratio desired. For example, these techniques may be useful to create arbitrary ratios without requiring sigma-delta or dithering computational circuitry. In one channel of the waveform generation logic, identified by reference numeral <b>6000</b>, the algebra module and state capture modules are removed and replaced by a period integrator module <b>6010</b> that receives a fixed or downloadable period value, in measurement units of (integer number and fraction of) taps. The dedicated processing channel <b>6000</b> serves as a locking channel for the delay line circuit <b>3010</b>, and comprises a dedicated switching module <b>112</b>L, dedicated output module <b>114</b>L, a phase/frequency detector (PFD) <b>6030</b> and a filter <b>6040</b>. No usable output is taken from the locking channel <b>6000</b>. Additional processing channels are provided comprised of switching module <b>112</b>(<b>1</b>) and output module <b>114</b> (<b>1</b>), switching module <b>112</b>(<b>2</b>) and output module <b>114</b>(<b>2</b>), etc., as well as the algebra module <b>108</b> (and the other supporting circuitry described herein but not shown in <figref idref="DRAWINGS">FIG. 22</figref> for simplicity). Usable output is taken from these additional processing channels and it should be understood that while only two are shown, there may be more or less than two.

The period integrator module <b>6010</b> is similar to the period integrator module <b>500</b> shown in <figref idref="DRAWINGS">FIGS. 5 and 6</figref>, described above. The function of the period integrator module <b>6010</b> is to determine when the next rising edge occurs by an amount, in taps, set by the period value, with respect to the reference clock signal. It keeps adding the period value (in integer number and fraction of taps) to its latest sum each cycle. The PFD <b>6030</b> receives at one input a locking signal and at another input the output of the output module <b>114</b>L. The PFD <b>6030</b> generates a phase difference output signal or signals that represent(s) (a magnitude and direction of) the phase difference between the locking signal and the waveform output by the output module <b>114</b>L. The phase difference output signal is coupled to a filter <b>6040</b> and the filter output (called delay adjust) is connected to each delay element module <b>120</b>a to <b>120</b>p in delay line circuit <b>1040</b> to adjust the delay (amount) of each delay element module. Thus, the locking channel <b>6000</b> serves to lock the delay line circuit <b>3010</b> to the external locking signal. The locked delay line circuit <b>3010</b> is in turn used by the switching modules <b>112</b>(<b>1</b>), <b>112</b>(<b>2</b>), etc., in each of the processing modules to produce corresponding output waveforms Clk<b>1</b>, Clk<b>2</b>, etc.

With the configuration shown in <figref idref="DRAWINGS">FIG. 22</figref>, the output signal of the output module <b>114</b>L is proportional to the frequency of the delay line circuit <b>3010</b> and moves (faster or slower) with that frequency. This output signal of the output module <b>114</b>L is then locked to any externally-supplied locking signal via the PFD <b>6030</b> and filter <b>6040</b>. For example, it may be desirable to lock the delay line circuit <b>3010</b> to a particular frequency but not equal that frequency, e.g., some multiple of the reference clock signal frequency. Moreover, because the period value in taps can be changed on the fly, it is possible to adjust the manner in which the locking loop operates according to changes in the host system.

To summarize, a waveform generator for producing an arbitrary waveform is provided comprising: a delay line circuit comprising a plurality of delay elements and a plurality of taps disposed between the delay elements, each tap providing a tap transition signal; an algebra module having an algebra data input port, a clock input port that is coupled to a reference clock signal and an algebra data output port, the algebra module generating a first signal at the algebra data output port in response to a second signal received at the algebra data input port, the first signal indicative of a first rising edge of an arbitrary waveform; a switch module having a switch input port in electrical communication with the algebra data output port, a plurality of switch tap input ports in electrical communication with said plurality of taps, and a switch output port, the switch module providing at the switch output port a selected transition signal corresponding to the tap transition signal provided from one of the plurality of taps, said one of the plurality of taps selected in response to the first signal received at the switch input port; and an output module having a transition signal input port in electrical communication with the switch output port, a window input port in electrical communication with the algebra data output port and a waveform output port in electrical communication with the clock input port of the algebra module, the output module generating the arbitrary waveform at the waveform output port in response to the selected transition signal received at the transition signal input port of the output module and the first signal received at the window input port. The delay line circuit may be part of a delay locked loop (DLL) circuit or a phase locked loop (PLL) circuit. Moreover, the waveform generator may comprise a plurality of switching modules and a corresponding plurality of output modules, wherein each switching module/output module pair cooperates to produce an output waveform (e.g., a clock signal at a desired frequency). Thus, the waveform generator may produce a plurality of output waveforms that may be independent of each other from a single reference clock signal (or multiple clock signals). The output signals may be at different frequencies, or the same (i.e., mesochronous signals) or close to the same frequency (plesiochronous signals).

Similarly, a method is provided for generating an arbitrary waveform comprising: (a) generating a continuous sequence of transitions in a line of delay elements; (b) counting the transitions occurring at one or more of the delay elements; (c) determining a desired first rising edge time and a first falling edge time to generate the arbitrary waveform; (d) selecting a first transition in the continuous sequence of transitions in response to the desired first rising edge time based on the counted transitions and an internal clock signal; (e) selecting a second transition in the continuous sequence of transitions in response to the desired first falling edge time based on the counted transitions and the internal clock signal; and (f) generating an output signal using the selected first transition and the selected second transition to create the arbitrary waveform. The step of generating the continuous sequence of transitions may occur in a plurality of delay elements of a phase locked loop circuit or a delay locked loop circuit. Furthermore, steps (c) through (f) may be performed so as to simultaneously produce a plurality of arbitrary waveforms (e.g., clock signals) that may be independent of each other.

The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments are therefore to be considered in all respects illustrative rather than limiting on the invention described herein. Scope of the invention is thus indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.