Memory system performing fast access to a memory location by omitting the transfer of a redundant address
Claim Score by NHIP
Abstract
A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.
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Expired 7 September 2014, 12 years ago.
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47 claims: 6 independent, 41 dependent
- 1A data processing system, comprising:a data processing unit;a memory which is divided into a plurality of banks such that an access is made to one of said banks at a time;a plurality of address registers coupled to said data processing unit, and corresponding to said plurality of banks;a comparator coupled to at least one of outputs from said address registers;and a controller coupled to said comparator , ;a first line for sending a row address strobe signal, which is shared with the plurality of banks, from the controller to the memory;a second line for sending a column address strobe signal, which is shared with the plurality of banks, from the controller to the memory;a third line for sending a bank signal, which is shared with the plurality of banks, from the controller to the memory;wherein said data processing unit accesses one of said banks , which is specified by the bank signal of the third line, for reading out data, and accesses another bank of said banks for writing data, wherein each of said plurality of address registers holds recently accessed addresses corresponding to said plurality of banks, wherein said comparator compares an access address for a bus access with contents of at least one of said address registers, when said data processing unit issues said bus access, and wherein said controller omits transfer of said access address to said memory in response to an indication of a coincidence by said comparator, when said bus access is a next bus access after a bus access to a different bank, said indication indicating a coincidence between said access address and said contents of said at least one of said address system registers .
- 5A processor LSI comprising:a plurality of address terminals for connecting with a main memory LSI, the main memory LSI using a synchronous dynamic memory having a plurality of banks such that an access is made to one of the plurality of banks at a time;a first external terminal for outputting a row address strobe signal, which is shared with the plurality of banks, to the main memory LSI;a second external terminal for outputting a column address strobe signal, which is shared with the plurality of banks, to the main memory LSI;a third external terminal for outputting a bank signal, which is shared with the plurality of banks, to the main memory LSI;a data processing unit;a plurality of address registers coupled to said data processing unit and provided corresponding to the banks;a selector coupled to said plurality of address registers;a comparator coupled to said selector and said data processing unit;and a controller coupled to said comparator, wherein one of the plurality of the banks is specified by the bank signal, which is determined based on information included in a currently accessed address output by said data processing unit, and accessed at one time;wherein said address registers hold recently accessed addresses, wherein said selector selects one of said address registers based on the information included in the currently accessed address, wherein said comparator compares a row address of the currently accessed address with a recently accessed row address held in the address register selected by said selector, and wherein said controller, responsive to an output from said comparator indicating that the row address of the currently accessed address is the same as the recently accessed row address, omits transfer of said row address of the currently accessed address and allows output of a column address of the currently accessed address from said first terminals.
- 13A processor LSI comprising:a plurality of address terminals for connecting with a main memory LSI, the main memory LSI having at least a first bank and a second bank such that an access is made to one of the first and second banks at a time, a first external terminal for outputting a row address strobe signal, which is shared with the plurality of banks, to the main memory LSI;a second external terminal for outputting a column address strobe signal which is shared with the plurality of banks, to the main memory LSI;a third external terminal for outputting a bank signal, which is shared with the plurality of banks, to the main memory LSI;wherein one of the plurality of the banks to be accessed is specified by the bank signal, wherein said processor LSI is enabled to perform a first access to the first bank and then perform a second access to the first bank, wherein when the value of a row address in the first access is different from the value of a row address in the second access, then said processor LSI outputs a row address and a column address from said address terminals, and wherein when the value of a row address in said first access is identical with the value of a row address in second access, then said processor LSI outputs a column address from said first terminals without outputting a row address.
- 23A data processing system, comprising:a data processing unit;a memory having a plurality of banks;a row address strobe signal line coupling said data processing unit and said memory and provided commonly to said plurality of banks;a column address strobe signal line coupling said data processing unit and said memory and provided commonly to said plurality of banks;a bank signal line coupling said data processing unit and said memory and provided commonly to said plurality of banks;a plurality of address registers holding a row address of a recently accessed address;and selection means for selecting one of said plurality of address registers using information of a specified bit among an access address issued by said data processing unit, wherein said bank signal line sends a bank control signal for selecting one from said plurality of banks, wherein when a row address of the access address issued by said data processing unit coincides with the content of the address register selected by said selection means, the row address in the access address issued by said data processing unit is allowed to prevent from being outputted to said memory.
- 31Broadest claimClaim Score 46, average(NHIP)A processor, comprising:an address terminal coupled to a synchronous memory having a plurality of banks including a first bank and a second bank;a first external terminal for outputting a row address strobe signal commonly to said plurality of banks;a second external terminal for outputting a column address strobe signal commonly to said plurality of banks;and a third external terminal for outputting a bank signal commonly to said plurality of banks, wherein said bank signal is a signal for selecting either one of said plurality of banks of said synchronous memory, wherein when said processor performs a first access to a first bank of said synchronous memory, performs a second access to a second bank of said synchronous memory and performs a third access to said first bank of said synchronous memory, said processor does not output a row address at the third access if the row address for said first access coincides with that for said third access.
- 38An external circuit control LSI comprising:a plurality of external terminals coupled to a processor LSI;and a plurality of second external terminals coupled to a main memory LSI having a plurality of banks including a first bank and a second bank, wherein said plurality of second external terminals comprises: an address terminal for outputting an access address;a terminal for outputting a row address strobe signal commonly to said plurality of banks;a terminal for outputting a column address strobe signal commonly to said plurality of banks;and a terminal for outputting a bank signal commonly to said plurality of banks, wherein said bank signal is a signal for selecting one to be accessed from said plurality of banks, and said external circuit control LSI is enabled to perform a first access to said first bank and thereafter perform a second access to said first bank, wherein when in said second access, a row address in said second access is different from a row address in said first access, said external circuit control LSI outputs a row address and a column address from said second external terminals, wherein when in said second access, the row address in said second access is the same as the row address in said first access, said external circuit control LSI outputs the column address from said second external terminals without outputting the row address therefrom.
Independent claims6
67 paragraphs in 4 sections, as filed
This is a continuation of application Ser. No. 08/815,600, filed Mar. 12, 1997 now U.S. Pat. No. 5,873,122; which is a continuation of Ser. No. 08/301,887, filed Sep. 7, 1994, now abandoned.
BACKGROUND OF THE INVENTION
The present invention generally relates to a data processing system, and more particularly to a circuit for controlling memories in a microprocessor LSI (Large Scale Integration) and microprocessor peripheral circuits.
Dynamic memories are generally referred to as DRAM (Dynamic Random Access Memory). Specifications of typical dynamic memory LSI's are described in, for example, “Hitachi IC Memory Data Book 3 (DRAM, DRAM Modules)”, pp. 445-464. A dynamic memory described in this document has ten address input terminals indicated by A<b>0</b>-A<b>9</b> which are shared to receive row and column addresses (see page 448). Also according to this literature, a read/write access requires a row address and a column address to be provided to the dynamic memory LSI in this order (see page 454), wherein read access time is 70 nanoseconds after the establishment of the externally provided address (1 nanosecond=1×10<sup>−9 </sup>second). Alternative to this read/write access, if a fast page mode (page 461) is used, after the first row and column addresses have been transferred, as long as second and subsequent accesses are made to the same row, transfer of the row address can be omitted, with the result that read access time required for the second and subsequent read accesses is reduced to 20 nanoseconds from the establishment of the external address.
An example of a DRAM control function designed for a conventional microprocessor (hereinafter simply called the “processor”) is described in “Hot Chips IV”, pp. 4.2.2-4.2.12, August. 1992, held in Stanford University. On page 4.2.3 of this document, a drawing is illustrated in which a processor LSI is directly connected to two banks of DRAM chips. Also, timing charts on pages 4.2.7 and 4.2.8 of this document respectively include descriptions “Check fast page cache-hit” and “Check fast page cache-miss”, from which it can be predicted that the fast page mode of the dynamic memory is used under certain hit conditions within the processor. This operation would be enabled, for example, by storing a row address with which a dynamic memory has been accessed at the previous time. The above-mentioned document, however, does not at all refer to how to use two-bank DRAM's or the relation between the cache-hit of the high speed mode and the two-bank DRAM's.
Assume now a conventional processor LSI which includes, among its terminals, dynamic memory address terminals which are used for both row and column addresses. <figref idref="DRAWINGS">FIG. 2</figref> shows an example of accesses performed by this processor. It should be noted that in <figref idref="DRAWINGS">FIG. 2</figref>, the horizontal direction represents the time axis, and reference numeral <b>201</b> designates an access request from the processor; <b>202</b> dynamic address terminals A<b>0</b>-A<b>9</b> of the processor; <b>203</b> a row address strobe (RAS−n) signal of a dynamic memory; and <b>204</b> a column address strobe (CAS−n) signal of the dynamic memory. A suffix “−n” to a signal line indicates that a signal on that line is of negative polarity.
This exemplary access occurs, for example, when a block of data, i.e., the contents of a memory in a certain region is copied to another region of the memory. In <figref idref="DRAWINGS">FIG. 2</figref>, a region from address A<b>000</b> is copied to a region from address <b>7040</b>. It should be noted that in this specification memory addresses are indicated in hexadecimal number. An explanatory diagram <b>205</b> shows how to use 32 bits of a physical address. Specifically, bits (<b>30</b>-<b>31</b>) of the physical address are assigned to an in-word address; bits (<b>21</b>-<b>29</b>) to a column address of a dynamic memory; and bits (<b>11</b>-<b>20</b>) to a row address of the dynamic memory. Here, bit (i) indicates the position of the i-th bit from the leftmost bit which is designated as bit <b>0</b> position. The copy is carried out by the following time-sequential operations.
Operation 1: The contents at address A<b>000</b> are read. A row address and column address are transferred to the dynamic memory. The row address given by the bit positions (<b>11</b>-<b>20</b>) of the physical address is “14”, then the column address given by the bit positions (<b>21</b>-<b>29</b>) is zero.
Operation 2: The contents of address A<b>004</b> are read. Since the row address at this time is the same as that at the previous time, transfer of the row address to the dynamic memory is omitted. Thus, the column address only is transferred to the dynamic memory.
Operation 3: The contents of address A<b>000</b> are written into address <b>7040</b>. A row address and column address for this location are transferred to the dynamic memory.
Operation 4: The contents of address A<b>004</b> are written into address <b>7044</b>. Since the row address at this time is the same as that at the previous time, the transfer of the row address to the dynamic memory is omitted. Thus, the column address only is transferred to the dynamic memory.
Since the subsequent four accesses perform similar operations to the above, explanation thereon will be omitted.
As shown by the example of <figref idref="DRAWINGS">FIG. 2</figref>, the prior art example has a problem that if a row address of a memory location (source) from which data is read and a row address of a memory location (destination) to which the data is written are different in the block copy processing, the fast mode for omitting the transfer of a row address of the dynamic memory is prohibited each time the access source and destination are switched.
SUMMARY OF THE INVENTION
It is an object of the present invention to solve the problem of the fast mode for omitting the transfer of a row address of a dynamic memory, which is prohibited depending on conditions.
It is another object of the present invention to provide a signal line interface for a processor LSI which allows the fast mode for omitting the transfer of a row address of a dynamic memory to be used in a processor which does not have address terminals for both row and column addresses, and which thereby simultaneously minimizes the amount of logic mounted external to the processor LSI.
It is another object of the present invention to provide a signal line interface for a processor LSI which allows information on a fast page operation mode corresponding to plural banks of synchronous dynamic memories to be set from the processor LSI, and which minimizes the amount of logic mounted external to the processor LSI.
According to one feature of the present invention, there is provided a data processing system comprising: a data processing unit; a memory; a plurality of address registers for holding recently accessed addresses; selector means for selecting one of the plurality of address registers by using particular bit information in a currently accessed address; comparator means for comparing, when the data processing unit issues a bus access to the outside, an access address for the bus access with the contents of the address register selected by the selector means in accordance with the particular bit information; and control means for performing an operation for omitting transfer of the access address to the memory when the result of a comparison made by the comparator means shows coincidence.
A concept of the above-mentioned feature will be explained below with reference to <figref idref="DRAWINGS">FIG. 1</figref>, an internal configuration of a processor which employs the present invention (the configuration in <figref idref="DRAWINGS">FIG. 1</figref> will be further explained in detail hereinunder; In the present invention, a processor LSI <b>100</b> includes a plurality of row address registers (storage units) <b>101</b>, <b>102</b>. One or a plurality of particular bits are specified within a plurality of address bits. The specified bits are hereinafter referred to as “DRAM bank bits”. The plurality of row address registers <b>101</b>, <b>102</b> hold row addresses of the respective banks which have been accessed at the previous time.
The dynamic memory is divided into a plurality of banks such that one bank in the dynamic memory specified by the bank bit is accessed at one time.
When the processor LSI issues a bus access to the outside, a coincidence comparator <b>107</b> compares an output value <b>101</b> of the row address register <b>101</b> or <b>102</b> selected by the bank bit of an access address with a row address portion of the access address. If the result <b>113</b> of comparison is true, the processor LSI performs an operation for omitting transfer of the row address to the dynamic memory LSI.
<figref idref="DRAWINGS">FIG. 3</figref> shows an access pattern of an information processing system employing the present invention. Components <b>301</b>, <b>114</b>, <b>117</b>, <b>116</b>, <b>305</b> in <figref idref="DRAWINGS">FIG. 3</figref> correspond to components <b>201</b>-<b>205</b> in <figref idref="DRAWINGS">FIG. 2</figref>, respectively, so that explanation thereon will be omitted. As shown in <b>205</b>, a 32-bit physical address of this example consists of the less significant two bits of bit positions <b>30</b>-<b>31</b> assigned to an in-word address; bits of bit positions <b>21</b>-<b>29</b> to a column address; bit (<b>20</b>) to a bank address of a dynamic memory; and bits of bit positions <b>9</b>-<b>19</b> to a row address of the dynamic memory. In one access, a dynamic memory LSI specified by the bank bit of bit position <b>20</b> only is accessed.
In one access, one bank in a dynamic memory specified by the bank bit only is accessed. During a period for accesses to addresses A<b>000</b>, A<b>004</b>, a dynamic memory LSI corresponding to bank <b>0</b> is accessed. On the other hand, during a period for access to addresses <b>7040</b>, <b>7044</b>, a dynamic memory LSI corresponding to bank <b>1</b> is accessed, but the dynamic memory LSI corresponding to bank <b>0</b> is not accessed. Subsequently, when address A<b>008</b> is to be read, the row address at this time is the same as the row address when the dynamic memory LSI corresponding to bank <b>0</b> was accessed at the previous time, so that transfer of the row address may be omitted. During this period, the dynamic memory LSI corresponding to bank <b>1</b> is not accessed. Subsequently, when data is written into address <b>7048</b>, the row address is the same as that when the dynamic memory LSI corresponding to the bank <b>1</b> was accessed at the previous time, so that transfer of the row address may be omitted.
Comparing <figref idref="DRAWINGS">FIG. 3</figref> with <figref idref="DRAWINGS">FIG. 2</figref>, it is understood that transfer of the row address may be omitted when the addresses A<b>008</b>, <b>7048</b> are accessed. Since access time required in this event is shorter as mentioned above, the omission of the transfer of the row address contributes to a higher processing speed.
When the foregoing block copy processing further continues, the fast page mode may be used to omit the transfer of the row address as long as the same rows are continuously accessed in both source and destination.
Other objects, configurations and effects of the present invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram showing the configuration of a processor LSI in an information processing system which employs the present invention;
<figref idref="DRAWINGS">FIG. 2</figref> shows an access pattern (changes in operation with the lapse of time) in a prior art information processing system;
<figref idref="DRAWINGS">FIG. 3</figref> shows an access pattern (changes in operation with the lapse of time) in the information processing system employing the present invention;
<figref idref="DRAWINGS">FIG. 4</figref> is a block diagram showing the configuration of a system which includes a synchronous dynamic memory divided into two banks;
<figref idref="DRAWINGS">FIG. 5</figref> is a block diagram showing dynamic memory banks and its control circuit in the information processing system employing the present invention;
<figref idref="DRAWINGS">FIG. 6</figref> is a block diagram showing the configuration of a processor LSI in another information processing system employing the present invention;
<figref idref="DRAWINGS">FIG. 7</figref> shows a bank selector circuit and a bank bit selector circuit associated with the processor shown in <figref idref="DRAWINGS">FIG. 6</figref>; and
<figref idref="DRAWINGS">FIG. 8</figref> is a block diagram showing the configuration of an information processing system employing the processor illustrated in FIG. <b>6</b>.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
<figref idref="DRAWINGS">FIG. 1</figref> shows an example of a processor, generally indicated by <b>100</b>, for use in an information processing system according to an embodiment of the present invention. The processor <b>100</b> includes row address registers (register=storage unit) <b>101</b>, <b>102</b>; bits <b>103</b>, <b>104</b> which indicate the validity of the row address registers <b>101</b>, <b>102</b>, respectively; and selector circuits <b>105</b>, <b>106</b>. The selector <b>105</b> selects one of outputs of the valid bits <b>103</b>, <b>104</b> in accordance with a bank address, and delivers the selected one onto a signal line <b>112</b>. Reference numeral <b>107</b> designates a coincidence comparator for comparing a row address in a access requested address <b>110</b> with a row address stored in one of the row address registers <b>101</b>, <b>102</b> selected by the selector circuit <b>106</b>; <b>108</b> a control circuit; and <b>109</b> a selector circuit.
The processor <b>100</b>, when accessing to an external dynamic memory, selects either a row address portion or a column address portion in the access requested address <b>110</b> by using the selector circuit <b>109</b> and outputs the selected address portion to an address terminal <b>114</b> having bits A(<b>0</b>:<b>10</b>) for dynamic memories. The control circuit <b>108</b> is applied with the output of a valid bit selected by the selector circuit <b>105</b> and with an output signal <b>113</b> of the coincidence comparator <b>107</b> indicative of the result of comparison between a row address in the access requested address <b>110</b> and a row address stored in one of the row address registers <b>101</b>, <b>102</b> selected by the selector circuit <b>106</b>. The control circuit <b>108</b> is also applied with a part of an address bus <b>110</b> corresponding to the bank bit. Then, the control circuit <b>108</b> outputs signal values of three external terminals BANK (<b>115</b>), RAS−n (<b>117</b>) (“−n” indicates a negative polarity signal), and CAS−n (<b>118</b>).
A 32-bit physical address, as illustrated in <figref idref="DRAWINGS">FIG. 3</figref>, includes fields respectively assigned to a row address, a column address, and a bank address.
A flow of processing executed by the processor <b>100</b> when generating an access request proceeds as follows.
First, an access request signal generated from a data processing unit (not described or shown since this is not so deeply related to the present invention) composed of a command processing unit and an operand processing unit, arranged inside the processor <b>100</b>, is transferred to the control circuit <b>108</b> through a signal line <b>111</b>. Simultaneously, an access requested address <b>110</b> is transferred through the address bus PA (<b>0</b>-<b>31</b>). The control circuit <b>108</b> selects one of the row address registers <b>101</b>, <b>102</b> by the selector circuit <b>106</b> in accordance with a bank address (bit <b>20</b>) in the access requested address. The control circuit <b>108</b> also selects one of the valid bits <b>103</b>, <b>104</b> by the selector circuit <b>105</b> in accordance with the bank address. When the row address selected by the selector circuit <b>106</b> is equal to a row address portion of the access requested address to cause the associated valid bit to be set to “1”, this is referred to as “hit”.
If a hit occurs, the dynamic memory will be accessed with the same row address as that in the previous access, so that the access at the present time will be performed in an operation mode for omitting transfer of the row address to the dynamic memory.
If a miss occurs, the dynamic memory is first accessed in an operation mode for transferring both the row and column address portions of an access requested address of the dynamic memory. Next, the row address portion is registered in one of the row address registers <b>101</b>, <b>102</b> selected by the bank address, and the valid bit <b>103</b> or <b>104</b> associated with the selected row address register is written to “1”. It should be noted that the valid bits <b>103</b>, <b>104</b> are set to “0” in an initial state immediately after power-on in order to prevent an erroneous hit from occurring when the row addresses accidentally match with each other in the first access after power-on.
<figref idref="DRAWINGS">FIG. 4</figref> shows a block diagram of a system including the processor <b>100</b>. The system also has synchronous dynamic memory LSI's <b>401</b>, <b>402</b>. The control signals A(<b>0</b>:<b>10</b>) (<b>114</b>), Bank (<b>115</b>), RAS−n (<b>117</b>), CAS−n (<b>116</b>) are connected to the memory LSI's <b>401</b>, <b>402</b>. The synchronous dynamic memory LSI <b>401</b> is divided into two banks <b>403</b>, <b>404</b> such that the memory bank <b>404</b> is accessed when the control signal BANK (<b>115</b>) is at “0”, and the memory bank <b>403</b> is accessed when BANK (<b>115</b>) is at “1”. As is well known, logic “0” on a signal line means “LOW” potential, and logic “1” means “HIGH” potential.
When the signal BANK (<b>115</b>) is at “0”, logic “1” is generated at the output of an invertor <b>407</b> and is transferred to a bank <b>0</b> memory control circuit <b>406</b>. This is an indication of an access to the bank <b>0</b> memory. Conversely, when the signal BANK (<b>115</b>) is at “1”, logic “0” is transferred to the bank <b>0</b> memory control circuit <b>405</b>. This is an indication of an access to a bank <b>1</b> memory.
In addition, each of the dynamic memory LSI's <b>401</b>, <b>402</b> has the following terminals: I/O<b>0</b>-<b>7</b> (<b>409</b>, <b>410</b>) representing an 8-bit data input/output signal; WE−n (<b>411</b>, <b>412</b>) representing a write command signal which remains at logic “0” during a write operation; CLK (<b>413</b>, <b>414</b>) representing a clock input terminal; CKE (<b>415</b>, <b>416</b>) representing a clock enable signal for controlling whether or not a clock is transferred to the inside; and DQM (<b>408</b>) representing an access mask signal which functions as an output enable signal in a read access for outputting the data input/output signal I/O<b>0</b>-<b>7</b>, and as a write enable signal in a write access for enabling the data input/output signal I/O<b>0</b>-<b>7</b> to be written each time the clock is applied thereto.
The dynamic memory LSI's <b>401</b>, <b>402</b> have several forms of operation mode information for their synchronous operation which are RAS delay (the number of clock cycles from RAS to a data access), CAS delay (the number of clock cycles from CAS to a data access), and burst length (a period in which the address is counted up from initial value to an end value and returned to the initial value). These mode information signals are written through the address bits A<b>0</b>-<b>10</b> when all of RAS−n (<b>116</b>), CAS−n (<b>116</b>), and WE−n (<b>411</b>) are at potential “L”.
<figref idref="DRAWINGS">FIG. 5</figref> shows dynamic memories and its control circuit in another system including the processor <b>100</b>. Blocks <b>501</b>, <b>503</b> each include a plurality of invertors. Another block <b>502</b> includes a plurality of two-input AND circuits, each of which generates an output value “1” only when both input values are “1”. A block <b>504</b> includes dynamic memories of bank <b>0</b>, and a block <b>505</b> includes dynamic memories of bank <b>1</b>. Lines <b>506</b>, <b>507</b> respectively carry a negative-polarity row address strobe signal and column address strobe signal for the dynamic memories <b>504</b> of bank <b>0</b>. Lines <b>508</b>, <b>509</b> respectively carry a negative-polarity row address strobe signal and column address strobe signal for the dynamic memories <b>505</b> of bank <b>1</b>.
When the signal BANK (<b>115</b>) is at “0”, negative pulses appearing on RAS−n (<b>117</b>), CAS−n (<b>116</b>) (see <b>303</b>, <b>304</b> in <figref idref="DRAWINGS">FIG. 3</figref>) are transferred to the signal lines <b>506</b>, <b>507</b>, respectively, but not to the signal lines <b>508</b>, <b>509</b>. As a result, a dynamic memory <b>504</b> in bank <b>0</b> is accessed. Conversely, when the signal BANK (<b>115</b>) is at “1”, the negative pulses appearing on RAS−n (<b>117</b>), CAS−n (<b>116</b>) are transferred to the signal lines <b>508</b>, <b>509</b>, respectively, but not to the signal lines <b>506</b>, <b>507</b>. As a result, a dynamic memory <b>505</b> in bank <b>1</b> is accessed.
<figref idref="DRAWINGS">FIG. 6</figref> shows an example of another processor, generally indicated by <b>600</b>, which employs the present invention. Since components <b>601</b>-<b>608</b> and signal lines <b>610</b>, <b>611</b>-<b>613</b> are arranged similarly to their correspondents <b>101</b>-<b>108</b>, <b>110</b>, <b>111</b>-<b>113</b> in <figref idref="DRAWINGS">FIG. 1</figref>, explanation thereon will be omitted. The processor <b>600</b> does not have a shared address terminal through which row and column addresses are specified, but a 32-bit address terminal A(<b>0</b>-<b>31</b>) (<b>614</b>) including a separate row address and column address.
A two-input selector <b>615</b> selects one of an access requested address <b>610</b> and an address stored in a register <b>617</b>, and delivers the selected one to the address terminal A(<b>0</b>:<b>31</b>) (<b>614</b>). An output buffer <b>616</b> for the processor <b>600</b> is arranged at the output of the selector <b>615</b>, and delivers an output with a logic value identical to that of an input.
When the two-input selector <b>615</b> selects the access requested address <b>610</b>, the resulting operation is similar to that explained in connection with FIG. <b>1</b>. This operation to be executed when the access requested address <b>610</b> is selected will be explained below.
When the processor <b>600</b> generates an access request, the following processing flow is executed. First, an access request signal from a processing unit including a command processing unit and an operand processing unit arranged within the processor <b>600</b> is transferred to a control circuit <b>608</b> through a signal line <b>611</b>. Simultaneously, an access address is transferred through an address bus PA(<b>0</b>:<b>31</b>) (<b>610</b>). The control circuit <b>608</b> selects one of outputs from row address registers <b>601</b>, <b>602</b> in accordance with a bank address in the access requested address. Also, a selector <b>605</b> selects one of valid bits <b>603</b>, <b>604</b> in accordance with the bank address.
If a hit occurs, the control circuit <b>608</b> sets an output terminal SAR (<b>609</b>) to “1”. The terminal SAR delivers an output signal which indicates an access to the same row region. The definition of “hit” is the same as that made in connection with the explanation of FIG. <b>1</b>.
If a miss occurs, the control circuit <b>608</b> sets SAR to “0”. Also, information is registered in the registers <b>601</b>, <b>602</b> and valid bits <b>603</b>, <b>604</b> as is done in the example of the processor <b>100</b>.
A circuit external to the processor LSI <b>600</b> detects that SAR (<b>609</b>) is at “1” to know that a fast operation mode may be used for omitting transfer of a row address of an associated dynamic memory.
The processor LSI <b>600</b>, unlike the processor LSI <b>100</b>, does not have bank bits fixed at predetermined positions. <figref idref="DRAWINGS">FIG. 7</figref> shows part of the configuration related to a bank bit selecting method. Since components <b>601</b>, <b>602</b>, <b>606</b>, <b>608</b>, <b>612</b> in <figref idref="DRAWINGS">FIG. 7</figref> have already been explained, repetitive explanation thereon will be omitted. A two-input selector <b>606</b> in <figref idref="DRAWINGS">FIG. 7</figref> is controlled by a bank bit control signal <b>703</b>. A 21-input selector <b>702</b> selects one from input signals <b>704</b>, <b>705</b>, . . . , <b>706</b>, <b>707</b> in accordance with a control signal <b>701</b> from the control circuit <b>608</b>, and delivers the selected signal onto a signal line <b>703</b>. Input signals <b>704</b>, <b>705</b>, <b>706</b>, <b>707</b> are individual address signals included in a requested address on the address bus PA(<b>0</b>:<b>31</b>) (<b>610</b>). The processor <b>600</b> can arbitrarily set the control signal <b>701</b> by using a particular command. In summary, an arbitrary bit within bit positions <b>0</b>-<b>20</b> in a requested address can be used as a bank address.
Next, explanation will be given of how the two-input selector <b>615</b> in <figref idref="DRAWINGS">FIG. 6</figref> selects the register <b>617</b>. Set in the register <b>617</b> is information on an operation mode (RAS delay, CAS delay, burst length) of a synchronous dynamic memory. By the processor <b>600</b> executing the particular command, the two-input selector <b>615</b> selects the register <b>617</b> and outputs information registered therein onto the address terminal A(<b>0</b>:<b>31</b>) (<b>614</b>). An operation mode setting operation is achieved for the synchronous dynamic memory connected external to the processor <b>600</b> by a combination of appropriate external circuits.
<figref idref="DRAWINGS">FIG. 8</figref> shows the configuration of an exemplary information processing system which employs the processor LSI <b>600</b>. The configuration in <figref idref="DRAWINGS">FIG. 8</figref> is mainly composed of the processor LSI <b>600</b>, an external circuit control LSI <b>801</b>, and main memory LSI's <b>402</b> using synchronous dynamic memories.
Explanation will first given of how an address signal <b>614</b> is transferred from the processor LSI <b>600</b>. The address signal <b>614</b> is applied to the external circuit control LSI <b>801</b> and stored in an address register <b>802</b> provided therein. Signal lines <b>805</b>, <b>806</b> from the address register <b>802</b> carry a row address and a column address to the main memory LSI's <b>402</b>, respectively. Either of the row address <b>805</b> and the column address <b>806</b> is selected by a two-input selector <b>803</b> and sent to a system address bus <b>811</b>. The address signal on the system address bus <b>811</b> is further transferred to an address terminal of the respective main memory LSI's <b>402</b>.
Within an address registered in the address register <b>802</b>, upper address bits <b>807</b> are decoded by an address decoder <b>814</b>, and the decoded result is transferred to a chip select terminal <b>813</b> of the respective main memory LSI's <b>402</b>.
A 32-bit system data bus <b>812</b> is used to communicate data between the processor LSI <b>600</b> and the main memory LSI's <b>402</b>. It should be noted that since the memory LSI <b>402</b> has a data terminal of eight bit width, the system of this embodiment should include at least four memory LSI's <b>402</b> for communicating 32-bit data.
The external circuit control LSI <b>801</b> includes an access request managing logic <b>804</b> for managing conditions related to the access. From the processor LSI <b>600</b>, an access request signal <b>808</b>, an identical address indicating signal <b>609</b>, and operation mode setting request signal <b>815</b> for dynamic memories are transferred to the access request managing logic <b>804</b>.
When the signal <b>815</b> is at logic “0”, the access request managing logic <b>804</b> operates as follows. First, when an access request exists in the signal <b>808</b> and the identical address indicating signal is at logic “0”, RAS−n (<b>809</b>) is issued to the main memory LSI's <b>402</b>, and simultaneously a row address <b>805</b> is delivered onto the system address bus <b>811</b>. Subsequently, CAS−n (<b>810</b>) is issued to the main memory LSI's <b>402</b>, and simultaneously a column address <b>805</b> is delivered onto the system address bus <b>811</b>.
Second, when an access request exists in the signal <b>808</b> and the identical address indicating signal is at logic “1”, issue of the RAS−n (<b>809</b>) and row address <b>805</b> is omitted, unlike the first case.
When the processor <b>600</b> executes the aforementioned particular command (the command mentioned when the register <b>617</b> was explained), the operation mode setting request signal <b>815</b> changes to logic “1”. When the signal <b>815</b> is at logic “0”, the access request managing logic <b>804</b> sets all of RAS−n (<b>809</b>), CAS−n (<b>810</b>), and WE−n (<b>816</b>) to potential “L”. Simultaneously with this, the value stored in the operation mode register <b>617</b> is transferred to the main memory LSI's <b>402</b> through the system address bus <b>811</b>. In this manner, the operation mode setting processing is carried out for the main memory LSI's <b>402</b>. This processing is performed during an initial operation after the power is turned on, or when the system is reset. Since the processor LSI <b>600</b> provides the operation mode setting request signal <b>815</b>, logics so far required for producing a signal used to generate an operation mode setting processing starting signal for the main memory LSI's <b>402</b>, for example, an address decoding logic, are made unnecessary.
The system of the present invention is implemented in HITACHI HM 5241605 series, 131072-word×16-bit×2-bank Synchronous Dynamic RAM which is incorporated herein by reference.
It will be understood that the present invention is not limited to the above described specific embodiments, but may be modified in various manner within the scope of its technical ideas. For example, while the number of row address registers and the number of banks in a dynamic memory are set to two, these numbers may be increased to four, eight, and so forth. Also, the row address registers and coincidence comparator are not necessarily arranged in the processor LSI, and in alternative, processing similar to that of the above embodiments may be performed external to the processor LSI, for example, in the external circuit control LSI <b>801</b>.
According to the embodiments of the present invention, row addresses of source and destination are held in row address registers for processing such as a block copy, so that a fast operation mode for dynamic memories can be used to omit transfer of the row address.
Also, since the row address hit information <b>690</b> is provided as an output signal of the processor LSI <b>600</b>, the embodiments of the present invention allow processors, which do not have a shared address terminal for both row and column addresses of a dynamic memory, to use the fast operation mode for dynamic memories, whereby the amount of logics external to the processor LSI is minimized, and transfer of a row address to the dynamic memories is omitted.
Further, according to the embodiments of the present invention, since the processor LSI <b>600</b> provides the operation mode setting request signal <b>815</b>, logics so far required for producing a signal used to generate an operation mode setting processing starting signal for the main memory LSI's <b>402</b>, for example, an address decoding logic and so on, are made unnecessary.
Contents4
9 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9
Every citation, both waysCites: the store holds 26 of 27
| Document | Relation | Office | Cited during |
|---|---|---|---|
| US4792891A | Cites | United States of America | Applicant |
| US4825358A | Cites | United States of America | Search report |
| US5187792A | Cites | United States of America | Search report |
| US5193161A | Cites | United States of America | Search report |
| US5329629A | Cites | United States of America | Search report |
| US5430686A | Cites | United States of America | Search report |
| US5461718A | Cites | United States of America | Search report |
| US5491808A | Cites | United States of America | Search report |
| US5652860A | Cites | United States of America | Search report |
| US5666494A | Cites | United States of America | Search report |
| US5873122A | Cites | United States of America | Search report |
| JPH03232186A | Cites | Japan | Applicant |
| JPH04299752A | Cites | Japan | Applicant |
| JPH0465739A | Cites | Japan | Search report |
| JPH0465739A | Cites | Japan | Applicant |
| JPH05165713A | Cites | Japan | Applicant |
| JPS4866745A | Cites | Japan | Applicant |
| JPS61127056A | Cites | Japan | Applicant |
| JPS61231640A | Cites | Japan | Applicant |
| JP5165713 | Cites | Japan | Third party observation |
| JP4866745 | Cites | Japan | Third party observation |
| JP61127056 | Cites | Japan | Third party observation |
| JP61231640 | Cites | Japan | Third party observation |
| JP3232186 | Cites | Japan | Third party observation |
| JP465739 | Cites | Japan | Third party observation |
| JP4299752 | Cites | Japan | Third party observation |
| "Performance analysis for a cache system with different DRAM" by N. Mekhiel et al, Electrical and Computer Engineering, 1993 Conference IEEE, 1993. | Non-patent | – | Search report |
| "A 50-ns 16 Mb DRAm with a 10-ns Data Rate and On-chip ECC" by H. Kalter et al, IEEE Journal of Solid-State Circuits vol. 25, No. 5 pp. 1113-1128, Oct. 1990. | Non-patent | – | Search report |
| "Implementation of a sub-10 ns series access mode to a standard" by Y. Watanabe et al, Custom Integrated Circuits, 1993 Conference IEEE, 1991. | Non-patent | – | Search report |
| Hitachi IC Memory Data Book 3, Sep. 1992. | Non-patent | – | Search report |
| "Hot Chips IV", by G. Langdon, Stanford University. pp. 4.2.2-4.2.12, Aug. 1992. | Non-patent | – | Search report |
| HM 5241605 131072-Word X 16-bit X2-bank Synchronous Dynamic RAM, Hitachi Semiconductor. pp. 1-6, 36-39, Feb. 20, 1994. | Non-patent | – | Search report |
| “Performance analysis for a cache system with different DRAM” by N. Mekhiel et al, Electrical and Computer Engineering, 1993 Conference IEEE, 1993. | Non-patent | – | Search report |
| “A 50-ns 16 Mb DRAm with a 10-ns Data Rate and On-chip ECC” by H. Kalter et al, IEEE Journal of Solid-State Circuits vol. 25, No. 5 pp. 1113-1128, Oct. 1990. | Non-patent | – | Search report |
| “Implementation of a sub-10 ns series access mode to a standard” by Y. Watanabe et al, Custom Integrated Circuits, 1993 Conference IEEE, 1991. | Non-patent | – | Search report |
| Hitachi IC Memory Data Book 3, Sep. 1992. | Non-patent | – | Search report |
| “Hot Chips IV”, by G. Langdon, Stanford University. pp. 4.2.2-4.2.12, Aug. 1992. | Non-patent | – | Search report |
| HM 5241605 131072-Word X 16-bit X2-bank Synchronous Dynamic RAM, Hitachi Semiconductor. pp. 1-6, 36-39, Feb. 20, 1994. | Non-patent | – | Search report |
7 members in 3 offices
Priority claims19
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| 81560097 | United States of America | A | |
| 81560097 | United States of America | A | |
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| 18890298 | United States of America | A | |
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| US6154807A | United States of America | A | |
| US6292867B1 | United States of America | B1 | |
| KR100298955B1 | Republic of Korea | B1 | |
| USRE41589EThis record | United States of America | E |
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Numbers
- Publication
- RE041589
- Publication, DOCDB
- RE41589
- Publication, EPODOC
- USRE41589E
- Application
- 10290367
- Application, DOCDB
- 29036702
- Application, EPODOC
- US20020290367
Titles
- English
- Memory system performing fast access to a memory location by omitting the transfer of a redundant address
Classification
- CPC, 3
- G06F12/0215
- G06F13/00
- G06F13/1631
- IPC, 3
- G06F12 00
- G06F12 06
- G06F12 02
- USPC, 2
- 711005000
- 711105000