Frequency-stabilized transceiver configuration

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of copending International Application No. PCT/DE 99/03274, filed Oct. 12, 1999, which designated the United States.

BACKGROUND OF THE INVENTION

Field of the Invention

The invention relates to a frequency-stabilized transceiver configuration which is intended to be used in communication terminals for wire-connected and/or wireless communication. The transceiver configuration has an A/D converter outputting a first digital data signal, a D/A converter, and a controllable oscillator circuit. The controllable oscillator circuit has a reference oscillator with an oscillating crystal as a resonator and outputs a sampling clock received by the A/D converter and the D/A converter. A digital data processing circuit receives the first digital data signal output by the A/D converter and processes, it further and outputs a second digital data signal to the D/A converter. A frequency section being a radio-frequency and/or an intermediate-frequency section is provided and has a frequency converter stage operated with a beat frequency derived from the controllable oscillator circuit.

Such transceiver configurations are known and described, for example, in the article titled “Radio Frequency Integrated Circuit Technology for Low-Power Wireless Communications”, L. E. Larson, IEEE Personal Communications, Pages 11-19, June 1998.

A central variable in the transmission of messages is the bandwidth available for transmission since it limits the maximum achievable number of messages which can be transmitted per unit time when a minimum transmission quality is stipulated. As a rule, the available bandwidth is limited. Apart from software approaches to the bandwidth problem which are also based on stipulating a suitable data structure, the best-possible utilization of the available bandwidth must also always be ensured on the hardware side.

In the field of mobile radios, for example, the available total bandwidth is divided into traffic channels with predetermined channel bandwidths, a certain traffic channel being assigned to a subscriber when he accesses the mobile radio network. The radio-frequency section of the communication terminal is set to the assigned channel frequency by the frequency converter stage and any bandwidth limiting of the signal received or to be transmitted, which is required for avoiding inter-channel cross-talk, is usually implemented is the intermediate-frequency, low-frequency or baseband region by filtering out signal components not needed by appropriate analog or digital bandpass or low pass filters.

To obtain the best-possible utilization of the channel bandwidth, it must be possible to adjust the frequency converter stage to the required channel frequency with high accuracy and stability with time. For this purpose, the oscillator circuit operating the frequency converter stage must have high frequency stability.

To achieve high frequency stabilities of the oscillator circuit, it is already known from the article mentioned initially for either the entire oscillator circuit or only the reference oscillator to be an external hybrid component. The disadvantage of these solutions is the relatively high cost entailed when using hybrid components.

An alternative solution also described in the article mentioned consists in providing a completely integrated implementation of the oscillator circuit. However, a completely integrated oscillator circuit exhibits too little frequency stability for many applications.

In the article titled “QPSK and BPSK Demodulator Chip Set for Satellite Applications” by R. van der Wal, IEEE Transactions on Consumer Electronics, US, Vol. 41, No. 1, pages 30 to 41 (1995), a controller QDMC for a quadrature demodulator is described which is implemented in the form of a chip. The controller exhibits two A/D converters for the I and Q signal branch and also contains a voltage controlled oscillator (VCO). The phase lock loop (PLL) control loop of the VCO contains an operational amplifier operated in a negative feedback circuit, the output of which is supplied to an oscillating crystal used as a resonator. The oscillating crystal and the negative feedback circuit of the operational amplifier (series circuit formed of a resistor and a capacitor) are constructed as external components which are not integrated in the chip.

SUMMARY OF THE INVENTION

With the foregoing and other objects in view there is provided, in accordance with the invention, a transceiver configuration for a communication terminal. The transceiver configuration contains an A/D converter outputting a first digital data signal, a D/A converter and a controllable oscillator circuit connected to the A/D converter and to the D/A converter. The controllable oscillator circuit has a reference oscillator with an oscillating crystal as a resonator and outputs a sampling clock received by the A/D converter and the D/A converter. A digital data processing circuit is connected to the A/D converter and to the D/A converter and receives the first digital data signal output by the A/D converter and processes it further and outputs a second digital data signal to the D/A converter. The A/D converter, the D/A converter, the data processing circuit and the controllable oscillator circuit, apart from the oscillating crystal of the reference oscillator, are constructed as a monolithically integrated circuit so that of the controllable oscillator circuit, only the oscillating crystal is implemented as an external component. A frequency section being a radio-frequency section and/or an intermediate-frequency section is connected to the A/D converter, to the D/A converter and to the controllable oscillator circuit. The frequency section has a frequency converter stage operating with a beat frequency derived from the controllable oscillator circuit.

Due to the integration of the oscillator circuit into the integrated circuit, which is complete apart from the oscillating crystal, a high overall degree of integration of the circuit configuration according to the invention is achieved as a result of which its production costs can be kept down. Due to the external configuration (“dislocation”) of the oscillating crystal with respect to the integrated circuit, it is still possible to guarantee high frequency stability.

An especially high degree of integration of the circuit configuration according to the invention, which is advantageous from the point of view of costs, is achieved if the integrated circuit contains other elements such as a digital filter, a channel estimator or a data detector.

In accordance with an added feature of the invention, the digital data processing circuit has a digital filter and a digital modulator.

In accordance with another feature of the invention, the digital data processing circuit has a channel estimator.

In accordance with a concomitant feature of the invention, a data detector is connected to the channel estimator.

Other features which are considered as characteristic for the invention are set forth in the appended claims.

Although the invention is illustrated and described herein as embodied in a frequency-stabilized transceiver configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.

The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

<figref idref="DRAWINGS">FIG. 1</figref> is a block circuit diagram of a circuit configuration according to the invention;

<figref idref="DRAWINGS">FIG. 2</figref> is a block circuit diagram of a circuit of an oscillator circuit shown in <figref idref="DRAWINGS">FIG. 1</figref>; and

<figref idref="DRAWINGS">FIG. 3</figref> is a circuit diagram of a reference oscillator shown in FIG. <b>2</b>.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In all the figures of the drawing, sub-features and integral parts that correspond to one another bear the same reference symbol in each case. Referring now to the figures of the drawing in detail and first, particularly, to <figref idref="DRAWINGS">FIG. 1</figref> thereof, there is shown an integrated circuit (IC) <b>1</b> provided for a communication terminal, for example a mobile telephone. The IC <b>1</b> contains a data processing circuit <b>2</b>, an A/D converter <b>6</b>, a D/A converter <b>7</b> and an oscillator circuit (VCO: voltage controlled oscillator) <b>8</b>.

The extent of the data processing circuit <b>2</b> is indicated by a dashed borderline in FIG. <b>1</b>. The data processing circuit <b>2</b> contains a digital signal conversion circuit <b>3</b> with a digital filter <b>3</b>′ contained therein, a channel estimator <b>4</b> and a digital I/Q modulator <b>5</b>. The data processing circuit <b>2</b> can exhibit, in a manner not shown, other digital circuit and control elements such as, for example, storage elements, micro-processors, micro-controllers, etc. and also other digital circuits such as, for example, a data detector D etc. which will still be mentioned in the text which follows.

An oscillator frequency f_ozgenerated by the VCO <b>8</b> can be varied via a control input <b>9</b> of the VCO <b>8</b> and is provided at an oscillator output <b>10</b> of the VCO <b>8</b> as a system clock to the IC <b>1</b> and especially as a sampling frequency to the A/D converter <b>6</b> and the D/A converter <b>7</b>.

The IC <b>1</b> operating in the low-frequency or baseband region is connected to a radio-frequency section <b>11</b> of a communication terminal.

At the receiving end, the radio-frequency section <b>11</b> can exhibit first and second down converters <b>13</b>, <b>14</b> which accept a received signal provided by a receiving antenna <b>12</b>. The down converters <b>13</b>, <b>14</b> are operated with beat or mixed frequency signals <b>16</b>, <b>17</b> which are phase-shifted by 90° with respect to one another and which are generated by a 90° phase shifter <b>15</b>. In consequence, analog output received signals <b>24</b>, <b>25</b> of the two down converters <b>13</b>, <b>14</b> also exhibit a 90° phase shift (so-called in-phase I and quadrature Q branch). The analog output received signals <b>24</b>, <b>25</b> are supplied to corresponding I and Q inputs of the A/D converter <b>6</b> which digitizes them independently of one another.

At the transmitting end of the radio-frequency section <b>11</b>, analog I and Q output signals <b>26</b>, <b>27</b>, which are also phase-shifted by 90° and are output by the D/A converter <b>7</b> are superimposed on one another in an adding stage <b>19</b> of the radio-frequency section <b>11</b> and an output transmit signal <b>28</b> formed in an adding stage <b>19</b> is supplied as input signal to an up converter <b>18</b>. The up converter <b>18</b> converts the output transmit signal <b>28</b>, by mixing it with a beat or mixing frequency signal <b>20</b>, into a transmit signal which is conducted to a transmitting antenna <b>21</b> (which, in practice, is identical to the receiving antenna <b>12</b>) and is radiated by it.

In addition, the radio-frequency section <b>11</b> has an n:m frequency multiplier <b>22</b>, the input of which is supplied with the oscillator frequency f_ozand which generates both the beat frequency signal <b>20</b> for the up converter <b>18</b> and a beat or mixing frequency signal <b>23</b>, which forms the basis of the down conversion, for the 90° phase shift <b>15</b>. The latter signals <b>20</b>, <b>23</b> are sinusoidal oscillations at a frequency f▭(n/m)*f_oz, n and m being integral numbers which, as a rule, are different for the two signals <b>20</b>, <b>23</b>.

The radio-frequency section <b>11</b> can be implemented in many other ways than those shown here and, in addition, can also contain, for example, an intermediate-frequency stage and suitable bandpass filters for limiting the bandwidth.

In the text which follows, the operation of the circuit configuration described is explained in further detail and numbers quoted relate to the global system for mobile communication (GSM) standard used in digital mobile radio.

When a subscriber radio signal transmitted by a base station on one of the traffic channels reserved for this purpose (in a range from 935 to 960 MHz, 200 kHz channel bandwidth) is received, the two down converters <b>13</b>, <b>14</b> are operated by the frequency multiplier <b>22</b>, by selecting suitable values for n and m, in such a manner that the analog output received signals <b>24</b>, <b>25</b> (I and Q branch) generated are in the low-frequency or baseband region. They can thus be sampled and digitized without problems by the A/D converter <b>6</b>. The oscillator frequency used for the sampling can be, for example, f_oz=13 MHz.

Digital data signals <b>29</b> (I branch) and <b>30</b> (Q branch), generated by the A/D converter <b>6</b>, are supplied to the signal conversion circuit <b>3</b>.

The signal conversion circuit <b>3</b> produces, if necessary, a digital frequency shift for the digital data signals <b>29</b>, <b>30</b> received, and subsequent digital filtering. The digital filtering provides the required bandwidth limiting (&lt;200 kHz) of the transmission path at the receiving end. It can be implemented, for example, by a digital low-pass filter contained in the signal conversion circuit <b>3</b> (in the case of data signals <b>29</b>, <b>30</b> in the baseband region) or a digital bandpass filter (in the case of data signals <b>29</b>, <b>30</b> in the low-frequency region).

The signal conversion circuit <b>3</b> is followed by the channel estimator <b>4</b>, the task of which consists of continuously (approximately every 0.5 ms) determining a current transfer function of the mobile radio channel by use of predetermined data sequences (so-called training sequences) which are regularly radiated by the base station and are known to the channel estimator <b>4</b>. The transfer function characterizes the instantaneous transfer characteristic of the mobile radio channel. The continuous predetermination of the transfer function is necessary because the wave propagation in the air interface of the mobile radio channel continuously changes due to changing environmental influences (for example, shielding and reflection on buildings).

The transfer functions determined (estimated) and the filtered digital received data are applied to a data detector D, via an output <b>31</b> of the channel estimator <b>4</b>. The detector D detects a digital data signal originally sent by using the transfer functions obtained. As a rule, further digital processing steps (demultiplexing, channel decoding, source decoding) follow which allow a complete reconstruction of the message sent. The configuration of the data processing circuit <b>2</b> depends to a great extent on the actual field of application of the communication terminal. For example, the channel estimator <b>4</b> can be omitted especially in the case of communication terminals which are connected by wire or optical fiber.

The operation at the transmitter end of the communication terminal is largely analogous to the operation at the receiver end described above.

The digital I/Q modulator <b>5</b> is supplied with a digital input signal E, which may first have been source-encoded, channel-encoded and multiplexed, via an input <b>32</b>. The digital I/Q modulator <b>5</b> keys the digital input signal E using a predetermined modulation method, for example Gaussian minimum shift keying (GMSK) and, at the same time, limits the bandwidth. At the output end, the I/Q modulator <b>5</b> provides the D/A converter <b>7</b> with keyed (modulated) digital data signals <b>33</b>, <b>34</b>. The frequencies of the corresponding analog I and Q output signals <b>26</b>, <b>27</b> are then converted in the up converter <b>18</b> in the manner already described.

A variation with time of the oscillator frequency f_ozcaused by frequency drift or frequency noise causes a corresponding change in the frequencies of the digital I and Q data signals <b>29</b>, <b>30</b> (at the receiving end) and the radio wave radiated (at the transmitting end). This is based on the fact that the beat frequency signals <b>20</b>, <b>23</b> supplied to the down and up converters <b>13</b>, <b>14</b>; <b>18</b> are derived from the oscillator frequency f_oxand thus also contain its frequency instabilities. Such frequency changes occurring at the receiving and transmitting end are unwanted since they result in a mismatch of the signals to the filtering (at the receiving end) in the signal conversion circuit <b>3</b> and, respectively, to the traffic channel frequency assigned (at the transmitting end). In both cases, effective bandwidth losses occur and increased inter-channel cross-talk may occur.

Frequency drifts of the oscillator frequency f_ozare corrected via the control input <b>9</b> of the VCO <b>8</b>. In the case of a mobile radio application, it can be performed, for example, during the frequency correction of the VCO <b>8</b>, which is necessary in any case, for taking into consideration the Doppler frequency shift between transmitted and received radio waves. For this purpose, the base station radiates at regular time intervals (for example every 47 ms), a frequency correction burst (FCB) in the form of a sinusoidal oscillation. The FCB is searched for, in a manner not shown in greater detail, in the radio-frequency stage <b>11</b> with a frequency pattern (for example 20 kHz spacing). The frequency standard can be determined with the accuracy of the spacing by tuning to the pattern frequency having the maximum received FCB signal strength. The oscillator frequency f_ozis then suitably corrected via a control voltage signal output by the radio-frequency section <b>11</b> and supplied to the control input <b>9</b> of the VCO <b>8</b>.

The frequency noise of the VCO <b>8</b> is component-related and is mainly generated in a reference oscillator which can be considered to be the resonator of the VCO <b>8</b>.

If maximum freedom from noise is required from the VCO <b>8</b>, (expensive) hybrid components must be used for the VCO <b>8</b> or its reference oscillator. According to the invention, however, the entire VCO <b>8</b> is constructed integrally in the IC <b>1</b> with the exception of an oscillating crystal <b>800</b>. As a result, a compromise between lower frequency noise and inexpensive construction is achieved which, in practice, is advantageous for a large number of applications.

<figref idref="DRAWINGS">FIG. 2</figref> shows by way of example a circuit diagram of the VCO <b>8</b> which is here configured in the form of PLL control loop.

The VCO <b>8</b> exhibits the aforementioned reference oscillator <b>80</b>, a controller <b>81</b>, a tracking oscillator <b>82</b>, a phase detector <b>83</b> and a comparison circuit <b>84</b>. The comparison circuit <b>84</b> is supplied with an output voltage signal of the phase detector <b>83</b> and a control voltage signal present at the control input <b>9</b>. From these two voltage signals, the comparison circuit <b>84</b> determines, for example by subtraction, a control error signal which is conducted to the controller <b>81</b>. The controller <b>81</b> controls, depending on the control error signal, the voltage controlled oscillator <b>82</b> which then generates a voltage signal U_ozwith the oscillator frequency f_oz. The PLL control loop is closed by the phase detector <b>83</b> which determines the phase shift between a voltage signal U_sat the frequency f_s, which is accepted by the reference oscillator <b>80</b>, and the voltage signal U_ozof the oscillator frequency f_oz, and returns this as an output voltage signal to the comparison circuit <b>84</b> as described.

<figref idref="DRAWINGS">FIG. 3</figref> shows a circuit diagram of the reference oscillator <b>80</b>. The circuit configuration of the reference oscillator <b>80</b> is known and is called a “Hartley Oscillator” in the art. It has an inductance L and a capacitor C which is connected in parallel with the inductance L. An oscillating crystal <b>800</b> connected in a positive feedback circuit to a transistor T is used as the resonator <b>800</b>. An adjustable capacitor C_sis connected in series with the oscillating crystal <b>800</b> and a resistor R is connected to a transistor T. According to the line drawn dot-dashed etc., and representing the extent of IC <b>1</b>, the inductance L, the transistor T, the adjustable capacitor C_sand the resistor R are constructed integrally in IC <b>1</b>, where the oscillating crystal <b>800</b> is not an integral element of IC <b>1</b>.