Technique to stabilize the chrominance subcarrier generation in a line-locked digital video system

FIELD OF THE INVENTION

0001The present invention relates to the field of line-locked video systems. More particularly, the present invention relates to the field of correcting phase shift in a chrominance subcarrier caused by the system in the process of genlocking.

BACKGROUND OF THE INVENTION

0002A line-locked video system is a digital system that acquires a line-by-line analog signal. An example of such a system would be a video decoder. Each line signal acquired by the system contains a synchronizing pulse and a “color burst,” neither of which carry information that is displayed on the screen. The synchronizing pulse is utilized so that a genlock PLL can locate the analog signal and lock onto it. The “color burst” is a series of eight cycles at the subcarrier frequency which appear in blanking intervals for synchronizing the television receiver to the chrominance signal. The display portion of the signal is transferred after both the synchronizing pulse and the “color burst” portion of the signal. Due to the continuous changing of the clock(CLK) signal from the genlocking step, disturbance is usually created in the chrominance subcarrier PLL which will result in a phase shift and consequently in color stripe artifact. A more detailed background description is set forth below.

0003The composite video signal contains information which is used by a video system to generate a video picture on a display, monitor or television. Each period, within the horizontal portion of a composite video signal contains information representing one horizontal output line which is to be output on the video display, monitor or television. Each horizontal period includes a horizontal synchronization pulse, a burst signal and a video information signal. In many video transmission systems, color or chrominance information is represented by a particular phase of the chrominance subcarrier signal that is amplitude modulated with color information. The horizontal synchronization pulse is used by a phase-locked loop to synchronize the system for displaying the next horizontal line of video information. The burst signal is used to synchronize the phase and frequency of a local oscillator to that of the encoding oscillator so that color information can be “decoded” into its baseband color differential components.

0004A video picture or frame is made up of a number of horizontal lines included within the video display. To display a video picture or frame the video system begins at the top of the screen and displays the information within the composite video signal one horizontal line at a time. The information for each horizontal line is contained within a horizontal period of the composite video signal. After each horizontal period, the video system moves to the next line and displays the information within the next horizontal period of the composite video system. This continues until the video system reaches the bottom line on the video display. After displaying the video information on the bottom line of the video display, the video system must reset itself to the top of the display in order to begin displaying the next frame. In order to allow the system to reset itself to the top of the video display, a vertical blanking period is included within the composite video signal after the video information for each frame. This vertical blanking period allows the video system to reset to the top of the video display and begin displaying the information for the horizontal lines of the next frame. Therefore, a number of horizontal periods, enough to comprise a frame or screen, are strung together, within the composite video signal. Between each frame, the composite video signal includes a vertical blanking period which allows the video system to perform a vertical reset and prepare to display the next frame by moving back up to the top of the video display.

0005In this type of system, a genlock PLL device is used to lock and align with the synchronizing pulse portion of the signal. In the receiver portion of this system, a chrominance subcarrier PLL is utilized to detect and lock onto the “color burst” portion of the analog signal. These two PLLs share a common CLK signal. When the genlock PLL locks and aligns the video signal, the CLK is adjusted accordingly. Because of this arrangement, the problem which is readily encountered is a phase shift disturbance of the SINE wave in the chrominance subcarrier PLL in the receiver. This disturbance is caused by the simultaneous locking of the genlock device, thereby causing continuous changing of the CLK signal.

SUMMARY OF THE INVENTION

0006The technique described in this patent application, to stabilize the chrominance subcarrier generation in a line-locked digital video system, includes several steps. This technique includes calculating a time shift occurring in an output waveform, converting that time shift into an equivalent phase shift and finally sending a phase correction number to a waveform generator block according to the equivalent phase shift.

0007First, the time shift in the output waveform is calculated. This is done by first calculating a DELT value which is representative of the amount of time the output waveform is shifted.

0008DELT is calculated by multiplying the sum of a sequence of digital numbers outputted by the limiter with the delay value of one delay element. This relationship is given by: <br />DELT=B*TAU<br /> where B is the sum of the limiter outputs and TAU is the delay value of one delay element.

0009Secondly, the average period of the output waveform TAV is calculated. This relationship is given by: <br />TAV=(2^m/F<b>2</b>)*((32−Q)*TAU)<br /> where TAU again is the delay value, F<b>2</b> is the frequency control number from the subcarrier phase locked loop, Q is a representation of the average value of the clockout period and m is the number of bits stored in the register of the waveform generator block.

0010The next step this technique implements is to convert the time shift to an equivalent phase shift of the output waveform or DELP. This relationship is given by: <br />DELP=Fracof((B*F<b>2</b>)/(2^m*(32−Q)))*360.<br /> this formula, the term Fracof represents the fractional cycle shift.

0011The last step is to send a phase correction number, represented by PHQ to the waveform generator block according to the calculated value of DELP. This relationship is given by: <br />PHQ=Fracof*((−B*F<b>2</b>)/(2^m*(32−Q)))*2^k.<br /> In this representation, the value of k is the number of bits in the loop up table of the waveform generator block. The phase correction number will remove the phase shift from the output waveform for each video line.

BRIEF DESCRIPTION OF THE DRAWINGS

0012<figref idref="DRAWINGS">FIG. 1</figref> illustrates a block schematic diagram of a simplified cable/satellite set top box with an extra analog input including an embodiment of the present invention.

0013<figref idref="DRAWINGS">FIG. 1a</figref> illustrates a block schematic diagram of a digital and analog video mixing scheme including an embodiment of the present invention.

0014<figref idref="DRAWINGS">FIG. 2</figref> illustrates a block schematic diagram of the preferred embodiment of the present invention.

0015<figref idref="DRAWINGS">FIG. 3</figref> illustrates a block schematic diagram of a clock generator circuit of the present invention.

0016<figref idref="DRAWINGS">FIG. 4</figref> illustrates a block schematic diagram of a digital loop filter and a phase accumulator logic of the present invention.

0017<figref idref="DRAWINGS">FIG. 5</figref> illustrates a block schematic diagram of a waveform generator(DDS) of the present invention.

0018<figref idref="DRAWINGS">FIG. 6</figref> illustrates a block schematic diagram of an alternative embodiment of the waveform generator(DDS) of the present invention.

0019<figref idref="DRAWINGS">FIG. 7</figref> illustrates a block schematic diagram of a phase correction block of the present invention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

0020In the preferred embodiment of the present invention, the system shown in <figref idref="DRAWINGS">FIG. 1</figref> represents a simplified cable/satellite set-top box. It consists of a video decoder <b>101</b> which digitizes and conditions the analog input signal, an MPEG decoder <b>102</b> which decompresses the digital cable/satellite video stream, a mixing/overlay circuitry <b>103</b> which combines the two for picture-in-picture, overlaying menus, fading, etc., or simply switches from one to the other, and finally a digital video encoder <b>104</b> which takes the combined digital output of the overlay circuitry <b>103</b>, converts it into the analog composite video format, which is then sent to a display unit <b>105</b>. The system clock for the overlay circuitry <b>103</b>, the digital video encoder <b>104</b> and the back-end of the MPEG decoder <b>102</b> is provided by the genlock circuitry embedded inside the video decoder. Before any mixing can be performed of the digital MPEG stream and the digitized analog video, the two must be synchronized horizontally and vertically.

0021In a line-locked system this is achieved by letting the genlock circuitry modulate the system clock until the video decoder <b>101</b>, MPEG decoder <b>102</b> and the digital video encoder <b>104</b> are all lined-up with the analog source. Strictly speaking, locking of the encoder is usually done through the horizontal and vertical sync and locking of the decoder to the analog source is done by modulating the system clock. With a noisy analog video source such as a VCR, this lock-up process requires continuous adjustments as the time-base of the oncoming video changes. This requires the system clock to be sped up or slowed down as appropriate. The main problem with modulating the clock is in the chrominance subcarrier generation blocks which are used both inside the video decoder <b>101</b> and the digital video encoder <b>104</b>. The one in the video decoder <b>101</b> locks up to the chrominance subcarrier of the received analog video to demodulate the high frequency chrominance into its base-band color difference signals.

0022The chrominance subcarrier generation block in the digital video encoder <b>104</b> does the opposite and modulates the base-band color difference signals into a high frequency chrominance signal. Almost universally, a Direct-Digital-Synthesis (DDS) approach (<figref idref="DRAWINGS">FIG. 6</figref>) is used to generate the chrominance subcarrier in both the video decoder <b>101</b> and the digital video encoder <b>104</b>. In this approach, the frequency and phase of the generated sinusoid waveform is a direct function of the system clock. Therefore, modulations in system clock results in phase shifts in the generated subcarrier waveform. This translates into very objectionable color artifacts, especially at the top of the screen. The subcarrier PLL inside of the video decoder <b>101</b> compensates to some degree for chroma subcarrier phase and frequency drifts due to very slowly varying or steady-state errors in the time base of the oncoming analog video. In that sense, it is beneficial to slave the DDS inside of the digital video encoder <b>104</b> to the one inside of the video decoder <b>101</b>, i.e. force the the same frequency control number F<b>2</b> to both.

0023However, the subcarrier PLL's are designed to have very small bandwidths in order to minimize jitter in the color subcarrier. Therefore, they can not correct color subcarrier phase shifts due to rapid changes in the analog video time base, such as in the case of VCR headswitches or tape wobbles. One potential solution to this problem will be to periodically reset the phase of the subcarrier. This will, however, require a reset signal with a very stable time basis. Since the unstable system clock can not be use, a separate crystal driven reset cirucitry will be needed, thus complicating the overall system.

0024An alternative embodiment is shown in <figref idref="DRAWINGS">FIG. 1</figref> a. Here the mixing is done in the analog domain. There is only one DDS, namely, the one in the video encoder <b>104</b>. The subcarrier PLL is in the genlocking overlay processor <b>106</b>. A phase detector measures the relative phase of the subcarrier coming from the encoder to the one in the analog source. The frequency number F<b>2</b> is dynamically updated (once per line) by the subcarrier PLL and sent to the encoder to lock the two subcarriers. Similar to <figref idref="DRAWINGS">FIG. 1</figref>, a phase correction term is sent to compensate for analog video time base variations.

0025In the preferred embodiment of the present invention, the effect of system clock modulation on the phase of subcarrier generation is calculated and a phase correction term is applied to both the waveform generator block (DDS) inside the video decoder <b>101</b> and the one inside the digital video encoder <b>104</b>. To track slowly varying time base errors, the frequency control number F<b>2</b> from the subcarrier PLL inside of the video decoder <b>101</b> is also sent.

0026Also in the preferred embodiment of the present invention, the clock generator <b>206</b> and the waveform generator <b>216</b> may be located in separate integrated circuits.

0027In such instances, it is desirable to have a technique which will simplify the interface between the two chips and yet continue to remove any phase shifts caused in the output waveform due to the modulation of the CLOCKOUT as a result of time base variations in the video source <b>200</b>. This new technique consists of accurately measuring, for each video line, the amount of phase distortion caused in the OUTPUT WAVEFORM as the time base of the video source <b>200</b> varies and sending once per video line a correction term which will undo this distortion. Since this correction term has to be sent at the low line rate and does not require synchronization to CLOCKOUT, it can be serialized in the serializer <b>219</b> and a single wire between the two chips can be used to serially transmit it once per video line.

0028In order to implement this new technique the architecture shown in FIG. <b>2</b> and <figref idref="DRAWINGS">FIG. 3</figref> is modified such that the amount of time correction made by the digital loop filter <b>214</b> can be computed. Specifically, the digital loop filter <b>214</b> and the phase accumulator logic <b>308</b> are combined into a single block shown in FIG. <b>4</b>.

0029<figref idref="DRAWINGS">FIG. 3</figref> illustrates a block schematic diagram of the clock generator circuit <b>206</b> illustrated in <figref idref="DRAWINGS">FIG. 2. A</figref> group of sixteen delay elements <b>1</b>-<b>16</b> form a ring oscillator <b>300</b>. Thus, the delay elements <b>1</b>-<b>16</b> are series-coupled in a ring such that an output of the last delay element <b>16</b> is coupled to an input of the first delay element <b>1</b>. Preferably, each of the delay elements <b>1</b>-<b>16</b> has an identical throughput delay, one to the other. According to the preferred embodiment, all the delay elements <b>1</b>-<b>16</b> are simultaneously manufactured in a single integrated circuit so that any manufacturing process induced variations in throughput delay will be identical in each of the delay elements <b>1</b>-<b>16</b>. A clock signal CLOCK IN generated by an oscillator <b>302</b> is applied to a first input of a phase comparator <b>304</b> while the output of the last delay element <b>16</b> is coupled to a second input of the phase comparator <b>304</b>. An output DELAY ADJUST of the phase comparator <b>304</b> is coupled to adjust an amount of delay for each delay element <b>1</b>-<b>16</b>. An output of each delay element <b>1</b>-<b>16</b> is coupled to a respective input D₀-D₁₅of a multiplexor <b>306</b>.

0030The oscillator <b>302</b> is preferably a crystal oscillator for ensuring accuracy and stability of the clock signal CLOCK IN and can include a divide-by circuit for reducing the frequency of the clock signal CLOCK IN from the crystal frequency. Therefore, the clock signal CLOCK IN has a precisely controlled frequency. The clock signal CLOCK IN is compared by the phase comparator <b>304</b> to the signal emerging from the last delay element <b>16</b>. The phase comparator <b>304</b> simultaneously adjusts the delay of all the delay elements <b>1</b>-<b>16</b> such that the combined delay for all the delay elements <b>1</b>-<b>16</b> is equal to one cycle of the clock signal CLOCK IN. Therefore, each input D₀-D₁₅of the multiplexor <b>306</b> has the same frequency as the clock signal CLOCK IN, but a unique phase. The last input D₁₅has the same phase as the clock signal CLOCK IN.

0031Because there are sixteen delay elements, sixteen different clock phase signals are available, however, a different number of delay elements can be utilized if desired. Further, if rising and trailing edges are both utilized, then thirty-two different clock phase signals are available. <figref idref="DRAWINGS">FIG. 3</figref> illustrates a phase-locked loop for controlling the delay of the delay elements <b>1</b>-<b>16</b>. It will be apparent that other means may be utilized for controlling the delay of the delay elements <b>1</b>-<b>16</b>, such as a frequency locked loop or a delay locked loop. Referring to <figref idref="DRAWINGS">FIG. 3</figref>, a delay locked loop can be implemented by coupling the input of the first delay element <b>1</b> to the first input of the phase comparator <b>304</b> (along with the clock signal CLOCK IN) rather than coupling the input of the first delay element <b>1</b> to the second input of the phase comparator <b>304</b>.

0032The digital sequence generated by the digital phase detector <b>204</b> represents the time base error associated with a portion of the video signal corresponding to the sync pulse. For each sync pulse the associated error, i.e. the time difference between the actual sync location determined by the video source <b>200</b> and the expected sync location determined by the video timing generator <b>208</b>, is processed in the loop filter and depending on the polarity of the error and the gains used in the loop filter (FIG. <b>4</b>), the CLOCKOUT is sped up or slowed down for an appropriate amount of time. This reduces, and at steady state, eliminates the time base error between the video source <b>200</b> and the video timing generator <b>208</b>. However, since the CLOCKOUT or some integer divisor of the CLOCKOUT is also used in the waveform generator <b>216</b> to synthesize the OUTPUT WAVEFORM, the amount of reduction DELT in the time base error achieved by modulating CLOCKOUT will also cause a shift in the OUTPUT WAVEFORM. In the case where video source <b>200</b> has large time base errors such as a VCR which can have microseconds of error at the beginning of each video field, the phase of the OUTPUT WAVEFORM, which is typically a sine wave with a constant frequency used to demodulate color information (in the case of a decoder) or modulate it (in the case of an encoder), will be randomized. In other words, as the time base errors are corrected, the color shifts will occur, especially at the top of the screen. Similar color shifts will also occur if the genlock circuitry modulates the system clock to track VCR wobbles.

0033The loop filter shown in <figref idref="DRAWINGS">FIG. 4</figref> consists of two paths. In path <b>1</b> (K<b>2</b> path), which contains the blocks <b>401</b>, <b>402</b>, <b>403</b>, <b>404</b>, <b>405</b> and <b>406</b>, the phase errors coming from the digital phase detector <b>204</b> are scaled through multiplication with a constant K<b>2</b>, added to the previous value of the accumulated phase errors and limited to prevent overflow. Hence for a given video line the output of the register <b>404</b> contains the running sum of the timing errors for all the previous lines up to the current line and effectively provides memory to the digital loop filter. Since the output of register <b>404</b> is determined by the sum of phase errors over a long period of time and the loop is closed through the loop filter and the phase accumulator logic in <figref idref="DRAWINGS">FIG. 4</figref>, the CLOCKOUT from the MUX <b>306</b>, the video timing generator <b>208</b>, the digital phase detector <b>204</b>, the output of the register <b>404</b> forms a representation of the average value of CLOCKOUT. The upper u-bits QU go directly to the adder <b>407</b> and constitute the integer part. The lower 1-bits QL go to an accumulator block consisting of adder <b>405</b> and register <b>406</b>. The overflow bit OB of adder <b>405</b> goes to adder <b>407</b>. Therefore, the lower 1-bits QL constitute the fractional part of the representation of the average value of CLOCKOUT period. The number of bits u+1 used to represent the number Q determines how accurately CLOCKOUT can be synthesized using the phase accumulator <b>308</b>, the MUX <b>306</b> and the phases available from the ring oscillator. In our implementation, 20 bits are used to represent Q. The integer part QU uses u=3 bits, while the fractional part QL uses 1=17 bits.

0034Assuming a 16 element ring oscillator driven by a stable external oscillator <b>302</b> as shown in FIG. <b>3</b> and using 16 phases available, the average period of CLOCKOUT is given by: <br />TCLOCKOUT=(32−Q/32)*TCLKIN=((32−Q)/32)*TCLKIN=((32−Q)/32)*32*TAU<br /> where the integer portion of Q is represented in binary as QU(u) QU(u−1), QU<b>0</b>, and the fractional portion of Q is represented in binary as QL(<b>1</b>) QL(1−1), QL<b>0</b>. TAU corresponds to the delay of one delay element which is assumed to be uniform.

0035The number of taps used in the ring oscillator determines the phase granularity of the resulting CLOCKOUT. More taps will give a CLOCKOUT with less jitter. Formula (1) above must be modified appropriately for a ring oscillator using more taps. In one embodiment, FCLKIN=50.625 MHz. This gives TCKLIN=19.75 Ns, TAU=600 Ps. The nominal value for Q=2.00, which gives the nominal FCLOCKOUT=54 MHz.

0036In contrast to the K<b>2</b> path which has memory and holds a representation of the average value of CLOCKOUT, the K<b>1</b> path which consists of <b>408</b>, <b>415</b>, <b>409</b>, <b>410</b> and <b>411</b> has no memory and responds to the instantaneous value of the time base error for a given line. For each video line, the time base error from the digital phase detector <b>204</b> is scaled through multiplication with a constant K<b>1</b>. The output of the multiplier is limited at limiter <b>415</b> such that the amount of time base error that the K<b>1</b> path acts on is restricted to a value which can be corrected in one video line. The resulting number B is loaded into a register <b>409</b>. Then, for each CLOCKOUT the output of the register <b>409</b> is limited at the limiter <b>410</b> to +/−L, the unlimited output is subtracted from the limited output and the result at the output of <b>411</b> is reloaded into register <b>409</b>. This process continues until the output of <b>409</b> becomes less than +/−L. Thus, the sequence of digital numbers at the output of the limiter <b>410</b> will consist of an appropriate number of +/−L's and a last number whose absolute value is less than L such that the sum of all numbers in the sequence adds up to B (e.g., for B=11 and L=2, the sequence will be 2, 2, 2, 2, 2, 1, 0, 0, 0 . . . ). The output of the limiter <b>410</b> is added to the upper bits of Q and the overflow bit OB at the adder <b>407</b>. The result of the addition after being limited at the limiter <b>412</b> to prevent underflow is applied to the phase accumulator which consists of adder <b>413</b> and the register <b>414</b>. The output of register <b>414</b> goes to the ring oscillator and chooses one of the 16 available phases. The limit L is chosen to be the nominal value of the integer part of Q. Therefore, in our implementation, L=2. This means that for L=0, the CLOCKOUT is at its nominal frequency. For L=2, CLOCKOUT will be running approximately 6% faster and for L=−2, it will be running approximately 6% slower.

0037Each number x in the digital sequence at the output of the limiter <b>410</b> will cause the phase accumulator to choose a tap which is x ahead (if x>0) or −x behind (if x<0) of what would have been normally chosen. Since a jump of x taps corresponds to a time shift of x*TAU, the total time shift caused by the K<b>1</b> path will simply be DELT=B*TAU. In the current embodiment, the polarities are adjusted so that B>0 if the sync pulse from the video source <b>200</b> comes sooner than expected and B<0 if the sync pulse comes later than expected. In the former case, the loop filter will cause the CLOCKOUT to speed up and in the latter case it will cause it to slow down. The effect of this speeding up and slowing down of the CLOCKOUT will be to advance or delay the whole constellation of pulses generated by the video timing generator <b>208</b> and in particular the sync pulse by an amount DELT so that the video source <b>200</b> and the video timing generator <b>208</b> can be aligned. For a given timing error on a video line, DELT will depend both on the K<b>1</b> and K<b>2</b> paths. However to maintain loop stability, K<b>1</b>/K<b>2</b> ratio is chosen to be very large (larger than 2¹⁶). That means that the effect of K<b>2</b> path can be to a great extent ignored and the time base correction DELT introduced by the digital loop filter will be determined by the K<b>1</b> path, i.e. mathematically: <br />DELT=B*TAU  (2)<br /> Note that in the current embodiment the limiter <b>410</b> is designed such that an addition of +/−L at the adder <b>407</b> will cause the CLOCKOUT to run about +/−6% of nominal.

0038Time base correction will be performed in the appropriate direction as long as the numbers in the digital sequence at the output of the limiter <b>410</b> are non-zero. In one video line, depending on the video standard there will be a nominal number NN of CLOCKOUT pulses. Since for each CLOCKOUT, there can be a time base correction of L*TAU, the maximum time base correction in one line will be given as NN*L*TAU. For example, in case of NTSC and CLOCKOUT nominally at 54 MHz, the number of CLOCKOUT's per line will be NN=858*4=3432. Thus, with L=2 and TAU=600 ps, the maximum time base correction which can be achieved from the K<b>1</b> path will be 3432*2*600 ps=4.2 us. This limitation is of no serious consequence, since even a very severe head-switch of 12 us can be compensated for in only three lines.

0039Thus, to ensure the validity of equation (2) above, the limiter <b>415</b> must be designed such that its output B is always less than NN*L.

0040Also in the preferred embodiment, the DDS is shown in FIG. <b>5</b>. The frequency number F<b>2</b> is applied to the first input of an adder <b>501</b>. The output of the adder is coupled to a register <b>502</b>. This register is clocked by the signal CLOCKOUT. Contents of the register are coupled to the 2^ndinput of the adder <b>501</b>. Therefore the value of the signal F<b>2</b> is accumulated over time in register <b>502</b> at the rate determined by the signal CLOCKOUT. This generates a series of values in the register <b>502</b> representative of a time base for the periodic signal relative to the signal CLOCKOUT. Note that the adder <b>501</b> is allowed to overflow and therefore the series of values stored in register <b>502</b> are coupled to a Look-up Table (LUT) to transform this periodic sawtooth waveform into a sinusoid wave. The number of bits m stored in register <b>502</b> determines the precision of the average period while the number of bits k in the LUT determines the phase precision in each clock cycle. The average period (TAV) of the OUTPUT WAVEFORM is thus given by: <br />TAV=(2^m/F<b>2</b>)*TCLOCKOUT  (3)

0041As can be seen in formula (3), the OUTPUT WAVEFORM period and frequency is a direct function of TCLOCKOUT. As explained above, for a given video line, the difference in the actual sync location and the expected sync location will create an error signal at the output of digital phase detector <b>204</b>. This error signal is applied to the digital loop filter <b>214</b> and causes the signal CLOCKOUT to be sped up or slowed downed. As a result, all of the pulses generated by the video timing generator <b>208</b> are delayed or advanced by an amount DELT depending on the polarity of the error signal. Since CLOCKOUT is also used in the waveform generator <b>216</b>, the OUTPUT WAVEFORM will also be shifted in time domain by an amount equal to DELT.

0042Again, the amount of time DELT the OUTPUT WAVEFORM is shifted is given by Formula (2). Combining Formulas (3) and (1) will produce: <br />TAV=(2^m/F<b>2</b>)*TCLOCKOUT=(2^m/F<b>2</b>)*(32−Q)*TAU  (4)<br /> The number of subcarrier cycles during the correction time DELT is given as: <br />NOFC=(DELT/TAV)  (5)

0043Since one full cycle corresponds to 360 degrees of phase shift which is indistinguishable from no phase shift, the effective number of subcarrier cycles shifted is given by the fractional part of NOFSC. For example, for DELT=1.5 us and TAV=279 ns, DELT/TAV=5.37 and the effective number of cycles shifted is 0.37.

0044Since one period TAV of the output waveform corresponds to 360 degrees, a fractional cycle shift will correspond to a phase shift DELP, given as: <br />DELP=Fracof(DELT/TAV)*360=Fracof(B*TAU/((2^m*(32−Q)*TAU)/F<b>2</b>))*360=Fracof(B*F<b>2</b>/(2_m*(32−Q)))*360  (6)

0045It is possible to correct for DELP by sending a correction term PHQ with the required resolution. Since the inherent phase resolution in the OUTPUT WAVEFORM is determined by k (number of bits in LUT), the current embodiment uses k bits of accuracy in the correction term PHQ. Note that theoretically up to m bits of accuracy is possible.

0046First, the waveform generator <b>216</b> is modified as in FIG. <b>6</b>. The correction term is calculated by observing the fact that a PHQ of 2^kadded through <b>602</b> for one CLOCKOUT cycle will shift the OUTPUT WAVEFORM phase by 360 degrees. Hence, to undo a phase shift of DELP, one can send a correction therm PHQ which will shift the OUTPUT WAVEFORM by −DELP. Then, <br />PHQ=(−DELP*2^k)/360=Fracof((−B*F<b>2</b>)/(2^m*(32−Q)))*2^k  (7)

0047A possible implementation of the correction term PHQ is done in the phase correction block in FIG. <b>7</b>. If the result of the division at the output of <b>705</b> is expressed in binary, the first k-bits before the decimal point will form PHQ. Since the PHQ term will have to be calculated only once per video line, the multipliers and divider shown in <figref idref="DRAWINGS">FIG. 7</figref> can have more than one clock cycle to finish the computation and can be implemented serially thereby reducing hardware complexity. In the current embodiment serial multiplier and dividers are used. For each line they compute PHQ before the start of chrominance subcarrier. That gives them about 5 us to finish the computation from the beginning of the line to the start of burst. The k-bits that form the phase correction term PHQ can be sent in parallel form to a waveform generator if it resides in the same circuit with the phase correction block, as will be the case with a video decoder. Otherwise, it can be serialized in the serializer <b>219</b> and sent to a second circuit which has its own waveform generator, as will be the case with a digital video encoder.

0048It will be readily apparent to one skilled in the art that other various modifications may be made to the preferred embodiment without departing from the spirit and scope of the invention as defined by the appended claims.