USRE40971E

Direct drive programmable high speed power digital-to-analog converter

Claim Score by NHIP

Abstract

A current source is provided according to the present invention. The current source includes N current sources configured in a parallel arrangement, wherein N is at least two. Each of the N current sources includes a respective control input. The current source also includes M delay elements. An mth one of the M delay elements includes an input in communication with an m−1th one of the M delay elements. M is equal to N−1, and an output of the mth one of the M delay elements is arranged in communication with the control input of an m+1th one of the N current sources.

USRE40971E, drawing sheet 1 — Sheet 1 of 10

Term

Term ended

Expired 18 December 2020, 5.8 years ago.

73 claims: 14 independent, 59 dependent

1
A current source comprising:N current sources configured in a parallel arrangement, wherein N is at least two, and wherein each of the N current sources includes a respective control input;and M delay elements, an mth one of the M delay elements including an input in communication with an m−1th one of the M delay elements, wherein M is equal to N−1, and wherein an output of the mth one of the M delay elements is arranged in communication with the control input of an m+1th one of the N current sources, wherein the M delay elements comprise at least one delay lock loop.
8
Broadest claimClaim Score 69, broad(NHIP)A current source comprising:N means for providing current configured in a parallel arrangement, wherein N is at least two, and wherein each of the N current providing means includes a respective means for inputting;and M means for delaying, an mth one of the M delaying means including means for inputting in communication with an m−1th one of the M delaying means, wherein M is equal to N−1, and wherein means for outputting of the mth one of the M delaying means is arranged in communication with the inputting means of an m+1th one of the N current providing means, wherein the M delaying means comprise at least one delay lock loop.
13
An apparatus comprising:N current sources configured in a parallel arrangement, wherein N is at least two, and wherein each of the N current sources includes a respective control input and a respective biasing input;and a biasing generator in communication with each of said biasing inputs of the N current sources;an apparatus input in communication with the control input of a first one of the N current sources;and M delay elements, an mth one of the M delay elements including an input in communication with an m−1th one of the M delay elements, wherein M is equal to N−1, and wherein an output of the mth one of the M delay elements is arranged in communication with the control input of an m+1th one of the N current sources, and wherein the first one of the M delay elements is in communication with the apparatus input, wherein the M delay elements comprise at least one delay lock loop.
22
An apparatus comprising:N means for providing current configured in a parallel arrangement, wherein N is at least two, and wherein each of the N current providing means includes respective means for inputting control signals and respective means for inputting biasing signals;means for biasing in communication with each of said biasing inputting means of the N current providing means;apparatus means for inputting signals in communication with the means for inputting control signals of a first one of the N current providing means;and M means for delaying, an mth one of the M delaying means including an input in communication with an m−1th one of the M delaying means, wherein M is equal to N−1, and wherein an output of the mth one of the M delaying means is arranged in communication with the control input of an m+1th one of the N current providing means, and wherein a first one of the M delaying means is in communication with the apparatus means for inputting signals, wherein the M delaying means comprises at least one delay lock loop.
31
An electrical circuit comprising:N transistor pairs configured in a parallel arrangement, where N comprises the total number of transistor pairs, wherein each of the transistor pairs comprises a first transistor in communication with a second transistor;a biasing transistor in communication with each of the first transistors of the N transistor pairs;a circuit input in communication with the second transistor of a first one of the N transistor pairs;an output in communication with each of the first transistors of the N transistor pairs;and M delay elements, an mth one of the M delay elements including an input in communication with an m−1th one of the M delay elements, wherein M is equal to N−1, and wherein an output of the mth one of the M delay elements is arranged in communication with an m+1th one of the N transistor pairs, and wherein a first one of the M delay elements is in communication with the circuit input, wherein the M delay elements comprise at least one delay lock loop.
37
An electrical circuit comprising:N means for providing current configured in a parallel arrangement, where N comprises the total number of current providing means, wherein each of the current providing means comprises first means for supplying current in communication with second means for supplying current;means for biasing in communication with each of the first means for supplying current of the N current providing means;circuit means for inputting signals in communication with the second means for supplying current of a first one of the N current providing means;means for outputting signals in communication with each of the first means for supplying current of the N current providing means;and M means for delaying, an mth one of the M delaying means including means for inputting in communication with an m−1th one of the M delaying means, wherein M is equal to N−1, and wherein outputting means of the mth one of the M delaying means is arranged in communication with an m+1th one of the N current providing means, and wherein a first one of the M delaying means is in communication with the circuit inputting means, wherein the M delaying means comprise at least one delay lock loop.
43
A method comprising the steps of:providing N transistor pairs configured in a parallel arrangement, where N comprises the total number of transistor pairs, wherein each of the transistor pairs comprises a first transistor in communication with a second transistor;biasing each of the first transistors of the N transistor pairs;inputting a signal to the second transistor of a first one of the N transistor pairs;outputting signals from each of the first transistors of the N transistor pairs;and providing M delay elements, an mth one of the M delay elements including an input in communication with an m−1th one of the M delay elements, wherein M is equal to N−1, and arranging an output of the mth one of the M delay elements in communication with an m+1th one of the N transistor pairs, and wherein a first one of the M delay elements is in communication with the input signal, wherein the M delay elements comprise at least one delay lock loop.
49
Digital-to-analog conversion apparatus, comprising:structure providing a multilevel digital control signal so that each level has a substantially similar bandwidth;a plurality of parallel digital-to-analog converters, each receiving a level of the provided multilevel digital control signal, each digital-to-analog converter converting the received level of the digital control signal into an analog signal;and structure combining outputs of said plurality of parallel digital-to-analog converters, further comprising a plurality of low pass filter respectively coupled to outputs of said plurality of parallel digital-to-analog converters.
53
Apparatus for converting a multilevel digital control signal into an analog signal, comprising:means for providing the multilevel digital control signal where each level has a substantially similar bandwidth;a plurality of digital-to-analog conversion means, coupled to said means for providing such that each digital-to-analog conversion means receives a different level of the multilevel digital control signal, each of said plurality of digital-to-analog conversion means converting the received level into an analog signal;means for combining the converted analog signals from said plurality of digital-to-analog conversion means, to form an analog output signal;and a plurality of low pass filter means respectively coupled to outputs of said plurality of digital-to-analog conversion means.
56
A direct drive programmable high speed power digital-to-analog converter comprising:a first digital to analog converter responsive to a first control signal;a second digital to analog converter response to a second control signal;a voltage buffer responsive to said first and second digital to analog converters to provide an analog output;a decoder to provide the first control signal to said first digital to analog converter and the second control signal to the second analog to digital converter, wherein the first digital to analog converter is activated in response to the first control signal, wherein the second digital to analog converter is activated in response to the second control signal, wherein said first and second control signals determine a slew rate of the analog output.
61
A direct drive programmable high speed power digital-to-analog converter comprising:a first digital to analog converter responsive to a first control signal;a second digital to analog converter response to a second control signal;a voltage buffer responsive to said first and second digital to analog converters to provide an analog output;a decoder to select any combination of said first and second digital to analog converters, wherein said first and second control signals determine a slew rate of the analog output, further comprising first and second low pass filters, wherein said first low pass filter is responsive to said first digital to analog converter and said voltage buffer is responsive to said first low pass filter, and wherein said second low pass filter is responsive to said second digital to analog converter and said voltage buffer is responsive to said second low pass filter.
62
A direct drive programmable high speed power digital-to-analog converter comprising:first digital to analog converter means responsive to a first control signal for generating a first signal having a first output level;second digital to analog converter means responsive to a second control signal for generating a second signal having a second output level;a voltage buffer responsive to said first and second signals for providing an analog output;decoding means for providing the first control signal to said first digital to analog converter means and the second control signal to the second analog to digital converter means, wherein the first digital to analog converter means is activated in response to the first control signal, wherein the second digital to analog converter means is activated in response to the second control signal, wherein said first and second control signals determine a slew rate of the analog output.
67
A direct drive programmable high speed power digital-to-analog converter comprising:first digital to analog converter means responsive to a first control signal for generating a first signal having a first output level;second digital to analog converter means responsive to a second control signal for generating a second signal having a second output level;a voltage buffer responsive to said first and second signals for providing an analog output;decoding means for selecting any combination of said first and second digital to analog converter means, wherein said first and second control signals determine a slew rate of the analog output, further comprising first and second low pass filter means for low pass filtering said first and second digital to analog converter means, and wherein said voltage buffer is responsive to said first and second low pass filter means.
68
A method for converting a digital signal to an analog signal comprising the steps of:(a) converting a digital signal to a first analog signal in response to a first control signal, the first analog signal having a first output level;(b) converting a digital signal to a second analog signal in response to a second control signal, the second analog signal having a second output level;(c) summing the first and second analog signals for providing an analog output;(e) decoding an input to generate the first and second control signals;(e) ( f ) activating step (a) in response to the first control signal;and (f) ( g ) activating step (b) in response to the second control signal;( h ) filtering the analog output to provide a filtered output;and ( i ) voltage buffering the filtered output, wherein said first and second control signals determine a slew rate of the analog output.

Independent claims14

53 paragraphs in 5 sections, as filed

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates generally to signal processing and signal waveshaping. More particularly, the present invention relates to signal processing and signal waveshaping of digital-to-analog converters.

Digital-to-analog conversion involves the process of converting digital codes into a continuous range of analog signal levels (voltage or current), for example, as discussed in Chapter 31, “D/A and A/D Converters” of The Electrical Engineering Handbook, ed. Richard C. Dorf, CRC Press 1993, the contents of which are hereby incorporated by reference. A digital-to-analog converter (hereinafter a DAC) is generally an electronic circuit that receives an n-bit codeword from an interface and generates an analog voltage or current that is proportional to the codeword.

One example of a DAC is discussed in U.S. Pat. No. 5,663,728, entitled A Digital-To-Analog Converter (DAC) and Method that set Waveform Rise and Fall Times to Produce an Analog Waveform that Approximates a Piecewise Linear Waveform to Reduce Spectral Distortion, issued on Sep. 2, 1997, the contents of which are hereby incorporated by reference. The DAC of the U.S. Pat. No. 5,663,728 patent employs a waveform shaping circuit to control the rise and fall times of each component waveform so that the analog waveform rising and falling edges settle to within a desired error bound of a linear output ramp.

U.S. Pat. No. 5,936,450, entitled A Waveshaping Circuit Using Digitally Controlled Weighted Current Summing, issued on Aug. 10, 1999, the contents of which are hereby incorporated by reference, discloses a waveshaping circuit. The waveshaping circuit of the U.S. Pat. No. 5,936,450 patent includes a controller and a current summing circuit controlled by the controller. The current summing circuitry selectively sinks combinations of component currents in response to a sequence of control signal sets to generate an output current signal having a desired waveform.

Many DACs attempt to generate desired signal waveform in response to a digital signal. For the purposes of this discussion, a signal output may include the output of a DAC and/or the output of one or more signal components within a DAC. For example, a signal component may correspond to an individual bit of a codeword. One conventional method generates a signal output with a slew rate controlled current source, as shown in FIG. 1. The voltage V measured across a resistor R is shown in FIG. 2. The waveform V includes sharp transition areas (e.g., corners) 1, 2 and 3, which may introduce electromagnetic interference. Such interference may inhibit accurate signal processing.

Another circuit which generates an output signal employs a current mirror 10 having an RC filter, as illustrated in <figref idref="DRAWINGS">FIG. 3. A</figref> current source 1 drives the current mirror 10. Current mirror 10 includes a first transistor 11 and a second transistor 12. Transistors 11 and 12 are preferably CMOS transistors. The first transistor 11 includes gate-to-drain feedback, and is coupled to transistors 12 through the RC filter. The RC filter limits rise and fall times of the input signal I. However, the R and C components are typically process and/or temperature dependent. Such dependence causes variation in the output waveform as shown in FIG. 4. The dashed lines in <figref idref="DRAWINGS">FIG. 4</figref> represent arbitrary output responses due to temperature and/or process variation. A stable output signal is difficult to obtain with such a circuit.

<figref idref="DRAWINGS">FIG. 5</figref> depicts a D/A circuit employing a DAC32, a low pass filter 34, a voltage buffer 36, a transistor 38, and a resistor 39. Each level of a multilevel input signal is provided to DAC 32 for conversion to an analog signal. The LPF34 then determines the rise time of the output of the DAC 32, and the output is passed to voltage buffer 36. This construction presents two problems. First, the R and C values of LPF34 will vary with temperature and process variations, and the output signal will have a poor waveshape where the rise times are not constant. Second, since all input current is passed through the same DAC, and since bandwidth is a function of current level, each level of the multilevel signal will present a different rise time.

These signal processing problems are not adequately addressed in the art. Accordingly, there is a need for a current source to control an output signal which is independent of temperature and process considerations. There is also a need for a DAC to generate a signal having selectable transition areas (corners). There is a further need of a circuit to generate desirable waveshapes.

SUMMARY OF THE INVENTION

The present invention addresses these signal processing problems by providing a circuit to generate a desired output signal. The present invention also provides a DAC for converting a digital signal into an analog signal with a desirable waveshape.

According to a first aspect of the present invention, a current source includes N current sources configured in a parallel arrangement, wherein N is at least two. Each of the N current sources includes a respective control input. The current source includes M delay elements, with an mth one of the M delay elements including an input in communication with an m−1th one of the M delay elements. M is equal to N−1, and an output of the mth one of the M delay elements is arranged in communication with the control input of an m+1th one of the N current sources.

According to another aspect of the present invention, an apparatus includes N current sources configured in a parallel arrangement, wherein N is at least two. Each of the N current sources includes a respective control input and a respective biasing input. The apparatus also includes a biasing generator in communication with each of the biasing inputs of the N current sources, an apparatus input in communication with the control input of a first one of the N current sources, and M delay elements, with an mth one of the M delay elements including an input in communication with an m−1th one of the M delay elements. M is equal to N−1, and an output of the mth one of the M delay elements is arranged in communication with the control input of an m+1th one of the N current sources. The first one of the M delay elements is in communication with the apparatus input.

A method of supplying current is provided according to still another aspect of the present invention. The method includes the steps of: (i) arranging first through n current sources in a parallel arrangement, where n comprises the total number of current sources, and wherein the first current source supplies a first current and the second through n current source respectively supplies second through n currents; and (ii) delaying the second through n currents each with respect the first current.

These and other objects, features and advantages will be apparent from the following description of the preferred embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be more readily understood from a detailed description of the preferred embodiments taken in conjunction with the following figures.

<figref idref="DRAWINGS">FIG. 1</figref> is a diagram of a conventional circuit, which includes a slew rate controlled current source.

<figref idref="DRAWINGS">FIG. 2</figref> is a graphical depiction of a waveshape corresponding to an output of the <figref idref="DRAWINGS">FIG. 1</figref> circuit.

<figref idref="DRAWINGS">FIG. 3</figref> is a view of a conventional circuit including a current mirror having an RC filter.

<figref idref="DRAWINGS">FIG. 4</figref> is a graphical depiction of a waveshape corresponding to an output of the <figref idref="DRAWINGS">FIG. 3</figref> circuit.

<figref idref="DRAWINGS">FIG. 5</figref> is a schematic block diagram of a D/A circuit.

<figref idref="DRAWINGS">FIG. 6</figref> is a graphical depiction of a waveshape having smooth transition areas.

<figref idref="DRAWINGS">FIG. 7</figref> is a circuit diagram of a current source according to the present invention.

<figref idref="DRAWINGS">FIG. 8</figref> is a graphical depiction of current components of the current source illustrated in FIG. 6.

<figref idref="DRAWINGS">FIG. 9</figref> is a graphical depiction of a resultant output waveshape from the current source illustrated in <figref idref="DRAWINGS">FIGS. 6 and 7</figref>.

<figref idref="DRAWINGS">FIG. 10</figref> is a graphical depiction of a waveform template, and a waveshape that fits within the template.

<figref idref="DRAWINGS">FIG. 11</figref> is a circuit diagram of a current source according to the present invention.

<figref idref="DRAWINGS">FIGS. 12a-12c</figref> are graphical depictions of waveshapes generated by the current source of FIG. 10.

<figref idref="DRAWINGS">FIG. 13</figref> is a circuit diagram of a current source according to the present invention.

<figref idref="DRAWINGS">FIG. 14</figref> is a circuit diagram of a current source having variable delay elements according to the present invention.

<figref idref="DRAWINGS">FIG. 15a</figref> is a graphical depiction of a waveform generated with uniform delay element.

<figref idref="DRAWINGS">FIG. 15b</figref> is a graphical depiction of a waveform generated with non-uniform delay element.

<figref idref="DRAWINGS">FIG. 16</figref> is a circuit diagram of a current source including a plurality of differential transistor pairs according to the present invention.

<figref idref="DRAWINGS">FIG. 17</figref> is a circuit diagram of an alternative embodiment according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will be described with respect to circuits and methods for shaping waveforms, and in particular, to a digital-to-analog converter (DAC) employing such a waveshaping circuit. However, as will be appreciated by those skilled in the art, the present invention is not limited to applications involving DACs, but also may be applied to other applications, such as signal processing, systems to control signal rise/fall time, signal storage, communications, etc. Moreover, while the present invention is particularly suited to applications in the read channel of a hard disk drive, many other applications will suggest themselves to persons of skill in the electrical engineering arts. Furthermore, the present invention is particularly suitable for use with the structure described in U.S. patent application Ser. No. 09/737743, entitled “Active Replica Transformer Hybrid”, filed concurrently herewith, the contents of which are incorporated herein by reference.

<figref idref="DRAWINGS">FIG. 6</figref> illustrates a desired signal output 20. The output waveform 20 includes smooth transition areas, which reduce noise such as electromagnetic interference. A preferred rise time (“Tr”) for a DAC is 3-5 nanoseconds (ns).

The present invention generates a signal to approximate the desired signal output 20 with a current source 30. As shown in <figref idref="DRAWINGS">FIG. 7</figref>, current source 30 includes a plurality of current sources. For example, current source 30 may include current sources I1, I2, I3 and I4. Current sources I1, I2, I3 and I4 each preferably generate a respective current In, where n is 1, 2, 3 or so forth. The signals In are preferably equal in magnitude and form, and may include a signal delay. In the <figref idref="DRAWINGS">FIG. 7</figref> example, current sources In each generate a linear ramp. For example, consider a signal I1, which includes a linearly rising edge starting at time t0. Current I2 mirrors current I1, except that I2 includes a linearly rising edge starting at time t0+Δt. The variable Δt represents an amount of delay time. Current I3 mirrors currents I1 and I2, except that current I3 includes a linearly rising edge starting at time t0+2Δt. Similarly, current I4 mirrors currents I1, I2, and I3, except that its linearly rising edge starts at time t0+3Δt. The relative waveform components for currents I1, I2, I3 and I4 are shown in FIG. 8.

Currents I1, I2, I3 and I4 are summed (or mixed) to produce a resultant waveform I0 as shown in FIG. 9. Waveform I0 approximates the desired output signal shown in FIG. 6. Like the desired output signal of <figref idref="DRAWINGS">FIG. 6</figref>, waveform I0 has many desirable properties. For example, I0 has selectable transition areas (corners). The transition areas can be smooth, or sharp, by selectively adjusting the length of Δt. Also, waveform I0 accommodates arbitrary rise/fall times.

The waveform I0 can also be adjusted by varying Δt to fit within specified requirements. For example, with reference to <figref idref="DRAWINGS">FIG. 10</figref>, waveform I0 can be adjusted to fit within a template 40, for example, as provided by the IEEE standard waveform shape. In this example, I0 has been optimized to produce low electromagnetic interference and to fit within the IEEE template 40.

The delay variable Δt is preferably controlled using a delayed-lock loop or is controlled by reference to an external clock. As such, Δt can be precisely regulated. A waveform which is independent of temperature and/or process considerations can then be generated.

The generation of a linear ramp is explained with reference to <figref idref="DRAWINGS">FIGS. 11-13</figref>. A signal is produced from current source 50, which includes a plurality of current sources I1 through In. Each of the plurality of current sources generates a replica signal I. In this example, input signal I is preferably a square waveform. The signal I is delayed by Δt from each subsequent current source, after the initial current source I1. For example, I2 is delayed by Δt, and In is delayed by n−Δt. The currents are summed (or mixed) in a known manner to produce an output which approximates a linear ramp.

With reference to <figref idref="DRAWINGS">FIG. 12a</figref>, the signal components of the individual current sources are relatively illustrated. <figref idref="DRAWINGS">FIG. 12b</figref> illustrates the resultant waveshape I0, which includes a stair-step pattern. A linear ramp, as shown in <figref idref="DRAWINGS">FIG. 12c</figref>, is approximated as the length of the delay variable Δt is decreased.

A circuit diagram of the current source 50 is shown in FIG. 13. Current source 50 includes a plurality of transistor pairs 52-56, where pair 56 represents the nth transistor pair. With reference to <figref idref="DRAWINGS">FIG. 13</figref>, a current source 51 drives transistor pair 52. Transistor pair 52 includes a transistor 52a communicating with a transistor 52b. Transistor 52a is preferably configured with gate-to-drain feedback. The gate of transistor 52b is biased so as to operate in an “on” state. The gate/drain of transistor 52a communicates with the gates of transistors 53a, 54a, 55a and 56a. The drains of transistors 53a-56a each communicates with an output Io. The gates of transistors 53b-56b each communicates with an input waveform Iin (e.g., a square signal), some through delay elements. For example, the gate of transistor 54b communicates with waveform Iin through delay element d1. The gate of transistor 55b communicates with waveform Iin through delay element d2 and delay element d1. Similarly, the gate of transistor 56b communicates with waveform Iin through each of the delay elements d1 through dn. In the preferred embodiment, each of delay elements d1-dn delays the signal by Δ. Delay elements can be realized via known delay locked loops.

The operational aspects of <figref idref="DRAWINGS">FIG. 13</figref> are now even further explained. Initially, waveform Iin is communicated to the gate of transistor 53b, which turns on the transistor pair 53. A signal I1, which is proportional to the waveform Iin, is output at Io. Waveform Iin is also communicated to delay element d1, which delays the waveform by Δ seconds. After Δ seconds, delay element d1 communicates the delayed waveform to the gate of 54b, which turns on the transistor pair 54. A signal I2, which is proportional to lin, is output at Io. The resultant waveform Io includes the sum (or mixture) of signals 11 and 12. The input waveform Iin is respectively delayed before communicating with the gates of transistors 55b and 56b. Transistor pairs 55 and 56 are activated (e.g., turned on) and respectively supply current 13 and In, which are added to the resultant waveform I. The current source 50, as shown in <figref idref="DRAWINGS">FIG. 11</figref>, is therefore realized.

There are many advantages of the configurations shown in <figref idref="DRAWINGS">FIGS. 11 and 13</figref>. For example, individual current sources (e.g., In) can be turned on/off on demand, particularly since Vgs is large and constant. Also, the current source 50 will generally consume less power than the current mirror shown in <figref idref="DRAWINGS">FIG. 3</figref>, particularly since a current mirror typically employs a DC bias. An additional advantage is that with a small Iin, the VGS voltage is also small (e.g., close to the threshold voltage VT). In such a case, VGS-VT-VDS equals a small number of current sources with negative VDS.

A further current source 60 is shown in FIG. 14. The current source 60 is configured in the same manner as the current source 50 shown in <figref idref="DRAWINGS">FIG. 13</figref>, except that the delay elements may include variable delays. The same components with respect to <figref idref="DRAWINGS">FIG. 13</figref> are labeled with their same reference numerals in FIG. 13. In the <figref idref="DRAWINGS">FIG. 14</figref> embodiment, delay elements Δ are non-uniform throughout the circuit. For example, Δ may involve a longer delay than Δn−1, and so forth. Non-uniform delays may be employed to generate a smooth waveform. Multiple delay-locked-loops are preferably used to achieve different delay times.

To illustrate, an output waveform processed with uniform delay elements is shown in FIG. 15a. Here a stair step waveform is produced, which may approximate a linear ramp, particularly as the variable Δ is decreased in length (e.g., time). In contrast, the amount of delay is varied with respect to individual delay elements as shown in FIG. 15b. The approximated waveshape of <figref idref="DRAWINGS">FIG. 15b</figref> is smooth (e.g., includes smooth transition areas) in comparison to the approximated linear waveshape of FIG. 15b. Seven steps (or corresponding current sources) are employed in a preferred embodiment for a Gigabit channel. Of course, the number of levels may be varied according to need or design without deviating from the scope of the present invention.

A further embodiment of a current source is illustrated in FIG. 16. The illustrated current source 70 includes a plurality of differential transistor pairs 72-74, where 74 represents the nth differential transistor pair. A bias current IB is supplied to the gate of transistors 72c, 73c and 74c. An input waveform Iin is communicated to the gates of 72a, 72b, 73a, 73b, 74a and 74b. In the case of transistor pair 73 and 74, the input waveform Iin is delayed through delay elements d1 and d1+dn, respectively. Buffers B1-BN are optionally included in the circuit 70 to buffer the input signal Iin. A differential output (Io+, Io−) is accordingly produced.

The advantages of the <figref idref="DRAWINGS">FIG. 16</figref> current source include constant power dissipation. Also, the circuit provides matching capabilities, for example, for use in an Ethernet channel.

One drawback of the differential amplifier in <figref idref="DRAWINGS">FIG. 16</figref> is that the differential amplifier is a Class A circuit which consumes unnecessary power even when no output is being transmitted. Moreover, a significant number of transistors is required to provide an adequately smoothed output current, thus requiring a large chip area. <figref idref="DRAWINGS">FIG. 17</figref> depicts a schematic diagram of another embodiment according to the present invention which operates in Class B wherein one DAC is provided for each level of the multilevel input signal. DACs 42, 44, . . . 46 may be provided with corresponding LPFs 43, 45, 4m. Preferably, a circuit according to <figref idref="DRAWINGS">FIG. 13</figref> supplies each DAC with a control current to provide a stair step output which defines the rise time. In such an embodiment, since each DAC receives control current, and not input current, the transistors which supply each DAC may be smaller than those used in the <figref idref="DRAWINGS">FIG. 13</figref> embodiment. Additionally, since the control signal determines the rise time of the output of each DAC, the LPFs merely produce a smoother output.

In <figref idref="DRAWINGS">FIG. 17</figref>, multilevel input signal D0, D1, . . . Dn is provided to the parallel DACs 42, 44, . . . 46. The number of DACs may be varied depending on the application. This embodiment solves two problems. First, by providing the <figref idref="DRAWINGS">FIG. 17</figref> circuit with a staircase waveform , for example, from <figref idref="DRAWINGS">FIG. 14</figref>, an LPF34 merely smoothes the staircase waveform rather than define rise time. Second, since the DACs are disposed in parallel, there will be no variations in rise time because each DAC has substantially the same current passing therethrough; that is there will be no bandwidth variation with resultant differences in rise time. The DACs may also be controlled by any appropriate circuitry, such as a decoder disposed prior to the DACs which would, in effect, select which DACs are activated by proper application of the input signals.

Thus, what has been described are circuits and methods to effectively shape a waveform. Furthermore, digital-to-analog conversion circuits employing such waveshaping circuits, which enhance signal conversion, have been described.

The individual components shown in outline or designated by blocks in the attached drawings are all well-known in the arts, and their specific construction and operation are not critical to the operation or best mode for carrying out the invention.

While the present invention has been described with respect to what is presently considered to be the preferred embodiments, it will be understood that the invention is not limited to the disclosed embodiments. To the contrary, the invention covers various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions. For example, the input signals for <figref idref="DRAWINGS">FIGS. 7</figref>, 11, , 13, 14 and 16 may be varied to produce different output waveforms. Also, the linear ramp produced by the current source of <figref idref="DRAWINGS">FIGS. 11 and 13</figref>, may be even further processed by the current source of <figref idref="DRAWINGS">FIG. 7</figref>, to produce smooth transition areas. Such modifications are within the scope of the present invention. Also, whereas the illustrated transistors are preferably CMOS transistor, n-type or p-type transistors may also be employed with the present invention.

Contents5

Every citation, both waysCites: the store holds 322 of 323

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US3297951A	Cites	United States of America	Applicant
US3500215A	Cites	United States of America	Applicant
US3521170A	Cites	United States of America	Applicant
US3543009A	Cites	United States of America	Applicant
US3793588A	Cites	United States of America	Search report
US3793589A	Cites	United States of America	Applicant
US3973089A	Cites	United States of America	Applicant
US4071842A	Cites	United States of America	Applicant
US4112253A	Cites	United States of America	Applicant
US4131767A	Cites	United States of America	Applicant
US4152541A	Cites	United States of America	Applicant
US4309673A	Cites	United States of America	Applicant
US4321753A	Cites	United States of America	Applicant
US4362909A	Cites	United States of America	Applicant
US4393370A	Cites	United States of America	Applicant
US4393494A	Cites	United States of America	Applicant
US4408190A	Cites	United States of America	Applicant
US4464545A	Cites	United States of America	Applicant
US4503421A	Cites	United States of America	Applicant
US4527126A	Cites	United States of America	Applicant
US4535206A	Cites	United States of America	Applicant
US4591832A	Cites	United States of America	Applicant
US4605826A	Cites	United States of America	Applicant
US4621172A	Cites	United States of America	Applicant
US4621356A	Cites	United States of America	Applicant
US4626803A	Cites	United States of America	Applicant
US4715064A	Cites	United States of America	Applicant
US4727566A	Cites	United States of America	Applicant
US4746903A	Cites	United States of America	Applicant
US4816830A	Cites	United States of America	Applicant
US4817081A	Cites	United States of America	Applicant
US4868571A	Cites	United States of America	Applicant
US4878244A	Cites	United States of America	Applicant
US4888762A	Cites	United States of America	Applicant
US4894820A	Cites	United States of America	Applicant
US4935919A	Cites	United States of America	Applicant
US4947171A	Cites	United States of America	Applicant
US4970715A	Cites	United States of America	Applicant
US4972360A	Cites	United States of America	Applicant
US4988960A	Cites	United States of America	Applicant
US4993045A	Cites	United States of America	Applicant
US4999830A	Cites	United States of America	Applicant
US5018134A	Cites	United States of America	Applicant
US5043730A	Cites	United States of America	Applicant
US5084865A	Cites	United States of America	Applicant
US5119365A	Cites	United States of America	Applicant
US5136260A	Cites	United States of America	Applicant
US5148427A	Cites	United States of America	Applicant
US5153450A	Cites	United States of America	Applicant
US5164725A	Cites	United States of America	Applicant
US5175764A	Cites	United States of America	Applicant
US5185538A	Cites	United States of America	Applicant
US5202528A	Cites	United States of America	Applicant
US5204880A	Cites	United States of America	Applicant
US5212659A	Cites	United States of America	Applicant
US5222084A	Cites	United States of America	Applicant
US5243346A	Cites	United States of America	Applicant
US5243347A	Cites	United States of America	Applicant
US5245231A	Cites	United States of America	Applicant
US5245654A	Cites	United States of America	Applicant
US5248956A	Cites	United States of America	Applicant
US5253249A	Cites	United States of America	Applicant
US5253272A	Cites	United States of America	Applicant
US5254994A	Cites	United States of America	Applicant
US5267269A	Cites	United States of America	Applicant
US5269313A	Cites	United States of America	Applicant
US5272453A	Cites	United States of America	Applicant
US5280526A	Cites	United States of America	Applicant
US5282157A	Cites	United States of America	Applicant
US5283582A	Cites	United States of America	Applicant
US5305379A	Cites	United States of America	Applicant
US5307064A	Cites	United States of America	Applicant
US5307405A	Cites	United States of America	Applicant
US5323157A	Cites	United States of America	Applicant
US5325400A	Cites	United States of America	Applicant
US5357145A	Cites	United States of America	Applicant
US5365935A	Cites	United States of America	Applicant
US5367540A	Cites	United States of America	Applicant
US5375147A	Cites	United States of America	Applicant
US5388092A	Cites	United States of America	Applicant
US5388123A	Cites	United States of America	Applicant
US5392042A	Cites	United States of America	Applicant
US5399996A	Cites	United States of America	Applicant
US5440514A	Cites	United States of America	Applicant
US5440515A	Cites	United States of America	Applicant
US5444739A	Cites	United States of America	Applicant
US5465272A	Cites	United States of America	Applicant
US5471665A	Cites	United States of America	Applicant
US5479124A	Cites	United States of America	Applicant
US5489873A	Cites	United States of America	Applicant
US5507036A	Cites	United States of America	Applicant
US5508656A	Cites	United States of America	Applicant
US5517141A	Cites	United States of America	Applicant
US5517435A	Cites	United States of America	Applicant
US5521540A	Cites	United States of America	Applicant

Showing 100 of 611

26 members in 1 office

This recordMember, by publication datePriority claim

Priority claims6

Priority claims
Document	Office	Kind	Date
73747400	United States of America	A	2000-12-18
73747400	United States of America	A	2000-12-18
22030405	United States of America	A	2005-09-06
09737474	–	–	–
US20000737474	–	–	–
US20050220304	–	–	–

Members26

Family members, oldest first
Document	Office	Kind
US6462688B1	United States of America	B1	2002-10-08
US6775529B1	United States of America	B1	2004-08-10
US6844837B1	United States of America	B1	2005-01-18
US7095348B1	United States of America	B1	2006-08-22
US7113121B1	United States of America	B1	2006-09-26
US7194037B1	United States of America	B1	2007-03-20
US7280060B1	United States of America	B1	2007-10-09
US7312739B1	United States of America	B1	2007-12-25
US7327995B1	United States of America	B1	2008-02-05
US7433665B1	United States of America	B1	2008-10-07
US7466971B1	United States of America	B1	2008-12-16
US7536162B1	United States of America	B1	2009-05-19
US7606547B1	United States of America	B1	2009-10-20
USRE40971EThis record	United States of America	E	2009-11-17
US7649483B1	United States of America	B1	2010-01-19
US2010074310A1	United States of America	A1	2010-03-25
US2010127909A1	United States of America	A1	2010-05-27
US7729429B1	United States of America	B1	2010-06-01
US7761076B1	United States of America	B1	2010-07-20
US7804904B1	United States of America	B1	2010-09-28
USRE41831E	United States of America	E	2010-10-19
US8009073B2	United States of America	B2	2011-08-30
US8045946B2	United States of America	B2	2011-10-25
US8050645B1	United States of America	B1	2011-11-01
US8503961B1	United States of America	B1	2013-08-06
US8880017B1	United States of America	B1	2014-11-04

77 transactions on the USPTO file

Allowed after 4 non-final rejections and 1 final rejection.

Non-final rejections: 4
Final rejections: 1
RCEs: 0
Appeals: 0

Over time

Point at a mark for the transaction

Transactions

Prosecution transactions, newest first
	Event	Code
2009-11-17	Recordation of Patent Grant MailedPGM/	PGM/
2009-10-28	Issue Notification MailedAllowedWPIR	WPIR
2009-10-14	Receipt into PubsR1021	R1021
2009-10-13	Dispatch to FDCD1935	D1935
2009-08-13	Dispatch to FDCD1935	D1935
2009-08-13	Dispatch to FDCD1935	D1935
2009-08-13	Application Is Considered Ready for IssuePILS	PILS
2009-08-12	Issue Fee Payment VerifiedN084	N084
2009-08-12	Issue Fee Payment VerifiedN084	N084
2009-08-12	Issue Fee Payment ReceivedIFEE	IFEE
2009-05-18	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2009-05-15	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2009-03-17	Response after Final ActionA.NE	A.NE
2009-03-17	Request for Extension of Time - GrantedXT/G	XT/G
2009-03-11	Miscellaneous Incoming LetterLET.	LET.
2009-03-10	Date Forwarded to ExaminerFWDX	FWDX
2009-02-11	Oath or Declaration Filed (Including Supplemental)C602	C602
2009-02-11	Response after Final ActionA.NE	A.NE
2008-11-18	Mail Final Rejection (PTOL - 326)Final rejectionMCTFR	MCTFR
2008-11-17	Final RejectionFinal rejectionCTFR	CTFR
2008-11-12	Date Forwarded to ExaminerFWDX	FWDX
2008-10-21	Response after Non-Final ActionA...	A...
2008-07-28	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2008-07-25	Non-Final RejectionNon-final rejectionCTNF	CTNF
2008-06-26	Date Forwarded to ExaminerFWDX	FWDX
2008-05-23	Response after Non-Final ActionA...	A...
2008-05-05	Mail Examiner Interview Summary (PTOL - 413)MEXIN	MEXIN
2008-04-30	Examiner Interview Summary Record (PTOL - 413)EXIN	EXIN
2008-02-28	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2008-02-22	Non-Final RejectionNon-final rejectionCTNF	CTNF
2008-02-05	Date Forwarded to ExaminerFWDX	FWDX
2008-01-11	Response after Non-Final ActionA...	A...
2007-10-11	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2007-10-10	Non-Final RejectionNon-final rejectionCTNF	CTNF
2007-09-06	Date Forwarded to ExaminerFWDX	FWDX
2007-09-04	Response after Non-Final ActionA...	A...
2007-08-01	Mail Examiner Interview Summary (PTOL - 413)MEXIN	MEXIN
2007-07-26	Examiner Interview Summary Record (PTOL - 413)EXIN	EXIN
2007-06-01	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2007-05-26	Non-Final RejectionNon-final rejectionCTNF	CTNF
2007-05-11	Case Docketed to Examiner in GAUDOCK	DOCK
2006-12-06	IFW TSS Processing by Tech Center CompleteTSSCOMP	TSSCOMP
2006-07-05	Paralegal Reissue Review CompletePRIR	PRIR
2006-01-29	Cleared by OIPE CSRL194	L194
2006-01-23	Cleared by OIPE CSRL194	L194
2006-01-23	Cleared by OIPE CSRL194	L194
2006-01-23	Cleared by OIPE CSRL194	L194
2006-01-23	Cleared by OIPE CSRL194	L194
2006-01-21	Cleared by OIPE CSRL194	L194
2006-01-21	Cleared by OIPE CSRL194	L194
2006-01-20	Cleared by OIPE CSRL194	L194
2006-01-12	Information Disclosure Statement consideredIDSC	IDSC
2006-01-12	Information Disclosure Statement (IDS) FiledM844	M844
2006-01-12	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2006-01-11	Information Disclosure Statement consideredIDSC	IDSC
2006-01-11	Reference capture on IDSRCAP	RCAP
2006-01-11	Information Disclosure Statement (IDS) FiledM844	M844
2006-01-11	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2006-01-10	Notice of Reissue Published in Official GazetteNRE.	NRE.
2005-12-12	Application Is Now CompleteCOMP	COMP
2005-12-10	Application Dispatched from OIPEOIPE	OIPE
2005-12-02	Cleared by OIPE CSRL194	L194
2005-11-21	Information Disclosure Statement consideredIDSC	IDSC
2005-11-21	Reference capture on IDSRCAP	RCAP
2005-11-21	Claims PTOCPTO	CPTO
2005-11-21	Preliminary AmendmentA.PE	A.PE
2005-11-21	Miscellaneous Incoming LetterLET.	LET.
2005-11-21	Information Disclosure Statement (IDS) FiledM844	M844
2005-11-21	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2005-11-21	Payment of additional filing fee/PreexamFLFEE	FLFEE
2005-11-21	A statement by one or more inventors satisfying the requirement under 35 USC 115, Oath of the ApplicOATHDECL	OATHDECL
2005-11-21	The identification of one or more legal entities other than the inventor(s), each such legal entityASGMT	ASGMT
2005-11-17	Cleared by OIPE CSRL194	L194
2005-09-17	IFW Scan & PACR Auto Security ReviewSCAN	SCAN
2005-09-13	Notice Mailed--Application Incomplete--Filing Date AssignedINCD	INCD
2005-09-06	Preliminary AmendmentA.PE	A.PE
2005-09-06	Initial Exam Team nnIEXX	IEXX

4 legal events, as the office reported them to INPADOC

Over the term

Point at a mark for the event

Events

Legal events, newest first
	Event	Code
2020-06-16	AssignmentAS	AS
2020-02-20	AssignmentAS	AS
2014-04-08	Fee paymentFPAY	FPAY
2010-04-08	Fee paymentFPAY	FPAY

Direct drive programmable high speed power digital-to-analog converter

Claim Score by NHIP

Abstract