Apparatus for generating target addresses within a circular buffer including a register for storing position and size of the circular buffer

This application is a continuation of application Ser. No. 07/368,365, filed Nov. 2, 1990, now abandoned.

FIELD OF THE INVENTION

The invention relates to the field of digital buffers and, more particularly, to the generation of addresses for accessing digital buffers. Even more particularly, the invention relates to the generation of addresses for accessing circular buffers.

BACKGROUND OF THE INVENTION

Digital information processors frequently employ digital memory buffers to temporarily store information en route to another device such as an input/output device or processor. A buffer may be constructed of dedicated hardware registers wired together or it may simply be a dedicated section of a larger memory. Such digital information buffers can take many forms. One such form is known as a circular buffer. In circular buffers, the addresses for accessing locations in the buffers typically are generated by modifying the contents of a pointer register which is external to the buffer area which points to an address location within the buffer. When that address is needed on the address bus, it is output from the pointer address and the pointer is incremented (or decremented) by a predetermined amount so as to be ready for the next instruction cycle which accesses the circular buffer. In circular buffers, means must be provided for “wrapping” the address around when the increment (or decrement) causes the address in the pointer register to fall without the bounds of the buffer. In other words, means must be provided for causing the address generator for the buffer to generate modulo addresses with the modulus being the length of the buffer.

In circular buffers, software techniques are generally used for the modulo address generation. These software address mapping techniques, however, require several instruction cycles to perform the necessary address comparisons, arithmetic operations and replacement of the pointer register contents. Such software address mapping is not fast enough for certain types of uses. Applications such as digital filters, Fast Fourier transforms, matrix manipulations and other common digital signal processing routines require a very rapid generation of memory references. Accordingly, software modulo address generation can significantly decrease the speed of fast signal processing apparatus. Accordingly, addressing schemes implemented in hardware are sometimes desirable.

One such hardware implemented system is disclosed in U.S. Pat. No. 4,800,524. The apparatus described in U.S. Pat. No. 4,800,524 comprises three registers external to the buffer, including (1) an L register which contains the length of the buffer, (2) an A register which contains the last address accessed in the buffer (this is the pointer register) and (3) an M buffer which contains an increment (or decrement) value to be added (or subtracted) from the A register. The apparatus also comprises two separate adder/subtractors, the first of which generates an absolute buffer address which is simply the contents of the A register added to the contents of the M register and a second adder/subtractor which generates a wrapped address by either adding (if M is positive) or subtracting (if M is negative) from the absolute address generated by the first adder the length of the buffer. Additional logic selects either the absolute address or the wrapped address responsive to the carry bits from the first and second adders. If the carry bits indicate that the absolute address generated is outside the boundaries of the buffer, the wrapped address is used and placed in the A register ready for the next access. Otherwise, the absolute address is selected and placed in the A register. The invention disclosed in the U.S. Pat. No. 4,800,524 patent is limited, however, in that in order for the system of examining the carry bits to work, the lower K bits of the buffer's base address (lowest address) must be zero, where K is the number of bits required to represent the length of the buffer and the length of the buffer must be a power of two. These limitations can be extremely inconvenient in certain applications.

It is one object of the present invention to provide an improved address generator for a circular buffer.

It is a further object of the present invention to provide an address generator for a circular buffer which places no restrictions on the size or the position in memory of the circular buffer.

It is another object of the present invention is to provide an address generator for a circular buffer which is substantially faster than software address generators.

SUMMARY OF THE INVENTION

The address generator of the present invention comprises four registers. In one preferred embodiment, the registers are as follows: <ul id="ul0001" list-style="none"><li id="ul0001-0001" num="0010">1) Base register, B, containing the lowest numbered address in the buffer,</li><li id="ul0001-0002" num="0011">2) an Index pointer register, I, containing the next address to be accessed in the buffer,</li><li id="ul0001-0003" num="0012">3) a Modify register, M, which is loaded with the increment (or decrement) value, and</li><li id="ul0001-0004" num="0013">4) a Length register, L, containing the length of the buffer.</li></ul>

In alternate embodiments, the Base or Length registers, but not both, can be replaced by an End register, E, which contains the highest address in the buffer.

In the preferred embodiment, when the circuit buffer is accessed by an instruction, the contents of the Index register are placed on the address bus and then the Index register is modified so as to be ready for the next access. When the modify value, M, is positive, adder/subtracters calculate the value of I+M (the absolute address) as well as I+M−L, (the wrap address). The output of the adder/subtractor which calculates I+M−L is compared to the output of register B. The output of the adder/subtractor which calculates I+M and the output of the adder/subtracter which calculates I+M−L are also placed as first and second inputs to a multiplexer. The output of the multiplexer is coupled to the input of the I register so as to select one of those two values as the new index value. If I+M−L is greater than or equal to B, the comparator controls the multiplexer to select the I+M−L input as the value to be loaded into the index register. Otherwise, the comparator controls the multiplexer to select the I+M input.

Alternate embodiments are possible where either the Length register or the Base register is replaced by an End register which contains the end value (i.e., the highest numbered address) of the buffer. Slight modification to the adder/subtracter circuitry would be necessary. In addition, any of these embodiments can be further modified for a system in which the modifier M is a negative value or where M may be positive or negative.

BRIEF DESCRIPTION OF THE DRAWING

<figref idref="DRAWINGS">FIG. 1</figref> shows an, exemplary circular buffer.

<figref idref="DRAWINGS">FIG. 2</figref> shows a first embodiment of the address generator of the present invention.

<figref idref="DRAWINGS">FIG. 3</figref> shows a second embodiment of the address generator of the present invention.

<figref idref="DRAWINGS">FIG. 4</figref> shows a third embodiment of the address generator of the present invention.

<figref idref="DRAWINGS">FIG. 5</figref> shows a fourth embodiment of the address generator of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

<figref idref="DRAWINGS">FIG. 1</figref> illustrates a typical circular buffer incorporated as part of a larger memory. The base address of the buffer is the lowest numbered address in the buffer. In the example in <figref idref="DRAWINGS">FIG. 1</figref> this is address <b>20</b>, represented as B in FIG. <b>1</b>. The highest address in the buffer is designated as the end address which in <figref idref="DRAWINGS">FIG. 1</figref> is address <b>39</b> and is indicated as E. A pointer into the buffer typically comprises a register containing the address of the next location in the buffer to be accessed. This register will hereinafter be termed the index register, I. Typically in a circular buffer, after each access, the index pointer is incremented or decremented a predetermined number of addresses so as to be prepared for the next access into the circular buffer. The number of address spaces which the index pointer is incremented or decremented will hereinafter be referred to as the modify amount and is represented in <figref idref="DRAWINGS">FIG. 1</figref> as M. It is common for the modify amount to be a fixed number which never changes. However, there are applications in which the modifier amount, M, may be varied.

As stated above, in a circular buffer, means must be provided for wrapping the index pointer around when the increment amount would cause the index pointer to exceed the bounds of the buffer. For instance, in <figref idref="DRAWINGS">FIG. 1</figref>, the index pointer is shown as pointing at address <b>35</b>. If the increment amount M, is 3, then the pointer will be updated to point to address number <b>38</b>. However, on the next increment of 3, the index pointer would normally point to address <b>41</b> which is beyond the bounds of the buffer. Accordingly, means must be provided for ensuring that when the increment of the index pointer causes it to exceed the end address of the buffer, it is wrapped around to the base of the buffer. For instance, on the next increment of the index pointer, the index pointer should point to address <b>21</b> rather than address <b>41</b>.

<figref idref="DRAWINGS">FIG. 2</figref> shows an address generator according to the present invention for generating addresses for a circular buffer such as the buffer shown in FIG. <b>1</b>. <figref idref="DRAWINGS">FIG. 2</figref> shows an embodiment of the invention in which the increment, M, is always positive or always negative, as is typical. However, other embodiments in which the modifier can be positive or negative are possible and are described later herein. The address generator of the preferred embodiment of the present invention comprises four registers, termed L, M, I and B. The L register <b>12</b> is initialized by loading it with the length of the circular buffer. The M register <b>19</b> is loaded with a increment (or decrement) value. The B register <b>14</b> is loaded with the base address of the circular buffer, i.e., the lowest numbered address if M is positive, or the highest numbered address if M is negative. The I register, which essentially comprises the pointer into the circular buffer, is automatically loaded with the base address when the base address is loaded into the B register. As shown in <figref idref="DRAWINGS">FIG. 2</figref>, OR-gate <b>16</b> assures that when a B register write enable instruction (B WREN <b>78</b>) is issued, the I register is also write enabled such that both the B and the I registers receive the base address being placed on the data bus <b>18</b>.

In most circular buffer applications, the buffer pointer, i.e., the I register, is incremented the same amount every time. Accordingly, a number can be permanently stored in the M register <b>19</b>. In situations where the increment, M, may vary, a multiplexer <b>20</b> is provided. Under the control of a processor (not shown), to avoid unnecessary obfuscation, multiplexer <b>20</b> can select as the increment either the data placed on the data bus by the processor or the output of the M register <b>19</b>.

The contents of the I register <b>16</b> are placed onto the address bus <b>26</b> in response to a processor instruction such as the I_WRENsignal <b>28</b> in FIG. <b>2</b>. The logic in the address generator of the present invention will then modify the contents of the I register so that it will be ready for the next access into the circular buffer. Accordingly, an instruction cycle instructing the I register to output its contents onto the address bus initiates the sequence to be described herein for modifying the contents of the I register.

As the contents of the I register are output onto the data bus, they are also fed into one input of an adder <b>22</b>. The other input of the adder is coupled to the output of the multiplexer <b>20</b> which contains the selected increment, M<b>0</b> The value I+M is output from the adder <b>22</b> and fed to one input of adder/subtractor <b>27</b>. At its other input, adder/subtractor <b>27</b> accepts the output of the L register which contains the length of the buffer. In the case where M is always positive, the adder/subtractor is set up to subtract L from I+M. However, if M is negative, then the adder/subtractor is set up to add the value of L to I+M.

If M is positive, then the value of I+M−L is compared with the base address, B, of the circular buffer by comparator <b>30</b>, as shown in FIG. <b>2</b>. The output of comparator <b>30</b> is the control signal to multiplexer <b>32</b>. Multiplexer <b>32</b> receives at input A the value of I+M−L output from adder/subtractor <b>27</b> and at input B the value of I+M output from adder <b>22</b>. The comparator determines if I+M−L is greater than or equal to B. If so, the comparator <b>30</b> outputs a signal which instructs the multiplexer to place at its output the value at its A input, I+M−L. Otherwise, the comparator instructs the multiplexer <b>32</b> to place at its output, the value at its B input, I+M. The output of the multiplexer is fed back to the input of the I register and represents the new pointer address which will be stored in the I register.

The purpose of the above-described operation of adder <b>22</b>, adder/subtractor <b>27</b>, comparator <b>30</b> and multiplexer <b>32</b> is explained as follows. The value of I+M output from adder <b>22</b> represents the new absolute value of the pointer (i.e., the old pointer value plus the increment M, regardless of whether it is within the bounds of the buffer). If the absolute value is within the range of the buffer, then no “wrapping around” is necessary and it can be placed directly into the I register. However, if it is beyond the range of the buffer, then the length of the buffer, L, must be subtracted from the absolute value in order to “wrap around” the address to modulo style. Adder/subtractor <b>27</b> calculates I+M−L whether it will be needed or not. Obviously, if I+M is within the buffer range, then subtracting the length, L, of the buffer from the absolute address will cause the address to be less than the base address of the buffer, thus indicating that “wrapping” is unnecessary. However, if I+M is beyond the bounds of the buffer, then I+M−L will be greater than or equal to the base address, B, of the buffer. Accordingly, comparator <b>30</b> determines if I+M−L is greater than or equal to the base address, B. If so, then I+M must have been beyond the range of the buffer and the comparator causes multiplexer <b>32</b> to place in the I register the value of I+M−L, rather than the value of I+M.

If M is negative, the operation is slightly modified. In this situation, the adder/subtractor <b>27</b> calculates the value of I+M (M being negative)+L instead of I+M−L, and the B register contains the highest numbered, rather than lowest numbered, address in the buffer. Accordingly, the comparator operation also must be modified so that, if the value as its A input, I+M+L, is less than or equal to the value at its B input, the highest address in the buffer, B, then it instructs the multiplexer <b>30</b> to select I+M+L. Otherwise it selects its other input, I+M.

As described above, depending on the sign of M, the adder/subtractor <b>27</b> and the comparator <b>30</b> perform slightly different operations. However, from a manufacturing standpoint, it is desirable to produce a single address generator which can be used in applications where M is positive or negative, rather than producing a separate device for each situation. Accordingly, in the preferred embodiment, adder/subtractor <b>27</b> and comparator <b>30</b> are designed to perform the separate above-described functions responsive to the sign bit of the contents of the M register. Accordingly, not only is the address generator capable of handling both of these situations (where M is positive or where M is negative), but, with a small amount of additional circuitry, it will also function properly where the sign of M can change during operation as discussed below.

Although the description of the invention above has been limited to situations where M is either known to be positive or negative, there are applications where the offset, M, can change from positive to negative during operation. For example, in the fast generation of phase values in high speed spread spectrum systems, the direction of movement in the circular buffer can change. Similarly, in phase locked loop situations, the direction of the offset can change. The present invention can be adapted to handle such situations. One possible adaptation would be to provide a further adder which adds the contents of the B register and the L register to derive the highest numbered address in the buffer and a further multiplexer responsive to the sign bits of M for selecting either the output of the B register (defined herein as the lowest address in the buffer) or the output of the additional adders as an input to the comparator <b>30</b>. The adder/subtracter is also responsive to the sign bit of the register for subtracting L from I+M, when the sign bit of M is positive or adding L to the I+M value, when the sign bit is negative. The comparator also is responsive to the sign bit. In the case where M is positive, if the comparator determines that its A input, I+M−L, is greater than or equal to its B input, the base address, B, then it instructs the multiplexer <b>32</b> to select its A input, I+M−L. However, if M is negative, the comparator output must be modified such that when the A input of the comparator, I+M+L, is less than or equal to the B input of the comparator, B+L, then the multiplexer must be instructed to select its A input, I+M, and its B input, I+M+L otherwise.

The speed of the calculation of the address can be further increased with a slight modification to the circuitry shown in FIG. <b>2</b>. As shown in <figref idref="DRAWINGS">FIG. 2</figref>, valid data does not appear at the output of adder/subtractor <b>27</b> until it receives the value of I+M from adder <b>22</b>. In other words, to obtain I+M±L for comparison with B, the comparator <b>30</b> must wait through the propagation delay of adder <b>22</b> plus the propagation delay of adder/subtractor <b>27</b>. The circuitry in <figref idref="DRAWINGS">FIG. 2</figref> can be modified as shown in <figref idref="DRAWINGS">FIG. 3</figref>, to avoid the need for the comparator to wait through this double propagation delay by providing another register and a different adder/subtracter <b>29</b> which has at its inputs the outputs of the B and L registers and calculates B±L. Then comparator <b>30</b> can compare I+M with B±L rather than comparing I+M±L with B. The former comparison is essentially the same as the latter, the value L simply being moved to the other side of the equation. In this embodiment the propagation delay through to the apparatus is reduced because the calculation of B±L occurs simultaneously with the calculation of I+M rather than sequentially afterwards. Of course, one could easily avoid the need for a second adder/subtracter by utilizing only one adder/subtracter and storing in a register the results of one of the addition/subtraction operations.

Additional alternate embodiments of the invention are shown in <figref idref="DRAWINGS">FIGS. 4 and 5</figref>. In order to define the circular buffer, one must know 1) its base address and its length (as is provided in the <figref idref="DRAWINGS">FIG. 2</figref> embodiment described above, 2) its end address and its length, or 3) its base address and end address. <figref idref="DRAWINGS">FIGS. 2 and 3</figref> illustrate embodiments utilizing registers containing the base address and length information noted in the first alternative. <figref idref="DRAWINGS">FIGS. 4 and 5</figref> illustrate alternate embodiments of the invention which utilize registers containing the information noted in the second and third alternatives.

In the <figref idref="DRAWINGS">FIG. 4</figref> embodiment, the L register is replaced by an E register <b>40</b> containing the end address of the buffer. Much of the logic of this embodiment is similar to the embodiment of <figref idref="DRAWINGS">FIG. 2</figref>; therefore, similar numbers are used for similar components. Adder/subtractor <b>28</b> and comparator <b>30</b> are replaced by adder/subtractor <b>42</b> and comparator respectively. In this embodiment, adder/subtractor <b>42</b> requires inputs from the E register, B register and adder <b>22</b>. Adder/subtractor <b>42</b> calculates I+M−E+B, regardless of the sign of M (assuming that the B register is initialized with the lowest address in the buffer when M is positive, and with the highest address when M is negative).

When M is positive, comparator <b>44</b> compares I+M−B+E to B. If I+M−E+B is less than or equal to B, then comparator <b>44</b> controls multiplexer <b>32</b> to select its A input, having the value I+M−E+B. Otherwise, multiplexer <b>32</b> is controlled by comparator <b>44</b> to select its B input, having the value I+M. When M is negative, the adder/subtractor <b>42</b> still calculates I+M−E+B and the comparator still compares I+M−E+B with the contents of the B register, but now must determine if I+M−E+B is less than or equal to B. If so, comparator <b>44</b> instructs multiplexer <b>32</b> to select its A input, the value I+M−E+B. Otherwise, multiplexer <b>32</b> is controlled by comparator <b>44</b> to select its B input, the value I+M. Minor modifications are necessary if M may be either positive or negative during operation.

<figref idref="DRAWINGS">FIG. 5</figref> shows another embodiment utilizing an L register <b>12</b>, E register <b>45</b>, I register <b>16</b> and M register <b>19</b>. The <figref idref="DRAWINGS">FIG. 5</figref> embodiment is substantially similar to the embodiments shown in <figref idref="DRAWINGS">FIG. 2</figref>, except that comparator <b>30</b> is replaced by comparator <b>50</b>. Adder/subtractor <b>28</b> remains the same as in FIG. <b>2</b> and calculates I+M−L, if M is positive, or I+M+L, if M is negative, just as in the <figref idref="DRAWINGS">FIG. 2</figref> embodiment. Comparator <b>50</b> compares the value of I+M output from adder <b>22</b>, with the contents of the E register. When M is positive, If I+M is less than or equal to E (which is the highest address, when M is positive), the comparator controls multiplexer <b>32</b> to select its B input, I+M. Otherwise, the multiplexer selects its A input, I+M−L. When M is negative, the comparator <b>50</b> determines if I+M is greater than or equal to the end address E (which is the lowest numbered address, when M is negative) and, if so, controls multiplexer <b>32</b> to select its B input, I+M. Otherwise, it selects its A input, I+M+L.

In the embodiment of <figref idref="DRAWINGS">FIG. 5</figref>, additional circuitry is necessary to automatically load the I register with the base address at initialization, compared with the previously discussed embodiments since, in this embodiment, there is no base register. Accordingly, the base address is derived from the contents loaded into the L and E registers and automatically loaded into the I register. Subtracter <b>70</b> receives at its inputs the output of the L register <b>12</b> and the E register <b>45</b>, subtracts L from E, and outputs that value to the input of the I register during the initial register loading process only. Since, in the embodiment shown in <figref idref="DRAWINGS">FIGS. 4 and 5</figref>, the I register is enabled by the E_WRENsignal <b>78</b>, the L register must be loaded before the E register in order for the subtracter to place the correct value in the I register. Alternate embodiments are possible. For example, as with <figref idref="DRAWINGS">FIG. 3</figref> it is possible to use adder/subtractor <b>28</b> to replace the additional subtracter <b>70</b>, by switching adder/subtractor <b>28</b> to calculate and load the I register with the base value at the time of register initialization.

The embodiment of <figref idref="DRAWINGS">FIG. 4</figref> can also be modified for situations in which M may alternate between a positive and negative value.

Having thus described a few particular embodiments of the invention, various alterations, modifications and improvements will readily occur to those skilled in the art. Such alterations, modifications and improvements as are made obvious by this disclosure are intended to be part of this description though not expressly stated herein, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only, and not limiting. The invention is limited only as defined in the following claims and equivalents thereto.