Synchronizing signal separating apparatus and method
Claim Score by NHIP
Abstract
The present invention provides a synchronizing signal separation. In accordance with the present invention, a sync pulse processing circuitry slices a video signal and senses the peaks of the synchronizing pulse. A reference generating circuitry divides the output from the sync pulse processing circuitry into a plurality of reference signals that are compared with the video signal, thereby producing logic level outputs. A sync restoring circuitry combines the logic level outputs to provide precisely reconstructed synchronizing pulses of the video signal. The present invention incorporates different standard functions with superior performance because it may be applied for different types of video signals.
Term
Term ended
Expired 18 February 2012, 14.6 years ago.
- Priority
- Filed
- Granted
- Expired
- Today
72 claims: 17 independent, 55 dependent
- 1A video signal processing apparatus for use with the synchronizing pulses thereof, said synchronizing pulses having at least a leading edge and a trailing edge including in combination:at least one sampling circuit for sampling said synchronizing pulses in response to a plurality of sampling signals to generate at least a first reference signal and a second reference signal, said reference signals respectively representing different levels of said synchronizing pulses, wherein said sampling circuit includes DC restoring for restoring said synchronizing pulses to a predetermined DC reference level which said DC restored synchronizing pulses are coupled to at least one comparing circuit for comparing said video signal with a level responding to said reference signals thereby providing at least a precision sliced pulse signal, with said sampling being independent of said precision sliced pulse signal.
- 4Broadest claimClaim Score 62, broad(NHIP)A video signal processing apparatus for use with synchronizing pulses of a video signal including:at least one sampling circuit for sampling said synchronizing pulses in response to a plurality of sampling signals provided, in response to said synchronizing pulses to generate at least a first reference signal and a second reference signal, said reference signals respectively representing different levels of said synchronizing pulses;and comparing circuit for comparing said synchronizing pulses with a level responding to said reference signals to generate precision sliced pulses, with said sampling being independent of said precision sliced pulses, and further comprising combining said precision sliced pulses to generate horizontal rate and vertical rate pulse signals.
- 6A synchronous signal processing apparatus for a video signal comprising:slicing means for slicing said video signal to generate sliced pulses, said sliced pulses corresponding to respective synchronous pulses of said video signal, each of said sliced pulses having a leading edge and a trailing edge;level detecting means for detecting respective levels of said synchronous pulses of said video signal in response to said leading and trailing edges and providing a first level signal in response to one of said edges and a second level signal in response to the other of said edges;and sync restoring means for detecting different levels of said synchronous pulses in response to said first and second level signals and generating a derived sync pulse output in response thereto.
- 13A video signal processing apparatus, said video signal having synchronous pulses of a pulse amplitude, said apparatus comprising:sync tip clamping means for clamping said video signal to provide a clamped pulse signal, respective pulse of said clamped pulse signal having a leading edge and a trailing edge;peak detecting means for sampling said video signal in response to said leading and trailing edges to generate a positive peak signal and a negative peak signal;level dividing means for dividing level between said positive and negative peak signals into a first reference level, a second reference level and a third reference level;and comparing means for comparing said video signal with respective said reference levels to generate logic level outputs.
- 17A video signal processing apparatus, said video signal having synchronous pulses of a pulse amplitude, said apparatus comprising:format selecting means responsive to the format of said video signal for determining the format of said video signal being processed;sync tip clamping means for clamping respective sync tips of said video signal to provide a clamped pulse signal corresponding to said synchronous pulses, each respective pulse of said clamped pulse signal having a leading edge and a trailing edge;sync slicing means coupling to said sync tip clamping means, for limiting an amplitude of said clamped pulse signal to provide a coarse sliced sync signal;peak detecting means for sampling positive and negative peaks respectively of said synchronous pulses of said video signal in response to said leading and trailing edges, thereby generating a positive peak signal and a negative peak signal;level dividing means for dividing level between said positive and negative peak signals into a first reference level, a second reference level and a third reference level, said first, second and third reference levels respectively representing different portion levels of said pulse amplitude;comparing means for comparing said video signal with respective said reference levels to generate logic level outputs;and restoring means coupling to said comparing means, for combining said logic level outputs to generate a plurality of precision synchronous outputs.
- 19A method for processing a synchronous signal of a video signal comprising steps of:slicing said video signal to generate a sliced sync pulse signal;sampling said video signal in response to respective leading edges and trailing edges of said sliced pulse signal so as to generate a first sample level signal and a second sample level signal;converting said first and second sample level signals into a first reference signal, a second reference signal and a third reference signal, said first reference signal representing a middle level of each synchronous pulse of said video signal, said second reference signal representing a upper level above said middle level and said third reference signal representing a lower level below said middle level;comparing said respective reference signals with said video signal to generate logic level outputs;and restoring desired synchronous pulses in response to said logic level outputs.
- 21A method of generating an output sync signal corresponding to the sync portion of a composite video signal which sync portion comprises a plurality of sync levels, one of which said sync levels includes blanking level, said method including the steps of:a. generating a plurality of level signals having magnitudes responsive to said sync levels, b. establishing at least one reference level between each of said sync levels in response to said level signals, the number thereof changeable in response to the number of said sync levels, c. for each said reference level established, generating a binary pulse version of said sync portion by comparison of said reference levels and said sync portion, d. generating said output sync signal in response to said binary pulse versions of step c.
- 22A method of generating an output sync signal corresponding to the sync portion of a composite video signal which sync portion comprises a plurality of sync tip levels and a blanking level, said method including:a. generating a plurality of level signals having magnitudes responsive to said sync tip levels, b. establishing a plurality of reference levels between said sync tip levels in response to said level signals, c. generating a plurality of binary pulse versions of said sync portion by comparison of said reference levels and said sync portion, d. combining said plurality of binary pulse versions to generate said output sync signal.
- 27An apparatus for deriving a logic level version of the sync portion of a video type signal, said sync portion having a plurality of levels, one of which may be a blanking level, said apparatus including:circuitry responsive to said sync portion to clamp the sync tip thereof to a known level thereby providing a clamped sync portion and to generate at least a first logic level sync signal in response to said clamped sync portion;circuitry for clamping said sync portion to a known level to provide a second clamped sync portion;circuitry for providing at least one reference signal in response to said first logic level sync signal and said second clamped sync portion;circuitry for comparing said second clamped sync portion to said reference signal to provide said logic level version.
- 31An apparatus for deriving a logic level version of the sync portion of a video type signal, said sync portion having a number of levels N, one of which may be a blanking level, and where N may be two or more depending on the format of said video type signal, said apparatus including:circuitry to provide a format signal changeable in response to the format of said video type signal;circuitry responsive to said sync portion to generate at least a first separated sync signal;circuitry for providing at least N−1 reference signal(s) in response to said sync portion and said first separated sync signal;and circuitry responsive to said sync portion and said format signal and said reference signal(s) for comparing said sync portion to said reference signal(s) to provide said logic level version.
- 35A video sync pulse circuit responsive to composite sync pulses which may be part of a composite video signal said circuit operative to provide a reference voltage corresponding to the 50% level of sync, including in combination:a) a coupling capacitor coupled to an input terminal to AC couple said composite sync pulses to a sync tip clamp circuit, said sync tip clamp circuit including a source of current operative to charge said coupling capacitor in a first direction and further including circuitry to charge said coupling capacitor in the opposite direction during at least a portion of the time said AC coupled sync tips surpass a reference, said charging action thus providing sync tip clamping to provide a sync tip clamped signal;b) a buffer, responsive to said sync tip clamped signal to buffer same to provide a buffered signal;c) a comparator responsive to said buffered signal and a reference to provide a compared sync signal;d) a plurality of pulse circuits responsive to said compared sync signal from said comparator to provide a first sample and hold pulse in response to the leading edge of said compared sync signal and a second sample and hold pulse in response to the trailing edge of said compared sync signal;e) a first sample and hold circuit responsive to said first sample and hold pulse and a DC restored form of said composite sync pulses to sample and hold the voltage level of sync tip;f) a second sample and hold circuit responsive to said second sample and hold pulse and blanking level of said DC restored form of said composite sync pulses to sample and hold the voltage level of blanking;g) a divider circuit responsive to the held voltage of sync tip and the held voltage of blanking to provide an in between voltage which is said reference voltage;wherein circuitry used to accomplish one of elements a) through g) may be shared between two or more elements.
- 36A video sync pulse separator separator circuit responsive to a composite video signal for providing horizontal and vertical sync pulses including in combination:a) a coupling capacitor to AC couple said composite video signal to a sync tip clamp circuit, said sync tip clamp circuit including a source of current operative to charge said coupling capacitor in a first direction and further including circuitry to charge said coupling capacitor in the opposite direction during at least a portion of the time any AC coupled sync tip surpasses a reference, said charging action thus sync tip clamping to provide a sync tip clamped signal;b) a buffer responsive to said sync tip clamped video signal to buffer said sync tip clamped video to provide a buffered signal;c) a comparator responsive to said buffered signal and a reference to provide a compared sync signal;d) a plurality of pulse circuits responsive to said compared sync signal from said comparator to provide a first sample and hold pulse in response to the leading edge of said compared sync signal and a second sample and hold pulse in response to the trailing edge of said compared sync signal;e) a first sample and hold circuit responsive to said first sample and hold pulse and sync tip of a DC restored form of said composite video signal to sample and hold the voltage level of sync tip;f) a second sample and hold circuit responsive to said second sample and hold pulse and blanking level of said DC restored form of said composite video signal to sample and hold the voltage level of blanking;g) a divider circuit responsive to the held voltage of sync tip and the held voltage of blanking to provide an in between reference voltage;h) a further comparator responsive to said reference voltage and comparison video to provide reference sync pulses, said comparison video being a version of said composite video signal of element a) having a known DC level;i) a half horizontal pulse eliminator circuit responsive to said reference sync pulses to output horizontal rate pulses;j) a vertical synchronizing filter circuit responsive to said reference sync pulses to output a vertical rate pulse;k) a field synchronizing circuit responsive to at least circuit element j) and to the relationship of horizontal sync pulses and the leading edge of vertical sync to output a field synchronizing pulse signifying odd and even fields, wherein circuitry used to accomplish one of elements a) through k) may be shared between a plurality of elements.
- 39A method for processing a sync portion of a video type signal, said sync portion having a plurality of levels, comprising steps to:a) a first separation of said sync portion to generate a first separated sync signal, including clamping the sync tip of said sync portion to a known level before said first separation;b) generating a plurality of level signals each being representative of a level of a second clamping of said sync portion, at least one of said level signals is also generated in response to said first separated sync signal;c) providing a reference signal in response to said plurality of level signals;d) a second separation of said second clamped sync portion in response to said reference signal to provide a second separated sync signal which is a version of said sync portion.
- 40A method for processing a sync portion of a video type signal, said sync portion having a plurality of levels, comprising steps to:a) a first separation of said sync portion to generate a first separated sync signal, including clamping the sync tip of said sync portion to a known level established by one or more semiconductor junction voltage drops before said first separation;b) generating a plurality of level signals each being representative of a level of a second clamping of said sync portion, at least one of said level signals is also generated in response to said first separated sync signal;c) providing a reference signal in response to said plurality of level signals;d) a second separation of said second clamped sync portion in response to said reference signal to provide a second separated sync signal which is a version of said sync portion.
- 65A video signal processing apparatus, wherein a video signal includes synchronous pulses of a pulse amplitude, comprising:a sync tip clamping device for clamping the video signal to provide a clamped pulse signal, wherein the sync tip clamping device includes a current, wherein the current varies in amount and polarity, and wherein a respective pulse of the clamped pulse signal includes a leading edge and a trailing edge;a peak detecting device for sampling the video signal in response to the leading and trailing edges to generate a positive peak signal and a negative peak signal;a level dividing device for dividing levels between the positive and negative peak signals into a first reference level, a second reference level and a third reference level;and a comparing device for comparing the video signal with respective reference levels to generate logic level outputs.
- 66A video signal processing apparatus, wherein a video signal includes synchronous pulses of a pulse amplitude, comprising:a format selecting device responsive to a format of the video signal for determining the format of the video signal being processed;a sync tip clamping device for clamping respective sync tips of the video signal to provide a clamped pulse signal corresponding to the synchronous pulses, wherein the sync tip clamping device includes a current, wherein the current varies in amount and polarity, and wherein each respective pulse of the clamped pulse signal includes a leading edge and a trailing edge;a sync slicing device, coupled to the sync tip clamping device, for limiting an amplitude of the clamped pulse signal to provide a coarse sliced sync signal;a peak detecting device for sampling positive and negative peaks respectively of the synchronous pulses of the video signal in response to the leading and trailing edges to generate a positive peak signal and a negative peak signal;a level dividing device for dividing levels between the positive and negative peak signals into a first reference level, a second reference level and a third reference level, wherein the first, second and third reference levels respectively represent different portion levels of the pulse amplitude;a comparing device for comparing the video signal with respective reference levels to generate logic level outputs;and a restoring device, coupled to the comparing device, for combining the logic level outputs to generate a plurality of precision synchronous outputs.
- 67A method of generating an output sync signal corresponding to a sync portion of a composite video signal, wherein the sync portion comprises a plurality of sync tip levels and a blanking level, the method comprising the steps of:a. ) generating a plurality of level signals having magnitudes responsive to the sync tip levels, wherein at least one of the level signals is held on a first capacitor;b. ) establishing a plurality of reference levels between the sync tip levels in response to the level signals;c. ) generating a plurality of binary pulse versions of the sync portion by comparison of the reference levels and the sync portion;and d. ) combining the plurality of binary pulse versions to generate an output sync signal.
Independent claims17
83 paragraphs in 4 sections, as filed
0001This application is a continuation of application Ser. No. 07/837,323, filed Feb. 18, 1992, now abandoned.
BACKGROUND OF THE INVENTION
0002The present invention relates to signal processing systems and, in particularlyparticular, to video signal processing. A major objective of the present invention is a synchronizing signal processing apparatus and a method that precisely recovers synchronizing signals of a video signal.
0003Much of modern technology depends on signal processing. A common application of signal processing is for the video signal. Usually, a video signal includes picture synchronizing information. The synchronizing information is transmitted for scanning in a receiver in exact synchronism with a camera-tube scanning. The synchronizing signal must first be recovered from the video signal.
0004More particularly, TV (Television) video signals, thean example of the video signal, are processed to obtain desired picture quality. A TV transmitting station modulates video and audio signals and transmits them out by an antenna so that TV receivers may receive them to produce the pictures. In order to precisely reproduce pictures, synchronizing information is added in the video signal so that the receivers can synchronously perform scanning operation as the TV transmitting station does.
0005Numerical and graphical criteria which describe essential aspects of a TV system,are employed in the design and operation of equipment to assure that the various parts of the system will operate in cooperative fashion at maximum performance. TV systems have a special need, compared with other communication systems, for definitive standards because television transmitters and receivers must operate in a precise “lock-and-key” relationship. In particular, the scanning of the image in the camera must be matched by the scanning in every associated receiver within a timing precision of approximately one-tenth of a millionth of a second, and with relative positions of picture details correct to a few hundredths of an inch as viewed on the CRT or other display.
0006To assure that any television receiver can receive programs from any transmitter within range, it is customary to set up a single set of standards with a group of neighboring countries. The TV transmitting stations of different countries and areas transmit video signals with different formats. For example, U.S.A., Canada and Japan et al. use the NTSC (National Television System Committee) system. France, Soviet Union et al. use the SECAM (Sequential Couleura Memoire) system. Germany and United Kingdom et al. then use the PAL (Phase Alternation Line) system. Moreover, HDTV (High Definition TV) creates a new system with images of high resolution. For all of these examples, the synchronizing signals added in their video signals are different.
0007Picture synchronizing information is obtained from the video signal by means of sync separation circuits. In addition, these circuits must separate this information from noise and interference during the reception of weak signals, particularly if impulse noise is present. To reproduce these different video signals of respective systems, different video signal processing devices are needed to provide required synchronizing signals.
0008Conventional video signal devices for processing the synchronizing information of the video signals can not be used for different standard video signals for providing reliable synchronizing signals, without affecting the reproduction of the video signals or causing high cost of video signal processing. What is needed is a synchronizing signal processing apparatus and method that precisely recovers synchronizing signals of the video signal and can be applied for processing different video signals.
SUMMARY OF THE INVENTION
0009In accordance with the present invention, a synchronizing signal processing apparatus includes means for sampling synchronizing signals and slicing a video signal in response to the sampled synchronizing signals. The synchronizing signal processing apparatus includes a sampling means that samples the synchronizing signals and provides at least a reference signal. The synchronizing signal processing apparatus also includes a comparing means that slices the video signal in response to the at least a reference signal representing different levels of each of the synchronizing pulses. Thus, the synchronizing signal processing apparatus generates logic level outputs. The video signal with which the present invention is used may be of a standard type having synchronizing pulses including horizontal synchronizing pulses.
0010The video signal may be sliced, before it is sampled, to eliminate noise. The sliced video signal corresponds to the synchronizing pulses. In response to the sliced video signal, the peaks of the synchronizing pulses of the video signal are precisely sampled. Two sampled signals represent the positive and negative peaks of the synchronizing pulses. The two sampled signals further are divided into three reference signals to compare with the video signal. After this comparison, the logic outputs are combined to recover synchronizing pulses that are reliable, precise and without noise.
0011A combining means couples to the comparing means so that the outputs from the comparing means are combined depending on the type of the video signal. The combining means generates a plurality of synchronizing signals.
0012To provide a vertical synchronizing signal, the present invention uses a filtering means that filters one of synchronizing signals output from the combining to provide a vertical synchronizing signal. The filter means shows a good frequency response characteristic for the vertical synchronizing signal.
0013The synchronizing signal processing method in accordance with the present invention comprises steps of slicing a video signal sampling the video signal in response to respective leading and trailing edges of the sliced signal, converting the sampled signal into at least a reference signal, comparing the reference signal with the video signals and combining the compared outputs to recover synchronizing pulses.
0014An advantage of the synchronizing signal processing apparatus and method is that the present invention incorporates several standard functions with superior performance. The synchronizing signal processing apparatus in accordance with the present invention is capable of operating with standard two level synchronizing pulses, for example, NTSC, PAL and SECAM type synchronizing pulses, and three level synchronizing pulses, for example HDTV synchronizing pulses. The present invention may also applied for other video type signals with synchronizing pulses.
0015Furthermore, the present invention provides good bandwidth properties and time constant in the video amplifier section. The combination of the both proper bandwidth and time constant gives considerably noise immunity against high frequency noise, yet maintains sufficient operation speed for high performance. Therefore, no additional compensation or filtering components are needed.
0016The synchronizing signal processing apparatus in accordance with the present invention may be easily adjusted for either two level or three level synchronizing pulses. The recovered synchronizing levels for video signals are characterized by high precision and reliability.
0017The logic level outputs of the comparing means are combined, the combination depending on whether the synchronizing pulses are two levels or three levels. In accordance with the present invention, the synchronizing signal processing apparatus may generate a TTL (Transistor-Transistor level) version of the synchronizing pulses.
0018The synchronizing signal processing apparatus in accordance with the present invention may be used with different video devices, which simplifies the design and manufacture of video devices, and significantly decreases the cost to make these video devices.
0019Another advantage of the synchronizing signal processing apparatus of the present invention is that it is suitable to be implemented by integrated circuits. Alternatively, the video signal processing can be implemented by software, such as in signal processing application. These and other features and advantages of the present invention are apparent from the description below with reference to the following drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
0020<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram of a synchronizing signal processing apparatus in accordance with the present invention.
0021<figref idref="DRAWINGS">FIG. 2</figref> illustrates a detailed circuit diagram of a sync pulse processing section of the synchronizing signal processing apparatus of FIG. <b>1</b>.
0022<figref idref="DRAWINGS">FIG. 3</figref> illustrates a detailed circuit diagram including a pulse width adjust and a reference sync generating section of the synchronizing signal processing apparatus of FIG. <b>1</b>.
0023<figref idref="DRAWINGS">FIG. 4</figref> illustrates a detailed circuit diagram of a sync restoring section of the synchronizing signal processing apparatus of FIG. <b>1</b>.
0024<figref idref="DRAWINGS">FIG. 5</figref> shows waveform diagrams of several nodes of the synchronizing signal processing apparatus.
0025<figref idref="DRAWINGS">FIG. 6</figref> shows a frequency response characteristic of a filter device of the synchronizing processing apparatus of FIG. <b>1</b>.
0026<figref idref="DRAWINGS">FIG. 7</figref> is a flow chart of a synchronizing signal processing method in accordance with the present invention.
0027<figref idref="DRAWINGS">FIGS. 8-11</figref> are four sheets of a detailed schematic of the preferred embodiment in accordance with the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
0028A synchronizing signal processing apparatus <b>100</b> in accordance with the present invention includes an input amplifier <b>102</b>, a video standard detector <b>103</b>, a sync pulse processing section <b>104</b>, a pulse width adjust <b>106</b>, an offset device <b>108</b>, a DC (Direct Current) restoration device <b>110</b>, a reference sync generating section <b>112</b> and a sync restoring section <b>114</b>.
0029Video signal <b>116</b><b>101</b>is applied to differential input amplifier <b>102</b> where video signal <b>101</b> is amplified to improve the ratio of signal/common mode noise. The video signal amplified by input amplifier <b>102</b> is fed to sync pulse processing section <b>104</b> which includes a sync tip clamp <b>116</b>, a sync slicer <b>118</b> and a sync tip peak <b>15</b> detector <b>120</b>.
0030The video signal is first clamped by sync tip clamp <b>116</b> to generate a clamped signal which has a known DC level of the synchronizing pulses. The clamped signal is then transferred to sync slicer <b>118</b> where the clamped signal is sliced, thereby generating a signal that has the same time period as that of the synchronizing pulses but at standard levels as compared to that of the synchronizing pulses, in this example TTL levels. To effectively eliminate interference and noise, the sync slicer <b>118</b> slices the synchronizing pulses at a known level which is preferred to be about half of the nominal expected amplitude of the synchronizing pulses. Due to the a known level which is approximately half the expected level, the operation of sync slicer <b>118</b> may be considered a coarse slicing operation which provides coarse sliced pulses. The sliced signal is coupled to sync tip peak detector <b>120</b>, in which peaks of synchronizing pulses of the video signal from DC restoration device <b>110</b> are sampled in response to the sliced signal.
0031The clamped signal is also delivered to pulse width adjust <b>106</b>. This clamped signal activates pulse width adjust <b>106</b> to generate a pulse trigger signal coupling to DC restoration device <b>110</b>. The pulse trigger signal determines the pulse width of the synchronizing pulses. A switch SW<sub>P </sub>is provided with pulse width adjust <b>106</b>. Changing the status of the switch SW<sub>P </sub>may adjust the width of the pulse trigger signal.
0032The video standard detector <b>103</b> is provided for determining the video signal output from the input amplifier <b>102</b>. When the video signal, for example, is a NTSC video signal, video standard detector <b>103</b> controls switch SW<sub>L</sub>, so that this switch is open, which indicates that the video signal is a NTSC TV signal. On the other hand, when the video signal output from the input amplifier <b>102</b> is a HDTV signal, the video standard detector <b>103</b> will turn switch SW<sub>P </sub>on. The video standard detector <b>103</b> also control switches SW<sub>T</sub>, SW<sub>U </sub>and SW<sub>L</sub>. The switches may be operated automatically in response to a video standard detector <b>103</b> which detects the type of signal <b>101</b>. Therefore, the synchronizing signal processing apparatus <b>100</b> in accordance with the present invention may process different video signals.
0033Offset device <b>108</b> provides a DC reference for DC restoration <b>110</b>. The amplified video signal from the input amplifier <b>102</b> is also coupled to DC restoration <b>110</b>. In response to the reference from offset device <b>108</b>, DC restoration <b>110</b> clamps the amplified video signal to eliminate DC shift and residual common mode noise.
0034Other types of DC restoration circuits may be used as is well known in the art. It is desired to have the video signal V<sub>O1 </sub>and V<sub>O2 </sub>restored to a known value. However, it should be noted that the DC restoration device <b>110</b> may be eliminated by directly AC coupling the video signal output from the input amplifier <b>102</b> to the reference sync generating section <b>112</b> and sync pulse processing section <b>104</b>. The operation of sync tip peak detector <b>120</b> will track the variations in the AC coupled video signal output from the input amplifier <b>102</b> and allow the comparator <b>122</b> to function properly. However, the use of a DC restoration device is preferred.
0035The DC restoration device <b>110</b> produces two output signals V<sub>O1 </sub>and V<sub>O2</sub>. The clamped video signal V<sub>O2 </sub>is delivered to sync tip peak detector <b>120</b>. In response to the sliced signal from the sync slicer <b>118</b>, sync tip peak detector <b>120</b> samples the positive and negative peaks of synchronizing pulses of the clamped video signal so as to provide two peak sample pulse signals. For purposepurposes of the present example, video is described with respect to positive white with the negative level of sync being that which is farthest from peak white video and the positive level of sync being that which is closest to the peak white value of the video. For two level sync, such as NTSC, the positive peak will correspond to video blanking level. The two peak sample pulse signals define each of the synchronizing pulsepulses. Divider <b>124</b> receives them and converts them into three pulse reference signals. The amplitudes of the pulse reference signals represent percentage levels of sync of V<sub>O2 </sub>during the respective ones of the peak sample pulses as represented by V<sub>h </sub>and V<sub>I</sub>.
0036Reference sync generating section <b>112</b> also includes a comparator <b>122</b>. The clamped video signal from DC restoration <b>110</b> and three pulse reference signals are coupled to comparator <b>122</b>. By comparison, comparator <b>122</b> outputs four level signals during each synchronizing pulse of the video signal. Due to the use of references which are responsive to the actual level of the sync pulse, the comparator <b>122</b> may be considered a precision comparator, which outputs precision sliced pulses. The four level signals represent different amplitudes of each synchronizing pulse as determined by the video sync being greater than none, one, two or three of the pulse reference signals.
0037A sync restoring section <b>114</b>, which includes combination logic <b>126</b> and vertical sync filter <b>128</b>, is arranged to receive the output signals from the comparator <b>122</b> of reference sync generating section <b>112</b>. The combination logic <b>126</b> is used to combine the four output signals from comparator <b>122</b> to recover reliable synchronizing signals. Switches SW<sub>U </sub>and SW<sub>L </sub>are arranged to control the switching between the HDTV video signal and conventional TV video signals, for example NTSC TV video signal.
0038The opening of switches SW<sub>U </sub>and SW<sub>L </sub>indicates that the synchronizing signal processing apparatus operates with conventional video signal. Otherwise, the closing of the switches SW<sub>U </sub>and SW<sub>L </sub>shows out that the apparatus operates with HDTV video signal. The position of another switch SW<sub>T </sub>is also related to the video signal being processed by the apparatus in accordingaccordance with the present invention. Therefore, the apparatus of the present invention is suitable to different video signals by changing status of these switches, which may respond automatically to the video standard detector <b>103</b> as well.
0039The vertical sync filter <b>128</b> is coupled to the combination logic <b>126</b>. A composite synchronizing signal C<sub>S </sub>from the combination logic <b>126</b> is coupled to it. The vertical sync filter <b>128</b> filters the composite synchronizing signal C<sub>S </sub>to provide a vertical synchronizing signal V<sub>S</sub>. The vertical sync filter <b>128</b> may respond to a composite synchronizing signal from other sections as well, for example from <b>112</b>.
0040The sync pulse processing section <b>104</b> of synchronizing signal processing apparatus <b>100</b> is detailed with reference to FIG. <b>2</b>. Input amplifier <b>102</b> includes two operational amplifiers OP<b>1</b> and OP<b>2</b>. OP<b>1</b> is used with OP<b>2</b> to eliminate common mode noise of the video signal <b>101</b>. The positive input of OP<b>1</b> receives one of input video signal <b>101</b> which is the common one (shield) of the input signals. Resistor R<b>1</b>, 100 KΩ, is an input resistor for stabilizing the DC component of the input video signal.
0041A resistor R<b>2</b> (75 Ω) and a switch SW<sub>l </sub>are connected between the input lines for terminating video signal <b>101</b>. When the input is taken from other than the end of a coaxial cable run, SW<sub>I </sub>is open. While the video signal <b>101</b> is applied to input amplifier <b>102</b> at the end of a coaxial cable run, SW<sub>L </sub>is closed so that the input resistance of input amplifier <b>102</b> is matching the output resistance of the circuitry providing video signal <b>101</b>, thereby reducing signal loss. Capacitor C<b>1</b> (0.1 μf) provides a high frequency bypass from the common to ground. R<b>2</b> is the terminating resistor (75 Ω). OP<b>1</b> and resistors R<b>3</b> (<b>1.10 kK</b>Ω) and R<b>4</b> (<b>499 ΩconstituteΩ</b>) <i>constitute </i>a negative feedback amplifier its gain being two approximately. The output of OP<b>1</b> is coupled to the negative input of OP<b>2</b> via resistor R<b>5</b>, 2.21 KΩ.
0042The positive input of OP<b>2</b> receives the signal directly from the input signal <b>116</b><b>101</b>. OP<b>2</b> and resistors R<b>6</b>, R<b>7</b> and potentiometer R<b>8</b> provide another feedback amplifier. Resistor R<b>6</b> and R<b>7</b> have the same resistance, 1.0 KΩ. The potentiometer R<b>8</b> has a resistance from 0-10 KΩ. Thus, the gain of the input amplifier <b>102</b> may be adjusted between 1.5-3. Due to the delay caused by OP<b>1</b>, the common mode component of input signal <b>101</b> arrives at the positive and negative inputs of OP<b>2</b> at slightly different moment. Under low frequency, the delay due to OP<b>1</b> is tolerable. However, high frequency components of the input video signal, after delay by OP<b>1</b>, would severely affect correlation of the common mode signal, causing distortion of the video signal. Therefore, a filter having capacitor C<b>1</b> of 0.01 μf is utilized to filter the interference and noise to ground.
0043The output of OP<b>2</b> is coupled to the sync tip clamp <b>116</b> of the sync pulse processing section <b>104</b>. The sync tip clamp <b>116</b> includes buffers OP<b>3</b> and OP<b>4</b>, and an amplifier OP<b>5</b>. Resistor R<b>9</b> (5.6 KΩ) is used with capacitor C<b>2</b> to by-pass undesired frequency components. The buffered video signal is coupled to the positive input of another buffer OP<b>4</b> via an isolating capacitor C<b>3</b>, 0.1 μf. A negative 12 V is applied to the isolating capacitor C<b>3</b> and the positive input of OP<b>4</b>, via a current limit resistor R<b>10</b>, 147 KΩ. R<b>10</b> effectively constitutes a constant current source. The isolating capacitor C<b>3</b> is used to isolate the direct current components of the video signal.
0044The negative 12 V applied to the capacitor C<b>3</b> draws node N<b>1</b> toward a negative level, pulling the video signal output from OP<b>3</b> to a negative level. The negative video signal, after buffering by buffer OP<b>4</b>, is coupled to the negative input of the amplifier OP<b>5</b> via a resistor R<b>11</b> with resistance of 10 KΩ. OP<b>5</b> and a resistor R<b>12</b> with resistance of 39 KΩ establishes a negative feedback amplifier. The positive input of OP<b>5</b> is grounded. The resistance of the resistor R<b>12</b> determines the maximum gain of amplifier OP<b>5</b>, which may be lowered if D<b>3</b>, D<b>4</b> conduct.
0045Normally, the output of OP<b>5</b> is negative. Two diodes D<b>1</b> and D<b>2</b> are provided to isolate the output of OP<b>5</b> from the node N<b>1</b>. When the output of OP<b>5</b> is above a level required to turn the D<b>1</b> and D<b>2</b> on, for example 1.2 V, the capacitor C<b>3</b> is charged positive. The resistor R<b>10</b> charges C<b>3</b> negative, but is countered by the current through D<b>1</b> and D<b>2</b> when the video signal is below the ground of the positive input of OP<b>5</b>, thus causing N<b>1</b> to move in a positive direction, which forces the output signal of OP<b>5</b> to be returned to a negative value. The other two diodes D<b>3</b> and D<b>4</b> are arranged between the negative input and output of OP<b>5</b>. When the video signal at the negative input of OP<b>5</b> is more positive by a level high enough to turn D<b>3</b> and D<b>4</b> on, the negative input and output of OP<b>5</b> are shorted so that OP<b>5</b> functions as a buffer and prevents large negative excursions at the output, thereby causing OP<b>5</b> to recover to normal status very quickly, when returning positive.
0046Sync slicer <b>118</b> includes a comparator CP<b>6</b>. The output of OP<b>5</b> is directed to the positive input of CP<b>6</b>. The output of OP<b>4</b> is directed to the negative input of CP<b>6</b>. By comparison of the signals at its inputs, CP<b>6</b> slices the synchronizing pulses of the video signal at about half of the amplitude. By using both the outputs of OP<b>4</b> and OP<b>5</b>, the comparison is less sensitive to noise and sync amplitude variations than if a fixed level were used. For the NTSC and HDTV video signals, the output of CP<b>6</b> has a delay of about 0.1 μs. Comparator CP<b>6</b> slices the amplitude of the synchronizing pulses without appreciable change of pulse width.
0047The sliced pulses output from CP<b>6</b> are directed to the sync tip peak detector <b>120</b>. The sync tip peak detector <b>120</b> includes sample switches SW<sub>1 </sub>and SW<sub>2</sub>, and two sample holders consisting of resistors R<b>15</b> and R<b>16</b> with the same resistance of 1 KΩ, and capacitors C<b>6</b> and C<b>7</b> with the same capacitance of 0.1 μf. Resistor R<b>15</b>, capacitor C<b>6</b> and switch SW<sub>1 </sub>constitute a sample and hold circuit. Resistor R<b>16</b> and capacitor C<b>7</b> and SW<sub>2 </sub>constitute another sample and hold circuit. Two buffers OP<b>7</b> and OP<b>8</b> are respectively coupled to the two sample and hold circuits to output the sampled signals.
0048The sliced pulses from CP<b>6</b> are first inverted by an invertor I<b>1</b>. Thus, the rising edge of the inverted pulses coincide with the trailing edge of the output pulses of CP<b>6</b>. Each of the inverted pulses is then differentiated at its rising edges, by means of a differential capacitor C<b>4</b> of 0.001 μf and a differential resistor R<b>13</b> of 330Ω. The switch SW<sub>1 </sub>is in the receipt of the signal V<sub>O2 </sub>output from the DC restoration device <b>110</b>. Usually, switch SW<sub>1 </sub>is tied to ground via resistor R<b>13</b>. Only upon the arrival of the rising edges of the inverted pulses, switch SW<sub>1 </sub>is activated to couple to the hold circuit having R<b>15</b> and C<b>6</b>. Therefore, corresponding to each falling edge of the sliced pulses output from CP<b>6</b>, R<b>15</b> and C<b>6</b> sample the positive peaks of the pulses. Note that the sliced sync from CP<b>6</b> is opposite in polarity to the sync of V<sub>O2</sub>. The sampled positive peak is held for the buffer OP<b>7</b> to output. The width of the differential pulse for sampling the video signal is set by C<b>4</b> and R<b>13</b>.
0049Similarly, after inversion twice by invertors I<b>2</b> and I<b>3</b>, the output of CP<b>6</b> is differentiated by a differential capacitor C<b>5</b> of 0.001 μf and a differentdifferential resistor R<b>14</b> of 330Ω. Thus a differential pulse is coupled to switch SW<sub>2</sub>. The differential pulses produced by C<b>5</b> and R<b>14</b> cause the switch SW<sub>2 </sub>to close so that a resistor R<b>16</b> of 1 KΩ and a capacitor C<b>7</b> of 0.1 μf hold the negative peaks of the synchronizing pulses. The two signals which operate sample switches SW<b>1</b>SW<sub>1 </sub>and SW<b>2</b>SW<sub>2 </sub>can be described as reference taking signals, since they take the instant samples which are in turn held by the hold capacitors to generate the voltage reference signals used by the divider <b>124</b> to provide reference for comparator <b>122</b>.
0050As a result, each of the pair of differential pulses produced by C<b>4</b>, R<b>13</b>, C<b>5</b> and R<b>14</b> defines the pulse position of respective synchronizing pulses. The relationship of the output pulses of CP<b>6</b> and the differential pulses is shown in FIG. <b>5</b>. Furthermore, buffers OP<b>7</b> and OP<b>8</b> deliver the peak sample signals to divider <b>124</b> for further processing.
0051The video signal amplified by the input amplifier <b>102</b> is also coupled to the DC restoration device <b>110</b>, referring to FIG. <b>3</b>. The DC restoration device <b>110</b> includes a voltage comparator CP<b>9</b>, a photosensitive element having a LED (light-emitting diode) D<sub>u </sub>and a photoresistor R<b>59</b>, an amplifiersamplifier OP<b>10</b> and a buffer OP<b>11</b>. A positive 5 V DC voltage is tied to a resistor R<b>17</b> or 1.0 KΩ, the left part of the photoresistor R<b>59</b> and the tap of R<b>16</b>R<b>59</b>is connected to ground. Thus, the voltage applied to the positive input of the CP<b>9</b> depends on the resistance of left part of R<b>59</b>. On the other hand, the positive 5 V is tied to a series connection of potentiometer R<b>18</b> and a resistor R<b>19</b> and to ground. Thus, the reference voltage at the negative input of CP<b>9</b> is defined by the position of the wiper of potentiometer R<b>18</b>. Therefore, adjusting the position of the wiper of potentiometer R<b>18</b> may change the input voltage at the negative input of CP<b>9</b>.
0052At the output of CP<b>9</b>, a positive 5 V is applied to the LED Du through a resistor R<b>20</b> of 200Ω. The positive 5 V provides an offset current to LED D<sub>u</sub>. The light intensity of the LED Du is in proportion to the current flowing through it. The resistance of photoresistor R<b>59</b> is inversely proportional to the light intensity. Therefore, the higher the output of CP<b>9</b>, the larger the current through the LED Du, the lower the resistance of the photoresistor R<b>59</b>. The lower resistance of R<b>59</b> makes the voltage applied to the positive input of CP<b>9</b> go down, thereby causing the output of CP<b>9</b> to decrease. CP<b>9</b> thus causes R<b>59</b> to maintain the voltage at the positive and negative inputs of CP<b>9</b> to be equal.
0053The output of the input amplifier <b>102</b> is coupled to the positive input of the amplifier OP<b>10</b> of DC restoration device <b>110</b>, via a resistor R<b>1</b>R<b>21</b>of 330Ω. The output of OP<b>10</b> is tied to the negative input via a feedback resistor R<b>22</b>, 1.0 KΩ and the right part of the photoresistor R<b>59</b> ties the negative input of OP<b>10</b> to ground. Because the output of CP<b>9</b> may change the resistance of R<b>59</b>, the gain of OP<b>10</b> is also controlled by the output of CP<b>9</b>. Therefore, changing the position of the wiper of potentiometer R<b>18</b> changes the gain of OP<b>10</b>.
0054The output of OP<b>10</b> is applied to the positive input of amplifier OP<b>11</b>. Along with a resistor R<b>23</b> of 1.0 KΩ, the operational amplifier OP<b>11</b> buffers the output of OP<b>10</b>. The video signal from buffer OP<b>11</b> is transferred to the sync tip peak detector <b>120</b> where the video signal is sampled in response to the pulses from the sync slicer <b>118</b>, as shown in FIG. <b>2</b>. The video signal output amplified by OP<b>10</b> is also sent out by an output resistor R<b>24</b>, 71.5Ω for other purposes.
0055An offset device <b>108</b> is arranged to provide a DC offset required by the operational amplifier OP<b>13</b> of the DC restoration device <b>110</b>. The offset device <b>108</b> includes a resistor network having a resistor R<b>57</b> (100 KΩ), a resistor R<b>57</b>R<b>56</b>(100 Ω) and a potentiometer R<b>55</b>. A positive 12 V is coupled to resistor R<b>57</b> and a negative 12 V is coupled to resistor R<b>25</b>R<b>56</b>. A voltage determined by the position of the wiper of potentiometer R<b>55</b> charges a capacitor C<b>13</b>of 0.1 μf via a resistor R<b>58</b> of 100 KΩ. The level on the capacitor C<b>13</b> is applied to the positive input of a buffer OP<b>12</b>.
0056The offset voltage is delivered to an integrator circuit established by a operational amplifier OP <b>13</b> and a capacitor C<b>8</b> (0.1 μf) bridging between the negative input and output of OP<b>13</b>. The positive input of OP<b>13</b> receives the offset voltage. The offset voltage is also coupled to a switch SW<sub>3</sub>. The common close status of SW<sub>3 </sub>couples the offset voltage to the negative input of OP<b>13</b> via a resistor R<b>25</b> of 10 KΩ. A capacitor C<b>9</b> of 0.001 μf is tied between ground and SW<sub>3 </sub>for filtering undesired frequency components and switching transients.
0057In accordance with the present invention, the pulse width adjust <b>106</b> is provided for . The pulse width adjust <b>106</b> includes two multivibrators <b>301</b> and <b>302</b>. The output from the sync slicer <b>118</b> is coupled to the AĀ input of <b>301</b>, as shown in <figref idref="DRAWINGS">FIG. 3. A</figref> positive 5 V, is tied to the clear input <o ostyle="single">Cl</o>r and the B input of <b>301</b>. Responding to each falling edge of the sliced signal from sync slicer <b>118</b>, the multivibrator <b>301</b> produces a low level pulse at the <o ostyle="single">Q</o> output of <b>301</b>. The width of the low level pulse is set by a resistor R<b>54</b> of 10 KΩ and a capacitor C<b>10</b> of 0.001 μf. The output from <b>301</b> is shown in FIG. <b>5</b>.
0058The output from sync slicer <b>118</b> is also coupled to the B input of multivibrator <b>302</b> via a delay circuit. This delay circuit includes two RC filters. A capacitor C<b>14</b> (51 pf) and a resistor R<b>28</b> (10 KΩ) form a RC filter and a capacitor C<b>12</b> (56 pf) and a resistor R<b>60</b> (2.5 KΩ) provide another one. Two invertors I<b>4</b> and I<b>5</b> are arranged between the two RC filters. An invertor I<b>6</b> is positioned between the B input of <b>302</b> and RC filter having C<b>12</b> and R<b>60</b>. A positive 5 V is applied to R<b>28</b> via a resistor R<b>58</b>R<b>27</b>(<b>1 kK</b>Ω) for providing a DC bias. This delay circuit delays the sliced signal from sync slicer <b>118</b> about 0.75 μs to 0.9 μs.
0059The pulses at the <o ostyle="single">Q</o> output of <b>301</b> trigger the multivibrator <b>302</b> via its Ā input so that the Q output of <b>302</b> is at high level. The delayed pulses by the delay circuit is applied to B input of <b>302</b>, triggering it so that the Q output of <b>302</b> is at a high level. The pulse width of output pulse from <b>302</b> is set by a resistor R<b>29</b> of 3.32 KΩ and a capacitor C<b>11</b> of 0.001 μf, if the apparatus <b>100</b> in accordance with the present invention operates under conventional TV video signal mode, for example, the NTSC video signal. When the apparatus <b>100</b> operates under the HDTV mode, a resistor R<b>30</b> of 1 KΩ is shunted with R<b>29</b> by closing of the switch SW<sub>p</sub>.
0060Therefore, the pulse width of Q output of <b>302</b> is between 2 μs and 2.5 μs for the NTSC video signal. This pulse occurs during blanking and burst portion of the NTSC video signal. On the other hand, the pulse width of the Q output of <b>302</b>, for the HDTV video signal, is from 0.5 μs to 0.7 μs. The pulse of Q output of <b>302</b> coincides with the blanking portion without exceeding it. The waveform at the Q output of <b>301</b> is shown in FIG. <b>5</b>.
0061The output pulses at the Q output of <b>302</b> activate the SW<sub>3 </sub>so that the output from OP<b>11</b> is coupled to the negative input of OP<b>13</b> via the RC filter having the resistor R<b>25</b> and the capacitor C<b>9</b>. During the high level of the pulses from <b>302</b>, the capacitor C<b>8</b> of the integrator OP<b>13</b> is charged up and down by the video signal from the buffer OP<b>11</b> depending on whether it is above or below the reference on the plus input of OP<b>13</b>, drawing the input voltage at the positive input of OP<b>10</b> up or down. As a result, the output of OP<b>10</b> is drawn up or down. After the Q output of <b>302</b> recovers to a low level, the switch SW<sub>3 </sub>is released so that the negative input of the operational amplifier OP<b>13</b> is coupled to the output of OP<b>12</b> of the offset device <b>108</b>. Thus, the <b>10</b> output of the operational amplifier OP<b>13</b> does not change.
0062The divider <b>124</b> of the reference sync generating section <b>112</b> includes four resistors R<b>31</b>, R<b>32</b>, R<b>33</b> and R<b>34</b>. The resistors R<b>31</b>-R<b>34</b> have the same resistance of 10 KΩ. Therefore, the output potential of the sync tip peak detector <b>120</b> is equally divided so that three reference potentials are provided. The first reference potential between the resistors R<b>33</b> and R<b>34</b> equals half of the output potential from the sync tip peak detector <b>120</b>. The second reference potential between the resistors R<b>31</b> and R<b>33</b> equals three-fourth of the output level from the sync tip peak detector <b>120</b>. The third reference potential between the resistors R<b>32</b> and R<b>34</b> equals one-fourth of the output level from the sync tip peak detector <b>120</b>. However, different reference potentials may also be obtained by changing the resistance of resistors R<b>31</b>-R<b>34</b>. Different combination of potentials on the positive inputs of CP<b>14</b>-CP<b>16</b> can be easily realized.
0063In accordance with the present invention, the comparator <b>122</b> of reference sync generating section <b>112</b> includes three comparators CP<b>14</b>, CP<b>15</b> and CP<b>16</b>. The first reference potential between the resistors R<b>33</b> and R<b>34</b> is applied to the positive input of comparator CP<b>14</b>. The second reference potential between the resistors R<b>31</b> and R<b>33</b> is applied to the positive input of the comparator CP<b>15</b>. The third reference potential is then applied to the positive input of the comparator CP<b>16</b>. The video signal output V<sub>O1 </sub>from the amplifier OP<b>10</b> of the DC restoration device <b>110</b> is coupled to respective negative inputs of three comparators CP<b>14</b>-CP<b>16</b> via resistor R<b>35</b>, R<b>36</b> and R<b>37</b>.
0064As for conventional TV video signals, for example, the NTSC video signal, CP<b>14</b> compares the first reference potential and the video signal V<sub>O1 </sub>so as to sense the middle levels of the horizontal and vertical synchronizing pulses. The comparator CP<b>15</b> then senses the video signal V<sub>O1 </sub>in response to the second reference potential and the rest of the video signal V<sub>O1 </sub>is regarded as noise. Because the switch SW<sub>1 </sub>of sync tip peak detector <b>120</b> closes during the blanking-burst period to sample the video signal, the second reference potential is set to a level lower than the blanking level. The switch SW<sub>2 </sub>of sync tip peak detector <b>120</b> closes during the negative synchronizing tip to sample the video signal, the third reference potential is thus set to a level higher than the negative tip. Two complementary outputs V<sub>P3 </sub>and V<sub>C3 </sub>from CP<b>16</b> are delivered to the combination logic <b>126</b>.
0065As a second example, when the apparatus <b>100</b> in accordance with the present invention is used for processing the HDTV video signal, the second reference potential represents a value between the blanking and positive peak synchronizing tip for the synchronizing pulses. The rest of the video signal V<sub>O1 </sub>is considered as noise. The first reference potential is set at the middle of the negative and positive synchronizing tip during synchronizing pulses, meaning at the blanking level. The purpose of this comparator CP<b>14</b> is to sense transition from the negative synchronizing tip to the positive synchronizing tip. The rest of the video signal V<sub>O1 </sub>is considered as noise. The reference potential and the output V<sub>P3 </sub>of CP<b>16</b> is the same as under the NTSC video signal. Therefore, outputs of comparator <b>122</b> are logic levels corresponding to the negative sync for these video signals.
0066The logic level outputs V<sub>P1</sub>, V<sub>P2</sub>, V<sub>P3 </sub>and V<sub>C3 </sub>from the comparator <b>122</b> are directed to the combination logic <b>126</b> of the sync restoring section <b>114</b>, as shown in FIG. <b>4</b>. The output V<sub>P1 </sub>of the comparator CP<b>14</b> is directed to an input of an AND gate A<b>1</b>. The signal V<sub>C3 </sub>output from the comparator CP<b>16</b> is inverted by an invertor I<b>7</b>, and is filtered by a RC filer having a resistor R<b>53</b> (200Ω) and a capacitor C<b>17</b> (0.001 μf). Before it is applied to another input of the AND gate A<b>1</b>, the filter signal V<sub>C3 </sub>is inverted again by an invertor I<b>8</b>. In order to preserve the combination logic generated sync information at the half way crossing, the output V<sub>C3 </sub>from the comparator CP<b>16</b> is delayed by the invertor I<b>7</b> and I<b>8</b> circuit for 85 ns-200 ns. Thus, the two input pulses are anded at the inputs of the AND gate A<b>1</b> so that the output of A<b>1</b> is a positive pulse.
0067Along with the output from the AND gate A<b>1</b>, the output V<sub>P2 </sub>from the comparator CP<b>15</b> is directed to an input of an OR gate O<b>1</b>. The positive pulse from A<b>1</b> and the V<sub>P2 </sub>active the OR gate O<b>1</b>, thereby producing a pulse which has a rising edge defined by the positive pulse from A<b>1</b> and a falling edge defined by V<sub>′P2</sub>. The output of OR gate O<b>1</b> is directed to another OR gate O<b>2</b>.
0068The output V<sub>C3 </sub>is also used to trigger a multivibrator <b>401</b> so that a high level is set at the <o ostyle="single">Q</o> output of the multivibrator <b>401</b>. The width of the high level is set by a resistor R<b>38</b> and a capacitor C<b>8</b>C<b>18</b>. In this case of, where capacitor C<b>8</b>C<b>18</b>has a capacitance of 0.001 μf and resistor R<b>38</b> has a resistance of 2.9 KΩ, the pulse width is between 1.4 μs-2.8 μs. The output high level at the <o ostyle="single">Q</o> output of <b>401</b> is directed to an input of an AND gate <b>35</b> A<b>2</b>. The anotherAnother input of A<b>2</b> receives the output V<sub>P3 </sub>from the comparator CP<b>16</b>. For the NTSC video signal, the output of A<b>2</b> is determined by signal V<sub>P3</sub>. Under the HDTV video signal, the output of A<b>2</b> is determined by the pulse at the <o ostyle="single">Q</o> output <b>401</b>. The minimum width for this pulse is 2.6 μs which is determined by the duration of the vertical interval pulses. The maximum width for this pulse is 2.8 μs which is determined by the duration of the blanking in horizontal lines.
0069The ANDed output from A<b>2</b> is applied to another input of OR gate O<b>2</b> so that the output from OR gate O<b>1</b> is ORed with the ANDed output from A<b>2</b>. Particularly, under processing the NTSC video signal, the ORed output of OR gate O<b>1</b> is completely determined by the ANDed output pulse from A<b>2</b>. The reason is that the negative ANDed output from A<b>2</b> is narrower than the negative ORed output from O<b>1</b>. The output of O<b>2</b> is a composite synchronizing output C<sub>S</sub>.
0070In order to extract horizontal synchronizing pulses from the output C<sub>S </sub>from the OR gate O<b>2</b>, a circuitry including multivibrators <b>402</b> and <b>403</b>, and OR gates O<b>3</b> and O<b>4</b> is designed. This circuitry eliminates every second half horizontal pulse from the vertical interval. The signal V<sub>C3 </sub>output from the comparator CP<b>16</b> is directed to the multivibrator <b>402</b>, where V<sub>C3 </sub>triggers the B input of <b>402</b> to set a low level at its <o ostyle="single">Q</o> output. The width of this low level is set by a capacitor C<b>19</b> (0.001 μf) and a resistor R<b>39</b> (11.3 KΩ). In this case, the low level lasts 6-10 μs. The 6 μs lower time limit is chosen to be greater than the horizontal synchronizing pulse duration. The upper time limit is chosen so that the pulse will not to get into active video signal.
0071The <o ostyle="single">Q</o> output of <b>402</b> triggers the B input of the multivibrator <b>403</b> so as to set a high level output at its Q output. The duration of the high level at the Q output of <b>403</b> is determined by a capacitor C<b>20</b> (0.001 μf) and the combination of resistors R<b>40</b> (68 KΩ) and R<b>41</b> (50 KΩ). The position of switch SW<sub>U </sub>is determined by the operation mode. For example, under the NTSC video signal, SW<sub>U </sub>is open so that the duration of the high level at the Q output of <b>403</b> is set by R<b>40</b> and C<b>12</b>C<b>20</b>, for example 35 μs-50 μs. On the other hand, if the apparatus <b>100</b> of the present invention is for processing the HDTV video signal, the switch SW<sub>U </sub>is closed so that R<b>41</b> is shunted across R<b>40</b>. Accordingly, the duration of the high level at the Q output of <b>403</b> is determined by C<b>20</b> and the shunted resistors R<b>40</b> and R<b>41</b>, for example 17 μs-20 μs.
0072The Q output of <b>403</b>, along with the <o ostyle="single">Q</o> output of <b>402</b>, is coupled to inputs of an OR gate O<b>3</b>. The output of OR gate O<b>3</b> is the OR of the outputs of the both multivibrators <b>402</b> and <b>403</b>. This output of O<b>3</b> coincides with the synchronizing tip but lasts a little longer. The output of <b>03</b>O<b>3</b>is directed to an OR gate O<b>4</b>. Another input of the OR gate O<b>4</b> receives the output from the OR gate O<b>2</b>. The OR gate O<b>4</b> serves to eliminate the half horizontal pulses during the vertical intervals, thereby producing a horizontal synchronizing output H<sub>S</sub>.
0073A multivibrator <b>404</b> is used to generate a horizontal square waveform output H<sub>Q</sub>. The output H<sub>S </sub>of the OR gate O<b>4</b> is coupled to the B input of <b>404</b> via the switch SW<sub>T</sub>. When the apparatus <b>100</b> of the present invention operates under the HDTV video signal, the rising edges of output H<sub>S </sub>triggers <b>404</b> at the B input to set a high level output at its Q output. Meanwhile, the switch SW<sub>L </sub>is closed so that the positive 5 V is applied to <b>404</b> via shunted resistors R<b>42</b> and R<b>43</b> and a capacitor C<b>21</b>. Accordingly, the duration of the high level depends on a capacitor C<b>21</b> and the resistance of shunted resistors R<b>42</b> and R<b>43</b>. If the capacitance of C<b>21</b> is set as 0.001 μf and R<b>42</b> and R<b>43</b> are respectively set as 51 KΩ, the duration is then 30 μs.
0074If the apparatus <b>100</b> of the present invention operates with the NTSC video signal, the output H<sub>S </sub>is reversed by an invertor I<b>6</b>I<b>9</b>so that the B input of <b>404</b> is triggered by the falling edges of the synchronizing pulse, setting a high level at its Q output. At the same time, the switch SW<sub>L </sub>is open so that the positive 5 V voltage is applied to <b>404</b> via only a resistor R<b>42</b>. Assuming R<b>42</b> has the resistance of 51 KΩ and C<b>31</b>C<b>21</b>has the capacitance of 0.001 μf, the duration of the high level at the Q output of <b>404</b> is 30 μs.
0075The output C<sub>S </sub>of OR gate O<b>2</b> is also directed to a vertical synchronizing filter circuitry including operational amplifiers OP<b>17</b> and OP<b>18</b>. A resistor R<b>44</b> of 37.4 KΩ and a capacitor C<b>22</b> of 0.001 μf bridge across the output and negative input of OP<b>17</b> to form a first stage low pass filter. The positive input of OP<b>17</b> is tied to ground. The composite synchronizing output C<sub>S </sub>is coupled to the negative input of OP<b>17</b> via a resistor R<b>52</b> of 39 KΩ. The output from OP<b>17</b> is coupled to the negative input of OP<b>18</b> via a 10 Ω resistor R<b>50</b>. The positive input of OP<b>18</b> is tied to ground. A resistor R<b>45</b> (10 KΩ) and a capacitor C<b>15</b> (0.001 μf) are shunted across the negative input and the output of OP<b>18</b>, thereby providing a second stage low pass filter.
0076This vertical filter circuitry employs a design <b>25</b> offsetting conventional optimal design. This design provides a frequency response characteristic without matching standard filter design curves which are commonly known. However, it is this design that provides a frequency response characteristic good for vertical synchronizing separation of the NTSC or HDTV video signal. This frequency response of the filter circuitry is shown in FIG. <b>6</b>.
0077The filtered signal is applied to a positive input of a comparator CP<b>19</b> via a 330Ω resistor R<b>51</b>. A resistor R<b>46</b> of <b>3.3 kK</b>Ω is bridged between the positive input and output of CP<b>19</b> to provide positive feedback hysteresis for CP<b>19</b>. A positive 5 V voltage is tied to ground via resistors R<b>47</b> and R<b>48</b>. R<b>47</b> has resistance of 20 KΩ and R<b>48</b> has resistance of 10 KΩ. A capacitor C<b>16</b> of 0.1 μf is shunted across resistor R<b>48</b>, thereby providing a stable reference voltage to the negative input of CP<b>19</b>. Furthermore, a positive 5 V voltage is applied to the output of CP<b>19</b> via a resistor R<b>49</b> (1 KΩ). Filter circuitry provides a vertical synchronizing output V<sub>S </sub>via CP<b>19</b> and inverted by an invertor <b>110</b>.
0078To obtain a field synchronizing output, the vertical synchronizing output from CP<b>19</b> is directed to a flip-flop <b>405</b>. The clear input CLR and set input PR of <b>405</b> are coupled to a positive 5 V. The CK input of <b>405</b> receives vertical sync and the D input of <b>405</b> is coupled to H sync square waveform the <o ostyle="single">Q</o> output of multivibrator <b>404</b>. The rising edges of the V<sub>S </sub>pulses activate the trigger <b>405</b> to produce the field synchronizing output F<sub>S</sub>. Upon arrival of the rising edges, the Q output of <b>405</b> is set to such a level that is same as that at its D input. In addition, an invertor I<b>11</b> is provided for outputting a reversed composite synchronizing output <o ostyle="single">C</o><sub>S</sub>.
0079A processing method <b>700</b> for synchronizing pulses of the video signals is shown in FIG. <b>7</b>. At step <b>701</b>, the video signal is sliced to produce synchronizing pulses. The video signal is then sampled in response to the sliced sync to precisely sense the sync tip peaks pulses, at step <b>702</b>, thereby providing two peak signal values representing the positive and negative peak values of each synchronizing pulse.
0080The peak signal values are further converted, at step <b>703</b>, into three reference signals which respectively represent the different levels relative to each synchronizing pulse. In particular, the three reference levels respectively represent the middle, upper and lower middle levels of the synchronizing pulse. Comparison of the three reference levels and the video signal is conducted at step <b>704</b>. As a result of this comparison, the logic pulse outputs are obtained. Step <b>705</b> is for restoring synchronizing pulses of the video signal by combining the logic outputs.
0081<figref idref="DRAWINGS">FIGS. 8-11</figref> show a more detailed schematic circuit of a preferred embodiment in accordance with the present invention. All of the components in <figref idref="DRAWINGS">FIGS. 8-11</figref> correspond directly to those presented in <figref idref="DRAWINGS">FIGS. 2-4</figref>. The differences between <figref idref="DRAWINGS">FIGS. 2-4</figref> and <b>8</b>-<b>11</b> are that all of components in <figref idref="DRAWINGS">FIGS. 8-11</figref> are marked with commercial identification and are therefore more available in market. Therefore, detailed product part numbers and nominal values of components are marked on the components of <figref idref="DRAWINGS">FIGS. 8-11</figref>. The operation principle and interconnection of the components of the circuitry shown in <figref idref="DRAWINGS">FIGS. 8-11</figref> are corresponding to FIG. <b>1</b> and <figref idref="DRAWINGS">FIGS. 2-4</figref> and one skilled in the art will be able to understand <figref idref="DRAWINGS">FIGS. 8-11</figref> from the forgoing description and explanation. Thus, the description of <figref idref="DRAWINGS">FIGS. 8-11</figref> is omitted here.
0082One skilled in the art will recognize that the above described functions and components are somewhat more complex than represented by the present block diagrams, however from the disclosure and teachings herein, taken with the available applications literature available from the manufacturers of the suggested components, or from other components which may be substituted as will be known from the above disclosure, the construction of a practical and operatable device will be well within the capability of one or ordinary skill in the art without resorting to further invention or undue experimentation.
0083It will be understood that the previous descriptions and explanations are given by way of example, and that numerous changes in the combinations of elements and functions as well as changes in design of the above may be made without departing from the spirit and scope of the invention as hereinafter claimed. In particular, it will be useful to combine the functions of the invention with other functions in a fashion so that such functions may be shared between devices or methods. These and other modification to and variations upon the embodiments described above are provided for by the present invention, the scope of which is limited only by the following claims.
Contents4
12 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9 Sheet 10 Sheet 11 Sheet 12
Every citation, both ways
| Document | Relation | Office | Cited during |
|---|---|---|---|
| US7787057B2 | Cited by | United States of America | Search report |
| US8154664B2 | Cited by | United States of America | Search report |
| US2008062326A1 | Cited by | United States of America | Pre-grant |
| US8634028B2 | Cited by | United States of America | Search report |
| US7940335B2 | Cited by | United States of America | Search report |
| US2011069236A1 | Cited by | United States of America | Pre-grant |
| US2012194746A1 | Cited by | United States of America | Pre-grant |
| US2008002057A1 | Cited by | United States of America | Pre-grant |
| GB1143241A | Cites | United Kingdom | Applicant |
| GB2200011A | Cites | United Kingdom | Applicant |
| US3569844A | Cites | United States of America | Applicant |
| US3706847A | Cites | United States of America | Applicant |
| US3819859A | Cites | United States of America | Applicant |
| US4097896A | Cites | United States of America | Applicant |
| US4115811A | Cites | United States of America | Applicant |
| US4233629A | Cites | United States of America | Applicant |
| US4298890A | Cites | United States of America | Applicant |
| US4305091A | Cites | United States of America | Applicant |
| US4313135A | Cites | United States of America | Applicant |
| US4385319A | Cites | United States of America | Applicant |
| US4498141A | Cites | United States of America | Applicant |
| US4520393A | Cites | United States of America | Applicant |
| US4532541A | Cites | United States of America | Applicant |
| US4573070A | Cites | United States of America | Applicant |
| US4665431A | Cites | United States of America | Applicant |
| US4680633A | Cites | United States of America | Applicant |
| US4703355A | Cites | United States of America | Applicant |
| US4812907A | Cites | United States of America | Applicant |
| US4816830A | Cites | United States of America | Applicant |
| US4829257A | Cites | United States of America | Applicant |
| US4866543A | Cites | United States of America | Applicant |
| US4868428A | Cites | United States of America | Applicant |
| US4872070A | Cites | United States of America | Applicant |
| US4882624A | Cites | United States of America | Applicant |
| US5097218A | Cites | United States of America | Applicant |
| US5202761A | Cites | United States of America | Applicant |
| US5260790A | Cites | United States of America | Applicant |
| US5424780A | Cites | United States of America | Applicant |
| US5432559A | Cites | United States of America | Applicant |
| US5459524A | Cites | United States of America | Applicant |
| US5486869A | Cites | United States of America | Applicant |
| US5530483A | Cites | United States of America | Applicant |
| US5543743A | Cites | United States of America | Applicant |
| US5548236A | Cites | United States of America | Applicant |
| US5550594A | Cites | United States of America | Applicant |
| US5572261A | Cites | United States of America | Applicant |
| US5592508A | Cites | United States of America | Applicant |
| US5635725A | Cites | United States of America | Applicant |
| US5675277A | Cites | United States of America | Applicant |
| US5675388A | Cites | United States of America | Applicant |
| US5751368A | Cites | United States of America | Applicant |
| US5754250A | Cites | United States of America | Applicant |
| US5793053A | Cites | United States of America | Applicant |
| US5834747A | Cites | United States of America | Applicant |
| US5874910A | Cites | United States of America | Applicant |
| US5920842A | Cites | United States of America | Applicant |
| US5946049A | Cites | United States of America | Applicant |
| US5949087A | Cites | United States of America | Applicant |
| US5996906A | Cites | United States of America | Applicant |
| US6078038A | Cites | United States of America | Applicant |
| US6098046A | Cites | United States of America | Applicant |
| US6141057A | Cites | United States of America | Applicant |
| US6191407B1 | Cites | United States of America | Applicant |
| US6308890B1 | Cites | United States of America | Applicant |
| US6330033B1 | Cites | United States of America | Applicant |
| US6351281B1 | Cites | United States of America | Applicant |
| US6392707B1 | Cites | United States of America | Applicant |
| US6421636B1 | Cites | United States of America | Applicant |
| US6469741B2 | Cites | United States of America | Applicant |
| US6529637B1 | Cites | United States of America | Applicant |
| USRE33535E | Cites | United States of America | Applicant |
| JPS5797274A | Cites | Japan | Applicant |
| JPS58178669A | Cites | Japan | Applicant |
| JPS63186270A | Cites | Japan | Applicant |
| GB1143241 | Cites | United Kingdom | Third party observation |
| GB2200011 | Cites | United Kingdom | Third party observation |
| JP97274 | Cites | Japan | Third party observation |
| JP178669 | Cites | Japan | Third party observation |
| JP186270 | Cites | Japan | Third party observation |
| Cooper, J. Carl, "Viewer Stress from Audio/Visual Sync Problems", SMPTE Journal, vol. 97, No. 2, pp. 140-142, Feb. 1988. | Non-patent | – | Applicant |
| Cooper, J. Carl, "Video-to-Audio Synchrony Monitoring and Correction", SMPTE Journal, vol. 97, No. 2, pp. 695-698, Sep. 1988. | Non-patent | – | Applicant |
| Cooper, J. Carl, "Sine Squared Shaping of Sync and Drive Pulses", IEEE Transactions on Broadcasting, vol. 36, No. 2, pp. 162-169, Jun. 1990. | Non-patent | – | Applicant |
| Cooper, J. Carl, "Second generation audio-to-video synchronization", Broadcast Engineering, pp. 68-72, Sep. 1995. | Non-patent | – | Applicant |
| Complaint by Defendent and Third Party Plaintiff Videotek, Inc. Against Third Party Defendant Gennum Corporation for Breach of Warranty dated Sep. 3, 2002. | Non-patent | – | Applicant |
| Product brochure-DVL 2002 Video Processor-"Maximizing Printer Quality". | Non-patent | – | Applicant |
| Product brochure-DPS-1 by Digital Video Systems-"First in a new advanced class of digital processors!". | Non-patent | – | Applicant |
| Product brochure -DPS-1 by Digital Video Systems-"Setting a new standard for the Industry/The Third Generation Time Base Corrector". | Non-patent | – | Applicant |
| DPS-1 Digital Processing System price list dated Oct. 1978. | Non-patent | – | Applicant |
| Brochure entitled DPS-1 Frame Store dated Mar. 1979. | Non-patent | – | Applicant |
| Promotional Brochure entitled Phaser dated Mar. 1979. | Non-patent | – | Applicant |
| Schematic for an electronic circuit-Digital Video Systems Drawing No. 1DS-5179-1 dated Sep. 21, 1976. | Non-patent | – | Applicant |
| Schematic for circuit design for Digital Video Systems dated 1979. | Non-patent | – | Applicant |
| Enlarged version of Exhibit 388, dated 1979. | Non-patent | – | Applicant |
| Schematic for the 1000GG drawn by Susan Van Nood dated Dec. 2, 1984. | Non-patent | – | Applicant |
| Schematic for IGC 7051-Input Clock Generator-Drawing No. 743H72, Digital Video Systems. | Non-patent | – | Applicant |
| Instruction manual-DTG 1000N Digital Test Generator, Leitch. | Non-patent | – | Applicant |
| Advance Product Information/DTG-1000 Digital Test Generator, Leitch. | Non-patent | – | Applicant |
| Propreitary Information/DTS-2000N Digital Television Scrambler & DTD-2000N Digital Television Descrambler, Preliminary Instruction Manual dated May 26, 1982. | Non-patent | – | Applicant |
| Input Clock Generator (ICG 7051-1) Preliminary Circuit Description and test Procedures-Prepared by Joseph Yu dated Sep. 1977. | Non-patent | – | Applicant |
| Schematic for Sync/Color Bars Generator, Sheet 1 of 6 dated May 30, 1989. | Non-patent | – | Applicant |
4 members in 1 office
Priority claims10
| Document | Office | Kind | Date |
|---|---|---|---|
| 83732392 | United States of America | A | |
| 83732392 | United States of America | A | |
| 16568893 | United States of America | A | |
| 16568893 | United States of America | A | |
| 85734104 | United States of America | A | |
| 07837323 | – | – | – |
| 08165688 | – | – | – |
| US19920837323 | – | – | – |
| US19930165688 | – | – | – |
| US20040857341 | – | – | – |
Members4
| Document | Office | Kind | |
|---|---|---|---|
| US5486869A | United States of America | A | |
| US5754250A | United States of America | A | |
| USRE40411E | United States of America | E | |
| USRE40412EThis record | United States of America | E |
70 transactions on the USPTO file
Allowed after 1 non-final rejection and 1 final rejection.
- Non-final rejections
- 1
- Final rejections
- 1
- RCEs
- 0
- Appeals
- 0
Over time
Point at a mark for the transactionTransactions
| Event | Code | |
|---|---|---|
| Recordation of Patent Grant MailedPGM/ | PGM/ | |
| Issue Notification MailedAllowedWPIR | WPIR | |
| Receipt into PubsR1021 | R1021 | |
| Dispatch to FDCD1935 | D1935 | |
| Application Is Considered Ready for IssuePILS | PILS | |
| Issue Fee Payment VerifiedN084 | N084 | |
| Issue Fee Payment ReceivedIFEE | IFEE | |
| Mail Notice of AllowanceAllowedMN/=. | MN/=. | |
| Notice of Allowance Data Verification CompletedAllowedN/=. | N/=. | |
| Entity status set to undiscounted (initial default setting or status change)BIG. | BIG. | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response after Final ActionA.NE | A.NE | |
| Mail Final Rejection (PTOL - 326)Final rejectionMCTFR | MCTFR | |
| Final RejectionFinal rejectionCTFR | CTFR | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Oath or Declaration Filed (Including Supplemental)C602 | C602 | |
| Response after Non-Final ActionA... | A... | |
| Mail Examiner Interview Summary (PTOL - 413)MEXIN | MEXIN | |
| Mail Non-Final RejectionNon-final rejectionMCTNF | MCTNF | |
| Non-Final RejectionNon-final rejectionCTNF | CTNF | |
| Withdraw Flagged for 5/25W525 | W525 | |
| Flagged for 5/25F525 | F525 | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Examiner Interview Summary Record (PTOL - 413)EXIN | EXIN | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Electronic Information Disclosure StatementEIDS. | EIDS. | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Mail-Petition Decision - DismissedMPTDI | MPTDI | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Cleared by OIPE CSRL194 | L194 | |
| Preliminary AmendmentA.PE | A.PE | |
| Cleared by OIPE CSRL194 | L194 | |
| Cleared by OIPE CSRL194 | L194 | |
| Cleared by OIPE CSRL194 | L194 | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Electronic Information Disclosure StatementEIDS. | EIDS. | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Cleared by OIPE CSRL194 | L194 | |
| Miscellaneous Incoming LetterLET. | LET. | |
| Petition EnteredPET. | PET. | |
| Mail Examiner Interview Summary (PTOL - 413)MEXIN | MEXIN | |
| Cleared by OIPE CSRL194 | L194 | |
| Examiner Interview Summary Record (PTOL - 413)EXIN | EXIN | |
| Miscellaneous Incoming LetterLET. | LET. | |
| Miscellaneous Incoming LetterLET. | LET. | |
| IFW TSS Processing by Tech Center CompleteTSSCOMP | TSSCOMP | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Corrected filing receiptCFRPT | CFRPT | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Notice of Reissue Published in Official GazetteNRE. | NRE. | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Application Is Now CompleteCOMP | COMP | |
| Application Dispatched from OIPEOIPE | OIPE | |
| Cleared by OIPE CSRL194 | L194 | |
| IFW Scan & PACR Auto Security ReviewSCAN | SCAN | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Preliminary AmendmentA.PE | A.PE | |
| Initial Exam Team nnIEXX | IEXX |
Numbers
- Publication
- RE040412
- Publication, DOCDB
- RE40412
- Publication, EPODOC
- USRE40412E
- Application
- 10857341
- Application, DOCDB
- 85734104
- Application, EPODOC
- US20040857341
Titles
- English
- Synchronizing signal separating apparatus and method
Classification
- CPC, 1
- H04N5/08
- IPC, 2
- H04N5 08
- H04N5 10
- USPC, 6
- 348525000
- 348521000
- 348529000
- 348530000
- 348531000
- 348E05017