Apparatus and method for transient suppression in synchronous data detection systems

BACKGROUND OF THE INVENTION

1. Technical Field

This invention relates to transient suppression techniques in synchronous data detection systems. These techniques are applicable for robust gain control, timing, and data recovery in a read channel of a magnetic recording system.

2. Description of Related Art

The magnetic storage industry has been increasing the areal density storage capacity of hard drives with various technological advancements to meet the computer industry's demand for more and better storage. Such advancements include the use of magnetoresistive (MR) heads and partial-response maximum likelihood (PRML) sequence detection. A MR head includes a MR element made out of a material which changes electrical resistance depending on the strength of the magnetic field in which it lies. A PRML system is a synchronous data detection system which includes partial-response signalling and maximum likelihood sequence detection.

MR heads are known in the industry to suffer from a transient phenomenon commonly referred to as thermal asperity (TA) events. A MR head normally glides over a spinning magnetic disk close to, but not touching, the disk surface. When a MR head hits a protruding object on the disk surface, the MR element heats up rapidly and the heat decays relatively slowly.

The effect of such a transient phenomenon is a sudden transient change in the baseline of the read-back signal coming from the MR head. This transient change contains a substantial low frequency component and causes loss of read-back data.

The extent of the read-back data lost due to such a transient depends on the robustness of the data detection system. A data detection system without any transient detection and suppression circuit may lose a large amount of data, even to the point that the error correcting code (ECC) used in the recording system cannot regenerate the user data.

A prior art method of handling a transient includes the following steps. First, the system detects the transient and halts data detection. Second, an analog front-end portion of the system is switched to high-pass mode to reduce the effect of the transient. Third, the system freezes both the gain of the gain control loop and the timing of the timing recovery loop. Fourth, the system waits for a period of time until the effect of the transient is below some threshold. This period of time is called the transient interval. Fifth, when the transient interval is over, the system resumes data detection. Sixth, the front-end is switched back to a lower AC coupling and the gain and timing are unfrozen.

There are at least two problems with the prior art method. First, even with the front-end high-pass function switched on, the transient interval is still quite long. Such a long transient interval may result in a loss of read-back data beyond the point of recovery by the ECC. Second, freezing the timing recovery and gain control loops means that the system halts tracking the timing and gain variations in the read-back signal. If the channel timing is not fully settled when the system is hit with a TA event, then freezing the timing loop will cause a large drift in the synchronous sampling points which may result in permanent synchronization loss and complete loss of user data. This problem has been shown both experimentally and through modelling.

SUMMARY

The present invention relates to a system and method for transient suppression in a synchronous data detection system. The present invention includes high-pass filtering of the signal produced by the sampling and shaping circuits before the signal enters the timing and gain control circuits. This high-pass filtering may be turned on when a transient is detected, in anticipation of a previously detected transient, or may be always on. Using the high-pass version of the shaped signal allows the timing loop and the gain loop to function during a transient interval, thus maintaining timing and gain lock during such an interval.

This high-pass filtering of the signal entering the timing and gain control circuits facilitates the tracking of the timing and gain variations in the read-back signal. The resulting improvements in tracking capability reduces the necessary length of the transient interval which shortens the time period during which tracking is halted. A shorter time during which tracking is halted leads to less read-back data loss and smaller drift in the synchronous sampling points. Thus, loss of read-back data beyond the point of recovery by ECC and permanent synchronization loss are prevented.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other more detailed and specific objects and features of the present invention are more fully disclosed in the following specification, reference being had to the accompanying drawings, in which:

FIG. 1A is a diagram of a first prior art synchronous data detection system.

FIG. 1B is a diagram of a first analog front-end circuit for the first prior art synchronous data detection system.

FIG. 1C is a diagram of a second analog front-end circuit, including a high-pass filter, for the first prior art synchronous data detection system.

FIG. 1D is a diagram of a high-pass filter.

FIG. 2A is a diagram of a second prior art synchronous detection system, including a transient detector.

FIG. 2B is a diagram of an analog front-end circuit, including a bypassable high-pass filter, for the second prior art synchronous detection system.

FIG. 2C is a diagram of a bypassable high-pass filter.

FIG. 2D is a diagram of a transient detector.

FIG. 2E shows illustrative graphs of various signals in the transient detector.

FIG. 3A is a diagram of a third synchronous data detection system, including a high-pass filter, in a first and alternate embodiment of the present invention.

FIG. 3B shows illustrative graphs of the input and output of the high-pass filter in the third synchronous data detection system.

FIG. 4 is a diagram of a fourth synchronous data detection system, including a bypassable high-pass filter, in a second and preferred embodiment of the present invention.

FIG. 5 is a diagram of a fifth synchronous data detection system in a third and alternate embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1A is a diagram of a first prior art synchronous data detection system <b>100</b>. Analog Front-End portion <b>102</b> or <b>103</b> receives an analog signal. In a typical magnetic storage system, this signal comes from the magnetic head. A constant signal level is desirable. Therefore, the analog front-end <b>102</b> or <b>103</b> typically contains a variable gain amplifier (VGA) <b>120</b> circuit. To keep the signal level constant, the VGA <b>120</b> receives a control signal from the gain control circuit <b>114</b>. The analog front-end <b>102</b> or <b>103</b> outputs an amplified signal.

Sampler circuit <b>104</b> receives the amplified signal from the analog front-end <b>102</b> or <b>103</b>. The sampler <b>104</b> may be an Analog-to-Digital Converter (ADC). The sampling is controlled by a clock signal output by a voltage controlled oscillator (VCO) <b>112</b>. The frequency and phase of the clock signal output by the VCO <b>112</b> is controlled by a timing control circuit <b>110</b>. If the sampler <b>104</b> is an ADC, the sampler <b>104</b> outputs a stream of digital samples. The sampler <b>104</b> may also be a sample-and-hold (SH) circuit. If the sampler <b>104</b> is a SH, it outputs a stream of analog samples.

Finite Impulse Response (FIR) filter <b>106</b> receives the output signal of the sampler <b>104</b>. The FIR filter <b>106</b> shapes the sampled signal so that it is suitable for input into a data detector <b>108</b>.

The data detector <b>108</b> receives the shaped signal from the FIR <b>106</b>. The data detector <b>108</b> could be a simple threshold detector, but a maximum likelihood sequence detector (i.e. a Viterbi detector) would provide better detection capability.

FIG. 1B is a diagram of a first analog front-end circuit <b>102</b> for the first prior art synchronous data detection system <b>100</b>. The variable gain amplifier (VGA) <b>120</b> receives an analog read-back signal containing read-back data and amplifies the signal by an amount determined by a control signal received from the gain control circuit <b>114</b>. The amplified signal output by the VGA may be input into an (optional) analog equalizer <b>122</b>. Such an equalizer <b>122</b> is a filter which modifies the shape of the signal and is optional because a similar function is performed after sampling by the FIR filter <b>106</b>.

FIG. 1C is a diagram of a second analog front-end circuit <b>103</b>, including a high-pass filter <b>130</b>, for the first prior art synchronous data detection system <b>100</b>. The high-pass filter <b>130</b> receives an analog read-back signal and filters out lower frequency components of the signal before outputting the signal to the VGA <b>120</b>. Such high-pass filtering reduces the effect of a thermal asperity event on the baseline of the read-back signal but also distorts the read-back signal.

FIG. 1D is a diagram of a high-pass filter <b>130</b>. The input of the high-pass filter <b>130</b> splits into two signal paths. The signal along the first path goes through a low-pass filter <b>140</b> and this is subtracted from the signal along the second path in a summation device <b>142</b>. The output of the summation device <b>142</b> is output by the high-pass filter <b>130</b>.

FIG. 2A is a diagram of a second prior art synchronous detection system <b>200</b>, including a transient detector <b>204</b>. The second system <b>200</b> is similar to the first system <b>100</b>, but in the second system <b>200</b> the sampled signal output by the sampler <b>104</b> is input into the transient detector <b>204</b> (in addition to being input into the FIR <b>106</b>). The transient detector <b>204</b> detects the presence of transients, such as thermal asperity events, in the sampled signal and outputs a TA_interval signal which indicates the duration of the transient.

In addition, the second system <b>200</b> includes a third analog front-end circuit <b>202</b> which receives the TA_interval signal from the transient detector <b>204</b>. The TA_interval signal controls a bypassable high-pass filter <b>210</b> in the third analog front-end circuit <b>202</b>.

FIG. 2B is a diagram of an analog front-end circuit <b>202</b>, including a bypassable high-pass filter <b>210</b>, for the second prior art synchronous detection system <b>200</b>. The bypassable high-pass filter <b>210</b> receives an analog read-back signal and high-pass filters the signal if the TA_interval signal received from the transient detector <b>204</b> indicates to do so based on the presence of a transient. The output of the bypassable high-pass filter is received by the VGA <b>120</b>.

FIG. 2C is a diagram of a bypassable high-pass filter <b>210</b>. The input of the bypassable high-pass filter <b>210</b> splits into two signal paths. The signal along the first path goes through a high-pass filter <b>130</b> before going into the first input (1) of a 2:1 multiplexer (MUX) <b>215</b>. The signal along the second path goes into the second input (0) of the 2:1 MUX <b>215</b>. The selection input (S) for the 2:1 MUX <b>215</b> is the TA_interval signal received from the transient detector <b>204</b> such that the first input (1) is output during the transient interval and the second input (0) is output otherwise.

FIG. 2D is a diagram of a transient detector <b>204</b>. In conjunction with FIG. 2D, FIG. 2E shows illustrative graphs of various signals in the transient detector <b>204</b>.

A low-pass filter <b>220</b> receives the sampled signal x from the sampler <b>104</b>. A sampled signal x is shown for purposes of illustration in FIG. <b>2</b>E. (Note that in actuality the signal x and subsequent signals should be sampled rather than continuous as shown in the illustration.) The “oscillations” in the illustration indicate the read-back data cells in the signal x. Near the time of a TA event, the signal x spikes up, and it is several cells before the effect of the TA event fades away from the signal x.

The low-pass filter <b>220</b> removes the higher frequency components from the signal x and outputs a low-pass filter y. The low-pass signal y is shown for purposes of illustration in FIG. <b>2</b>E. As shown in the illustration, the read-back data information is generally removed by the low-pass filtering, leaving only the effect on the signal from the TA event.

The threshold detector <b>222</b> receives the low-pass signal y and outputs a threshold signal z. The threshold signal is shown for purposes of illustration in FIG. <b>2</b>E. As shown in the illustration, the threshold signal z is low if the low-pass signal y is below a predetermined threshold, and is high if the low-pass signal is above the predetermined threshold.

The pulse widener <b>224</b> receives the threshold signal z and outputs a “thermal asperity interval” (TA_interval) signal. The TA_interval signal is shown for purposes of illustration in FIG. <b>2</b>E. As shown in the illustration, the TA_interval begins low like the threshold signal z, goes high when the threshold signal z becomes high, but does not go back low until substantially after the threshold signal z goes back low. The purpose of this widening of the pulse is to allow enough time for the transient produced by the TA event to decay to an amplitude sufficiently small in comparison to the amplitude of the normal read-back date signal (i.e., the amplitude of the “oscillations” in the sampled signal x).

FIG. 3A is a diagram of a third synchronous data detection system <b>300</b>, including a high-pass filter <b>130</b>, in a first and alternate embodiment of the present invention. In conjunction with FIG. 3A, FIG. 3B shows illustrative graphs of the input and output of the high-pass filter <b>130</b> in the third synchronous data detection system <b>300</b>.

The third system <b>300</b> adds to the first system <b>100</b> a strategically placed high-pass filter <b>130</b>. The high-pass filter <b>130</b> receives the shaped signal from the FIR filter <b>106</b>, and outputs a high-pass signal to the timing control circuit <b>110</b> and to the gain control circuit <b>114</b>. As illustrated in FIG. 3B, the effect of the TA event is present in the shaped signal but is substantially removed from the high-pass signal.

The removal of the effect of the transient from the signal entering the timing <b>110</b> and gain <b>114</b> control circuits facilitates the tracking of the timing and gain variations in the read-back signal. If the effect of the transient is not removed from the signal, then the effect of the transient throws off the phase-locked loop (PLL) of the timing control circuit <b>110</b> and the gain adjustment scheme of the gain control circuit <b>114</b>.

FIG. 4 is a diagram of a fourth synchronous data detection system <b>400</b>, including a bypassable high-pass filter <b>210</b>, in a second and preferred embodiment of the present invention. The fourth system <b>400</b> adds to the first system <b>100</b> a transient detector <b>204</b> and a strategically placed bypassable high-pass filter <b>210</b>. The transient detector <b>204</b> receives the sampled signal from the sampler <b>104</b> and outputs a TA_interval signal which indicates when the read-back signal is affected by a transient. The bypassable high-pass filter <b>210</b> receives the shaped signal from the FIR <b>106</b> and sends its output to the timing <b>110</b> and gain <b>114</b> control circuits. The TA_interval signal controls the bypassable high-pass filter <b>210</b> such that the high-pass filtering is switched on (i.e., the first input (1) is selected by MUX <b>215</b> in FIG. 2C) during the time when there is substantial effect by the transient in the read-back signal (i.e., when the TA_interval signal is high).

In this way, switching on the high-pass filtering substantially removes the effect of the transient from the signal entering the timing <b>110</b> and gain <b>114</b> control circuits. This facilitates the tracking of the timing and gain variations during the transient interval.

FIG. 5 is a diagram of a fifth synchronous data detection system <b>500</b> in a third and alternate embodiment of the present invention. The fifth system <b>500</b> includes an analog front-end <b>202</b> that is different from the analog front-end <b>102</b> or <b>130</b> in the fourth system <b>400</b>. The analog front-end circuit <b>202</b> of the fifth system <b>500</b> includes a bypassable high-pass filter <b>210</b> (see FIG. 2B) that is controlled by the TA_interval signal from the transient detector <b>204</b>.

The fifth system <b>500</b> thus includes two bypassable high-pass filters <b>210</b>: one in the analog front-end and the other before the timing <b>110</b> and gain <b>114</b> controls. Both bypassable high-pass filters <b>210</b> have their high-pass filtering switched on during the transient interval (i.e., when the TA_interval is high). The addition of the high pass filtering in the analog front-end <b>202</b> substantially removes the effect of the transient on the read-back signal but also distorts the read-back signal.

The above description is included to illustrate the operation of the preferred embodiment and is not meant to limit the scope of the invention. The scope of the invention is to be limited only by the following claims. From the above discussion, many variations will be apparent to one skilled in the art that would yet be encompassed by the spirit and scope of the invention.