Multi-wafer stacking by Ox-Ox bonding

PRIORITY CLAIM AND CROSS-REFERENCE

0001This application is a divisional of U.S. patent application Ser. No. 14/483,908, filed on Sep. 11, 2014, entitled “3DIC Interconnect Devices and Methods of Forming Same,” which claims the benefit of U.S. Provisional Application Ser. No. 62/005,763, filed on May 30, 2014, entitled “Multi-Wafer Stacking by Oxide-Oxide Bonding,” which applications are hereby incorporated herein by reference in their entireties.

BACKGROUND

0002The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size (e.g., shrinking the semiconductor process node towards the sub-20 nm node), which allows more components to be integrated into a given area. As the demand for miniaturization, higher speed and greater bandwidth, as well as lower power consumption and latency has grown recently, there has grown a need for smaller and more creative packaging techniques of semiconductor dies.

0003As semiconductor technologies further advance, stacked semiconductor devices, e.g., 3D integrated circuits (3DIC), have emerged as an effective alternative to further reduce the physical size of a semiconductor device. In a stacked semiconductor device, active circuits such as logic, memory, processor circuits and the like are fabricated on different semiconductor wafers. Two or more semiconductor wafers may be stacked on top of one another to further reduce the form factor of the semiconductor device.

0004Two semiconductor wafers may be bonded together through suitable bonding techniques. The commonly used bonding techniques include direct bonding, chemically activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermo-compressive bonding, reactive bonding and/or the like. An electrical connection may be provided between the stacked semiconductor wafers. The stacked semiconductor devices may provide a higher density with smaller form factors and allow for increased performance and lower power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS

0005Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

0006<figref idref="DRAWINGS">FIGS. 1-6</figref> are cross-sectional views of various processing steps during fabrication of interconnect structures between a plurality of bonded workpieces in accordance with some embodiments.

0007<figref idref="DRAWINGS">FIG. 7</figref> illustrates exemplary top views of interconnects in accordance with some embodiments.

0008<figref idref="DRAWINGS">FIG. 8</figref> is a flow diagram illustrating a method of forming interconnect structures between a plurality of bonded workpieces in accordance with some embodiments.

DETAILED DESCRIPTION

0009The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

0010Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

0011The present disclosure will be described with respect to embodiments in a specific context, namely, a method for forming interconnect structures for a stacked semiconductor device. Other embodiments, however, may be applied to a variety of semiconductor devices. Hereinafter, various embodiments will be explained in detail with reference to the accompanying drawings.

0012<figref idref="DRAWINGS">FIGS. 1-6</figref> are cross-sectional views of various processing steps during fabrication of interconnect structures between a plurality of bonded workpieces in accordance with some embodiments. Referring first to <figref idref="DRAWINGS">FIG. 1</figref>, a first workpiece <b>100</b> and a second workpiece <b>200</b> is shown prior to a bonding process in accordance with various embodiments. In an embodiment, the second workpiece <b>200</b> has similar features as the first workpiece <b>100</b>, and for the purpose of the following discussion, the features of the second workpiece <b>200</b> having reference numerals of the form “2xx” are similar to features of the first workpiece <b>100</b> having reference numerals of the form “1xx.” The various elements of the first workpiece <b>100</b> and the second workpiece <b>200</b> will be referred to as the “first <element> 1xx” and the “second <element> 2xx,” respectively.

0013In an embodiment, the first workpiece <b>100</b> comprises a first substrate <b>102</b>. The first substrate <b>102</b> may be formed of silicon, although it may also be formed of other group III, group IV, and/or group V elements, such as silicon, germanium, gallium, arsenic, and combinations thereof. The first substrate <b>102</b> may also be in the form of silicon-on-insulator (SOI). The SOI substrate may comprise a layer of a semiconductor material (e.g., silicon, germanium and/or the like) formed over an insulator layer (e.g., buried oxide and/or the like), which is formed on a silicon substrate. In addition, other substrates that may be used include multi-layered substrates, gradient substrates, hybrid orientation substrates, any combinations thereof and/or the like.

0014The first substrate <b>102</b> may further comprise a variety of electrical circuits (not shown). The electrical circuits formed on the first substrate <b>102</b> may be any type of circuitry suitable for a particular application. In accordance with some embodiments, the electrical circuits may include various n-type metal-oxide semiconductor (NMOS) and/or p-type metal-oxide semiconductor (PMOS) devices such as transistors, capacitors, resistors, diodes, photo-diodes, fuses and/or the like.

0015The electrical circuits may be interconnected to perform one or more functions. The functions may include memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry and/or the like. One of ordinary skill in the art will appreciate that the above examples are provided for illustrative purposes only and are not intended to limit the various embodiments to any particular applications.

0016Referring further to <figref idref="DRAWINGS">FIG. 1</figref>, first inter-metal dielectric (IMD) layers <b>104</b> are formed over the first substrate <b>102</b>. As shown in <figref idref="DRAWINGS">FIG. 1</figref>, the first IMD layers <b>104</b> may comprise first interconnects <b>108</b><i>a</i>-<b>108</b><i>d </i>(collectively referred to as first interconnects <b>108</b>). The first IMD layers <b>104</b> and the first interconnects <b>108</b> form first metallization layers over the first substrate <b>102</b>. Generally, metallization layers are used to interconnect the electrical circuitry to each other and to provide an external electrical connection. One skilled in the art will appreciate that number of stacked layers and the number and placement of the interconnects within the respective layers are provided for illustration only and are not limiting the scope of the present disclosure. In some embodiments, the interconnects comprise conductive lines/traces, and conductive vias extending between and interconnecting vertically adjacent conductive lines/traces.

0017The first IMD layers <b>104</b> may be formed, for example, of a low-K dielectric material, such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), FSG, SiO_xC_y, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like, by any suitable method known in the art, such as spinning, chemical vapor deposition (CVD), and plasma-enhanced CVD (PECVD).

0018The first interconnects <b>108</b> may be formed through any suitable formation process (e.g., lithography with etching, damascene, dual damascene, or the like) and may be formed using suitable conductive materials such as copper, aluminum, aluminum alloys, copper alloys or the like. In some embodiments, each of the first interconnects <b>108</b> may further comprise a diffusion barrier layer and/or an adhesion layer (not shown) to protect the first IMD layers from metal poisoning. The diffusion barrier layer may comprise one or more layers of TaN, Ta, TiN, Ti, CoW, or the like, and may be deposited by physical vapor deposition (PVD), or the like.

0019<figref idref="DRAWINGS">FIG. 1</figref> further illustrates a first bonding layer <b>106</b> formed over the first IMD layers <b>104</b> of the first workpiece <b>100</b>. As described below the first bonding layer <b>106</b> is subsequently used to bond the first workpiece <b>100</b> and the second workpiece <b>200</b>, and may comprise any suitable material for bonding depending on a particular bonding method used. In some embodiments, the first bonding layer <b>106</b> is a first passivation layer <b>106</b>. The first passivation layer <b>106</b> may be formed of one or multiple layers comprising silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, undoped silicon glass, phosphosilicate glass, compounds thereof, composites thereof, combinations thereof, or the like, deposited by any suitable method, such as spin-on, CVD, PECVD, or the like. These materials and processes are provided as examples and other materials and processes may be used.

0020It should also be noted that one or more etch stop layers (not shown) may be positioned between adjacent layers of the first workpiece <b>100</b>, e.g., the first IMD layers <b>104</b> and the first substrate <b>102</b>, or between individual layers of the first IMD layers <b>104</b>. Generally, the etch stop layers provide a mechanism to stop an etching process when forming vias and/or contacts. The etch stop layers are formed of a dielectric material having a different etch selectivity from adjacent layers, e.g., the underlying first substrate <b>102</b> and the overlying first IMD layers <b>104</b>. In an embodiment, etch stop layers may be formed of SiN, SiCN, SiCO, CN, combinations thereof, or the like, deposited by CVD or PECVD techniques.

0021In some embodiments, the first workpiece <b>100</b> and the second workpiece <b>200</b> may be wafers and/or dies formed using a complementary metal-oxide-semiconductor (CMOS) process, a micro-electro-mechanical systems (MEMS) process, or the like. The first workpiece <b>100</b> and the second workpiece <b>200</b> may be sensor wafers and/or dies such as, for example, a backside illumination sensor (BIS) wafer and/or die, logic wafers and/or dies such as, for example, application-specific integrated circuit (ASIC) devices comprising analog-to-digital converters, data processing circuits, memory circuits, bias circuits, reference circuits, any combinations thereof and/or the like.

0022In an embodiment, the first workpiece <b>100</b> and the second workpiece <b>200</b> are arranged with device sides (also referred as front sides) of the first substrate <b>102</b> and the second substrate <b>202</b> facing each other as illustrated in <figref idref="DRAWINGS">FIG. 1</figref>. As discussed in greater detail below, the first workpiece <b>100</b> and the second workpiece <b>200</b> will be bonded and openings will be formed extending from a backside (opposite the device side) of the second workpiece <b>200</b> to the selected portions of the first interconnects <b>108</b> of the first workpiece <b>100</b>, such that portions of selected second interconnects <b>208</b> of the second workpiece <b>200</b> will also be exposed. The openings will be subsequently filled with a conductive material, thereby forming electrical contacts on the backside of the second workpiece <b>200</b> to electrically interconnect the first workpiece <b>100</b> and the second workpiece <b>200</b>. Subsequently, one or more additional workpieces will be bonded to the first workpiece <b>100</b> and the second workpiece <b>200</b> and additional interconnect structures will be formed to eclectically interconnect the one or more additional workpieces to the first workpiece <b>100</b> and the second workpiece <b>200</b>.

0023<figref idref="DRAWINGS">FIG. 2</figref> illustrates the first workpiece <b>100</b> and the second workpiece <b>200</b> after bonding in accordance with an embodiment. As shown in <figref idref="DRAWINGS">FIG. 1</figref>, the second workpiece <b>200</b> will be stacked and bonded on top of the first workpiece <b>100</b>. In the illustrated embodiment, the first workpiece <b>100</b> and the second workpiece <b>200</b> are bonded using dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding) by bonding the first passivation layer <b>106</b> of the first workpiece <b>100</b> to the second passivation layer <b>206</b> of the second workpiece <b>200</b>. In other embodiments, the first workpiece <b>100</b> and the second workpiece <b>200</b> may be bonded using, for example, a direct bonding process such as metal-to-metal bonding (e.g., copper-to-copper bonding), metal-to-dielectric bonding (e.g., oxide-to-copper bonding), hybrid boding (e.g., dielectric-to-dielectric and metal-to-metal bonding), any combinations thereof and/or the like.

0024It should be noted that the bonding may be at wafer-to-wafer level, wherein the first workpiece <b>100</b> and the second workpiece <b>200</b> are bonded together, and are then singulated into separated dies. Alternatively, the bonding may be performed at the die-to-die level, or the die-to-wafer level.

0025After the first workpiece <b>100</b> and the second workpiece <b>200</b> are bonded, a thinning process may be applied to the backsides of the first workpiece <b>100</b> and/or the second workpiece <b>200</b>. The thinning process may be implemented by using suitable techniques such as grinding, polishing, a SMARTCUT® procedure, an ELTRAN® procedure, and/or chemical etching.

0026Referring further to <figref idref="DRAWINGS">FIG. 2</figref>, a first opening <b>210</b> and a second opening <b>212</b> are formed on the backside of the second workpiece <b>200</b>. As discussed in greater detail below, electrical connections will be formed extending from a backside of the second workpiece <b>200</b> to select ones of the first interconnects <b>108</b> of the first workpiece <b>100</b> and to select ones of the second interconnects <b>208</b> of the second workpiece <b>200</b>. The first opening <b>210</b> and the second opening <b>212</b> represent openings in which the backside contacts will be formed. The first opening <b>210</b> and the second opening <b>212</b> may be formed using photolithography techniques. Generally, photolithography techniques involve depositing a photoresist material, which is subsequently irradiated (exposed) and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material from subsequent processing steps, such as etching. A suitable etching process, such as a reactive ion etch (RIE) or other dry etch, an anisotropic wet etch, or any other suitable anisotropic etch or patterning process may be applied to the second substrate <b>202</b> of the second workpiece <b>200</b>. As a result, the first opening <b>210</b> and the second opening <b>212</b> are formed in the second substrate <b>202</b>.

0027Also shown in <figref idref="DRAWINGS">FIG. 2</figref> is an optional anti-reflection coating (ARC) layer <b>214</b>. The ARC layer <b>214</b> reduces the reflection of the exposure light used during the photolithography process to pattern a patterned mask (not shown), which reflection may cause inaccuracies in the patterning. The ARC layer <b>214</b> may be formed of a nitride material (e.g., silicon nitride), an organic material (e.g., silicon carbide), an oxide material, high-k dielectric, and the like. The ARC layer <b>214</b> may be formed using suitable techniques such as CVD and/or the like.

0028Other layers may be used in the patterning process. For example, one or more optional hard mask layers may be used to pattern the second substrate <b>202</b>. Generally, one or more hard mask layers may be useful in embodiments in which the etching process requires masking in addition to the masking provided by the photoresist material. During the subsequent etching process to pattern the second substrate <b>202</b>, the patterned photoresist mask will also be etched, although the etch rate of the photoresist material may not be as high as the etch rate of the second substrate <b>202</b>. If the etch process is such that the patterned photoresist mask would be consumed before the etching process is completed, then an additional hard mask may be utilized. The material of the hard mask layer or layers is selected such that the hard mask layer(s) exhibit a lower etch rate than the underlying materials, such as the materials of the second substrate <b>202</b>.

0029Referring further to <figref idref="DRAWINGS">FIG. 2</figref>, a dielectric film <b>216</b> is formed over the backside of the second substrate <b>202</b> and along sidewalls and bottoms of the first opening <b>210</b> and the second opening <b>212</b> in accordance with an embodiment. The dielectric film <b>216</b> provides greater passivation and isolation between electrical contacts formed in the first opening <b>210</b> and the second opening <b>212</b>, and device circuits formed on the second substrate <b>202</b>. In some embodiments, the dielectric film <b>216</b> comprises a multilayer structure, which provides greater protection than a single film during, for example, a subsequent etch process to form electrical contacts to selected ones of the first interconnects <b>108</b> and the second interconnects <b>208</b>. Additionally, the dielectric film <b>216</b> may provide protection against metal ions diffusing into the second substrate <b>202</b>.

0030The dielectric film <b>216</b> may be formed of various dielectric materials commonly used in integrated circuit fabrication. For example, the dielectric film <b>216</b> may be formed of silicon dioxide, silicon nitride or a doped glass layer such as boron silicate glass and the like. Alternatively, dielectric layer may be a layer of silicon nitride, silicon oxynitride, polyamide, a low-k dielectric, or a high-k dielectric, or the like. In addition, a combination of the foregoing dielectric materials may also be used to form the dielectric film <b>216</b>. In some embodiments, the dielectric film <b>216</b> may be formed using suitable techniques such as sputtering, oxidation, CVD and/or the like.

0031<figref idref="DRAWINGS">FIG. 2</figref> further illustrates a patterned mask <b>218</b> formed over the backside of the second substrate <b>202</b> in accordance with an embodiment. The patterned mask <b>218</b> may be, for example, a photoresist material that has been deposited, masked, exposed, and developed as part of a photolithography process. The patterned mask <b>218</b> is patterned to define via openings extending through the second IMD layers <b>204</b> of the second substrate <b>202</b> and at least some of the first IMD layers <b>104</b> of the first substrate <b>102</b>, thereby exposing portions of select ones of the first interconnects <b>108</b> and the second interconnects <b>208</b>, as explained in greater detail below.

0032<figref idref="DRAWINGS">FIG. 3</figref> illustrates the semiconductor device shown in <figref idref="DRAWINGS">FIG. 2</figref> after one or more additional etching processes are performed in accordance with an embodiment. A suitable etching process, such as a dry etch, an anisotropic wet etch, or any other suitable anisotropic etch or patterning process, may be performed on the semiconductor device to form a third opening <b>302</b> and a fourth opening <b>304</b>.

0033As illustrated in <figref idref="DRAWINGS">FIG. 3</figref>, the third opening <b>302</b> extends the first opening <b>210</b> to the second interconnects <b>208</b><i>a </i>and <b>208</b><i>b</i>, and to the first interconnect <b>108</b><i>a</i>. The fourth opening <b>304</b> extends the second opening <b>212</b> to the second interconnect <b>208</b><i>f</i>. In an embodiment, the second interconnects <b>208</b> are formed of suitable conductive materials such as copper, which exhibits a different etching rate (selectivity) than the second IMD layers <b>204</b>. As such, the second interconnects <b>208</b><i>a </i>and <b>208</b><i>b </i>function as a hard mask layer for an etching process of the second IMD layers <b>204</b>. A selective etching process may be employed to etch the second IMD layers <b>204</b> rapidly while etching only portions of the second interconnects <b>208</b><i>a</i>, <b>208</b><i>b</i>, and <b>208</b><i>f</i>. In some embodiments, the second interconnects <b>208</b><i>a </i>and <b>208</b><i>b </i>may be dummy conductive lines and may not provide electrical connection between the electrical circuits of the second workpiece <b>200</b>.

0034As shown in <figref idref="DRAWINGS">FIG. 3</figref>, the exposed portion of the second interconnects <b>208</b><i>a </i>and <b>208</b><i>b </i>may be partially etched away, thereby forming a first recess <b>308</b> in the second interconnects <b>208</b><i>a </i>and <b>208</b><i>b</i>, as the etch process continues toward the first interconnect <b>108</b><i>a</i>. In addition, the exposed portion of the second interconnect <b>208</b><i>f </i>may be partially etched, thereby forming a second recess <b>310</b> in the second interconnect <b>208</b><i>f</i>. Depths of the first recess <b>308</b> and the second recess <b>310</b> may vary depending on a variety of applications and design needs. In some embodiments, the first recess <b>308</b> has a first depth D₁between about 1000 Å and about 8000 Å, and the second recess <b>310</b> has a second depth D₂between about 1000 Å and about 8000 Å. In some embodiments, the second interconnects <b>208</b><i>a </i>and <b>208</b><i>b</i>, and the second interconnect <b>208</b><i>f </i>are subject to the same etch process and, therefore, the first depth D₁is equal to the second depth D₂.

0035The selective etch process continues until the first interconnect <b>108</b><i>a </i>and the second interconnect <b>208</b><i>f </i>are exposed, thereby forming a first combined opening extending from the backside of the second workpiece <b>200</b> to the first interconnect <b>108</b><i>a </i>of the first workpiece <b>100</b>, and a second combined opening extending from the backside of the second workpiece <b>200</b> to the second interconnect <b>208</b><i>f </i>of the second workpiece <b>200</b>, as illustrated in <figref idref="DRAWINGS">FIG. 3</figref>.

0036It should be noted that the selective etch process may extend through a variety of various layers used to form the first IMD layers <b>104</b>, the second IMD layers <b>204</b>, the first passivation layer <b>106</b>, and the second passivation layer <b>206</b>, which may include various types of materials and etch stop layers. Accordingly, the selective etch process may utilize multiple etchants to etch through the various layers, wherein the etchants are selected based upon the materials being etched.

0037In some embodiments, the patterned mask <b>218</b> may be fully consumed during the selective etch process described above. In other embodiments, a portion of the patterned mask <b>218</b> may still remain on the backside of the second workpiece <b>200</b> after the selective etch process is completed. The remaining portion of the patterned mask <b>218</b> may be removed by using suitable stripping techniques such as chemical solvent cleaning, plasma ashing, dry stripping and/or the like. The techniques are well known and hence are not discussed in further detail herein to avoid repetition.

0038<figref idref="DRAWINGS">FIG. 4</figref> illustrates various conductive material formed within the first opening <b>210</b> and the third opening <b>302</b>, and within the second opening <b>212</b> and the fourth opening <b>304</b> in accordance with various embodiments. In some embodiments, the conductive materials may be formed by depositing one or more diffusion and/or barrier layers and depositing a seed layer (not shown). For example, a diffusion barrier layer <b>402</b> comprising one or more layers of Ta, TaN, TiN, Ti, CoW, or the like is formed along the sidewalls of the first opening <b>210</b>, the second opening <b>212</b>, the third opening <b>302</b> and the fourth opening <b>304</b>. The seed layer may be formed of copper, nickel, gold, any combination thereof and/or the like. The diffusion barrier layer <b>402</b> and the seed layer may be formed by suitable deposition techniques such as PVD, CVD and/or the like. Once the seed layer has been deposited in the openings, a conductive material, such as tungsten, titanium, aluminum, copper, any combinations thereof and/or the like, is filled into of the first opening <b>210</b>, the second opening <b>212</b>, the third opening <b>302</b> and the fourth opening <b>304</b>, using, for example, an electro-chemical plating process, thereby forming a first conductive plug <b>404</b> and a second conductive plug <b>406</b> (also referred as through oxide vias (TOVs)).

0039<figref idref="DRAWINGS">FIG. 4</figref> also illustrates removal of excess materials, e.g., excess conductive materials, from the backside of the second substrate <b>202</b>. In some embodiments, the dielectric film <b>216</b> may be left along the backside of the second substrate <b>202</b> to provide additional protection from the environment. In the illustrated embodiment, the excess conductive materials may be removed using an etch process, a planarization process (e.g., a CMP process), or the like, using the dielectric film <b>216</b> as a stop layer.

0040As shown in <figref idref="DRAWINGS">FIG. 4</figref>, the first conductive plug <b>404</b> comprises three portions. A first portion of the first conductive plug <b>404</b> is from the first interconnect <b>108</b><i>a </i>to the second interconnects <b>208</b><i>a </i>and <b>208</b><i>b</i>. The first portion of the first conductive plug <b>404</b> is of a first width W₁as shown in <figref idref="DRAWINGS">FIG. 4</figref>. A second portion of the first conductive plug <b>404</b> is from the second interconnects <b>208</b><i>a </i>and <b>208</b><i>b </i>to the front side of the second substrate <b>202</b>. The second portion of the first conductive plug <b>404</b> is of a second width W₂as shown in <figref idref="DRAWINGS">FIG. 4</figref>. A third portion of the first conductive plug <b>404</b> is from the front side of the second substrate <b>202</b> to the backside of the second substrate <b>202</b>. The third portion of the first conductive plug <b>404</b> is of a third width W₃as shown in <figref idref="DRAWINGS">FIG. 4</figref>.

0041In some embodiments, the third width W₃is greater than the second width W₂, and the second width W₂is greater than the first width W₁as illustrated in <figref idref="DRAWINGS">FIG. 4</figref>. The first width W₁may be between about 0.4 μm and about 2 μm, the second width W₂may be between about 0.6 μm and about 8 μm, and the third width W₃may be between about 1.2 μm and about 11 μm.

0042As also shown in <figref idref="DRAWINGS">FIG. 4</figref>, the second conductive plug <b>406</b> comprises two portions. A first portion of the second conductive plug <b>406</b> is from the second interconnect <b>208</b><i>f </i>to the front side of the second substrate <b>202</b>. The first portion of the second conductive plug <b>406</b> is of a fourth width W₄as shown in <figref idref="DRAWINGS">FIG. 4</figref>. A second portion of the second conductive plug <b>406</b> is from the front side of the second substrate <b>202</b> to the backside of the second substrate <b>202</b>. The second portion of the second conductive plug <b>406</b> is of a fifth width W₅as shown in <figref idref="DRAWINGS">FIG. 4</figref>.

0043In some embodiments, the fifth width W₅is greater than the fourth width W₄as illustrated in <figref idref="DRAWINGS">FIG. 4</figref>. The fourth width W₄may be between about 0.6 μm and about 8 μm, and the fifth width W₅may be between about 1.2 μm and about 11 μm.

0044<figref idref="DRAWINGS">FIG. 4</figref> further illustrates a first redistribution layer (RDL) <b>408</b> formed over the backside of the second workpiece <b>200</b> in accordance with some embodiments. In the illustrated embodiment, the first RDL <b>408</b> comprises one or more dielectric layers <b>412</b> with conductive elements <b>410</b> disposed within the one or more dielectric layers <b>412</b>. In some embodiments, the one or more dielectric layers <b>412</b> may be formed using similar materials and methods as the first passivation layer <b>106</b> and the description is not repeated herein. Moreover, the conductive elements <b>410</b> may be formed using similar materials and methods as the first interconnects <b>108</b> and the description is not repeated herein. As described below in greater detail, the first RDL <b>408</b> allows for power and signals from the first conductive plug <b>404</b> and the second conductive plug <b>406</b> to be routed across the backside of the second workpiece <b>200</b> to workpieces that are subsequently bonded to the second workpiece <b>200</b>.

0045<figref idref="DRAWINGS">FIG. 5</figref> illustrates a resulting structure after a third workpiece <b>500</b> is bonded to the structure of <figref idref="DRAWINGS">FIG. 4</figref> and contacts are formed on a backside of the third workpiece <b>500</b> to electrically interconnect the first workpiece <b>100</b>, the second workpiece <b>200</b>, and the third workpiece <b>500</b>. In an embodiment, the third workpiece <b>500</b> has similar features as the first workpiece <b>100</b> and the second workpiece <b>200</b>, and for the purpose of the following discussion, the features of the third workpiece <b>500</b> having reference numerals of the form “5xx” are similar to features of the first workpiece <b>100</b> having reference numerals of the form “1xx.” The various elements of the third workpiece <b>500</b> will be referred to as the “third <element> 5xx.”

0046Referring further to <figref idref="DRAWINGS">FIG. 5</figref>, the third workpiece <b>500</b> and the structure of <figref idref="DRAWINGS">FIG. 4</figref> are arranged with a front side of a third substrate <b>502</b> facing a backside of the second substrate <b>202</b>. The third workpiece <b>500</b> is bonded to the second workpiece <b>200</b> by bonding a third bonding layer <b>506</b> to a topmost dielectric layer of the one or more dielectric layers <b>412</b>. In the illustrated embodiment, the third bonding layer <b>506</b> is a third passivation layer <b>506</b>, and the third workpiece <b>500</b> and the second workpiece <b>200</b> are bonded using methods as described above with reference to <figref idref="DRAWINGS">FIG. 2</figref> and the description is not repeated herein.

0047As shown in <figref idref="DRAWINGS">FIG. 5</figref>, a third conductive plug <b>520</b> and a fourth conductive plug <b>522</b> are formed to electrically interconnect the third workpiece <b>500</b> and the second workpiece <b>200</b>. In the illustrated embodiment, the third conductive plug <b>520</b> and the fourth conductive plug <b>522</b> are formed using methods as described above with reference to <figref idref="DRAWINGS">FIGS. 2-4</figref>. In particular, openings are formed on the backside of the third workpiece <b>500</b> that are similar to a combined opening comprising the first opening <b>201</b> and the third opening <b>302</b>. The openings are formed to expose the conductive elements <b>410</b> of the first RDL <b>408</b> using methods as described above with reference to <figref idref="DRAWINGS">FIGS. 2-3</figref>, using a second ARC layer <b>510</b>, second dielectric film <b>512</b>, third interconnects <b>508</b><i>d </i>and <b>508</b><i>e</i>, and third interconnects <b>508</b><i>f </i>and <b>508</b><i>g </i>to aid a patterning process, and the detail description is not repeated herein. In the illustrated embodiment, the third interconnects <b>508</b><i>d </i>and <b>508</b><i>e </i>and the third interconnects <b>508</b><i>f </i>and <b>508</b><i>g </i>function as hard mask layers as illustrated in <figref idref="DRAWINGS">FIG. 5</figref>.

0048Subsequently, the openings are filled with various conductive material to form the third conductive plug <b>520</b> and the fourth conductive plug <b>522</b> comprising a second barrier layer <b>518</b> using methods as described above with reference to <figref idref="DRAWINGS">FIG. 4</figref> and the detailed description is not repeated herein. In the illustrated embodiment, the third conductive plug <b>520</b> and the fourth conductive plug <b>522</b> have structures similar to the first conductive plug <b>404</b> described above with reference to <figref idref="DRAWINGS">FIG. 4</figref> and the description is not repeated herein. In addition, a second RDL <b>524</b> is formed over the backside of the third workpiece <b>500</b> using method as described above with reference to <figref idref="DRAWINGS">FIG. 4</figref> and the description is not repeated herein. In the illustrated embodiment, the second RDL <b>524</b> comprises one or more dielectric layers <b>528</b> with conductive elements <b>526</b> disposed within the one or more dielectric layers <b>528</b>.

0049As shown in <figref idref="DRAWINGS">FIG. 5</figref>, the third conductive plug <b>520</b> and the fourth conductive plug <b>522</b> electrically interconnect the third workpiece <b>500</b> to the first workpiece <b>100</b> and the second workpiece <b>200</b>. In particular, the third conductive plug <b>520</b> is electrically connected to the first conductive plug <b>404</b> using one of the conductive elements <b>410</b> of the first RDL <b>408</b>. In some embodiments, depending on the design of the third workpiece <b>500</b>, contacts such as the third conductive plug <b>520</b> may not be formed at a desired place in the third workpiece <b>500</b>. For example, in some embodiments, the third conductive plug <b>520</b> may not be formed directly above the first conductive plug <b>404</b> because the third workpiece <b>500</b> may comprise functional circuitry directly above the first conductive plug <b>404</b>. In such cases, the conductive elements <b>410</b> of the first RDL <b>408</b> is employed to route an electrical signal from the first conductive plug <b>404</b> to a location more appropriate for forming the third conductive plug <b>520</b> as illustrated in <figref idref="DRAWINGS">FIG. 5</figref>.

0050<figref idref="DRAWINGS">FIG. 6</figref> illustrates a semiconductor structure after one or more additional workpieces are bonded to the semiconductor structure of <figref idref="DRAWINGS">FIG. 5</figref> and contacts such as, for example, the first conductive plug <b>404</b> are formed to electrically interconnect the additional workpieces to the first workpiece <b>100</b>, the second workpiece <b>200</b> and the third workpiece <b>500</b>. In particular, <figref idref="DRAWINGS">FIG. 6</figref> illustrates a topmost portion of a topmost workpiece <b>600</b> bonded to the semiconductor structure of <figref idref="DRAWINGS">FIG. 5</figref>. In an embodiment, the topmost workpiece <b>600</b> has similar features as the first workpiece <b>100</b>, the second workpiece <b>200</b>, and the third workpiece <b>500</b>, and for the purpose of the following discussion, the features of the topmost workpiece <b>600</b> having reference numerals of the form “6xx” are similar to features of the first workpiece <b>100</b> having reference numerals of the form “1xx.” The various elements of the topmost workpiece <b>600</b> will be referred to as the “fourth <element> 6xx.”

0051Referring further to <figref idref="DRAWINGS">FIG. 6</figref>, the one or more additional workpieces, such as the topmost workpiece <b>600</b>, and the semiconductor structure of <figref idref="DRAWINGS">FIG. 5</figref> are arranged with front sides of substrates of the one or more additional workpieces (e.g., a fourth substrate <b>602</b> of the topmost workpiece <b>600</b>) facing a backside of the third substrate <b>502</b>. In the illustrated embodiment, the one or more additional workpieces and the semiconductor structure of <figref idref="DRAWINGS">FIG. 5</figref> are bonded using methods as described above with reference to <figref idref="DRAWINGS">FIG. 2</figref> and the description is not repeated herein.

0052After each of the additional workpieces are bonded to a prior semiconductor structure (such as, e.g., the semiconductor structure of <figref idref="DRAWINGS">FIG. 5</figref>), one or more contacts, such as the first conductive plug <b>404</b>, are formed on a backside of each of the additional workpieces to electrically interconnect each of the additional workpiece to the prior semiconductor structure. In the illustrated embodiments, the contacts are formed using methods as descried above with reference to <figref idref="DRAWINGS">FIGS. 2-4</figref> and the description is not repeated herein.

0053Referring further to <figref idref="DRAWINGS">FIG. 6</figref>, the topmost portion of the topmost workpiece <b>600</b> comprises the fourth substrate <b>602</b>, the third ARC layer <b>610</b> and the third dielectric film <b>612</b> formed thereon. <figref idref="DRAWINGS">FIG. 6</figref> also illustrates a fifth conductive plug <b>616</b> and a sixth conductive plug <b>618</b> formed on a backside of the fourth substrate <b>602</b>. In the illustrated embodiment, the fifth conductive plug <b>616</b> and the sixth conductive plug <b>618</b> are formed using methods as described above with reference to <figref idref="DRAWINGS">FIGS. 2-4</figref> and the description is not repeated herein. The fifth conductive plug <b>616</b> and the sixth conductive plug <b>618</b> comprise a third barrier layer <b>614</b> as illustrated in <figref idref="DRAWINGS">FIG. 6</figref>. In addition, a third RDL <b>620</b> is formed over the backside of the topmost workpiece <b>600</b> using methods as described above with reference to <figref idref="DRAWINGS">FIG. 4</figref> and the description is not repeated herein. In the illustrated embodiment, the third RDL <b>620</b> comprises one or more dielectric layers <b>624</b> with conductive elements <b>622</b> disposed within the one or more dielectric layers <b>624</b>.

0054<figref idref="DRAWINGS">FIG. 6</figref> also shows that bond pads <b>626</b> formed on the third RDL <b>620</b> to provide contacts to the conductive elements <b>622</b> of the third RDL <b>620</b>. In an embodiment the bond pads <b>626</b> are formed of a conductive material such as aluminum, although other suitable materials, such as copper, tungsten, or the like, may alternatively be utilized. In some embodiment, the third RDL <b>620</b> may be patterned using, for example, photolithographic masking and etching process to form openings in the third RDL <b>620</b> to expose the conductive elements <b>622</b> in the third RDL <b>620</b>. A suitable material may be deposited to fill the openings using a process such as CVD or PVD, although other suitable materials and methods may alternatively be utilized. Once the material for the bond pads <b>626</b> has been deposited, any excessive material overfilling the openings may be removed using an etch process, a planarization process (e.g., a CMP process), or the like, using a topmost dielectric layer of the one or more dielectric layers <b>624</b> as a stop layer.

0055In some embodiments, wire bonds <b>628</b> are utilized to allow for electrical connection to components and systems external to a stacked device illustrated in <figref idref="DRAWINGS">FIG. 6</figref>. In an embodiment an electronic flame off (EFO) wand may be used to raise the temperature of a gold wire within a capillary controlled by a wire clamp (not illustrated). Once the temperature of the gold wire is raised to between about 150° C. and about 250° C., the gold wire is contacted to each of the bond pads <b>626</b> to form the respective wire bonds <b>628</b>. Another end of the wire of each of the wire bonds <b>628</b> is then contacted and bonded to a ponding pad of an external system to provide electrical connection. One skilled in the art will recognize that ball bonds, solder bumps, micro bumps, copper pillars, and the like may also be used to electrically connect the stacked device of <figref idref="DRAWINGS">FIG. 6</figref> to external devices.

0056It should further be noted while <figref idref="DRAWINGS">FIGS. 1-6</figref> illustrate interconnects (e.g., the second interconnects <b>208</b><i>a </i>and <b>208</b><i>b</i>) that function a hard mask layer, one skilled in the art will recognize that other features may also be used as hard mask layers. For example, a plurality of isolation regions, poly-silicon regions, any combinations thereof and/or the like may be used as the hard mask layers.

0057<figref idref="DRAWINGS">FIG. 7</figref> illustrates exemplary top views of the second interconnects <b>208</b><i>a </i>and <b>208</b><i>b </i>in accordance with various embodiments of the present disclosure. While the cross sectional view of the second interconnects <b>208</b><i>a </i>and <b>208</b><i>b </i>shows that the second interconnect <b>208</b><i>a </i>and the second interconnect <b>208</b><i>b </i>are two separate interconnects (see <figref idref="DRAWINGS">FIG. 3</figref>), these two interconnects may form a continuous annular shaped region as viewed from top as shown in <figref idref="DRAWINGS">FIG. 7</figref>. In some embodiments, the inside diameter of the annular shaped region is equal to the first width W₁. In some embodiments, the third interconnects <b>508</b><i>d </i>and <b>508</b><i>e</i>, and the third interconnects <b>508</b><i>f </i>and <b>508</b><i>g </i>may also form annular shaped regions as viewed from top. The annular shapes may be similar to those illustrated in <figref idref="DRAWINGS">FIG. 7</figref>. It should be noted that internal and external surfaces of the annular shaped regions as illustrated in <figref idref="DRAWINGS">FIG. 7</figref> are for illustrative purpose only and the internal and the external surfaces may have variety of shapes, such as square, circle, oval, triangular, polygonal and/or the like.

0058<figref idref="DRAWINGS">FIG. 8</figref> is a flow diagram illustrating a method of forming interconnect structures between a plurality of bonded workpieces in accordance with some embodiments. The method begins in step <b>802</b>, wherein a plurality of substrates to be bonded is provided. The substrates may be processed wafers (such as those illustrated, for example, in <figref idref="DRAWINGS">FIG. 6</figref>), dies, a wafer and a die, or the like.

0059In step <b>804</b>, a first substrate and a second substrate are bonded as discussed above with reference to <figref idref="DRAWINGS">FIGS. 1 and 2</figref>. Subsequently, first conductive plugs are formed on a backside of the second substrate to electrically interconnect the first substrate and the second substrate as discussed above with reference to <figref idref="DRAWINGS">FIGS. 2-4</figref>. In step <b>806</b>, a first redistribution layer (RDL), such as that discussed above with reference to <figref idref="DRAWINGS">FIG. 4</figref>, is formed over the backside of the second substrate.

0060In step <b>808</b>, a third substrate is bonded to the first RDL layer, and second conductive plugs are formed on a backside of the third substrate as discussed above with reference to <figref idref="DRAWINGS">FIG. 5</figref>. In step <b>810</b>, a second RDL, such as that discussed above with reference to <figref idref="DRAWINGS">FIG. 5</figref>, is formed over the backside of the third substrate.

0061In step <b>812</b>, one or more additional substrates are bonded to a stacked device formed at step <b>810</b> as discussed above with reference to <figref idref="DRAWINGS">FIG. 6</figref>. After each bonding step to bond each of the additional substrates to a stacked device formed during the previous bonding step, a plurality of conductive plugs are formed to electrically interconnect each of the additional substrates to the stacked device formed during the previous bonding step as discussed above with reference to <figref idref="DRAWINGS">FIG. 6</figref>. In some embodiments, steps <b>810</b> and <b>812</b> may be optional and the method may end at step <b>808</b>.

0062One advantageous feature of the above described method is that the method allows reduction of a conductive plug critical dimension below the dimension achievable, for example, by conventional photolithography methods. Accordingly, by interconnecting bonded workpieces using conductive plugs as described above with respect to <figref idref="DRAWINGS">FIGS. 1-6</figref> may lead to semiconductor devices with reduced form factors. In addition, redistribution layers interposed between bonded workpieces may help to rearrange locations of conductive plugs within each of the bonded workpieces.

0063According to an embodiment, a semiconductor device comprises a first workpiece. The first workpiece comprises a first substrate, and first metallization layers formed on a front side of the first substrate, the first metallization layers having a first interconnect. The semiconductor device further comprises a second workpiece bonded to the first workpiece. The second workpiece comprises a second substrate, and second metallization layers formed on a front side of the second substrate, the second metallization layers having a second interconnect, wherein the front side of the second substrate faces the front side of the first substrate. The semiconductor device further comprises a first redistribution layer (RDL) formed on a backside of the second substrate, the backside of the second substrate being opposite the front side of the second substrate, and a first conductive plug extending from the backside of the second substrate to the first interconnect, the first conductive plug extending through the second interconnect. The semiconductor device further comprises a third workpiece bonded to the second workpiece. The third workpiece comprises a third substrate, and third metallization layers formed on a front side of the third substrate, the third metallization layers having a third interconnect, wherein the front side of the third substrate faces the backside of the second substrate. The semiconductor device further comprises a second conductive plug extending from a backside of the third substrate to the first RDL, the second conductive plug extending through the third interconnect, the backside of the third substrate being opposite the front side of the third substrate.

0064According to another embodiment, a semiconductor device comprises a first workpiece. The first workpiece comprises a first substrate, first dielectric layers formed on a front side of the first substrate, and a first interconnect formed within the first dielectric layers. The semiconductor device further comprises a second workpiece stacked atop the first workpiece. The second workpiece comprises a second substrate, second dielectric layers formed on a front side of the second substrate, wherein the front side of the first substrate faces the front side of the second substrate, and a second interconnect formed within the second dielectric layers. The semiconductor device further comprises a first redistribution layer (RDL) formed on a backside of the second substrate, the backside of the second substrate being opposite the front side of the second substrate, and a first conductive plug extending from the backside of the second substrate to the first interconnect, the first conductive plug electrically interconnecting the first RDL, the first interconnect, and the second interconnect. The semiconductor device further comprises a third workpiece stacked atop the second workpiece. The third workpiece comprises a third substrate, third dielectric layers formed on a frond side of the third substrate, and a third interconnect formed within the third dielectric layers, wherein the front side of the third substrate faces the backside of the second substrate. The semiconductor device further comprises a second conductive plug extending from a backside of the third substrate to the first RDL, the second conductive plug electrically interconnecting the first RDL and the third interconnect, the backside of the third substrate being opposite the front side of the third substrate.

0065According to yet another embodiment, a method of forming a semiconductor device, the method comprises providing a first workpiece, the first workpiece having a first interconnect formed in one or more first dielectric layers on a first side of the first workpiece, providing a second workpiece, the second workpiece having a second interconnect formed in one or more second dielectric layers on a first side of the second workpiece, and bonding the first workpiece to the second workpiece such that the first side of the first workpiece faces the first side of the second workpiece. The method further comprises forming a first opening from a second side of the second workpiece, the second side of the second workpiece being opposite the first side of the second workpiece, wherein the first opening extends from the second side of the second workpiece to the first interconnect, the first opening extending through the second interconnect, filling the first opening with a conductive material, and forming a first redistribution layer (RDL) on the second side of the second workpiece. The method further comprises providing a third workpiece, the third workpiece having a third interconnect formed in one or more third dielectric layers on a first side of third workpiece, and bonding the third workpiece to the second workpiece such that the first side of the third workpiece faces the second side of the second workpiece. The method further comprises forming a second opening from a second side of the third workpiece, the second side of the third workpiece being opposite the first side of the third workpiece, wherein the second opening extends from the second side of the third workpiece to the first RDL, the second opening extending through the third interconnect, and filling the second opening with the conductive material.

0066According to yet another embodiment, a semiconductor device includes a first workpiece. The first workpiece includes a first substrate, and first metallization layers on a front side of the first substrate, the first metallization layers having a first interconnect. The semiconductor device further includes a second workpiece bonded to the first workpiece. The second workpiece includes a second substrate, and second metallization layers on a front side of the second substrate, the second metallization layers having a second interconnect, wherein the front side of the second substrate faces the front side of the first substrate. The semiconductor device further includes a first redistribution layer (RDL) on a backside of the second substrate, the backside of the second substrate being opposite the front side of the second substrate. The semiconductor device further includes a first conductive plug extending from the backside of the second substrate to the first interconnect, wherein the first conductive plug extends through the second interconnect, wherein the first conductive plug has a first width as it extends from the backside of the second substrate to the front side of the second substrate, a second width as it extends from the front side of the second substrate to the second interconnect and a third width as it extends from the second interconnect to the first interconnect, wherein the first width is greater than the second width, and wherein the second width is greater than the third width. The semiconductor device further includes a third workpiece bonded to the second workpiece. The third workpiece includes a third substrate, and third metallization layers on a front side of the third substrate, the third metallization layers having a third interconnect, wherein the front side of the third substrate faces the backside of the second substrate. The semiconductor device further includes a second conductive plug extending from a backside of the third substrate to the first RDL, the second conductive plug extending through the third interconnect, the backside of the third substrate being opposite the front side of the third substrate.

0067According to yet another embodiment, a semiconductor device includes a first workpiece. The first workpiece includes a first substrate, first dielectric layers on a front side of the first substrate, and a first interconnect within the first dielectric layers. The semiconductor device further includes a second workpiece stacked atop the first workpiece. The second workpiece includes a second substrate, second dielectric layers on a front side of the second substrate, wherein the front side of the first substrate faces the front side of the second substrate, and a second interconnect within the second dielectric layers. The semiconductor device further includes a first redistribution layer (RDL) on a backside of the second substrate, the backside of the second substrate being opposite the front side of the second substrate. The semiconductor device further includes a first conductive plug extending from the backside of the second substrate to the first interconnect, the first conductive plug electrically interconnecting the first RDL, the first interconnect, and the second interconnect, wherein the first conductive plug has a first width within the second substrate, a second width within the second dielectric layers and a third width within the second interconnect, wherein the first width is greater than the second width, and wherein the second width is greater than the third width. The semiconductor device further includes a third workpiece stacked atop the second workpiece. The third workpiece includes a third substrate, third dielectric layers on a frond side of the third substrate, and a third interconnect within the third dielectric layers, wherein the front side of the third substrate faces the backside of the second substrate. The semiconductor device further includes a second conductive plug extending from a backside of the third substrate to the first RDL, the second conductive plug electrically interconnecting the first RDL and the third interconnect, the backside of the third substrate being opposite the front side of the third substrate.

0068According to yet another embodiment, a semiconductor device includes a first workpiece. The first workpiece includes a first substrate, a first conductive feature on a front side of the first substrate, and a first insulating layer on the front side of the first substrate, the first conductive feature being interposed between the first substrate and the first insulating layer. The semiconductor device further includes a second workpiece bonded to the first workpiece. The second workpiece includes a second substrate, a second conductive feature on a front side of the second substrate, and a second insulating layer on the front side of the second substrate, the second conductive feature being interposed between the second substrate and the second insulating layer, the second insulating layer physically contacting the first insulator layer. The semiconductor device further includes a first redistribution layer (RDL) on a backside of the second substrate, the backside of the second substrate being opposite the front side of the second substrate. The semiconductor device further includes a first conductive plug extending from the backside of the second substrate to the first conductive feature, wherein the first conductive plug has a first width as it extends from the backside of the second substrate to the front side of the second substrate, a second width as it extends from the front side of the second substrate to the second conductive feature and a third width as it extends through the first insulating layer and the second insulating layer, wherein the first width is greater than the second width, and wherein the second width is greater than the third width. The semiconductor device further includes a third workpiece bonded to the second workpiece. The third workpiece includes a third substrate, a third conductive feature on a front side of the third substrate, and a third insulating layer on the front side of the third substrate, the third conductive feature being interposed between the third substrate and the third insulating layer, the third insulating layer physically contacting the first RDL. The semiconductor device further includes a second conductive plug extending from a backside of the third substrate to the first RDL, the backside of the third substrate being opposite the front side of the third substrate.

0069The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.