Dynamic simulated motor for controller testing
Summary by NHIP
Dynamic Motor Simulator
The apparatus uses a simulator unit to process control signals and generate feedback representing variable frequency drive and load operation. Distinctive elements include simulating DC bus voltage, transistor desaturation conditions, and temperature readings at specific nodes like inverter and rectifier heat sinks.
Claim Score by NHIP
Abstract
A controller is configured to generate control signals to control a variable frequency drive coupled with a load. A simulator receives the control signals and processes the control signals. The simulator simulates a variable frequency drive and a load by generating feedback signals based on a model and the control signals. The controller receives the feedback signals from the simulator.

Term
9.6 yearsleft in the term
Expires 17 April 2036, including 814 days of term adjustment.
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26 claims: 4 independent, 22 dependent
- 1An apparatus comprising:a microprocessor-based controller configured to output variable frequency drive (VFD) control signals and receive VFD feedback signals;a simulator unit including a processing device, a memory device structured to store a set of instructions, and an input/output device structured configured to receive the VFD control signals from the controller and output the VFD feedback signals to the controller;anda computer configured to communicate simulation parameters to the simulator unit and operation commands to the controller;wherein the simulator unit is configured to execute the set of instructions with the processing device so as to simulate operation of a variable frequency drive operatively coupled to a load, including: processing the VFD control signals to determine one or more simulated inverter output voltages;processing the simulated inverter output voltages using a load model to determine one or more simulated inverter output currents;processing the simulated inverter output voltages and the simulated inverter output currents to determine the VFD feedback signals;andproviding the VFD feedback signals to the controller;wherein the simulator unit is further configured to process the simulation parameters and the VFD control signals to simulate a DC bus voltage of the variable frequency drive and the VFD feedback signals include the simulated DC bus voltage.
- 9Broadest claimClaim Score 53, average(NHIP)A method, comprising:generating, with a control unit, control signals configured to control a variable frequency drive;simulating operation of the variable frequency drive and the load with a simulator;receiving, at the simulator, the control signals from the control unit;determining simulated inverter output voltages based on the control signals;determining simulated output currents based on a simulation mode that uses the simulated inverter output voltages;generating simulated operational data that includes the simulated inverter output voltages and the simulated output current;providing the simulated operational data to the control unit;andcontrolling operation of the simulator and the control unit with a computer configured to provide simulation parameters to the control unit and provide output commands to the control unit;processing the simulation parameters and the control signals to simulate a DC bus voltage of the variable frequency drive and the simulated operational data include a simulated DC bus voltage.
- 15A system, comprising:a controller configured to output control signals to a variable frequency drive, wherein the control signals include voltages configured to control one or more switching devices to output a pulse width modulated (PWM) signal;a simulator including a processing device and a memory device structured to store a set of instructions which, when executed by the processing device, are configured to simulate the variable frequency drive and the load, including: receiving the control signals;processing the control signals to determine first simulated operational data;determining second simulated operational data based on a load model and the first simulated operational data;determining feedback signals based on the first simulated operational data and the second simulated operational data;andtransmitting the feedback signals to the controller;anda computer configured to communicate simulation parameters with the simulator;wherein the simulator is further configured to process the simulation parameters and the control signals to simulate a DC bus voltage of the variable frequency drive and the feedback signals include the simulated DC bus voltage.
- 22A method, comprising:generating control signals, with a first computing device, to control operation of a variable frequency drive and a load;receiving the control signals with a second computing device;selecting, with a third computing device, a simulation mode to be used by the second computing device;processing the control signals to determine one or more first simulated operational data with the second computing device;processing, with the second computing device, the first simulated operational data according to the simulation mode from the third computing device and a load model to determine one or more second simulated operational data:processing, with the second computing device, the first simulated operational data and the second simulated operational data to determine feedback signals including DC bus voltage;transmitting the feedback signals to the first computing device;andmonitoring performance of the first computing device and the second computing device with the third computing device.
Independent claims4
61 paragraphs in 5 sections, as filed
CROSS-REFERENCE TO RELATED APPLICATIONS
The present application claims the benefit of U.S. Provisional Patent Application No. 61/756,264, filed on Jan. 24, 2013, which is hereby incorporated by reference in its entirety.
BACKGROUND
Variable frequency drives may handle high voltages and high currents in a number of applications including, for example, heating, ventilation, air conditioning, or refrigeration (HVACR) systems. An individual may be seriously injured or other components of or connected to the variable frequency may be damaged during the testing of the control system for the variable frequency drive. There is a need to provide testing and evaluation of the control system of the variable frequency drive. Existing approaches suffer from various shortcomings relative to these and other needs such as the need for cumbersome and expensive equipment, computational complexity and inefficiency, failsafe shortcomings, inability to simulate various modes of operation and/or failure modes and others. There remains a need for the unique and inventive apparatuses, methods and systems disclosed herein.
SUMMARY
An exemplary embodiment includes a simulator that simulates operation of a variable frequency drive coupled with a load. The simulator receives control signals from a control unit being tested, such as a microprocessor-based controller. The simulator processes the control signals and transmits feedback signals to the control unit. Other embodiments include apparatuses, systems, devices, hardware, methods, and combinations for a simulator that simulate a variable frequency drive and a load and provide an interface for receiving drive control signals from a device under test and providing feedback signals to the device under test. Further embodiments, forms, features, aspects, benefits, and advantages of the present application shall become apparent from the description and figures provided herewith.
BRIEF DESCRIPTION OF THE FIGURES
The description herein makes reference to the accompanying figures wherein like reference numerals refer to like parts throughout the several views, and wherein:
<figref idref="DRAWINGS">FIG. 1</figref> is schematic block diagram of an exemplary simulation system.
<figref idref="DRAWINGS">FIG. 2</figref> is schematic flow diagram of an exemplary process for controlling and monitoring the testing of a controller.
<figref idref="DRAWINGS">FIG. 3</figref> is schematic flow diagram of an exemplary process for controlling a variable frequency drive operatively coupled with a load.
<figref idref="DRAWINGS">FIG. 4</figref> is a schematic flow diagram of an exemplary process for simulating a variable frequency drive operatively coupled with a load.
<figref idref="DRAWINGS">FIG. 5</figref> is a schematic flow diagram of an exemplary process for determining currents based on an inductive load model.
<figref idref="DRAWINGS">FIG. 6</figref> is a schematic flow diagram of an exemplary process for determining currents based on an induction motor.
<figref idref="DRAWINGS">FIG. 7</figref> is a schematic block diagram of an exemplary computing device.
DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS
For the purposes of promoting an understanding of the principles of the invention, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended. Any alterations and further modifications in the described embodiments, and any further applications of the principles of the invention as described herein are contemplated as would normally occur to one skilled in the art to which the invention relates.
<figref idref="DRAWINGS">FIG. 1</figref> illustrates a system <b>10</b> for testing a controller <b>12</b>. The controller <b>12</b> is configured to control a variable frequency drive and a load. The load may be an inductive load, an induction motor, and/or a permanent magnet motor. In addition, the motor simulated may be designed to drive a chiller that is part of a heating, ventilating, air-conditioning, or refrigeration (HVACR) system. The system <b>10</b> includes a simulator <b>14</b>, which simulates the operation of a variable frequency drive and a load. This allows the controller <b>12</b> to be tested without connecting the controller <b>12</b> to an actual variable frequency drive and motor.
The system <b>10</b> also includes a computer <b>16</b> to control and monitor the testing of the controller <b>12</b>. The computer <b>16</b> communicates with the controller <b>12</b> over a bus <b>18</b>, which may be implemented using an inter-module communication protocol. The computer <b>16</b> may send commands to the controller <b>12</b>. For example, the computer <b>16</b> may instruct the controller <b>12</b> when to turn on or turn off, which mode to operate in, and/or use certain parameters during operation, among other commands. The controller <b>12</b> may also report status information to the computer <b>16</b>. The status information may include data about the testing and operation of the controller <b>12</b>.
The computer <b>16</b> communicates with the simulator <b>14</b> over a bus <b>20</b>. In one embodiment, the bus <b>20</b> is implemented using a modbus communication protocol. The computer <b>16</b> may select a particular load model and/or simulation mode <b>22</b> for the simulator <b>14</b> to utilize. Furthermore, the load model <b>22</b> may be stored on the computer <b>16</b> and then sent to the simulator <b>14</b> or the simulator <b>14</b> may store one or more load models and the computer <b>16</b> selects the particular one for use. The computer <b>16</b> may also send parameters <b>24</b> to the simulator <b>14</b>, which may be stored in a parameter table. The parameters <b>24</b> are used by the simulator to simulate a variable frequency drive and load. The simulator <b>14</b> also sends status information to the computer <b>16</b> using the bus <b>20</b>. The status information may include data about the simulation and testing of the controller <b>12</b>. The computer <b>16</b> also may have an interface that allows a user to select and issue commands and/or parameters.
The controller <b>12</b> transmits one or more control signals <b>26</b> to the simulator <b>14</b>. The control signals <b>26</b> are configured to control a variable frequency drive and a load such as a motor. In addition, the control signals <b>26</b> may be configured to provide a pulse width modulated (PWM) signal at an inverter output, for example, by providing switch control signals which are voltage boosted and provided to control switching devices operating in concert to generate the PWM signal. For simplicity of description, such control signals will be referred to herein as PWM control signals. The simulator <b>14</b> processes the control signals <b>26</b> and uses them with the selected model <b>22</b> and/or parameters <b>24</b> to simulate operation of a variable frequency drive and a load to generate one or more feedback signals. Moreover, the simulator <b>14</b> may simulate one or more of the following components of the variable frequency drive including a rectifier, a DC voltage bus, an inverter, a gate drive module, fault sensors, current sensors, voltage sensors, temperature sensors, and the like.
The simulator <b>14</b> may process the control signals <b>26</b>, including a PWM control signal, to determine one or more simulated inverter output voltages <b>28</b> based on the control signals <b>26</b>, the model <b>22</b>, and/or parameters <b>24</b>. The simulated inverter output voltages <b>28</b> may be sent to the controller <b>12</b> as feedback signals.
The simulator <b>14</b> may then use the selected load model <b>22</b> and the simulated inverter output voltages <b>28</b> to determine one or more simulated output currents <b>30</b>. The parameters <b>24</b> may also be used in determining the simulated output currents <b>30</b>. These output currents would typically be measured by current sensors at an output of the inverter of the variable frequency drive such as at a load or motor terminal. For example, the simulated output currents <b>30</b> may represent the current at a motor terminal for each phase, multiple phases, or all of the phases of the variable frequency drive. The simulated output currents <b>30</b> may also be provided to the controller <b>12</b> as feedback signals.
The simulator <b>14</b> is also configured to simulate a DC voltage bus of a variable frequency drive by determining one or more simulated DC bus voltages <b>32</b> based on the control signals <b>26</b>, the model <b>22</b>, and/or parameters <b>24</b>. As one example, a DC voltage bus may include a positive DC voltage rail and a negative DC voltage rail. Thus, the simulated DC bus voltages <b>32</b> may include a simulated positive DC rail voltage and/or a simulated negative DC rail voltage. It shall be understood that the terms positive and negative in this context are relative and that the actual polarities may be both positive, both negative, positive and negative, positive and zero, or negative and zero in various embodiments. The simulated DC bus voltages <b>32</b> may also be provided to the controller <b>12</b> as feedback signals.
The simulator <b>14</b> is also configured to simulate one or more temperature sensors by determining one or more simulated temperature readings <b>34</b> of a variable frequency drive based on the control signals <b>26</b>, the model <b>22</b>, and/or parameters <b>24</b>. For example, the simulator <b>14</b> may determine a simulated temperature or a simulated temperature reading for one or more of the following locations in the variable frequency drive: at the transistors at the output of each phase of the inverter, at a heat sink for the inverter, and at a heat sink for the rectifier. Other locations on a variable frequency drive or motor for generating simulated temperature readings are contemplated. The simulated temperature readings <b>34</b> may also be provided to the controller <b>12</b> as feedback signals.
The simulator <b>14</b> is also configured to generate simulated fault conditions <b>36</b>. The simulated fault conditions <b>36</b> may be based on the control signals <b>26</b>, model <b>22</b>, and/or parameters <b>24</b>. For example, the simulator <b>14</b> may determine that the control signals <b>26</b> are causing a fault condition <b>36</b> such as a desaturation of a transistor that is part of the inverter of a variable frequency drive. Another example of a fault condition <b>36</b> is setting a simulated voltage or simulated current high or low. Another example of a fault condition is adjusting the flux scaling. Other examples include a fault in the communication bus, such as ASCII bus, between the simulator <b>14</b> and the controller <b>12</b>. Other examples of faults related to the motor include a current/ground fault and a current/missing phase. Other examples of faults related to the variable frequency drive include current, voltage, measured ambient temperature, transistor drive desaturation detection, system/safety interaction, measured heat sink temperature, and bus voltage. Other fault conditions <b>36</b> are also contemplated.
The simulator <b>14</b> may also generate a simulated fault condition <b>36</b> based on the model <b>22</b> and/or parameters <b>24</b>. In this way, the computer <b>16</b> may initiate a particular fault condition <b>36</b> to determine whether the controller <b>12</b> can correctly identify the fault condition <b>36</b> and adjust the control signals <b>26</b> correctly in response to the identified fault condition <b>36</b>. The simulated fault condition <b>36</b> may also be provided to the controller <b>12</b> as feedback signals. In one embodiment, the simulator <b>14</b> provides the simulated fault conditions <b>36</b> to the controller <b>12</b> regularly. However, it is also contemplated that the controller <b>12</b> may poll the simulator <b>14</b> for fault data and the simulator <b>14</b> responds to the poll with the simulated fault conditions <b>36</b>.
Although the various feedback signals, such as simulated inverter output voltages <b>28</b>, simulated output currents <b>30</b>, simulated DC bus voltages <b>32</b>, simulated temperature readings <b>34</b>, and simulated fault conditions <b>36</b> are shown as separate feedback lines, these feedback signals may be provided to the controller <b>12</b> together or separately or a combination thereof. For example, some of the simulated data or feedback signals may be provided to the controller <b>12</b> in a digital format such as ASCII, while other simulated data or feedback signals are provided to the controller <b>12</b> in an analog format.
<figref idref="DRAWINGS">FIG. 2</figref> illustrates a process <b>40</b> that may be implemented by the computer <b>16</b> to control and monitor the operation of the simulator <b>14</b> and the controller <b>12</b>. Operations illustrated for all of the processes in the present application are understood to be examples only, and operations may be combined or divided, and added or removed, as well as re-ordered in whole or in part, unless explicitly stated to the contrary.
Process <b>40</b> begins with operation <b>42</b> in which the computer <b>16</b> determines and sends commands to the controller <b>12</b> and/or the simulator <b>14</b>. For example, the computer <b>16</b> may instruct the controller <b>12</b> and/or the simulator <b>14</b> to power on, begin operation, and/or start a testing sequence. Other commands in addition to or in place of those described are contemplated.
Process <b>40</b> proceeds from operation <b>42</b> to operation <b>44</b>. At operation <b>44</b>, the computer <b>16</b> sets various parameters in the controller <b>12</b> and/or the simulator <b>14</b>. For example, the computer <b>16</b> may select a load model <b>22</b> to be used by the simulator <b>14</b>. The computer <b>16</b> may also initiate simulated fault conditions <b>36</b> and/or set certain parameters that would cause a simulated fault condition <b>36</b> to be generated by the simulator <b>14</b>. In addition the computer <b>16</b> may set parameters in the controller <b>12</b> that are used by the controller <b>12</b> in generating the control signals <b>26</b>. Other parameters in addition to or in place of those described are contemplated.
Process <b>40</b> proceeds from operation <b>44</b> to operation <b>46</b>. At operation <b>46</b>, the computer <b>16</b> receives status information regarding the operation of the controller <b>12</b> and/or the simulator <b>14</b>. For example, the controller <b>12</b> may report to the computer <b>16</b> whether the controller <b>12</b> has identified any simulated fault conditions <b>36</b> and how the controller <b>12</b> corrected the control signals <b>26</b> in response to the identified fault conditions <b>36</b>. As another example, the simulator <b>14</b> may report to the computer <b>16</b> various simulated data generated that is included in the feedback signals. This would allow a user of the computer <b>16</b> to determine whether controller <b>12</b> is generating the correct control signals <b>26</b> to control a variable frequency drive and motor appropriately. Other status information in addition to or in place of those described are contemplated.
Process <b>40</b> then proceeds to operation <b>48</b> in which it is determined whether testing should end. If testing should end, process <b>40</b> proceeds to operation <b>49</b> in which shutdown or exit commands are sent to the controller <b>12</b> and/or the simulator <b>14</b>. If testing should not end, then process <b>40</b> proceeds back to operation <b>42</b> where a new set of test commands may be issued. It is contemplated that a user of the computer <b>16</b> may use a computer interface to select and send commands and/or parameters to the controller <b>12</b> and/or simulator <b>14</b>.
<figref idref="DRAWINGS">FIG. 3</figref> illustrates a process <b>50</b> that may be implemented by the controller <b>12</b> for controlling a variable frequency drive and a load such as a motor. At operation <b>52</b>, the controller <b>12</b> receives one or more commands from the computer <b>16</b>. The commands may instruct the controller <b>12</b> how to carry out a particular test sequence or execute a mode of operation. For example, one example of a test sequence may be powering the motor at full capacity for a period of time and then powering the motor at partial capacity over another period of time. The commands may also include a power on or shut down command. Other commands in addition to or in place of those described are contemplated.
Process <b>50</b> then proceeds from operation <b>52</b> to operation <b>54</b>. At operation <b>54</b>, the controller <b>12</b> determines whether the command is a shutdown or an end test command. If the command is a shutdown or an end test command, then process <b>50</b> proceeds to operation <b>56</b> in which the controller <b>12</b> exits from testing. Otherwise, process <b>50</b> proceeds to operation <b>58</b>.
At operation <b>58</b>, the controller <b>12</b> generates the control signals <b>26</b>, which may include a PWM control signal. The control signals <b>26</b> may be tailored to the specific variable frequency drive and/or motor hardware that the controller <b>12</b> believes that it is controlling. For example, the commands and parameters received from the computer <b>16</b> may indicate the particular hardware of the variable frequency drive and/or motor to be driven, which allows the controller <b>12</b> to tailor the control signals <b>26</b> for that hardware. As another example, the commands and/or parameters may establish a test sequence or mode of operation to be executed by the controller <b>12</b>. For example, the commands and/or parameters may establish a period of time that controller <b>16</b> should operate, whether to power the variable frequency drive and motor fully or partially, and the like.
Process <b>50</b> then proceeds to operation <b>60</b> in which the controller <b>12</b> receives feedback signals from the simulator <b>14</b>. The controller <b>12</b> processes the feedback signals to determine whether the control signals <b>26</b> are producing the correct voltages and currents in the variable frequency drive and motor and whether any fault conditions <b>36</b> exist. If the controller determines that the voltages, currents, and/or temperature readings are not at approximately the target values or if there is a fault condition, the controller <b>12</b> will adjust the control signals <b>26</b> to correct the issue.
Process <b>50</b> then proceeds from operation <b>62</b> to operation <b>64</b> in which the controller <b>12</b> reports status information to the computer <b>16</b>. The status information may include any information about the operation of the controller <b>12</b> including information about the control signals <b>26</b>, information about any of the simulated data received in the feedback signals, and/or any information that indicates a fault condition. Process <b>50</b> then proceeds from operation <b>64</b> back to operation <b>52</b> in which controller <b>12</b> receives data such as a command from the computer <b>16</b>.
<figref idref="DRAWINGS">FIG. 4</figref> illustrates a schematic flow diagram of a process <b>70</b> that may be implemented by the simulator <b>14</b> for simulating a variable frequency drive and a load such as a motor or an inductive test load. Process <b>70</b> begins with operation <b>72</b> in which the simulator <b>14</b> receives data in the form of commands and/or parameters from the computer <b>16</b>. As discussed above, the commands and/or parameters from the computer <b>16</b> relates to the particular type of variable frequency drive and/or load that the simulator <b>14</b> will simulate as well as any fault conditions that are to be simulated. For example, the computer <b>16</b> may select a particular type of load to be simulated such as an inductive load, an induction motor, and/or a permanent magnet motor.
Process <b>70</b> proceeds from operation <b>72</b> to operation <b>74</b> in which it is determined whether the command is to exit the testing or shutdown the simulator <b>14</b>. If the received command is a shutdown or exit command, then process <b>70</b> proceeds to operation <b>72</b> in which the testing is exited and/or the simulator <b>14</b> a shutdown. If the command is not a shutdown or exit command, then process <b>70</b> proceeds to operation <b>78</b>.
At operation <b>78</b>, the simulator <b>14</b> receives the control signals <b>26</b> from the controller <b>12</b>. The control signals <b>26</b> include a PWM control signal, which is used by the switching devices, e.g., transistors, of the inverter to generate the output voltage and output current to power the load such as a motor.
Process <b>70</b> then proceeds from operation <b>78</b> to operation <b>80</b>. In operation <b>80</b>, the simulator <b>14</b> simulates the inverter of a variable frequency drive by determining one or more simulated inverter output voltages <b>28</b> based on the control signals <b>26</b>, the model <b>22</b>, and/or parameters <b>24</b>. The simulator <b>14</b> may determine a simulated inverter output voltage <b>28</b> for some or all of the phases of the variable frequency drive being simulated. In addition, at operation <b>80</b>, the simulator <b>14</b> may also increment a voltage counter that may be part of a parameters table. The voltage counter may be used by the simulator <b>14</b> for performing various voltage and/or current calculations.
Process <b>70</b> then proceeds from operation <b>80</b> to one of operations <b>82</b>, <b>84</b>, or <b>86</b>, which relate to the various load models <b>22</b> that may be used by simulator <b>14</b>. The simulator <b>14</b> will use the load model <b>22</b> selected by the computer <b>16</b>. As shown in <figref idref="DRAWINGS">FIG. 4</figref>, there are three load models: an inductive load, an induction motor, or a permanent magnet motor. It is contemplated that other loads and models may be used with the present application other than the three shown in <figref idref="DRAWINGS">FIG. 4</figref>.
Process <b>70</b> then proceeds to operation <b>88</b> in which the simulated output currents <b>30</b> are determined based on the control signals <b>26</b>, the model <b>22</b>, parameters <b>24</b> and/or the simulated inverter output voltages <b>28</b>. <figref idref="DRAWINGS">FIGS. 5 and 6</figref> and their accompanying description will describe the process for calculating the simulated output currents <b>30</b> in more detail.
Process <b>70</b> then proceeds to operation <b>90</b> in which the simulator <b>14</b> determines the simulated DC bus voltages <b>32</b> based on the control signals <b>26</b>, the model <b>22</b>, and/or parameters <b>24</b>. Furthermore, the simulator <b>14</b> may determine a positive DC rail voltage and a negative DC rail voltage.
Process <b>70</b> then proceeds from operation <b>90</b> to operation <b>92</b> in which the simulator <b>14</b> determines one or more simulated temperature readings based on the control signals <b>26</b>, the model <b>22</b>, and/or parameters <b>24</b>. The locations of the simulated temperature readings <b>34</b> may include at the transistors at the output of each phase of the inverter, at a heat sink for the inverter, and heat sink for the rectifier.
Process <b>70</b> then proceeds from operation <b>92</b> to operation <b>94</b> in which the simulator <b>14</b> generates simulated fault conditions <b>36</b> based on the control signals <b>26</b>, the model <b>22</b>, and/or parameters <b>24</b>. One example of a fault condition is a desaturation of a transistor of the inverter being simulated. Other examples of faults include setting simulated voltages, simulated currents, and/or simulated temperature readings high or low, which may indicate a fault condition or failure to the controller <b>12</b>. Other fault conditions in addition to or in place of those discussed are also contemplated.
Process <b>70</b> then proceeds from operation <b>94</b> to operation <b>96</b> in which the simulator <b>14</b> generates one or more feedback signals based on the simulated inverter output voltages <b>28</b>, the simulated output currents <b>30</b>, the simulated DC bus voltages <b>32</b>, the simulated temperature readings <b>34</b>, and the simulated fault conditions <b>36</b>. The feedback signals are then provided by the simulator <b>14</b> to the controller <b>12</b>.
Process <b>70</b> then proceeds from operation <b>96</b> to operation <b>98</b> in which simulator <b>14</b> updates its parameter tables based on data received from the computer <b>16</b>, the control signals <b>26</b> from the controller <b>12</b>, and/or based on the simulated data calculated such as the simulated inverter output voltages <b>28</b>, the simulated output currents <b>30</b>, the simulated DC bus voltages <b>32</b>, the simulated temperature readings <b>34</b>, and the simulated fault conditions <b>36</b>. Process <b>70</b> then proceeds from operation <b>98</b> back to operation <b>72</b> and operation <b>74</b> in which the simulator <b>14</b> determines whether to exit testing or to continue.
<figref idref="DRAWINGS">FIG. 5</figref> illustrates a schematic flow diagram of a process <b>100</b> that may be implemented by the simulator <b>14</b> for determining the simulated output currents <b>30</b> according to an inductive load model as shown at operation <b>82</b> in <figref idref="DRAWINGS">FIG. 4</figref>. Process <b>100</b> begins at operation <b>102</b> in which the simulated inverter output voltages <b>28</b> are inputted and transformed from a three coordinate system ABC to a two coordinate system αβ. This transformation may be performed to simplify the calculations to determine the simulated output currents. It is contemplated that although a three-phase system is shown, other systems with a different number of phases may be used with the present application.
Process <b>100</b> then proceeds from operation <b>102</b> to operation <b>104</b>. At operation <b>104</b>, the simulator <b>14</b> solves the following equations to determine the currents where L is inductance, v is voltage, and i is current, and the subscripts a, b, c refer to the three phases:
<maths id="MATH-US-00001" num="00001"><math overflow="scroll"><mtable><mtr><mtd><mrow><mrow><mrow><mi>L</mi><mo></mo><mfrac><mi>d</mi><mrow><mi>d</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mi>t</mi></mrow></mfrac><mo></mo><msub><mi>i</mi><mi>a</mi></msub></mrow><mo>=</mo><mrow><msub><mi>v</mi><mi>a</mi></msub><mo>-</mo><msub><mi>ri</mi><mi>a</mi></msub></mrow></mrow><mo></mo><mstyle><mtext></mtext></mstyle><mo></mo><mrow><mrow><mi>L</mi><mo></mo><mfrac><mi>d</mi><mrow><mi>d</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mi>t</mi></mrow></mfrac><mo></mo><msub><mi>i</mi><mi>b</mi></msub></mrow><mo>=</mo><mrow><msub><mi>v</mi><mi>b</mi></msub><mo>-</mo><msub><mi>ri</mi><mi>b</mi></msub></mrow></mrow><mo></mo><mstyle><mtext></mtext></mstyle><mo></mo><mrow><mrow><mi>L</mi><mo></mo><mfrac><mi>d</mi><mrow><mi>d</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mi>t</mi></mrow></mfrac><mo></mo><msub><mi>i</mi><mi>c</mi></msub></mrow><mo>=</mo><mrow><msub><mi>v</mi><mi>c</mi></msub><mo>-</mo><msub><mi>ri</mi><mi>c</mi></msub></mrow></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>1</mn><mo>)</mo></mrow></mtd></mtr></mtable></math></maths>
After the equations are solved, process <b>100</b> then proceeds from operation <b>104</b> to operation <b>106</b>. In operation <b>106</b>, the data is transformed from a two coordinate system αβ to a three coordinate system ABC. The outputs of operation <b>106</b> are the simulated output currents <b>30</b>.
<figref idref="DRAWINGS">FIG. 6</figref> illustrates a schematic flow diagram of a process <b>110</b> that may be implemented by the simulator <b>14</b> for determining the simulated output currents <b>30</b> according to an induction motor model as shown at operation <b>84</b> in <figref idref="DRAWINGS">FIG. 4</figref>. Process <b>110</b> begins at operation <b>112</b> in which the simulated inverter output voltages <b>28</b> are inputted and transformed from a three coordinate system ABC to a two coordinate system αβ. This transformation may be performed to simplify the calculations to determine the simulated output currents <b>30</b>. It is contemplated that although a three-phase system is shown, other systems with a different number of phases may be used with the present application.
Process <b>110</b> then proceeds from operation <b>112</b> to operation <b>114</b>. At operation <b>114</b>, the simulator <b>14</b> converts the voltages from a stator frame of reference to a rotor frame of reference. Process <b>110</b> then proceeds from operation <b>114</b> to operation <b>116</b>, which solves the following equations to determine the currents where L is inductance, v is voltage, i is current, ψ is flux, r<sub>s </sub>is linkage, ω<sub>b </sub>is rated frequency (rad/sec), Z<sub>b </sub>is 100% (normalized) impedance, C<sub>i </sub>is a factor to allow 1.0 to represent an overcurrent condition, C<sub>w </sub>is a factor to allow 1.0 to represent an overspeed condition M is normalized rotational inertia (units of seconds), and σL<sub>s </sub>is an induction motor parameter:
<maths id="MATH-US-00002" num="00002"><math overflow="scroll"><mtable><mtr><mtd><mrow><mrow><mrow><mfrac><mrow><mi>σ</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><msub><mi>L</mi><mi>s</mi></msub></mrow><msub><mi>Z</mi><mi>b</mi></msub></mfrac><mo></mo><mfrac><mi>d</mi><mrow><mi>d</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mi>t</mi></mrow></mfrac><mo></mo><msubsup><mi>i</mi><mi>ds</mi><mi>r</mi></msubsup></mrow><mo>=</mo><mrow><msubsup><mi>v</mi><mi>ds</mi><mi>r</mi></msubsup><mo>-</mo><mrow><msubsup><mi>r</mi><mi>s</mi><mi>′</mi></msubsup><mo></mo><msubsup><mi>i</mi><mi>ds</mi><mi>r</mi></msubsup></mrow><mo>+</mo><mrow><mfrac><msub><mi>ω</mi><mi>r</mi></msub><msub><mi>ω</mi><mi>b</mi></msub></mfrac><mo></mo><mrow><mo>(</mo><mrow><msub><mi>L</mi><mi>s</mi></msub><mo>-</mo><mfrac><msubsup><mi>L</mi><mi>m</mi><mn>2</mn></msubsup><msub><mi>L</mi><mi>r</mi></msub></mfrac></mrow><mo>)</mo></mrow><mo></mo><msubsup><mi>i</mi><mi>qs</mi><mi>r</mi></msubsup></mrow><mo>+</mo><mrow><mfrac><msub><mi>L</mi><mi>m</mi></msub><msub><mi>L</mi><mi>r</mi></msub></mfrac><mo></mo><mfrac><msub><mi>r</mi><mi>r</mi></msub><msub><mi>L</mi><mi>r</mi></msub></mfrac><mo></mo><msubsup><mi>ψ</mi><mi>dr</mi><mi>r</mi></msubsup></mrow><mo>+</mo><mrow><mfrac><msub><mi>L</mi><mi>m</mi></msub><msub><mi>L</mi><mi>r</mi></msub></mfrac><mo></mo><mfrac><msub><mi>ω</mi><mi>r</mi></msub><msub><mi>ω</mi><mi>b</mi></msub></mfrac><mo></mo><msubsup><mi>ψ</mi><mi>qr</mi><mi>r</mi></msubsup></mrow></mrow></mrow><mo></mo><mstyle><mtext></mtext></mstyle><mo></mo><mrow><mrow><mfrac><mrow><mi>σ</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><msub><mi>L</mi><mi>s</mi></msub></mrow><msub><mi>Z</mi><mi>b</mi></msub></mfrac><mo></mo><mfrac><mi>d</mi><mrow><mi>d</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mi>t</mi></mrow></mfrac><mo></mo><msubsup><mi>i</mi><mi>qs</mi><mi>r</mi></msubsup></mrow><mo>=</mo><mrow><msubsup><mi>v</mi><mi>qs</mi><mi>r</mi></msubsup><mo>-</mo><mrow><msubsup><mi>r</mi><mi>s</mi><mi>′</mi></msubsup><mo></mo><msubsup><mi>i</mi><mi>qs</mi><mi>r</mi></msubsup></mrow><mo>-</mo><mrow><mfrac><msub><mi>ω</mi><mi>r</mi></msub><msub><mi>ω</mi><mi>b</mi></msub></mfrac><mo></mo><mrow><mo>(</mo><mrow><msub><mi>L</mi><mi>s</mi></msub><mo>-</mo><mfrac><msubsup><mi>L</mi><mi>m</mi><mn>2</mn></msubsup><msub><mi>L</mi><mi>r</mi></msub></mfrac></mrow><mo>)</mo></mrow><mo></mo><msubsup><mi>i</mi><mi>ds</mi><mi>r</mi></msubsup></mrow><mo>-</mo><mrow><mfrac><msub><mi>L</mi><mi>m</mi></msub><msub><mi>L</mi><mi>r</mi></msub></mfrac><mo></mo><mfrac><msub><mi>ω</mi><mi>r</mi></msub><msub><mi>ω</mi><mi>b</mi></msub></mfrac><mo></mo><msubsup><mi>ψ</mi><mi>dr</mi><mi>r</mi></msubsup></mrow><mo>+</mo><mrow><mfrac><msub><mi>L</mi><mi>m</mi></msub><msub><mi>L</mi><mi>r</mi></msub></mfrac><mo></mo><mfrac><msub><mi>r</mi><mi>r</mi></msub><msub><mi>L</mi><mi>r</mi></msub></mfrac><mo></mo><msubsup><mi>ψ</mi><mi>qr</mi><mi>r</mi></msubsup></mrow></mrow></mrow><mo></mo><mstyle><mtext></mtext></mstyle><mo></mo><mrow><mrow><mfrac><mn>1</mn><msub><mi>ω</mi><mi>b</mi></msub></mfrac><mo></mo><mfrac><mi>d</mi><mrow><mi>d</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mi>t</mi></mrow></mfrac><mo></mo><msubsup><mi>ψ</mi><mi>dr</mi><mi>r</mi></msubsup></mrow><mo>=</mo><mrow><mrow><mfrac><msub><mi>L</mi><mi>m</mi></msub><msub><mi>L</mi><mi>r</mi></msub></mfrac><mo></mo><msub><mi>r</mi><mi>r</mi></msub><mo></mo><msubsup><mi>i</mi><mi>ds</mi><mi>r</mi></msubsup></mrow><mo>-</mo><mrow><mfrac><msup><mi>r</mi><mi>r</mi></msup><msub><mi>L</mi><mi>r</mi></msub></mfrac><mo></mo><msubsup><mi>ψ</mi><mi>dr</mi><mi>r</mi></msubsup></mrow></mrow></mrow><mo></mo><mstyle><mtext></mtext></mstyle><mo></mo><mrow><mrow><mfrac><mn>1</mn><msub><mi>ω</mi><mi>b</mi></msub></mfrac><mo></mo><mfrac><mi>d</mi><mrow><mi>d</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mi>t</mi></mrow></mfrac><mo></mo><msubsup><mi>ψ</mi><mi>qr</mi><mi>r</mi></msubsup></mrow><mo>=</mo><mrow><mrow><mfrac><msub><mi>L</mi><mi>m</mi></msub><msub><mi>L</mi><mi>r</mi></msub></mfrac><mo></mo><msub><mi>r</mi><mi>r</mi></msub><mo></mo><msubsup><mi>i</mi><mi>qs</mi><mi>r</mi></msubsup></mrow><mo>-</mo><mrow><mfrac><msup><mi>r</mi><mi>r</mi></msup><msub><mi>L</mi><mi>r</mi></msub></mfrac><mo></mo><msubsup><mi>ψ</mi><mi>qr</mi><mi>r</mi></msubsup></mrow></mrow></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>2</mn><mo>)</mo></mrow></mtd></mtr><mtr><mtd><mrow><mrow><mrow><msub><mi>C</mi><mi>i</mi></msub><mo></mo><mfrac><mrow><mi>σ</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><msub><mi>L</mi><mi>s</mi></msub></mrow><msub><mi>Z</mi><mi>b</mi></msub></mfrac><mo></mo><mfrac><mi>d</mi><mrow><mi>d</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mi>t</mi></mrow></mfrac><mo></mo><msubsup><mi>i</mi><mi>ds</mi><mi>r</mi></msubsup></mrow><mo>=</mo><mrow><msubsup><mi>v</mi><mi>ds</mi><mi>r</mi></msubsup><mo>-</mo><mrow><msub><mi>C</mi><mi>i</mi></msub><mo></mo><msubsup><mi>r</mi><mi>s</mi><mi>′</mi></msubsup><mo></mo><msubsup><mi>i</mi><mi>ds</mi><mi>r</mi></msubsup></mrow><mo>+</mo><mrow><msub><mi>C</mi><mi>ω</mi></msub><mo></mo><msub><mi>C</mi><mi>i</mi></msub><mo></mo><mfrac><msub><mi>ω</mi><mi>r</mi></msub><msub><mi>ω</mi><mi>b</mi></msub></mfrac><mo></mo><mrow><mo>(</mo><mrow><msub><mi>L</mi><mi>s</mi></msub><mo>-</mo><mfrac><msubsup><mi>L</mi><mi>m</mi><mn>2</mn></msubsup><msub><mi>L</mi><mi>r</mi></msub></mfrac></mrow><mo>)</mo></mrow><mo></mo><msubsup><mi>i</mi><mi>qs</mi><mi>r</mi></msubsup></mrow><mo>+</mo><mrow><mfrac><msub><mi>x</mi><mi>m</mi></msub><msub><mi>x</mi><mi>r</mi></msub></mfrac><mo></mo><mfrac><msub><mi>r</mi><mi>r</mi></msub><msub><mi>x</mi><mi>r</mi></msub></mfrac><mo></mo><msubsup><mi>ψ</mi><mi>dr</mi><mi>r</mi></msubsup></mrow><mo>+</mo><mrow><msub><mi>C</mi><mi>ω</mi></msub><mo></mo><mfrac><msub><mi>x</mi><mi>m</mi></msub><msub><mi>x</mi><mi>r</mi></msub></mfrac><mo></mo><mfrac><msub><mi>ω</mi><mi>r</mi></msub><msub><mi>ω</mi><mi>b</mi></msub></mfrac><mo></mo><msubsup><mi>ψ</mi><mi>qr</mi><mi>r</mi></msubsup></mrow></mrow></mrow><mo></mo><mstyle><mtext></mtext></mstyle><mo></mo><mrow><mrow><msub><mi>C</mi><mi>i</mi></msub><mo></mo><mfrac><mrow><mi>σ</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><msub><mi>L</mi><mi>s</mi></msub></mrow><msub><mi>Z</mi><mi>b</mi></msub></mfrac><mo></mo><mfrac><mi>d</mi><mrow><mi>d</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mi>t</mi></mrow></mfrac><mo></mo><msubsup><mi>i</mi><mi>qs</mi><mi>r</mi></msubsup></mrow><mo>=</mo><mrow><msubsup><mi>v</mi><mi>qs</mi><mi>r</mi></msubsup><mo>-</mo><mrow><msub><mi>C</mi><mi>i</mi></msub><mo></mo><msubsup><mi>r</mi><mi>s</mi><mi>′</mi></msubsup><mo></mo><msubsup><mi>i</mi><mi>qs</mi><mi>r</mi></msubsup></mrow><mo>-</mo><mrow><msub><mi>C</mi><mi>ω</mi></msub><mo></mo><msub><mi>C</mi><mi>i</mi></msub><mo></mo><mfrac><msub><mi>ω</mi><mi>r</mi></msub><msub><mi>ω</mi><mi>b</mi></msub></mfrac><mo></mo><mrow><mo>(</mo><mrow><msub><mi>L</mi><mi>s</mi></msub><mo>-</mo><mfrac><msubsup><mi>L</mi><mi>m</mi><mn>2</mn></msubsup><msub><mi>L</mi><mi>r</mi></msub></mfrac></mrow><mo>)</mo></mrow><mo></mo><msubsup><mi>i</mi><mi>ds</mi><mi>r</mi></msubsup></mrow><mo>-</mo><mrow><mfrac><msub><mi>x</mi><mi>m</mi></msub><msub><mi>x</mi><mi>r</mi></msub></mfrac><mo></mo><mfrac><msub><mi>ω</mi><mi>r</mi></msub><msub><mi>ω</mi><mi>b</mi></msub></mfrac><mo></mo><msubsup><mi>ψ</mi><mi>dr</mi><mi>r</mi></msubsup></mrow><mo>+</mo><mrow><msub><mi>C</mi><mi>ω</mi></msub><mo></mo><mfrac><msub><mi>x</mi><mi>m</mi></msub><msub><mi>x</mi><mi>r</mi></msub></mfrac><mo></mo><mfrac><msub><mi>r</mi><mi>r</mi></msub><msub><mi>x</mi><mi>r</mi></msub></mfrac><mo></mo><msubsup><mi>ψ</mi><mi>qr</mi><mi>r</mi></msubsup></mrow></mrow></mrow><mo></mo><mstyle><mtext></mtext></mstyle><mo></mo><mrow><mrow><mfrac><mn>1</mn><msub><mi>ω</mi><mi>b</mi></msub></mfrac><mo></mo><mfrac><mi>d</mi><mrow><mi>d</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mi>t</mi></mrow></mfrac><mo></mo><msubsup><mi>ψ</mi><mi>dr</mi><mi>r</mi></msubsup></mrow><mo>=</mo><mrow><mrow><msub><mi>C</mi><mi>i</mi></msub><mo></mo><mfrac><msub><mi>x</mi><mi>m</mi></msub><msub><mi>x</mi><mi>r</mi></msub></mfrac><mo></mo><msub><mi>r</mi><mi>r</mi></msub><mo></mo><msubsup><mi>i</mi><mi>ds</mi><mi>r</mi></msubsup></mrow><mo>-</mo><mrow><mfrac><msub><mi>r</mi><mi>r</mi></msub><msub><mi>L</mi><mi>r</mi></msub></mfrac><mo></mo><msubsup><mi>ψ</mi><mi>dr</mi><mi>r</mi></msubsup></mrow></mrow></mrow><mo></mo><mstyle><mtext></mtext></mstyle><mo></mo><mrow><mrow><mfrac><mn>1</mn><msub><mi>ω</mi><mi>b</mi></msub></mfrac><mo></mo><mfrac><mi>d</mi><mrow><mi>d</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mi>t</mi></mrow></mfrac><mo></mo><msubsup><mi>ψ</mi><mi>qr</mi><mi>r</mi></msubsup></mrow><mo>=</mo><mrow><mrow><msub><mi>C</mi><mi>i</mi></msub><mo></mo><mfrac><msub><mi>L</mi><mi>m</mi></msub><msub><mi>L</mi><mi>r</mi></msub></mfrac><mo></mo><msub><mi>r</mi><mi>r</mi></msub><mo></mo><msubsup><mi>i</mi><mi>qs</mi><mi>r</mi></msubsup></mrow><mo>-</mo><mrow><mfrac><msub><mi>r</mi><mi>r</mi></msub><msub><mi>L</mi><mi>r</mi></msub></mfrac><mo></mo><msubsup><mi>ψ</mi><mi>qr</mi><mi>r</mi></msubsup></mrow></mrow></mrow><mo></mo><mstyle><mtext></mtext></mstyle><mo></mo><mrow><mrow><mi>M</mi><mo></mo><mfrac><mi>d</mi><mrow><mi>d</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mi>t</mi></mrow></mfrac><mo></mo><mfrac><msub><mi>ω</mi><mi>r</mi></msub><msub><mi>ω</mi><mi>b</mi></msub></mfrac><mo></mo><msubsup><mi>ψ</mi><mi>qr</mi><mi>r</mi></msubsup></mrow><mo>=</mo><mrow><mrow><mfrac><msub><mi>C</mi><mi>i</mi></msub><msub><mi>C</mi><mi>ω</mi></msub></mfrac><mo></mo><mfrac><msub><mi>x</mi><mi>m</mi></msub><msub><mi>x</mi><mi>r</mi></msub></mfrac><mo></mo><mrow><mo>(</mo><mrow><mrow><msub><mi>ψ</mi><mi>dr</mi></msub><mo></mo><msub><mi>i</mi><mi>qs</mi></msub></mrow><mo>-</mo><mrow><msub><mi>ψ</mi><mi>qr</mi></msub><mo></mo><msub><mi>i</mi><mi>ds</mi></msub></mrow></mrow><mo>)</mo></mrow></mrow><mo>-</mo><mrow><mfrac><mn>1</mn><msub><mi>C</mi><mi>ω</mi></msub></mfrac><mo></mo><msub><mi>T</mi><mi>load</mi></msub></mrow></mrow></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>3</mn><mo>)</mo></mrow></mtd></mtr></mtable></math></maths>
Process <b>110</b> then proceeds from operation <b>116</b> to operation <b>118</b>. At operation <b>118</b>, the simulator <b>14</b> converts the system from a rotor frame of reference to a stator frame of reference. Process <b>110</b> then proceeds to operation <b>120</b> in which the data is transformed from a two coordinate system αβ to a three coordinate system ABC. The outputs of operation <b>110</b> are the simulated output currents <b>30</b>.
The process for determining the simulated output currents <b>30</b> in which a permanent magnet motor model is used is similar to the process <b>110</b> where an induction motor model is used. Moreover, the equations to be solved for a permanent magnet motor would been those known to persons of ordinary skill in the art.
<figref idref="DRAWINGS">FIG. 7</figref> is a schematic block diagram of a computing device <b>200</b>. The computing device <b>200</b> is one example of a controller, simulator, and/or computer configuration which may be utilized in connection with the controller <b>12</b>, simulator <b>14</b>, and/or computer <b>16</b> shown in <figref idref="DRAWINGS">FIG. 1</figref>. Computing device <b>200</b> includes a processing device <b>202</b>, an input/output device <b>204</b>, memory <b>206</b>, and operating logic <b>208</b>. Furthermore, computing device <b>200</b> communicates with one or more external devices <b>210</b>.
The input/output device <b>204</b> allows the computing device <b>200</b> to communicate with the external device <b>210</b>. For example, the input/output device <b>204</b> may be a network adapter, network card, interface, or a port (e.g., a USB port, serial port, parallel port, an analog port, a digital port, a modbus interface, an ASCII interface, VGA, DVI, HDMI, FireWire, CAT 5, or any other type of port or interface). The input/output device <b>204</b> may be comprised of hardware, software, and/or firmware. It is contemplated that the input/output device <b>204</b> includes more than one of these adapters, cards, or ports.
The external device <b>210</b> may be any type of device that allows data to be inputted or outputted from the computing device <b>200</b>. For example, the external device <b>210</b> may be a handheld computer or diagnostic tool, a controller, a simulator, a computer, a server, a printer, a display, an alarm, an illuminated indicator such as status indicator <b>152</b>, a keyboard, a mouse, or a touch screen display. Furthermore, it is contemplated that the external device <b>210</b> may be integrated into the computing device <b>200</b>. It is further contemplated that there may be more than one external device in communication with the computing device <b>200</b>.
Processing device <b>202</b> can be of a programmable type, a dedicated, hardwired state machine, or a combination of these; and can further include multiple processors, Arithmetic-Logic Units (ALUs), Central Processing Units (CPUs), Digital Signal Processors (DSPs) or the like. For forms of processing device <b>202</b> with multiple processing units, distributed, pipelined, and/or parallel processing can be utilized as appropriate. Processing device <b>202</b> may be dedicated to performance of just the operations described herein or may be utilized in one or more additional applications. In the depicted form, processing device <b>202</b> is of a programmable variety that executes algorithms and processes data in accordance with operating logic <b>208</b> as defined by programming instructions (such as software or firmware) stored in memory <b>206</b>. Alternatively or additionally, operating logic <b>208</b> for processing device <b>202</b> is at least partially defined by hardwired logic or other hardware. Processing device <b>202</b> can be comprised of one or more components of any type suitable to process the signals received from input/output device <b>204</b> or elsewhere, and provide desired output signals. Such components may include digital circuitry, analog circuitry, or a combination of both.
Memory <b>206</b> may be of one or more types, such as a solid-state variety, electromagnetic variety, optical variety, or a combination of these forms. Furthermore, memory <b>206</b> can be volatile, nonvolatile, or a combination of these types, and some or all of memory <b>206</b> can be of a portable variety, such as a disk, tape, memory stick, cartridge, or the like. In addition, memory <b>206</b> can store data that is manipulated by the operating logic <b>208</b> of processing device <b>202</b>, such as data representative of signals received from and/or sent to input/output device <b>204</b> in addition to or in lieu of storing programming instructions defining operating logic <b>208</b>, just to name one example. As shown in <figref idref="DRAWINGS">FIG. 7</figref>, memory <b>206</b> may be included with processing device <b>202</b> and/or coupled to the processing device <b>202</b>.
The processes <b>40</b>, <b>50</b>, <b>70</b>, <b>100</b>, and <b>110</b> may be implemented in operating logic <b>208</b> as operations by software, hardware, artificial intelligence, fuzzy logic, or any combination thereof, or at least partially performed by a user or operator. In certain embodiments, modules represent software elements as a computer program encoded on a computer readable medium, wherein the controller <b>12</b>, simulator <b>14</b>, and/or computer <b>16</b> performs the described operations when executing the computer program.
The present application refers to some voltages, currents, and/or readings as being determined “approximately.” As used herein, “approximately” is to generally account for the error or impreciseness of measuring a voltage or current or they may change over small amounts of time. The number of volts or amps that are acceptable under “approximately” depends on the system. In some systems, less than one volt or one amp may be acceptable, but in other systems, several volts or several amps will be within “approximately.” In addition, even if a comparison or evaluation does not refer to “approximately,” the present application presumes that there is an accounting for the impreciseness in the system.
While the invention has been described in connection with what is presently considered to be the preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiment(s), but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims, which scope is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures as permitted under the law. Furthermore it should be understood that while the use of the word preferable, preferably, or preferred in the description above indicates that feature so described may be more desirable, it nonetheless may not be necessary and any embodiment lacking the same may be contemplated as within the scope of the invention, that scope being defined by the claims that follow. In reading the claims it is intended that when words such as “a,” “an,” “at least one” and “at least a portion” are used, there is no intention to limit the claim to only one item unless specifically stated to the contrary in the claim. Further, when the language “at least a portion” and/or “a portion” is used the item may include a portion and/or the entire item unless specifically stated to the contrary.
Contents5
10 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9 Sheet 10
Every citation, both waysCites: the store holds 17 of 18
| Document | Relation | Office | Cited during |
|---|---|---|---|
| CN107576518A | Cited by | China | Search report |
| US2022221849A1 | Cited by | United States of America | Search report |
| WO2008006116A2 | Cites | World Intellectual Property Organization (WIPO) | Applicant |
| US2009085572A1 | Cites | United States of America | Search report |
| US2012133389A1 | Cites | United States of America | Applicant |
| US2012191439A1 | Cites | United States of America | Applicant |
| US2012232869A1 | Cites | United States of America | Applicant |
| US5524498A | Cites | United States of America | Applicant |
| US7199549B2 | Cites | United States of America | Search report |
| US7880460B2 | Cites | United States of America | Search report |
| US8108191B1 | Cites | United States of America | Applicant |
| US8249845B1 | Cites | United States of America | Applicant |
| US8880250B2 | Cites | United States of America | Search report |
| US9490682B2 | Cites | United States of America | Search report |
| US20090085572A1 | Cites | United States of America | Search report |
| US20120133389A1 | Cites | United States of America | Applicant |
| US20120191439A1 | Cites | United States of America | Applicant |
| US20120232869A1 | Cites | United States of America | Applicant |
| WO2008006116 | Cites | World Intellectual Property Organization (WIPO) | Applicant |
6 priority claims, no other members on record
Priority claims6
| Document | Office | Kind | Date |
|---|---|---|---|
| 201361756264 | United States of America | P | |
| 201361756264 | United States of America | P | |
| 201414162924 | United States of America | A | |
| 61756264 | – | – | – |
| US201361756264P | – | – | – |
| US201414162924 | – | – | – |
75 transactions on the USPTO file
Allowed after 2 non-final rejections, 1 final rejection and 1 RCE.
- Non-final rejections
- 2
- Final rejections
- 1
- RCEs
- 1
- Appeals
- 0
Over time
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| Event | Code | |
|---|---|---|
| Recordation of Patent Grant MailedPGM/ | PGM/ | |
| Patent Issue Date Used in PTA CalculationAllowedPTAC | PTAC | |
| Email NotificationEML_NTR | EML_NTR | |
| Issue Notification MailedAllowedWPIR | WPIR | |
| Dispatch to FDCD1935 | D1935 | |
| Dispatch to FDCD1935 | D1935 | |
| Application Is Considered Ready for IssuePILS | PILS | |
| Issue Fee Payment VerifiedN084 | N084 | |
| Issue Fee Payment ReceivedIFEE | IFEE | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Notice of AllowanceAllowedMN/=. | MN/=. | |
| Notice of Allowance Data Verification CompletedAllowedN/=. | N/=. | |
| Reasons for AllowanceEX.R | EX.R | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response after Non-Final ActionA... | A... | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Non-Final RejectionNon-final rejectionMCTNF | MCTNF | |
| Non-Final RejectionNon-final rejectionCTNF | CTNF | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Disposal for a RCE / CPA / R129AbandonedABN9 | ABN9 | |
| Request for Continued Examination (RCE)RCEX | RCEX | |
| Workflow - Request for RCE - BeginBRCE | BRCE | |
| Mail Interview Summary - Applicant Initiated - TelephonicMEXAT | MEXAT | |
| Interview Summary - Applicant Initiated - TelephonicEXAT | EXAT | |
| Miscellaneous Incoming LetterLET. | LET. | |
| Email NotificationEML_NTR | EML_NTR | |
| Mail Advisory Action (PTOL - 303)MCTAV | MCTAV | |
| Advisory Action (PTOL-303)CTAV | CTAV | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response after Final ActionA.NE | A.NE | |
| Electronic request for Examiner InterviewM865E | M865E | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Final Rejection (PTOL - 326)Final rejectionMCTFR | MCTFR | |
| Final RejectionFinal rejectionCTFR | CTFR | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response after Non-Final ActionA... | A... | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Non-Final RejectionNon-final rejectionMCTNF | MCTNF | |
| Non-Final RejectionNon-final rejectionCTNF | CTNF | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Close TICLTI | CLTI | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Transfer Inquiry to GAUTI1050 | TI1050 | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Oath or Declaration Filed (Including Supplemental)C602 | C602 | |
| Email NotificationEML_NTR | EML_NTR | |
| Change in Power of Attorney (May Include Associate POA)PA.. | PA.. | |
| Correspondence Address ChangeC.AD | C.AD | |
| Electronic Information Disclosure StatementEIDS. | EIDS. | |
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| Application ready for PDX access by participating foreign officesCCRDY | CCRDY | |
| Email NotificationEML_NTR | EML_NTR | |
| PG-Pub Issue NotificationPG-ISSUE | PG-ISSUE | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Email NotificationEML_NTR | EML_NTR | |
| Application Is Now CompleteCOMP | COMP | |
| Application Is Now CompleteCOMP | COMP | |
| Filing Receipt - UpdatedFLRCPT.U | FLRCPT.U | |
| Application Dispatched from OIPEOIPE | OIPE | |
| FITF set to NO - revise initial settingFTFI | FTFI | |
| Patent Term Adjustment - Ready for ExaminationPTA.RFE | PTA.RFE | |
| Additional Application Filing FeesADDFLFEE | ADDFLFEE | |
| Notice Mailed--Application Incomplete--Filing Date AssignedINCD | INCD | |
| Filing ReceiptFLRCPT.O | FLRCPT.O | |
| Cleared by OIPE CSRL194 | L194 | |
| Applicants have given acceptable permission for participating foreignAPPERMS | APPERMS | |
| IFW Scan & PACR Auto Security ReviewSCAN | SCAN | |
| Entity status set to undiscounted (initial default setting or status change)BIG. | BIG. | |
| Initial Exam Team nnIEXX | IEXX |
3 legal events, as the office reported them to INPADOC
Over the term
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|---|---|---|
| Maintenance fee paymentMAFP | MAFP | |
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| AssignmentAS | AS |
Numbers
- Publication
- 09939795
- Publication, DOCDB
- 9939795
- Publication, EPODOC
- US9939795
- Application
- 14162924
- Application, DOCDB
- 201414162924
- Application, EPODOC
- US201414162924
Titles
- English
- Dynamic simulated motor for controller testing
Patent term adjustment
- A delay
- +552 daysthe office missed an examination deadline
- B delay
- +262 dayspendency past three years
- Net adjustment
- 814 days
Classification
- CPC, 2
- G05B17/02
- G05B23/0205
- IPC, 2
- G05B17 02
- G05B23 02
- USPC, 2
- 318787000
- 001001000