Digital-to-analog converter system and method

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 14/676,142, filed Apr. 1, 2015, which claims the benefit of priority of U.S. Provisional Patent Application No. 61/973,558 filed Apr. 1, 2014, which is hereby incorporated by reference.

FIELD

The present disclosure relates generally to Radio Frequency Digital-to-Analog Conversion. More particularly, the present disclosure relates to Radio Frequency Digital-to-Analog Conversion for application in cellular base stations.

BACKGROUND

Modern Multi-Band Radio Frequency (RF) systems, such as “4G” Cellular systems, are running into fundamental limitations of previous-generation systems, which requires system designers to fundamentally change the structure of the underlying system circuitry. Previous-generation systems are constructed, for the most part, using classic RF system techniques, such as analog mixers and separate analog Base Band and RF filters. Newer systems are transitioning to make use of two new classes of circuits: RF Digital/Analog Converters (RF DACs) and RF Analog/Digital Converters (RF ADCs). These RF converters push the Analog/Digital boundary much closer to the antenna, increasing the available RF bandwidth available and allowing for much more flexibility in the system, by pushing functionality that was previously in the analog circuits into digital circuits or even into software. This latter functionality is often called “Software Defined Radio”, or SDR, and is seen as the ultimate in flexibility, allowing major functional changes of the RF system through a software or firmware download.

In order to understand an RF DAC, it is helpful to understand the fundamentals of a conventional RF transmit signal chain. <figref idref="DRAWINGS">FIG. 1</figref> shows a representative previous-generation signal chain; not all previous-generation signal chains would contain all the elements of <figref idref="DRAWINGS">FIG. 1</figref> and there may be variants, however the differences can be readily understood.

The signal chain accepts Base Band (BB) In-Phase/Quadrature (I/Q) sample data from the BBMedia Access Controller (MAC) through a Digital Interface <b>100</b>. The I/Q data (that is, the I-data and the Q-data) is interpolated to a higher sample rate through an interpolator <b>110</b>, and then is optionally modulated to adjust the center frequency to an Intermediate Frequency (IF) through a Digital Quadrature Modulator (DQM, <b>120</b>). The interpolated and modulated I and Q digital signals are fed through two DACs (<b>140</b>) to produce an analog signal, which is filtered by two matched BB/IF filters (<b>150</b>). The filtered signal data is mixed using an Analog Quadrature Modulator (AQM, <b>160</b>) with a Local Oscillator (LO) clock to produce an RF output. An RF Filter (<b>170</b>) filters the AQM output before amplifying it using a Power Amplifier (PA, <b>180</b>) to produce the signal that will be actually transmitted by the antenna (<b>190</b>).

In addition to the circuit elements, <figref idref="DRAWINGS">FIG. 1</figref> has two clocks. The first, the Base Band Clock (often referred to as SYSCLK), determines the sample data rate at the Digital Interface, and is also used to clock the Interpolator, DQM, and DACs. For convenience, <figref idref="DRAWINGS">FIG. 1</figref> shows all blocks running from the same clock, SYSCLK, however depending upon the details of the actual system, some other clock SYSCLK·M (M being an integer) or SYSCLK/M might actually be used in a particular block. Powers of 2 (i.e. 2^N) are commonly used for M because they allow for ready use of efficient Digital Signal Processor (DSP) filter techniques, but other factors may also be used. The second clock, the Local Oscillator clock (LO) drives the AQM and sets the center frequency of the transmitted RF output. The structure and operation of the AQM are well known to those skilled in the art.

One key difficulty in the design of a conventional RF transmit signal chain comes in the relationship between the two clock frequencies. SYSCLK is, of necessity, a standard fixed frequency; in cellular base stations, this is typically a power of 2 multiple of 122.88 MHz or 153.6 MHz, however other frequencies may be chosen depending upon the system design. LO is typically the center frequency of the desired RF signal band or is slightly offset from it and, depending upon the particular frequency band being used, can vary widely from system to system. Because these two frequencies (SYSCLK and LO) are set by two different constraints, they are often completely unrelated to each other, which in turn creates challenges in frequency planning.

Frequency planning essentially boils down to determining a pair of frequencies for SYSCLK and LO, together with an IF that when taken together create an interference-free range of frequencies for a desired RF band. Due to a number of practical circuit issues, harmonics of SYSCLK and LO will often mix together and create spurs, and if one of these spurs is in the desired RF band, performance of the RF system will be degraded. When desired RF bands are narrow, both as a fraction of the available BB/IF bandwidth and the LO frequency, frequency planning can be straightforward. However in modern RF systems, especially those that make use of Digital Pre-Distortion (DPD), the required RF bandwidths are becoming much wider relative both to the BB/IF bandwidth and the LO frequency and, as a result, the frequency planning challenges are becoming harder.

Another key difficulty in the design of a conventional RF transmit signal chain comes from the BB/IF filters. In these systems, the BB/IF filters are the point where the signals cross from one clock domain (SYSCLK) into the other (LO), therefore these filters, which smooth the discrete output signal generated by the DAC to make them appear to be continuous, often must have comparatively large attenuation at multiples of SYSCLK in order to attenuate images and to minimize any coupling between the two clock domains that could create spurs at the output. This requirement in turn requires that the BB/IF filters be of comparatively high order, which often creates significant design challenges. Some of the challenges relate to the cost (bill of materials), non-idealities, and filter design time. A high-order differential LC filter uses multiple high-precision components, which are expensive and occupy a large printed circuit board area. Amplitude and/or phase mismatch between the BB/IF filters introduce nonlinearities that degrade system performance. In addition, it is difficult to provide a flat filter response over a wide bandwidth. Any ripple or roll-off also degrades system response. Lastly, it is common for these radio systems to support different radio bands. It follows that the BB/IF filters will therefore need to be different for each radio band. This scales the design time as well as the number of components needed to realize the different BB/IF filters. This greatly complicates the radio system.

In early designs, IF's could be relatively large, and the signals going into the AQM were radically asymmetric in frequency. As a result, the BB/IF filters were truly bandpass IF filters, and every frequency band required a different filter design, which created additional challenges for RF system vendors in designing and maintaining many band-specific designs. As RF bandwidths increased, there was a push to increase the available bandwidth from the BB portion of the system, which in turn resulted in a push to Low-IF or Zero-IF (ZIF) systems. This modification reduced the need for band-specific designs, making these filters truly BB filters, however created an increased potential for additional effects due to mismatch between the I and Q filters. These effects, such as I/Q Impairment (IQI) and LO FeedThru (LOFT), become challenges that the system designer needs to deal with, either by increased production costs to tune the filters or, more commonly, by the addition of new blocks to measure these effects and correct for them in the digital domain.

RF DAC Transmit Signal Chains

Many modern RF transmit signal chains are moving to RF DACs, essentially DACs whose outputs are already modulated, in order to simplify the frequency planning challenges and remove the BB/IF filters, while at the same time increasing the available RF bandwidth at the antenna. An example of such a signal chain is shown in <figref idref="DRAWINGS">FIG. 2</figref>. In <figref idref="DRAWINGS">FIG. 2</figref>, and in all successive figures, an attempt has been made to use similar identification numbers to identify similar blocks. As with <figref idref="DRAWINGS">FIG. 1</figref>, BB I/Q samples are received from a MAC through the Digital Interface <b>100</b>. These signals are interpolated to a higher sample rate with the interpolator <b>210</b>, then modulated by the DQM <b>220</b>, and converted to an analog signal by the RF DAC <b>240</b>. The modulated signal is in turn filtered by an RF filer <b>270</b> and is then amplified by the PA <b>180</b> for transmission via the antenna <b>190</b>.

For convenience, <figref idref="DRAWINGS">FIG. 2</figref> shows all blocks driven by a single clock, SYSCLK, however as with <figref idref="DRAWINGS">FIG. 1</figref>, the various blocks are likely driven by multiple different clocks, all integer multiples of SYSCLK. In particular, because the RF DAC <b>240</b> is running at a significantly higher sample rate (Fs) than the I/Q DACs <b>140</b>, the interpolator <b>210</b> and DQM <b>220</b> are similarly going to have significantly higher output sample rates than the interpolator <b>110</b> and DQM <b>120</b>.

By performing the modulation in the digital domain, using DQM <b>220</b> instead of AQM <b>160</b>, and by removing the BB/IF filters <b>150</b>, all system issues caused by analog imperfections or mismatch have been removed. The challenges of maintaining multiple complex band-specific filter designs have also been removed, and furthermore because there is only a single clock domain in the system, the frequency planning challenges caused by having two clock domains are also gone, allowing greater freedom to increase RF bandwidths to accommodate modern system requirements.

Finally, because the characteristics at the output are completely determined by digital circuitry, system designers are free to envision new and different ways of constructing the systems, bringing the ability to increase system modularity and/or move to the ideal of having a Software-Defined Radio (SDR).

RF DAC Transmit Signal Chain Challenges

While the RF DAC Transmit Signal Chain of <figref idref="DRAWINGS">FIG. 2</figref> has significant advantages over the conventional signal chain of <figref idref="DRAWINGS">FIG. 1</figref>, a system designer has several new challenges to overcome.

The first two RF DAC challenges are the so-called “sin(x)/x” or “sinc” response inherent to DAC designs and the images that come from the DAC discrete-time output. The output from a DAC over time is not a smooth continuous signal; it instead has a discrete-time staircase shape, sometimes called a “zero order hold”. In turn, the zero-order hold has a frequency response that is given by the equation sin(x)/x, which is plotted in <figref idref="DRAWINGS">FIG. 3</figref>. The vertical axis of this figure is the frequency response in dB, while the horizontal axis is the output frequency as a fraction of Fs, which is the DAC sample rate or the DAC sampling frequency. As is shown, the sin(x)/x response creates a frequency response notch at Fs, meaning that all signal energy at the sample rate is completely attenuated. There are additional notches at Fs·2, Fs·3, and so on, however these are not shown. Also shown in <figref idref="DRAWINGS">FIG. 3</figref> are the first and second “Nyquist Zones”, which are frequency bands whose width is equal to the Nyquist Frequency Fs/2. Nyquist Zone 1 is a frequency band that extends from DC to Fs/2 and Nyquist Zone 2 is a frequency band that extends from Fs/2 to Fs. There are additional Nyquist Zones that extend beyond Fs that are not shown; for example Nyquist Zone 3 extends from Fs to Fs·3/2, while Nyquist Zone 4 extends from Fs·3/2 to Fs·2. Because the DAC output is a discrete-time signal, output signals that are centered on DC have images centered on Fs, Fs·2, Fs·3, and so on. Therefore, any signal energy in Nyquist Zone 1 will have an image (mirrored at Fs/2) in Nyquist Zone 2 and vice versa. There are additional images in all other Nyquist Zones, but for the purposes of this discussion this is not important.

Examining the sin(x)/x frequency response in <figref idref="DRAWINGS">FIG. 3</figref>, the challenges it causes are clear. <figref idref="DRAWINGS">FIG. 4</figref> shows the frequency response of two representative RF signals <b>401</b> and <b>402</b> transmitted in Nyquist Zone 1. For example, if an RF system designer wished to use the RF signal <b>401</b>, centered around Fs·0.125, there would only be approximately 1 dB of attenuation at the center frequency of the RF signal <b>401</b> due to the sin(x)/x response, which for most systems is relatively easy to accommodate. However, if the RF designer wished to use the RF signal <b>402</b> centered around Fs·0.375, there would be approximately 2 dB of attenuation at the center frequency of the RF signal <b>402</b>, meaning that approximately 20% of the signal power is lost due to the sin(x)/x response. Additionally, as is shown at <figref idref="DRAWINGS">FIG. 4</figref>, sin(x)/x roll-off across the bands of the RF signals <b>401</b> and <b>402</b> can be significant, which means that the RF designer likely must compensate for this (most likely by using digital techniques) to create a flatter response over frequency.

Additionally, the images from these two RF signals <b>401</b> and <b>402</b> create challenges to the RF system designer. <figref idref="DRAWINGS">FIG. 4</figref> shows the images <b>411</b> and <b>412</b> (in Nyquist Zone 2) of the RF signals <b>401</b> and <b>402</b> (in Nyquist Zone 1). Images <b>411</b> (centered at Fs·0.875) and <b>412</b> (centered at Fs·0.625) are both in Nyquist Zone 2. Image <b>411</b> is approximately 16 dB attenuated relative to frequency response of the RF signal <b>401</b>, and is furthermore spaced relatively far away. As a result, the required RF filter <b>270</b> (shown in <figref idref="DRAWINGS">FIG. 2</figref>) required to reject the image <b>411</b> is relatively straight forward to construct. However, to use such a system for an RF center frequency of 4 GHz would require a sample frequency Fs of 32 Gsps (Giga samples per second), which is a significant challenge in and of itself. For comparison, if the RF signal <b>402</b> were to have a center frequency of 4 GHz, the required Fs would be a comparatively modest 10.67 Gsps. However, the image <b>412</b>, is much closer to the RF signal <b>402</b> than the image <b>411</b> is to the RF signal <b>401</b>, and is also only approximately 4 dB lower than RF signal <b>402</b>. In general the larger an image is or the closer it is to the signal, the harder it is to filter out, which in turn requires a higher complexity (and cost) RF filter <b>270</b>, which means that there is a direct engineering tradeoff between DAC sample rate and RF filter cost.

<figref idref="DRAWINGS">FIG. 5</figref> shows an alternate approach, with RF signal <b>503</b> transmitted in Nyquist Zone 2 (centered at Fs·0.75) and its image <b>513</b> in Nyquist Zone 1 (centered at Fs·0.25). In this scenario, the image <b>513</b> is approximately 9 dB higher than the RF signal <b>503</b>, however the signal-to-image spacing is significantly greater than that of RF signal <b>402</b> to image <b>412</b> (<figref idref="DRAWINGS">FIG. 4</figref>), which simplifies the design of the RF filter <b>270</b>. For operation at 4 GHz, RF signal <b>503</b> requires a sample rate of only 5.33 Gsps, which is much lower than that required for either RF signals <b>401</b> or <b>402</b> of <figref idref="DRAWINGS">FIG. 4</figref>; however the DAC sin(x)/x response has attenuated the RF signal <b>503</b> by approximately 10 dB, meaning that approximately 90% of the signal power has been lost due to the DACs sin(x)/x response.

Another challenge that RF DACs pose for the RF system designer is again frequency planning. Like the two-clock frequency planning challenges of <figref idref="DRAWINGS">FIG. 1</figref>, the frequency planning challenges of a one-clock system, like <figref idref="DRAWINGS">FIG. 2</figref>, arise from the fixed-frequency BB clock SYSCLK. However unlike <figref idref="DRAWINGS">FIG. 1</figref>, where SYSCLK and LO are unrelated, in <figref idref="DRAWINGS">FIG. 2</figref> the DAC's Fs (sample frequency) is a multiple of SYSCLK which means that the system designer must choose an appropriate multiple in order to make the challenges from sin(x)/x and images manageable. For example, an RF band centered around 4 GHz with a SYSCLK of 122.88 MHz and a signal placement similar to RF signal <b>402</b> (<figref idref="DRAWINGS">FIG. 4</figref>) requires a sample frequency Fs approximately 10.67 Gsps, or approximately SYSCLK·83. A multiple of 83 is challenging to accomplish; it is more likely that the system designer will chose a power of 2 (i.e. 64 or 128) or (much less likely) a power of 2 multiplied by a 3 or by 5 (i.e. 80 or 96). The further the chosen multiple is away from the ideal multiple, the less ideal the resulting system is. If the multiple (and therefore Fs) is too low, the closer the RF signal will be to the frequency response notch at Fs/2, and in fact, in this scenario, a multiple of 64 will actually result in the signal band ending up in Nyquist Zone 2. If the multiple (and therefore Fs) is too high, the RF DAC must run at a higher frequency.

One approach to operating in the Nyquist zone 2 that has been used in several recent designs makes use of what is called “Mix Mode” or “RF Mode”. In this approach, the RF DAC is configured to produce an IF signal, and then the DAC inverts its output during the second half of every sample, usually using a slight variation on the Differential Quad Switching (DQS) technique. Referring now to <figref idref="DRAWINGS">FIG. 6</figref>, in one step this translates an IF signal <b>604</b> that was originally in Nyquist Zone 1 into an RF signal <b>604</b>A in Nyquist Zone 2 and an image <b>614</b>A of in Nyquist Zone 3, with only approximately 3 dB reduction in signal level due to sin(x)/x effects. While this technique is quite effective, it is only effective in Nyquist Zone 2 and the frequency spacing between RF signal <b>604</b>A and image <b>614</b>A must be considered (in Nyquist Zone 3) which reduces its utility somewhat.

Yet another shortcoming of RF DAC systems is the required DAC sample rate, Fs, and the resulting power that it dissipates. Simply put, the higher Fs is, the more complex the design of the RF DAC is and the more power it dissipates. Almost all RF DAC systems in use today are segmented CMOS current-mode designs, using arrays of matched current sources (each current source representing a DAC Least Significant Bit, or LSB) coupled to current steering structures (one per current source) that produce their outputs as differential currents. Most designs make use of Differential Quad Switching (DQS) approaches in order to minimize effects on the output caused by rise and fall mismatches. In CMOS logic, dynamic power increases linearly both with frequency and with the total capacitance being driven. The DQS structures are driven by arrays of digital latches, and delay mismatch between these latches appears as gain mismatch between individual LSB elements. In many modern RF DAC designs, LSB gain mismatch due to latch delay mismatches is the dominant source of mismatch, and in order to reduce this the devices that make up the latches are physically large, which increases the total capacitance being driven and therefore increases the power. As Fs increases, power increases, but additionally the required latch mismatch is reduced, so the devices are made even larger, with the end result that dynamic power in the latch array tends to increase at a higher rate than just with Fs. For a 4 GHz LO, this means that Fs=10.67 Gsps required for RF signal <b>402</b> (<figref idref="DRAWINGS">FIG. 4</figref>) will dissipate much less power than the Fs=32 Gsps required for RF signal <b>401</b> (<figref idref="DRAWINGS">FIG. 4</figref>), and Fs=5.67 Gsps required for RF signal <b>503</b> (<figref idref="DRAWINGS">FIG. 5</figref>) will dissipate even less. In fact, depending upon the technology the RF DAC is implemented in (Silicon CMOS, BiCMOS, or bipolar or exotic process such as SiGe, GaAs, or InP) and the minimum feature size (180 nm, 130 nm, 90 nm, 65 nm, 40 nm, 28 nm, 20 nm, or smaller) it may not even be possible to implement the chosen Fs without moving to a totally different architecture, which may increase power even more.

Taken together, the DAC sin(x)/x response, the DAC images, frequency planning, and power dissipation mean that the RF DAC transmit signal chain designer has a large design space to choose from, trading off RF DAC sample rate and architecture, RF filter complexity, and digital complexity all in order to achieve the required target specifications while overcoming all these challenges. If the RF system is intended to cover a wide range of LOs, as in a modern 4G system where LO's can potentially cover a continuous range approximately 400 MHz to 4 GHz, all the design space is much larger, because now the system must either be designed to accommodate the worst-case combination of conditions or the system must be reconfigured depending upon the LO frequency in order to remain efficient.

To date, available RF DAC solutions have not simultaneously provided a wide LO frequency range, high RF bandwidths, simple frequency planning, and high power efficiency.

Therefore, improvements in RF DACs are desirable.

SUMMARY

In a first aspect, the present disclosure provides a radio frequency digital-to-analog converter (DAC) system. The system comprises a first DAC to receive a first sample stream and to generate a first DAC output, a second DAC to receive a second sample stream and to generate a second DAC output; and a multiplexer unit to obtain the first DAC output and the second DAC output, the multiplexer unit to calculate a complementary output from the first DAC output to obtain a complementary first DAC output and a complementary output from the second DAC output to obtain a complementary second DAC output, the multiplexer to generate an interleaved output signal that contains a repeating sequence defined by: first DAC output, complementary second DAC output, complementary first DAC output, and second DAC output, the first DAC and the second DAC being clocked by a local oscillator, the repeating sequence spanning a single period of the local oscillator.

In a second aspect, the present disclosure provides a method of effecting digital-to-analog conversion. The method comprises: converting a first analog sample stream into a first output, the first output being a first digital output; generating a complementary output of the first output to obtain a first complementary output; converting a second analog sample stream into a second output, the second output being a second digital output; generating a complementary output of the second output to obtain a second complementary output; multiplexing the first output, the first complementary output, the second output, and the second complementary output to obtain an interleaved signal that contains a repeating sequence defined by: first output, second complementary output, first complementary output, and second output, a conversion of the first analog sample stream and of the second analog sample stream being effected in accordance with a local oscillator, the repeating sequence spanning a single period of the local oscillator.

Other aspects and features of the present disclosure will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments in conjunction with the accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present disclosure will now be described, by way of example only, with reference to the attached Figures.

<figref idref="DRAWINGS">FIG. 1</figref> shows a prior art RF Transmit Signal Chain.

<figref idref="DRAWINGS">FIG. 2</figref> shows a prior art Single-Clock RF DAC Transmit Signal Chain.

<figref idref="DRAWINGS">FIG. 3</figref> is a graph showing a prior art DAC sin(x)/x Frequency Response.

<figref idref="DRAWINGS">FIG. 4</figref> is a graph showing a prior art RF DAC Images from Nyquist Zone 1.

<figref idref="DRAWINGS">FIG. 5</figref> is a graph showing prior art RF DAC Images from Nyquist Zone 2.

<figref idref="DRAWINGS">FIG. 6</figref> is a graph showing a prior art Mix-Mode RF DAC Frequency Response and Images.

<figref idref="DRAWINGS">FIG. 7</figref> is a graph showing a prior art RF DAC ‘RFZ Mode’ Frequency Response.

<figref idref="DRAWINGS">FIG. 8</figref> shows a prior art 2-Way Interleaved DAC.

<figref idref="DRAWINGS">FIG. 9</figref> shows a prior art 2-Way Interleaved DAC Timing Diagram.

<figref idref="DRAWINGS">FIG. 10</figref> is a 2-Way Interleaved DAC system in accordance with an embodiment of the present disclosure.

<figref idref="DRAWINGS">FIG. 11</figref> shows a timing diagram for the DAC system of <figref idref="DRAWINGS">FIG. 10</figref>.

<figref idref="DRAWINGS">FIG. 12</figref> shows a prior art 4-Way Interleaved DAC.

<figref idref="DRAWINGS">FIG. 13</figref> shows a 4-Way Summed (Moving Average Filter) DAC system in accordance with another embodiment of the present disclosure.

<figref idref="DRAWINGS">FIG. 14</figref> is a 4-Tap and 2-Tap Moving Average Filter Responses in accordance with embodiments of the present disclosure.

<figref idref="DRAWINGS">FIG. 15</figref> shows an embodiment of a Programmable Summation DAC system in accordance with embodiments of the present disclosure.

<figref idref="DRAWINGS">FIG. 16A</figref> shows an RF DAC Analog Block Diagram in accordance with embodiments of the present disclosure.

<figref idref="DRAWINGS">FIG. 16B</figref> shows how a serial stream is divided into four parallel offset sub-streams.

<figref idref="DRAWINGS">FIG. 17</figref> shows an RF DAC Analog Transistor-Level Schematic in accordance with embodiments of the present disclosure.

<figref idref="DRAWINGS">FIG. 18</figref> shows an RF DAC Analog Timing Diagram in accordance with embodiments of the present disclosure.

<figref idref="DRAWINGS">FIG. 19</figref> shows a Two-Clock RF DAC Transmit Signal Chain in accordance with embodiments of the present disclosure.

<figref idref="DRAWINGS">FIG. 20</figref> is a flowchart of a method in accordance with embodiments of the present disclosure.

DETAILED DESCRIPTION

Generally, the present disclosure provides a method and system for Radio Frequency Digital-to-Analog Conversion. Embodiments of the RF DAC architecture of the present disclosure incorporate many individual elements, both analog and digital. Many of the elements are innovative, as is the combination of elements to produce the overall RF DAC.

The present disclosure provides an Interleaved Radio Frequency Digital-to-Analog Converter (RF DAC) suitable for use in cellular base stations and optimized to give both a wide RF tuning range and a wide RF bandwidth. The RF DAC uses two levels of interleaving, the first providing a direct conversion path from Base Band (BB) to RF, and the second providing a variable interleaving factor through the use of summation of DAC outputs to optimize the output bandwidth as a function of the RF center frequency. Digital Interpolation, including an arbitrary sample rate conversion filter, allows the DAC to operate from a wide range of possible BB sample rates; the RF DAC sample rate is a fixed ratio of the RF center frequency. As a result, the spurious outputs from the RF DAC are at known locations that are easy to filter out, minimizing the frequency planning tasks required for a complete n RF system design. In certain embodiments, the RF DAC of the present disclosure is frequency-agile, power efficient, and is capable of covering an LO frequency range from at least 400 MHz to 4 GHz, with a wide RF bandwidth that is at least 800 MHz at LO frequencies greater than 1 GHz.

The first element of RF DAC embodiments of the present disclosure is the sample rate. Similar to the “RF Mode” DAC from <figref idref="DRAWINGS">FIG. 6</figref> where successive output signals from an RF DAC are inverted, effectively multiplying a BB/IF signal by a repetitive “1, −1, 1, −1” signal to modulate from BB/IF to RF, there is a similar RF DAC mode, known as “RFZ” mode (Radio Frequency Return-to-Zero mode), where a real BB/IF signal, sampled at a sample frequency Fs₁, is effectively up-sampled to a sample frequency by Fs=Fs₁·4 by repeating samples and then multiplied by a repetitive “1, 0, −1, 0” signal. Overall, the RFZ DAC uses up-sampling to create multiple images of the real BB/IF, then uses a Finite Impulse Response discrete-time filter select the double-sided image entered around Fs·0.25 as the desired output. The frequency response of such an RFZ DAC is shown in <figref idref="DRAWINGS">FIG. 7</figref>, showing the modulated RF signal <b>705</b> (centered in the middle of Nyquist Zone 1, at Fs·0.25) and the image <b>715</b> (centered at Fs·0.75). The frequency response around signal <b>705</b> is quite flat, with approximately 7 dB of attenuation: 1 dB from sin(x)/x effects and 6 dB because the output is only active half the time because the RFZ DAC acts similar to a Return-to-Zero (RZ) DAC. The double-sided RF response is undesirable, but the flat frequency response and wide spacing from the signal to the image are both highly desirable. As a result of this, the RF DAC embodied in the present disclosure is constructed to operate with Fs=LO·4, which means for an LO that covers 400 MHz to 4 GHz, the RF DAC must cover a range of 1.6 Gsps to 16 Gsps.

The second element of the architecture of RF DAC embodiments of the present disclosure is that it is a 2-way interleaved DAC. Many of the highest-speed DAC designs are constructed in two parts: a number of lower-speed Sub-DACs and an extremely high-speed analog multiplexer to time-interleave the Sub-DAC outputs together. A 2-way interleaved DAC, shown in <figref idref="DRAWINGS">FIG. 8</figref>, consists of two Sub-DACs <b>840</b> and a multiplexer <b>860</b>. Each Sub-DAC operates at half the desired output sample rate, for example, 8 Gsps for each Sub-DAC for an effective output sample rate of 16 Gsps.

The timing diagram of such an interleaved DAC is shown in <figref idref="DRAWINGS">FIG. 9</figref>. The output from Sub-DAC #<b>0</b> transitions on the rising edge of the clock, while the output from Sub-DAC #<b>1</b> transitions on the falling edge of the clock. The multiplexer <b>860</b> output is selected synchronously by the clock, and is selected during the time that the input is stable. Because the output transitions depend only on the multiplexer control input, any uncertainty on the transition times at the Sub-DAC outputs are irrelevant, which removes a major source of quantization noise in non-interleaved DACs, and in turn allows the latches that drive the Sub-DAC current steering outputs to be sized largely without consideration for mismatch. Given that the intended output sample rate is 16 Gsps (or any other suitable value) and power is an important system consideration, reducing the latch size (and power) is a significant improvement.

One downside to the interleaved architecture when combined with a current steering structure is that the Sub-DACs must always be enabled, therefore the 2:1 multiplexer must always steer the current from the un-used Sub-DAC to a low-impedance “dump” node, which effectively wastes 50% of the static bias power in the DAC structure. However comparing this wasted static power to the dynamic power saved in the DAC latches by going to the interleaved architecture shows an overall net power savings.

The third element of the architecture of RF DAC embodiments of the present disclosure involves combining the first two elements to build a 2-way interleaved RF DAC, as is shown in <figref idref="DRAWINGS">FIG. 10</figref>. Sub-DACs <b>840</b> are now I and Q Sub-DACs <b>1040</b> (in-phase Sub-DAC and quadrature-phase Sub-DAC), and the 2:1 multiplexer <b>860</b> is now the 4:1 multiplexer <b>1060</b>, with the two additional inputs to the multiplexer being inverted versions of the two Sub-DAC outputs. In accordance with the present disclosure, a multiplexer unit is a functional block that receives the Sub-DAC's outputs, generates (or calculates) a complementary output of the Sub-DAC's outputs and generates an interleaved output signal that contains a repeating sequence using the Sub-DAC's outputs or their complementary outputs. The I and Q Sub-DACs produce a complex BB signal, so this RF DAC structure is capable of producing a single-sided output response, unlike the double-sided output response of an RFZ DAC.

The timing diagram of such a 2-Way Interleaved RF DAC is shown in <figref idref="DRAWINGS">FIG. 11</figref>. Similar to the 2-Way Interleaved DAC of <figref idref="DRAWINGS">FIG. 9</figref>, inputs are selected based on the DAC clock, minimizing the effects of any timing uncertainty at the Sub-DAC outputs. The DAC clock has a 50% duty cycle. On alternate cycles, either the Sub-DAC outputs or their negative versions (complementary outputs) are selected, with the end result that the I Sub-DAC (as seen at the output) is effectively a full-rate signal multiplied by the sequence “1, 0, −1, 0” while the Q Sub-DAC is similarly effectively a full-rate signal multiplied by the sequence “0, −1, 0, 1”. As a result, the complex BB signal at the output from the I and Q Sub-DACs is modulated up to the RF frequency Fs/4 directly with the full-rate output signals following the sequence “I, −Q, −I, Q”. With this particular switching sequence, the 4:1 interleaving multiplexer is effectively operating as an AQM. While the two Sub-DACs each operate similar to an RFZ DAC with 6 dB of attenuation due to their RZ nature, the interleaving operation results in the overall RF DAC appearing as a conventional Non-Return-to-Zero (NRZ) DAC, meaning that the 6 dB attenuation due of the RZ coding is removed, leaving only the 1 dB attenuation due to sin(x)/x effects. In order to avoid signal images, this circuit requires that I and Q sample streams be aligned so that the Q signal stream is effectively delayed by a time equal to a quarter of the LO period.

The fourth element to the architecture is to use a programmable summation based DAC to reduce the power required to build the I and Q Sub-DACs. Even with the reduction in power that comes from reducing the sample rate from the output sample rate of 16 Gsps to the Sub-DAC sample rate of 8 Gsps, building two 8 Gsps Sub-DACs is also power-prohibitive, so these Sub-DACs are also interleaved, this time 4 ways instead of 2 ways. A 4-way interleaved DAC is shown in <figref idref="DRAWINGS">FIG. 12</figref>. Similar to the 2-way interleaved DAC in <figref idref="DRAWINGS">FIG. 8</figref>, it consists of 4 Sub-DACs <b>1240</b> and a 4:1 multiplexer <b>1241</b>, and it operates in a similar way. This reduces the DAC Fs by a factor of 4, from 8 Gsps to 2 Gsps.

However this particular structure can be quite power inefficient if the RF DAC is implemented as a current steering structure. As with the 2-way interleaved structure, each Sub-DAC must always be active, meaning that the 4:1 multiplexer must steer the current from any un-used DAC to a low-impedance “dump” node, effectively wasting 75% of the power. However, because the RF DAC structure of <figref idref="DRAWINGS">FIG. 10</figref> requires that the I and Q Sub-DACs only produce low-frequency BB signals, another option, shown at <figref idref="DRAWINGS">FIG. 13</figref>, is used. In the structure of <figref idref="DRAWINGS">FIG. 13</figref>, the four Sub-DACs <b>1340</b> are summed together with a summation block <b>1341</b> rather than using a 4:1 multiplexer. A summation block can also be referred to as a summation device. This has two advantages: first, no static bias power is wasted and second, each of the Sub-DACs <b>1340</b> can be made one quarter the size of Sub-DACs <b>1240</b> saving yet more dynamic power.

This summation, however comes with downside: the summation of four Sub-DACs <b>1340</b> results in a 4-tap Moving-Average Filter (MAF, a Finite Impulse Response filter that produces the sum or average of a number of successive samples) response at the DAC output, <b>1401</b> in <figref idref="DRAWINGS">FIG. 14</figref>. It is important to note that Fs in this figure corresponds to Fs of the overall RF DAC, not the Fs of the I/Q Sub-DACs <b>1040</b> (<figref idref="DRAWINGS">FIG. 10</figref>) nor the Summed Sub-DACs <b>1340</b> (<figref idref="DRAWINGS">FIG. 13</figref>). This frequency response (which can also be referred to as a transfer function) can be corrected relatively easily by adding a simple fixed DSP equalizer to implement the inverse of the MAF response (an Inverse MAF or IMAF) in the digital circuits that precede the DAC. However, even with the IMAF the desire to cover wide RF bandwidths at low LO rates causes an issue. At LO=4 GHz and Fs=16 Gsps, we wish to have an RF bandwidth of at least 800 MHz, which corresponds to BB of 400 MHz, or Fs·0.05, which has an attenuation due to the MAF of less than 1 dB. However at LO=1 GHz and Fs=4 Gsps, we also wish to have an RF bandwidth of at least 800 MHz, which is again a BB of 400 MHz, or Fs·0.2. In this scenario, the attenuation at the band edge due to the 4-tap MAF is approximately 12 dB, which is prohibitive.

Alternatively, in this same scenario we can instead use a 2-tap MAF (a MAF that sums together two inputs), which has the response <b>1402</b> in <figref idref="DRAWINGS">FIG. 14</figref>, and the loss due to the 2-tap MAF response across the signal band is approximately 1 dB, which again can be readily compensated for with a similar IMAF filter. In order to select between the 4-tap and the 2-tap MAF, the structure in <figref idref="DRAWINGS">FIG. 15</figref> is used, which adds a set of digital multiplexers <b>1542</b> at the inputs to the Sub-DACs <b>1340</b> which allow the Sub-DACs to be driven in parallel at lower LO frequencies. The multiplexers <b>1542</b> that receive the I sample streams can be referred to as a switching unit and the multiplexers <b>1542</b> that receive the Q sample streams can be referred to as another switching unit.

For LO frequencies of 2-4 GHz, the four Sub-DACs are driven independently at sample rates of 1-2 Gsps and act as a 4-tap MAF. For LO frequencies of 1-2 GHz, the four Sub-DACs are driven in pairs at 1-2 Gsps, with Sub-DACs #<b>3</b> and #<b>2</b> driven together and Sub-DACs #<b>1</b> and #<b>0</b> driven together. This effectively results in there being two Sub-DACs, each double the size (with an additional bit of resolution) compared to the 2-4 GHz case, and there being a 2-tap MAF at the output. This can be continued at LO frequencies less than 1 GHz where all four Sub-DACs <b>1340</b> can be driven together, acting as a single large DAC (with two additional bits of resolution) without the MAF response. As will be clear to one skilled in the art, this technique is not limited to use with four Sub-DACs; for example it is possible to drive six Sub-DAC's as either six individual Sub-DAC's with a 6-tap MAF response, three pairs with a 3-tap MAF response, two groups of three with a 2-tap MAF response, or a single large group of six.

Combining the structure of <figref idref="DRAWINGS">FIG. 10</figref> with the structure of <figref idref="DRAWINGS">FIG. 15</figref> produces the analog block diagram of the complete RF DAC shown in <figref idref="DRAWINGS">FIG. 16A</figref>. The I/Q Sub-DACs <b>1040</b> are constructed of the input multiplexers <b>1542</b>, the eight Sub-DACs <b>1340</b>, and the summation blocks <b>1341</b>. The summed outputs are combined by the 4:1 multiplexer <b>1060</b> to produce the final output. The output operates at a maximum sample rate of 16 Gsps, and each of the 8 Sub-DACs <b>1340</b> operates at a maximum sample rate of 2 Gsps. Depending upon the output sample rate and the required RF bandwidth, the 8 Sub-DACs <b>1340</b> are updated as 8 individual DACs, 4 pairs, or 2 quads.

Each sub-stream input into each I Sub-DAC and each Q Sub-DAC stems from a respective I sample stream and a Q sample stream. <figref idref="DRAWINGS">FIG. 16B</figref> shows an example of an initial serial I or Q sample stream <b>500</b>. This serial stream <b>500</b> is split into four parallel sub-streams streams <b>502</b> running at a lower sample rate, then each of the parallel sub-streams <b>502</b> is delayed by a different amount of time so that one sub-stream transitions every time the original serial stream transitioned. This produces four sub-streams <b>504</b> that are input into respective Sub-DACs. For applications where the four Sub-DACs are operating in two pairs, the initial serial I or Q data stream <b>500</b> is divided into two parallel offset sub-streams, and for applications where the four Sub-DACs are operating as a single larger DAC, the original serial I or Q data stream is used directly. As shown in <figref idref="DRAWINGS">FIG. 16B</figref>, the initial sample stream <b>500</b> is representable as sub-streams <b>504</b> that are interleaved with each other.

An example of a practical transistor-level implementation of the analog portions (<b>1340</b>, <b>1341</b>, and <b>1060</b>) is shown in <figref idref="DRAWINGS">FIG. 17</figref>. This is an all-NMOS design, implemented using current steering techniques throughout. The I/Q Sub-DACs <b>1340</b> are shown as the DQS structures <b>1740</b>. The detailed implementation of the DQS structures <b>1740</b> and the circuitry required to drive them is well known to those skilled in the art. Because the outputs from <b>1740</b> are current-mode, summation <b>1341</b> of <figref idref="DRAWINGS">FIG. 13</figref> is performed simply by wiring the outputs in parallel, which is shown as functional block <b>1741</b> in <figref idref="DRAWINGS">FIG. 17</figref>. The 4:1 multiplexer <b>1060</b> is shown as the array of 16 NMOS transistors <b>1760</b>, which steer the currents between the differential analog outputs OUTP/OUTN and the low-impedance DUMP node.

The timing diagram for this circuit is shown in <figref idref="DRAWINGS">FIG. 18</figref>. The 4:1 multiplexer inputs LO[3:0] are a set of four 25% duty cycle clocks that successively connect the I or Q Sub-DACs to OUTP/OUTN or to DUMP.

In addition to the analog portions, the RF DAC requires a significant amount of digital support circuitry. A high-level block diagram showing the complete RF DAC transmit signal chain is shown in <figref idref="DRAWINGS">FIG. 19</figref>.

Comparing <figref idref="DRAWINGS">FIG. 19</figref> to <figref idref="DRAWINGS">FIG. 1</figref> and <figref idref="DRAWINGS">FIG. 2</figref>, the design of <figref idref="DRAWINGS">FIG. 19</figref> has the same digital interface <b>100</b>. The interpolator <b>1910</b> and DQM <b>1920</b> are similar in functionality to that of <b>110</b> and <b>120</b>, only needing to address IF modulation rather than RF modulation as in <b>210</b> and <b>220</b>. An additional interpolator <b>1930</b> of <figref idref="DRAWINGS">FIG. 19</figref> is an arbitrary interpolator, allowing sample rate conversion between the two clocks, SYSCLK and LO. An additional digital delay element <b>1931</b> is inserted in one of the two paths in order to align samples to the interleaved DAC and avoid images, and the IMAF blocks <b>1932</b> are used to compensate for the MAF response of the I/Q Sub-DACs. The RF DAC <b>1940</b> is the 2-way interleaved RFZ structure of <figref idref="DRAWINGS">FIG. 16A</figref> and <figref idref="DRAWINGS">FIG. 17</figref>. The output from the DAC is filtered by the RF Filter <b>1970</b> before amplification by the PA <b>180</b> for transmission over the antenna <b>190</b>.

As with <figref idref="DRAWINGS">FIG. 1</figref> and <figref idref="DRAWINGS">FIG. 2</figref>, the individual blocks are shown as if they are driven either by SYSCLK or by LO, where in reality they will likely be driven by clocks that are related to these clocks by integer factors, and these factors are application-dependent.

The arbitrary interpolation block <b>1930</b> is a flexible complex DSP engine, implementing a continuously-variable fractional delay filter. The implementation details of this block are, of necessity, well beyond the scope of this document, but it is important to note that its inclusion allows a great deal of flexibility, allowing digital control of delay and phase through the system, allowing synchronization of multiple RF DACs for Multi-Input/Multi-Output (MIMO) applications, and also allowing active compensation of I/Q delay mismatch within the RF DAC, mismatch that would result in interleaving distortion (similar to IQI and LOFT) at the output. In practice, the additional delay element <b>1931</b> can also be merged into <b>1930</b> as an additive delay applied to one of the paths.

Not shown, but likely to be included in a complete system, are additional digital blocks for adjusting I/Q gain and offset and a filter to compensate for the residual DAC sin(x)/x response. Because this RF DAC naturally operates with a sample rate Fs=LO·4, the sin(x)/x correction is comparatively minor, needing to correct only for approximately 1 dB of flatness compared to 10 dB or more that would be required for alternative RF DAC architectures that run with lower sample rates.

<figref idref="DRAWINGS">FIG. 20</figref> shows a flowchart of a method of converting an analog signal into a digital signal, in accordance with certain embodiments of the present disclosure. At action <b>2000</b>, a first analog sample stream is converted into a first output, which is digital. The first analog sample stream can be an in-phase sample stream or a quadrature-phase stream obtained from an initial analog signal. At action <b>2002</b>, a complementary output of the first output is generated.

At action <b>2004</b>, a second analog sample stream is converted into a second output, which is digital. The second analog sample stream will be an in-phase sample stream when the first analog stream is a quadrature-phase sample stream and vice-versa. At action <b>2006</b>, a complementary output of the second output is generated.

At action <b>2008</b>, the first output, the first complementary output, the second output, and the second complementary output are multiplexed to obtain an interleaved signal that contains a repeating sequence defined by: first output, second complementary output, first complementary output, and second output. At actions <b>2000</b> and <b>2004</b>, the conversion of the first analog sample stream and of the second analog sample stream is effected in accordance with a local oscillator and, the repeating sequence spans a single period of the local oscillator.

In the preceding description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the embodiments. However, it will be apparent to one skilled in the art that these specific details are not required. In other instances, well-known electrical structures and circuits are shown in block diagram form in order not to obscure the understanding. For example, specific details are not provided as to whether the embodiments described herein are implemented as a software routine, hardware circuit, firmware, or a combination thereof.

Embodiments of the disclosure or portions of such embodiments can be represented as a computer program product stored in a machine-readable medium (also referred to as a computer-readable medium, a processor-readable medium, or a computer usable medium having a computer-readable program code embodied therein). The machine-readable medium can be any suitable tangible, non-transitory medium, including magnetic, optical, or electrical storage medium including a diskette, compact disk read only memory (CD-ROM), memory device (volatile or non-volatile), or similar storage mechanism. The machine-readable medium can contain various sets of instructions, code sequences, configuration information, or other data, which, when executed, cause a processor to perform steps in a method according to an embodiment of the disclosure. Those of ordinary skill in the art will appreciate that other instructions and operations necessary to implement the described implementations can also be stored on the machine-readable medium. The instructions stored on the machine-readable medium can be executed by a processor or other suitable processing device, and can interface with circuitry to perform the described tasks.

The above-described embodiments are intended to be examples only. Alterations, modifications and variations can be effected to the particular embodiments by those of skill in the art. The scope of the claims should not be limited by the particular embodiments set forth herein, but should be construed in a manner consistent with the specification as a whole.