US9898564B2

SSTA with non-gaussian variation to second order for multi-phase sequential circuit with interconnect effect

Summary by NHIP

Second-order SSTA for multi-phase circuits

The method performs statistical static timing analysis on integrated circuits with multi-phase sequential elements and interconnects. It employs forward breadth-first search followed by backward depth-first traversal to identify critical paths while accounting for non-Gaussian variations up to quadratic order and cross-talk effects.

Claim Score by NHIP

Read claim 1, the broadest

Abstract

In the present invention the issue of SSTA in multi-phase sequential circuit with cross-talk in consideration of non-uniform timing constraint and process variations up to the 2nd order is proposed. Use forward breadth first search to calculate the accumulated probabilities at each node for clock phases and edge probability with respect to input and output clock phases, followed by backward depth first traversal to find all critical paths with their probabilities greater than user specified threshold. A method is proposed to pre-characterize the timing library including second order variations. For cross-talk, the poles and residues of admittance matrix and voltage transfer are carried out to 2nd order variations. Effective capacitances and waveforms at interconnect input or driver's immediate output are calculated to 2nd order variations. Delays at victim outputs are then calculated to 2nd order variations and fed back to SSTA, the probability of path occurrence can be calculated accurately.

US9898564B2, drawing sheet 1
Sheet 1 of 819

Term

8.6 yearsleft in the term

Expires 12 May 2035, including 125 days of term adjustment.

  1. Priority
  2. Filed
  3. Granted
  4. Today
  5. Expires

13 claims: 1 independent, 12 dependent

  1. 1
    Broadest claimClaim Score 40, average(NHIP)A computer-implemented method for performing SSTA of an integrated circuit with multi-phase sequential elements with interconnect, comprising the computer-implemented steps of:accepting said integrated circuit connectivity into SSTA;and using path analysis including both forward bread first search and backward depth first traversal considering constraint with multi-phase sequential elements to generate critical paths in terms of probability of path occurrence considering non-Gaussian variation up to quadratic order;and identifying the said critical paths based on the user-defined threshold in terms of probability of path occurrence for more accurate design for manufacturing;and considering gate and interconnect delays with non-Gaussian variation up to quadratic order in the said path analysis;and handling cross-talk issue with non-Gaussian variation up to quadratic order in the said path analysis;and characterizing cells with non-Gaussian variation up to quadratic order.