Planar cavity MEMS and related structures, methods of manufacture and design structures
Summary by NHIP
Planar Cavity MEMS Formation
The method forms a Micro-Electro-Mechanical System by creating discrete wire structures, sacrificial silicon layers, and an electrode on an insulator. Simultaneous venting uses a XeF2 etchant through a hole sealed with dielectric and nitride cap materials to define cavities.
Claim Score by NHIP
Abstract
A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a beam structure and an electrode on an insulator layer, remote from the beam structure. The method further includes forming at least one sacrificial layer over the beam structure, and remote from the electrode. The method further includes forming a lid structure over the at least one sacrificial layer and the electrode. The method further includes providing simultaneously a vent hole through the lid structure to expose the sacrificial layer and to form a partial via over the electrode. The method further includes venting the sacrificial layer to form a cavity. The method further includes sealing the vent hole with material. The method further includes forming a final via in the lid structure to the electrode, through the partial via.
Term
Projected expiry 23 December 2030.
- Priority
- Filed
- Granted
- Today
- Projected expiry
14 claims: 3 independent, 11 dependent
- 1A method of forming at least one Micro-Electro-Mechanical System (MEMS), comprising:forming a first sacrificial layer over discrete wires;forming a beam over the first sacrificial layer;forming an insulator layer on the first sacrificial layer;forming a cavity via in the insulator layer, exposing a portion of the first sacrificial layer;forming an electrode on the insulator layer;forming a second sacrificial layer over the beam and in the cavity via;forming a lid material over the second sacrificial layer and the electrode;providing simultaneously a vent hole in the lid material to expose at least the second sacrificial layer and to form a partial via over the electrode;venting the first sacrificial layer and the second sacrificial layer to form at least a lower cavity and an upper cavity, respectively;sealing the vent hole with a dielectric material and a nitride cap;forming a polyimide material on the nitride cap;and forming a final via through the lid material by etching the lid through the partial via, to the electrode, wherein the partial via is formed at a same time as the vent hole, and after venting the first sacrificial layer and the second sacrificial layer, the vent hole is sealed with the dielectric material and the nitride cap, the first sacrificial layer and the second sacrificial layer are silicon material vented using a XeF 2 etchant through the vent hole, and the dielectric material, the nitride cap, and the polyimide material are formed in the partial via.
- 2A method of forming at least one Micro-Electro-Mechanical System (MEMS), comprising:forming a first sacrificial layer over discrete wires;forming a beam over the first sacrificial layer;forming an insulator layer on the first sacrificial layer;forming a cavity via in the insulator layer, exposing a portion of the first sacrificial layer;forming an electrode on the insulator layer;forming a second sacrificial layer over the beam and in the cavity via;forming a lid material over the second sacrificial layer and the electrode;providing simultaneously a vent hole in the lid material to expose at least the second sacrificial layer and to form a partial via over the electrode;venting the first sacrificial layer and the second sacrificial layer to form at least a lower cavity and an upper cavity, respectively;sealing the vent hole with a dielectric material and a nitride cap;forming a polyimide material on the nitride cap;and forming a final via through the lid material by etching the lid through the partial via, to the electrode, wherein the partial via is formed at a same time as the vent hole, and after venting the first sacrificial layer and the second sacrificial layer, the vent hole is sealed with the dielectric material and the nitride cap, and the dielectric material, the nitride cap, and the polymide material are formed in the partial via.
- 8Broadest claimClaim Score 51, average(NHIP)A method of forming at least one Micro-Electro-Mechanical System (MEMS), comprising:forming a first sacrificial layer over discrete wires;forming a beam over the first sacrificial layer;forming an insulator layer on the first sacrificial layer;forming a cavity via in the insulator layer, exposing a portion of the first sacrificial layer;forming an electrode on the insulator layer;forming a second sacrificial layer over the beam and in the cavity via;forming a lid material over the second sacrificial layer and the electrode;providing simultaneously a vent hole in the lid material to expose at least the second sacrificial layer and to form a partial via over the electrode;venting the first sacrificial layer and the second sacrificial layer to form at least a lower cavity and an upper cavity, respectively;sealing the vent hole with material, the material comprises dielectric material and a nitride cap;forming a polyimide material on the nitride cap;forming a final via through the lid material by etching the lid through the partial via, to the electrode;and etching the partial via to form the final via to expose an underlying electrode, wherein the dielectric material, the nitride cap, and the polyimide material are formed in the partial via.
Independent claims3
116 paragraphs in 5 sections, as filed
CROSS REFERENCE TO RELATED APPLICATIONS
Field of the Invention
0001The invention relates to semiconductor structures and methods of manufacture and, more particularly, to planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures.
BACKGROUND
0002Integrated circuit switches used in integrated circuits can be formed from solid state structures (e.g., transistors) or passive wires (MEMS). MEMS switches are typically employed because of their almost ideal isolation, which is a critical requirement for wireless radio applications where they are used for mode switching of power amplifiers (PAs) and their low insertion loss (i.e., resistance) at frequencies of 10 GHz and higher. MEMS switches can be used in a variety of applications, primarily analog and mixed signal applications. One such example is cellular telephone chips containing a power amplifier (PA) and circuitry tuned for each broadcast mode. Integrated switches on the chip would connect the PA to the appropriate circuitry so that one PA per mode is not required.
0003Depending on the particular application and engineering criteria, MEMS structures can come in many different forms. For example, MEMS can be realized in the form of a cantilever beam structure. In the cantilever structure, a cantilever arm (suspended electrode with one end fixed) is pulled toward a fixed electrode by application of an actuation voltage. The voltage required to pull the suspended electrode to the fixed electrode by electrostatic force is called pull-in voltage, which is dependent on several parameters including the length of the suspended electrode, spacing or gap between the suspended and fixed electrodes, and spring constant of the suspended electrode, which is a function of the materials and their thickness. Alternatively, the MEMS beam could be a bridge structure, where both ends are fixed.
0004MEMS can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form small structures with dimensions in the micrometer scale with switch dimensions of approximately 5 microns thick, 100 microns wide, and 200 microns long. Also, many of the methodologies, i.e., technologies, employed to manufacture MEMS have been adopted from integrated circuit (IC) technology. For example, almost all MEMS are built on wafers and are realized in thin films of materials patterned by photolithographic processes on the top of the wafer. In particular, the fabrication of MEMS uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask.
0005For example, in MEMS cantilever type switches the fixed electrodes and suspended electrode are typically manufactured using a series of conventional photolithographic, etching and deposition processes. In one example, after the suspended electrode is formed, a layer of sacrificial material, e.g., the spin-on polymer PMGI made by Microchem, Inc., is deposited under the MEMS structure, to form a cavity, and over the MEMS structure to form a cavity. The cavity over the MEM is used to support the formation of a cap, e.g., SiN dome, to seal the MEMS structure. However, this poses several shortcomings. For example, it is known that MEMS cavities formed with spin-on polymers such as PMGI, are non-planar. Non-planar MEMS cavities, though, introduce issues including, for example, lithographic depth of focus variability and packaging reliability due to dielectric cracking. In addition, MEMS cavities formed with spin-on polymers require processing at low temperatures, to avoid reflowing or damaging the polymer; and the polymer can leave organic (i.e., carbon containing) residues in the cavity post venting.
0006Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.
SUMMARY
0007In a first aspect of the invention, a method of forming at least one Micro-Electro-Mechanical System (MEMS) comprises forming a beam structure and an electrode on an insulator layer, remote from the beam structure. The method further comprises forming at least one sacrificial layer over the beam structure, and remote from the electrode. The method further comprises forming a lid structure over the at least one sacrificial layer and the electrode. The method further comprises providing simultaneously a vent hole through the lid structure to expose the sacrificial layer and to form a partial via over the electrode. The method further comprises venting the sacrificial layer to form a cavity. The method further comprises sealing the vent hole with material. The method further comprises forming a final via in the lid structure to the electrode, through the partial via.
0008In another aspect of the invention, a method of forming at least one Micro-Electro-Mechanical System (MEMS) comprises forming a first sacrificial layer on discrete wires. The method further comprises forming a beam on the first sacrificial layer. The method further comprises forming an insulator layer on the first sacrificial layer. The method further comprises forming a cavity via in the insulator layer, exposing a portion of the first sacrificial layer. The method further comprises forming an electrode on the insulator layer. The method further comprises forming a second sacrificial layer over the beam and in the cavity via. The method further comprises forming a lid material over the second sacrificial layer and the electrode. The method further comprises providing simultaneously a vent hole to expose at least the second sacrificial layer and to form a partial via over the electrode. The method further comprises venting the first sacrificial layer and the second sacrificial layer to form at least a lower cavity and an upper cavity, respectively. The method further comprises sealing the vent hole with material. The method further comprises forming a final via through the lid material by etching the lid through the partial via, to the electrode.
0009In another aspect of the invention, a structure comprises a first cavity structure with discrete wires and a beam structure. The structure further comprises an insulator layer at least partially surrounding the first cavity. The structure further comprises an electrode on the insulator layer. The structure further comprises a second cavity formed over the beam structure and surrounded by a lid material, which also covers the electrode. The structure further comprises sealed vent holes in the lid material, that opened to at least the second cavity. The structure further comprises a final via formed within the lid material and which extends to the electrode, the final via having an upper cross section larger than a lower cross section. The electrode is remote from the first cavity and the second cavity.
0010In another aspect of the invention, a design structure tangibly embodied in a machine readable storage medium for designing, manufacturing, or testing an integrated circuit is provided. The design structure comprises the structures of the present invention. In further embodiments, a hardware description language (HDL) design structure encoded on a machine-readable data storage medium comprises elements that when processed in a computer-aided design system generates a machine-executable representation of the MEMS, which comprises the structures of the present invention. In still further embodiments, a method in a computer-aided design system is provided for generating a functional design model of the MEMS. The method comprises generating a functional representation of the structural elements of the MEMS.
0011In particular aspects, the method in a computer-aided design system for generating a functional design model of a MEMS, comprises: generating a functional representation of a beam structure; generating a functional representation of an electrode on an insulator layer, remote from the beam structure; generating a functional representation of at least one sacrificial layer over the beam structure, and remote from the electrode; generating a functional representation of a lid structure over the at least one sacrificial layer and the electrode; generating a functional representation of simultaneously providing a vent hole through the lid structure to expose the sacrificial layer and to form a partial via over the electrode; generating a functional representation of venting the sacrificial layer to form a cavity; generating a functional representation of sealing the vent hole with material; and generating a functional representation of forming a final via in the lid structure to the electrode, through the partial via.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
0012The present invention is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention.
0013<figref idref="DRAWINGS">FIGS. 1-23C and 26A-33</figref> show various structures and related processing steps in accordance with the invention;
0014<figref idref="DRAWINGS">FIGS. 24A-24F</figref> show top structural views of MEMS devices fabricated using the processes shown in accordance with aspects of the invention;
0015<figref idref="DRAWINGS">FIG. 25</figref> shows several topography graphs (i.e., atomic force microscopy data) showing data for silicon divot depth vs. oxide polish;
0016<figref idref="DRAWINGS">FIG. 34</figref> is a flow diagram of a design process used in semiconductor design, manufacture, and/or test; and
0017<figref idref="DRAWINGS">FIG. 35A</figref> shows a structure and process which reduces or eliminates an oxide seam in deposited silicon due to incoming topography, in accordance with aspects of the invention (compared to <figref idref="DRAWINGS">FIG. 35B</figref> which shows the oxide seam).
DETAILED DESCRIPTION
0018The invention relates to semiconductor structures and methods of manufacture and, more particularly, to planar cavity (e.g., flat or planar surfaces) Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure. Advantageously, the methods of forming the structures reduce overall stress on the MEMS structure, as well as reduce material variability of the MEMS device. In embodiments, the structures and methods of forming the planar (e.g., flat or planar surfaces) MEMS devices use a sacrificial layer to form a cavity adjacent to the MEMS beams. In further embodiments, a two level MEMS cavity is formed using a reverse damascene process to form a planar (e.g., flat or planar surface) structure. The MEMS structures of the present invention can be used, for example, as a single or dual wire beam contact switch, dual wire beam capacitor switch, or single dual wire beam air gap inductor, amongst other devices.
0019<figref idref="DRAWINGS">FIG. 1</figref> shows a beginning structure and related processing steps in accordance with aspects of the invention. The structure disclosed in the next several set of paragraphs is a MEMS capacitor switch, although the methods and structures are also applicable to other MEMS switches, such as ohmic contact switches, which would not use a MEMS capacitor dielectric; MEMS accelerometers; etc. The structure includes, for example, a substrate <b>10</b>. The substrate <b>10</b>, in embodiments, can be any layer of a device. In embodiments, the substrate <b>10</b> is a silicon wafer coated with silicon dioxide or other insulator material known to those of skill in the art. An interconnect <b>12</b> is provided within the substrate <b>10</b>. The interconnect <b>12</b> can be, for example, a tungsten or copper stud formed in a conventionally formed via. For example, the interconnect <b>12</b> can be formed using any conventional lithographic, etching and deposition process, known to those of skill in the art for forming studs, such as damascene. The interconnect <b>12</b> could contact other wiring levels, CMOS transistors or other active devices, passive devices, etc. as known in the art.
0020In <figref idref="DRAWINGS">FIG. 2</figref>, a wiring layer is formed on the substrate <b>10</b> to form multiple wires <b>14</b> using conventional deposition and patterning processes. For example, the wiring layer can be deposited on the substrate to a depth of about 0.05 to 4 microns; although other dimensions are also contemplated by the present invention. In embodiments, the wiring layer <b>14</b> is deposited to a depth of 0.25 microns. Thereafter, the wiring layer is patterned to form the wires (lower electrodes) <b>14</b> having a wire spacing (gap) <b>14</b><i>a </i>therebetween. In embodiments, the wire space aspect ratio, which is determined by the ratio of the height of the wire <b>14</b> to the wire spacing <b>14</b><i>a</i>, may affect material variability, (e.g., topography) as discussed in more detail with reference to <figref idref="DRAWINGS">FIG. 25</figref>. For example, a low aspect ratio of 1:20 could be formed from a 50 nm tall wire <b>14</b> with a 1000 nm space <b>14</b><i>a</i>; and a high aspect ratio of 1:1 could be formed from a 500 nm tall wire with a 500 nm space. These aspect ratio values are for reference only and, as will be discussed herein, the conformality of a sacrificial film <b>18</b> (<figref idref="DRAWINGS">FIG. 3</figref>) determines what wire space aspect ratio is required.
0021At least one of the wires <b>14</b> is in contact (direct electrical contact) with the interconnect <b>12</b>. In embodiments, the wires <b>14</b> can be formed from aluminum or an aluminum alloy such as AlCu, AlSi, or AlCuSi; although other wiring materials are also contemplated by the present invention. For example, the wires <b>14</b> can be a refractory metal such as Ti, TiN, TiN, Ta, TaN, and W, or AlCu, amongst other wiring materials. In embodiments, the wires <b>14</b> can be doped with Si, e.g., 1%, to prevent the metal, e.g., Al, from reacting with an upper cavity layer material, e.g., silicon. In embodiments the aluminum portion of the wire can be doped with Cu, e.g. 0.5%, to increase the electromigration resistance of the wire. In embodiments, the wires could be formed from pure refractory metals, such as TiN, W, Ta, etc.
0022The surface morphology of wire <b>14</b> is determined by the atomic surface roughness as well as the presence of metal hillocks. Metal hillocks are bumps in the metal, typically about 10 nm-1000 nm wide and 10 nm-1000 nm tall. For aluminum wiring cladded in TiN below and above, for example 200 nm AlCu cladded with 10/20 nm Ti/TiN below and 30 nm TiN above, a typical metal hillock could be 50 nm wide and 100 nm tall. For MEMS capacitors, where the wire <b>14</b> is coated with dielectric and is used as the lower capacitor plate, the presence of hillocks or a high value of atomic surface roughness decreases the capacitance density because the upper capacitor plate, which is formed from the MEMS beam, cannot closely contact the lower capacitor plate, which is formed from wire <b>14</b>.
0023Surface roughness can be measured using an atomic force microscope (AFM) or an optical profiler, and several known methods exist for measuring and quantifying the width and height of hillocks. In embodiments, hillocks are quantified by measuring the minimum to maximum height using an AFM of wire areas typically ranging from 1 to 10,000 square microns, and the surface roughness by calculating the root mean square (RMS) roughness in areas with or without hillocks. In one embodiment, surface roughness is the RMS roughness of a 2 μm<sup>2 </sup>area without visible hillocks.
0024Table 1 summarizes metal hillock and surface roughness data for a variety of wire materials measured using an AFM. The root mean square (RMS) roughness was measured in areas without visible metal hillocks in an approximate 2 μm<sup>2 </sup>area. The maximum peak-to-valley hillock value was measured in an approximate 10,000 m<sup>2 </sup>area. The purely refractory metal wire options had by far the lowest roughness and hillocks but the highest resistance. Wires with AlCu have much lower resistance but much higher roughness and hillocks than purely refractory metal wires. Adding sufficient Ti under and over the AlCu and annealing the wafers at 350° C. to 450° C. for sufficient time to form the TiAl<sub>3 </sub>silicide, i.e., 400° C. for 1 hour, either before or after patterning, dramatically reduces the hillock minimum to maximum height while slightly increasing the RMS surface roughness, due to reduced aluminum volume. In exemplary embodiments, the wires <b>14</b> are annealed after patterning and etched to reduce TiAl<sub>3</sub>-induced metal etch problems. Thinner Ti, e.g., 5 nm under and over the AlCu, had minimal or no effect on hillock reduction; whereas, 10 nm and 15 nm of Ti dramatically reduced the hillocks and were equivalent. When the Ti reacts with aluminum to form TiAl<sub>3</sub>, the aluminum (e.g., AlCu) thickness is reduced in approximately a 3:1 fashion; i.e., for each 10 nm of Ti, 30 nm of aluminum is consumed to form TiAl<sub>3</sub>; and, to always leave some unreacted AlCu in the wire, the Ti:AlCu thickness ratio, where the Ti thickness comprises the layers under and over the AlCu, needs to be less than 1:3. This means that, for optimal hillock reduction and wire resistance taking into account the Ti and AlCu as deposited thickness variability, the as-deposited Ti thickness range should be greater than 5% and less than 25% of the as-deposited AlCu thickness.
0025<tables id="TABLE-US-00001" num="00001"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="6"><colspec colname="1" colwidth="49pt" align="left" /><colspec colname="2" colwidth="35pt" align="center" /><colspec colname="3" colwidth="35pt" align="center" /><colspec colname="4" colwidth="28pt" align="center" /><colspec colname="5" colwidth="35pt" align="center" /><colspec colname="6" colwidth="35pt" align="center" /><thead><row><entry namest="1" nameend="6" rowsep="1">TABLE 1</entry></row><row><entry namest="1" nameend="6" align="center" rowsep="1" /></row><row><entry /><entry>AlCu</entry><entry /><entry /><entry>Maximum</entry><entry /></row><row><entry>Process</entry><entry>Ta/TiN or</entry><entry /><entry>RMS</entry><entry>Peak-</entry></row><row><entry>(TiN = 32</entry><entry>Ta</entry><entry>Lower and</entry><entry>rough-</entry><entry>Valley</entry></row><row><entry>nm for</entry><entry>thickness</entry><entry>upper Ti</entry><entry>ness</entry><entry>hillock</entry><entry>Resistance</entry></row><row><entry>each layer)</entry><entry>(nm)</entry><entry>thickness</entry><entry>(nm)</entry><entry>(nm)</entry><entry>(Ω/SQ)</entry></row><row><entry namest="1" nameend="6" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="6"><colspec colname="1" colwidth="49pt" align="left" /><colspec colname="2" colwidth="35pt" align="center" /><colspec colname="3" colwidth="35pt" align="center" /><colspec colname="4" colwidth="28pt" align="center" /><colspec colname="5" colwidth="35pt" align="char" char="." /><colspec colname="6" colwidth="35pt" align="char" char="." /><tbody valign="top"><row><entry>TiN/AlCu/TiN</entry><entry>200</entry><entry>NA</entry><entry>4.6</entry><entry>148</entry><entry>0.18</entry></row><row><entry>Ti/AlCu/Ti/TiN</entry><entry>200</entry><entry> 5</entry><entry>6.8</entry><entry>119</entry><entry>0.24</entry></row><row><entry>Ti/AlCu/Ti/TiN</entry><entry>200</entry><entry>10</entry><entry>6.4</entry><entry>43</entry><entry>0.32</entry></row><row><entry>Ti/AlCu/Ti/TiN</entry><entry>200</entry><entry>15</entry><entry>6.2</entry><entry>46</entry><entry>0.42</entry></row><row><entry>TiN</entry><entry> 32</entry><entry>NA</entry><entry>2.3</entry><entry>27</entry><entry>100</entry></row><row><entry>Ta/TiN</entry><entry>200/32</entry><entry>NA</entry><entry>2.4</entry><entry>29</entry><entry>2</entry></row><row><entry namest="1" nameend="6" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>
0026Metal hillock formation can also be induced by the layout of the wires. For example, a solid layout (<figref idref="DRAWINGS">FIG. 26A</figref>) will tend to have both a greater number of metal hillocks and taller hillocks, than a layout broken up into narrow lines using slots ‘S’ (<figref idref="DRAWINGS">FIGS. 26B and 26C</figref>) or holes ‘H’ (<figref idref="DRAWINGS">FIG. 26D</figref>).
0027More specifically, <figref idref="DRAWINGS">FIGS. 26A-26D</figref> show top view layouts of the MEMS capacitor plates with solid (<figref idref="DRAWINGS">FIG. 26A</figref>), slotted “S” (<figref idref="DRAWINGS">FIGS. 26B and 26C</figref>), and holed “H” (<figref idref="DRAWINGS">FIG. 26D</figref>) layouts. The holed (<figref idref="DRAWINGS">FIG. 26D</figref>) layout “H” could use diamonds (shown), octagons, circles, ovals, squares, plus-shaped, or any shapes cut out from the layout all represented by reference “H”. The slotted and holed layouts are designed both to minimize hillock formation and to not significantly increase the effective wire resistance or decrease the capacitor plate area, due to the removal of the metal. If a slotted layout “S” is used (<figref idref="DRAWINGS">FIG. 26B</figref>) then the slot width is typically minimized so as to not decrease the capacitor plate area or increase the effective wire resistance. For example, a slot width of 1 μm and the slots placed on a 6 μm pitch could be used; or a similar ratio of these values (i.e., 0.4 μm slot width and 2.4 μm pitch). For the holed version in <figref idref="DRAWINGS">FIG. 26D</figref>, the volume of metal removed by the holes would be kept to around 20% or less, so as not to substantially increase the effective wire resistance or reduce the capacitance. For example, 1 μm<sup>2 </sup>area holes taking up 20% of the overall wire area could be used.
0028The volume of metal removed by slotting or holing the wires is also determined by the tendency to form hillocks. For example, refractory metals are not sensitive to forming hillocks and may not need to be slotted or holed. The tendency to form hillocks in aluminum or aluminum alloys increases as the wire thickness increases and the capping refractory metal (i.e., TiAl<sub>3</sub>/TiN, TiN, etc.) thickness decreases. For taller wires, e.g., >=1 μm, the volume of metal needed to be removed by slotting or holing may be higher; wherein for shorter wires, e.g., <0.2 μm, the volume of metal needed to be removed by slotting or holing may be lower. The pitch is defined as the repeating wire width+space. For a 5 μm pitch with 1 um space, the wire width would be 4 μm.
0029For embodiments, the wire width between the slots would be 4 μm and spacing from the vertical end of the wires to the edge of the wire shape would also be 4 μm. Layouts using the slot algorithm where the ends of the slots are closed, shown in <figref idref="DRAWINGS">FIG. 26B</figref>, are subject to hillock formation at the end of the slots, due to increased local area or other geometry-induced effects. This is shown in <figref idref="DRAWINGS">FIG. 26E</figref>, which shows a closed slot layout with equal spacing both between the slots and between the slots and the ends of the wire shapes A<b>1</b>. To reduce or eliminate the tendency to form hillocks in this location, the spacing between the vertical end of the slots and the end of the wire shape can be reduced to less than the slotted wire width, as shown in <figref idref="DRAWINGS">FIG. 26F</figref>, which shows a wire width of A<b>1</b> and slot spacings to the wire edge or slot edge of A<b>2</b> and A<b>3</b>, which are both less than A<b>1</b>. This applies to orthogonal slots (i.e., slots ending in a perpendicular 90 degree angle fashion) as well as angled slots (i.e., slots ending at 45 degrees or another angle), as shown in <figref idref="DRAWINGS">FIG. 26</figref>. Another potential problem caused by slotting wires is the formation of a triple point in the subsequent silicon deposition above an uncapped slot. When the slots or holes are not capped, as shown in <figref idref="DRAWINGS">FIG. 26C</figref> or the upper portion of <figref idref="DRAWINGS">FIG. 26D</figref>, the subsequent silicon deposition can form a triple point, labeled “TP” in <figref idref="DRAWINGS">FIG. 26C</figref>, over the end of the uncapped slot, resulting in a defect in the silicon surface which can propagate up to subsequent wiring or other levels. To avoid this defect, the slotted ends can, optionally, be capped or closed, as shown in <figref idref="DRAWINGS">FIG. 26B</figref>. A similar triple point defect can occur for a holed design, again which can be eliminated to closing the hole. Open and closed holes are shown in the upper and lower portions of <figref idref="DRAWINGS">FIG. 26D</figref>.
0030Depending on the patterning of the wiring, voids or seams can form in the sacrificial material, e.g. silicon, between and above the spaces between the wires during later processing steps as described below. A seam is a region in the silicon in a gap between the underlying wires or other topography which is created as a byproduct of the silicon deposition profile. These seams can contain impurities, such as oxygen, and can cause subsequent problems due to either the presence of oxidized silicon or the seam opening up due to CMP, wet chemical, RIE, or other downstream processes. That is, if the aspect ratio of the spacing to the height of the wires <b>14</b> is high, voids or seams can form in upper layers during subsequent deposition processes. These voids or seams can affect the topography of the material, e.g. silicon, especially if there is a under or over polishing during a subsequent process step; or if the voids oxidize during deposition of the subsequent film. Alternatively, if a damascene or reverse damascene process is employed for wiring level <b>14</b>, then the surface will be substantially planer and subsequent layers will not be sensitive to forming voids. A reverse damascene process is one where the wires would be deposited and patterned, followed by a dielectric deposition and planarization step such that the wire surfaces were exposed but there was planer dielectric between the wires.
0031In <figref idref="DRAWINGS">FIG. 3</figref>, an insulator layer (dielectric layer) <b>16</b> is formed on the multiple wires <b>14</b> and exposed portions of the substrate <b>10</b>. In embodiments, the insulator layer <b>16</b> is an oxide deposited to about 80 nm; although other dimensions are also contemplated by the present invention. The combined thickness of lower MEMS capacitor insulator layer <b>16</b> and the subsequent upper MEMS capacitor insulator layer <b>34</b> shown in <figref idref="DRAWINGS">FIG. 11</figref>, determine the breakdown voltage and time dependent dielectric breakdown properties of the MEMS capacitor. For MEMS operation at 50V, the breakdown voltage needs to be greater than 50V, typically greater than 100V, to ensure high MEMS capacitor reliability. A combined MEMS capacitor insulator thickness of 160 nm is sufficient to be highly reliable for 50V MEMS operation. This insulator layer <b>16</b>, which is only required if a MEMS capacitor is being fabricated, will form the lower capacitor plate dielectric. The insulator layer <b>16</b> also acts as a barrier between the metal in wire <b>14</b>, e.g., aluminum, and the subsequent material <b>18</b>, i.e., silicon. Silicon and aluminum will react to form an intermetallic which is difficult to remove and, if formed, can block MEMS beam activation by blocking the beam from fully collapsing during actuation. The formation of this intermetallic can be prevented by a robust insulator layer <b>16</b>. Note that insulator layer <b>16</b> needs to be deposited at temperatures compatible with aluminum wiring, e.g., under about 420° C. and preferably under about 400° C., which precludes using highly conformal dielectrics such as liquid phase chemical deposition (LPCVD) SiO<sub>2</sub>, which is deposited at temperatures much greater than about 420° C. Deposition options for insulator layer <b>16</b> include one or more of plasma-enhanced CVD (PECVD), sub-atmospheric CVD (SACVD), atmospheric pressure CVD (APCVD), high density plasma CVD (HDPCVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). This layer will be discussed in more detail with regard to <figref idref="DRAWINGS">FIGS. 27A-27C</figref>.
0032A layer of sacrificial cavity material <b>18</b> such as, for example, silicon, tungsten, tantalum, germanium, or any material which can subsequently be selectively removed using, for example XeF<sub>2 </sub>gas, to the insulator layer <b>16</b> or the wire <b>14</b> if the insulator layer <b>16</b> is absent, is deposited on the insulator layer <b>16</b>; or on layer <b>14</b> if the insulator layer <b>16</b> is not present. In embodiments, silicon is used for layer <b>18</b>. The layer <b>18</b> can be deposited using any conventional plasma vapor deposition (PVD), PECVD, rapid thermal CVD (RTCVD), or LPCVD which operates at temperatures compatible with the wiring <b>14</b>, e.g., <420° C. In embodiments, the layer <b>18</b> is deposited to a height of about 0.1 to 10 microns which is determined by the MEMS gap requirement, and is patterned using conventional lithographic and reactive ion etching (RIE) steps. One example would use a silicon thickness of about 2.3 microns.
0033A common RIE etch gas for silicon is SF<sub>6 </sub>where the SF<sub>6 </sub>is diluted with other gases such as CF<sub>4</sub>, nitrogen, or argon. The silicon deposition process used to deposit silicon layer <b>18</b> can generate seams between wires and at the edges of wires, as discussed above. If these seams are oxidized or have other impurities in them, then they are difficult to etch during the silicon layer <b>18</b> etch step or during the final silicon cavity venting etch. To avoid leaving oxidized seams on the wafer after silicon layer <b>18</b> etch, a combination of argon dilution with rf bias power applied to the wafer to simultaneously sputter and RIE etch the surface can be used. Voids <b>20</b> can form over the spaces <b>14</b><i>a </i>between wires <b>14</b>, due to poor step coverage or conformality of the layer <b>18</b>. The width of the void <b>20</b>, spacing from the substrate <b>10</b>, and spacing from the surface of the silicon <b>20</b><i>a</i>, is determined by the aspect ratio of the wire <b>14</b>, the conformality of the silicon deposition and the shape of the insulator layer <b>16</b>.
0034<figref idref="DRAWINGS">FIGS. 27A-27C</figref> show several insulator layer <b>16</b> shapes over the wires <b>14</b>. The wires <b>14</b> shown in <figref idref="DRAWINGS">FIG. 27A</figref> are drawn with an undercut of the AlCu under the upper TiN/TiAl<sub>3 </sub>layer <b>14</b>′. This undercut often occurs during metal RIE processing and, if present, increases the difficulty of obtaining good wire <b>14</b> sidewall coverage of insulator layer(s) <b>16</b>. <figref idref="DRAWINGS">FIG. 27A</figref> shows the formation of the insulator layer <b>16</b> using conformal processes such as, for example, LPCVD, APCVD or SACVD. These conformal deposition processes provide nearly uniform insulator thickness on the top, side, and bottom surfaces <b>16</b>A, <b>16</b>B, and <b>16</b>C. These conformal deposition processes, when operated at temperatures compatible with aluminum or copper-based wiring, e.g. under 420 C, may have poor capacitor dielectric properties, for example, high leakage current, low voltage breakdown, or poor TDDB reliability. This profile provides a step formation <b>300</b> in the void <b>20</b>. <figref idref="DRAWINGS">FIG. 27B</figref> shows the formation of the insulator layer <b>16</b> using PECVD or PVD. This profile provides a “bread loafed” or “double tapered” profile formation <b>305</b> in the void <b>20</b>. Although these “bread loafed” films are not conformal, they may have excellent capacitor dielectric properties due to their plasma deposition. To reduce or eliminate the void <b>20</b>, it is desirable to have a tapered profile, as shown in <figref idref="DRAWINGS">FIG. 27C</figref>, which improves the layer <b>18</b> step coverage and reduces or eliminates the void <b>20</b>.
0035Divots <b>19</b> (see, e.g., <figref idref="DRAWINGS">FIG. 8 or 9A</figref>) may form over the voids or seams <b>20</b>, on the layer <b>18</b> surface, between the wires <b>14</b>. The voids <b>20</b> and divots <b>19</b> form due to the spacing between the wires <b>14</b>, and they can vary depending on the height of the layer <b>18</b>, as well as the spacing and/or height of the wires <b>14</b>. These divots <b>19</b> can deepen during subsequent processing, such as chemical mechanical processing, as discussed below in regards to <figref idref="DRAWINGS">FIG. 8</figref>. These divots <b>19</b> and seams can oxidize during subsequent processing such as exposure to humid air, an oxidizing ambient photoresist strip, or a plasma oxide deposition and these oxidized silicon regions will not be removed during the final silicon venting or removal step. If this happens, then these oxidized silicon residuals, which are under the MEMS beam, can block the MEMS beam from contacting the lower electrode (wire) <b>14</b>, resulting in poor actuation. (See, e.g., element <b>19</b><i>a </i>in <figref idref="DRAWINGS">FIG. 33</figref>.) Tapering the insulator layer <b>16</b> profile (<figref idref="DRAWINGS">FIG. 27C</figref>) reduces or eliminates this effect by eliminating the void and divot, as does eliminating the void by improving the silicon deposition gapfill. The profile can be tapered (<figref idref="DRAWINGS">FIG. 27C</figref>) by depositing a high density plasma CVD oxide as part or all of the insulator layer <b>16</b>. Alternatively, an insulator deposition and one or more sputter etch back and subsequent insulator deposition(s) could produce the same tapered profile of the insulator layer <b>16</b>. Alternatively, as discussed below, the silicon deposition can be modified to taper the silicon profile to 45 degrees by in-situ sputtering the silicon film in the PVD silicon deposition chamber.
0036The insulator layer <b>16</b> over wire <b>14</b> also acts to block reaction, alloying, or interdiffusion of the wire <b>14</b> material and the layer (cavity material) <b>18</b>. For example, if wire <b>14</b> contains aluminum, then the aluminum can react with the silicon to form an aluminum silicide, which is difficult or impossible to remove during the subsequent layer <b>18</b> (sacrificial layer) venting or removal step. This aluminum silicide formation can occur in the upper wire corners, for example, because the insulator layer <b>16</b> has a retrograde deposition profile (<figref idref="DRAWINGS">FIG. 27B</figref>) or has little coverage in the upper wire corner (<figref idref="DRAWINGS">FIG. 27C</figref>), resulting in exposed aluminum to the layer <b>18</b> deposition. Although this problem can be reduced or eliminated by increasing the thickness of the insulator layer, increasing the thickness is not always possible because of the associated reduction in capacitance of the MEMS capacitor formed using wire <b>14</b> as a bottom plate. In addition, wire surface or corner defects (not shown) could block the insulator layer <b>16</b> from fully coating the aluminum. This aluminum-silicon reaction can result in protruding aluminum silicide whisker-like features that can block or partially block the MEMS beam from actuating. To prevent this layer <b>16</b> and <b>18</b> reaction, a conformal barrier, such ALD Al<sub>2</sub>O<sub>3 </sub>(alumina), ALD Ta<sub>2</sub>O<sub>5 </sub>(tantalum pentaoxide), or a combination of both can be deposited. In one exemplary embodiment, layer <b>16</b> consists of 80 nm of HDPCVD oxide followed by 15 nm of ALD alumina. ALD films have extremely slow deposition rates and, although they could be used solely as the MEMS capacitor dielectric, it may be impractical because of the long deposition times and high manufacturing costs. One ALD alumina film has a deposition rate of 1 nm per minute, which means that it would take 80 minutes to deposit a 80 nm film. Thus using a combination of fast deposition SiO<sub>2 </sub>and slow deposition alumina is optimal. Note that the ALD alumina or similar film can be used under the 80 nm of oxide; and also can be used under the upper MEMS electrode <b>38</b> to block silicon reaction with the upper MEMS electrode.
0037In <figref idref="DRAWINGS">FIG. 3A</figref>, an optional processing step of forming a dielectric peg <b>16</b><i>a</i>, (e.g., oxide peg) is shown in accordance with aspects of the invention. In this optional step, the oxide peg <b>16</b><i>a </i>can be formed prior to the formation of the deposition insulator layer <b>16</b>. For example, the oxide peg <b>16</b><i>a </i>can be a deposited PECVD SiO<sub>2 </sub>film, which is patterned and etched on the wires <b>14</b> using conventional lithographic and etching processes. With this option, the oxide peg <b>16</b><i>a </i>could be patterned and etched first, followed by the wire <b>14</b> patterning and etching; or the wire <b>14</b> could be patterned and etched first followed by the oxide peg <b>16</b><i>a </i>deposition and etching. Patterning and etching the oxide peg <b>16</b><i>a </i>prior to the wire <b>14</b> patterning and etching avoids increasing the aspect ratio <b>14</b><i>a </i>incoming to insulator layer <b>16</b> deposition because the oxide between wires <b>14</b> is not etched during etching of the oxide peg <b>16</b><i>a</i>. In addition, if the oxide peg <b>16</b><i>a </i>is patterned and etched after the wires <b>14</b> are patterned and etched, then the perfluorocarbon-based RIE chemistry used to etch the oxide peg <b>16</b><i>a </i>could also etch the top TiN layer of the wire <b>14</b>, resulting in a degraded surface and degraded MEMS capacitor electrical yield or reliability. The oxide peg <b>16</b><i>a</i>, when placed over the MEMS actuators in regions away from the MEMS capacitor or contact head, forms a protective layer during MEMS operation, which can prevent the conductor in the MEMS beam from electrically arcing to the lower actuator electrode in areas that the MEMS beam does not need to closely contact the lower electrode. Since the preferred process patterns and etches the oxide peg prior to patterning and etching the wire <b>14</b>, it is desirable to avoid having the spaces <b>14</b><i>a </i>between the wires <b>14</b> intersect the oxide peg. After formation of the oxide peg <b>16</b><i>a</i>, the insulator layer <b>16</b> and layer <b>18</b> can be formed as described above.
0038As optional processing steps, the layer <b>18</b> can be planarized using, for example, a chemical mechanical polishing (CMP) and then, optionally, additional material (silicon) can be deposited on the polished layer <b>18</b> to provide a seamless silicon layer on the surface of the lower silicon MEMS cavity. Note that conventional CMP and subsequent cleaning processes, such as brush cleans, dilute hydrofluoric acid (DHF), buffered hydrofluoric acid (BHF), cryogenic cleans, etc. would be performed after any CMP step to remove the native oxide formed on the silicon surface. For example, referring to <figref idref="DRAWINGS">FIG. 4A</figref>, the layer <b>18</b> is deposited on the insulator layer <b>16</b> using a conventional deposition process such as, for example, PVD. As shown in <figref idref="DRAWINGS">FIG. 4A</figref>, voids <b>20</b> can be formed in the layer <b>18</b>, between the wires <b>14</b>, with the divots <b>19</b> formed over the voids <b>20</b>. As shown in <figref idref="DRAWINGS">FIG. 4B</figref>, the layer <b>18</b> is planarized using, for example, a CMP process. In <figref idref="DRAWINGS">FIG. 4C</figref>, a second layer of material <b>22</b>, e.g., silicon, is deposited on the planarized layer <b>18</b>. In <figref idref="DRAWINGS">FIG. 4D</figref>, the silicon layers <b>18</b> and <b>22</b> (which form now a single layer (hereinafter referred to as layer <b>18</b>) are patterned using conventional lithographic and reactive ion etching (RIE) steps. This silicon deposition, CMP, and second deposition process eliminates the divots <b>19</b> in the silicon surface, eliminates the chance of oxidizing the seam <b>20</b>, and partially or completely planarizes the topography on the silicon surface due to the incoming wire <b>14</b> and wire space <b>14</b><i>a </i>topography.
0039One set of example thicknesses would be a 250 nm tall wire <b>14</b>, a 500 nm space <b>14</b><i>a </i>between wires <b>14</b>, a 2 micron initial silicon <b>18</b> deposition thickness, a 400 nm silicon CMP removal over the wires <b>14</b> to planarize the 250 nm step over wires <b>14</b>, and a subsequent silicon deposition <b>22</b> thick enough to partially remain on the wafer during the subsequent reverse oxide planarization processes shown in <figref idref="DRAWINGS">FIGS. 5-8</figref>. In one exemplary embodiment, 200 nm of silicon is removed from the regions above wires <b>14</b> and substantially less than 50 nm in the spaces between wires <b>14</b><i>a</i>, which partially planarizes the regions over the wires <b>14</b> and spaces <b>14</b><i>a. </i>
0040Silicon CMP is commonly performed to form deep trench DRAM capacitors, as known in the art. With this type of silicon CMP, the CMP process is optimized to maximize the selectivity to the pad insulator (e.g. SiO<sub>2 </sub>or oxide) films on the wafer surface, i.e., the silicon CMP rate is maximized and the oxide CMP rate is minimized such that the selectivity of silicon to oxide is 50:1. This type of silicon CMP process is optimal for silicon films deposited using CVD but can cause problems for silicon films deposited using PVD. PVD silicon films polished with conventional selective silicon CMP processes may have problems with defects in the PVD silicon film which can cause the local polish rate to be reduced. These PVD silicon defects, which may be due to oxidized silicon, other impurities, or the silicon grain structure, can cause the selective silicon CMP process to leave underpolished point defects on the polished silicon surface.
0041To avoid these point defects during silicon CMP, a less selective or non-selective silicon polish process can be used, e.g., using a SiO<sub>2 </sub>polish chemistry and process instead of a silicon CMP polish chemistry and process. The use of a less selective silicon polish process eliminates these point surface defects post polish. An example of a selective silicon polish is a basic media, such as TMAH with silica abrasive with a ph high enough to dissolve silicon, i.e., >12, which has a silicon:SiO<sub>2 </sub>selectivity of 50:1; an example of a non-selective silicon polish is basic media, such as KOH, with a ph<12, which is too low to dissolve the silicon, using a silica abrasive. This non-selective silicon CMP process would have silicon: SiO<sub>2 </sub>selectivities of less than 50:1 and, in one exemplary embodiment, would be in the range of 2:1 to 1:2.
0042To avoid polishing into the void <b>20</b>, it is desirable for the first silicon deposition to be thick enough to bury the void below the surface. Silicon is opaque to optical wave lengths of light. If the subsequent lithographic process used to pattern the silicon uses optical wave lengths, then the silicon CMP process should not fully planarize either alignment structures using the wire level topography; or partially filled alignment structures using the damascene level <b>12</b>. If the subsequent lithographic processes use infrared light or other methods that can detect features under the silicon, then these precautions are not needed.
0043A thin native oxide (e.g., SiO<sub>2</sub>) forms on any silicon surface exposed to air or oxygen, even at room temperature. When the silicon is etched or vented during subsequent processing, the presence of this native oxide can either block the etch or venting, or can remain on the wafer as a few monolayer SiO<sub>2 </sub>film. To avoid this, either the silicon surface should be hydrogen passivated by exposing the silicon to vapor, plasma, or liquid hydrofluoric acid (HF), or a preclean using, for example, a rf biased argon sputter preclean, should be performed immediately prior to depositing the second silicon layer <b>22</b>, without exposing the wafer to air or oxygen.
0044Referring to <figref idref="DRAWINGS">FIG. 5</figref>, an insulator material (e.g., oxide) <b>24</b> is deposited on the layer <b>18</b>. The oxide deposition can be, for example, a conventional conformal deposition process, depositing the oxide layer <b>24</b> to a depth of about approximately the same as the silicon <b>18</b> height, e.g., about 2.3 μm for a 2.3 micron thick layer <b>18</b>. For example, the deposition process can be a 400° C. PECVD oxide deposited using TEOS or silane as a silicon source and oxygen or N<sub>2</sub>O as an oxygen source, as known in the art. If the oxide layer <b>24</b> thickness is intentionally thinner than the height of the silicon layer <b>18</b>, then the subsequent oxide CMP process shown in <figref idref="DRAWINGS">FIG. 8</figref> will overpolish and planarize the surface of the silicon layer <b>18</b>. Conversely, if the oxide layer <b>24</b> thickness is intentionally thicker than the height of the silicon layer <b>18</b>, then the subsequent oxide CMP process shown in <figref idref="DRAWINGS">FIG. 8</figref> will underpolish the surface of the silicon layer <b>18</b> and leave it buried below the oxide surface. Both process options can be desirable, depending on how important minimizing the silicon surface <b>18</b> overpolish is vs. planarizing the oxide layer <b>24</b> or silicon <b>18</b> surface topography from wiring levels <b>14</b>. In one exemplary embodiment, silicon <b>18</b> layer is about 2.3 microns, the oxide layer <b>24</b> is about 2.1 microns, and the optional oxide etchback step shown in <figref idref="DRAWINGS">FIG. 7</figref> is targeted at a full oxide removal, i.e., >2.1 microns. This results in the subsequent oxide polish process further planarizing the silicon layer <b>18</b>.
0045In <figref idref="DRAWINGS">FIG. 6</figref>, an optional reverse etch (reverse damascene process) is performed in accordance with aspects of the invention. More specifically, a resist <b>26</b> is deposited on the oxide layer <b>24</b> and is patterned to form an opening <b>28</b>, with the resist edges <b>26</b><i>a </i>overlapping with edges of the underlying layer <b>18</b>. That is, the resist <b>26</b> will slightly mask the underlying layer <b>18</b>. The overlap needs to be greater than 0 and can be, for example, 3 microns and is minimized to reduce the oxide layer <b>24</b> left to be planarized during the subsequent CMP process. If the overlap is negative, then the subsequent RIE etch will etch into the lower portion of oxide layer <b>24</b>, resulting in a deep trench adjacent to the silicon layer <b>18</b>, which could cause problems such as residual metal from the subsequent wiring level inside the deep trench, resulting in electrical wire shorting at subsequent levels, and which should be avoided. As shown, the opening is a reverse image of the patterned layer <b>18</b>.
0046As shown in <figref idref="DRAWINGS">FIG. 7</figref>, the oxide material <b>24</b> is etched using conventional RIE processes. In embodiments, as shown in <figref idref="DRAWINGS">FIG. 7</figref>, the etching process results in a “picture frame” <b>30</b>, which surrounds the underlying layer <b>18</b>. If the oxide material <b>24</b> is etched completely down to the surface of layer <b>18</b>, then the oxide overpolish in regions away from the layer <b>18</b> will be minimized. This can be desirable to minimize the overpolish of layer <b>18</b>, to reduce its thickness tolerance; and to eliminate the possibility of leaving residual oxide over the silicon in the MEMS capacitor or contact area. Alternatively, some oxide can be left over layer <b>18</b>, as shown in <figref idref="DRAWINGS">FIG. 7</figref>.
0047In <figref idref="DRAWINGS">FIG. 8</figref>, the oxide material <b>24</b> is planarized, e.g., to be planar (e.g., a nearly flat or planar surface) with the underlying layer <b>18</b>. In embodiments, this process will also planarize the underlying silicon layer <b>18</b>, which will advantageously result in a planar cavity structure (e.g., having flat or planar surfaces) in subsequent processing steps. The planarization process can be, for example, a CMP process. Unexpectedly, and as discussed in more detail with reference to <figref idref="DRAWINGS">FIG. 25</figref>, the oxide CMP can minimize the variability of the underlying layer <b>18</b>; for example, depending on the wiring spacing, the polishing of the oxide material <b>24</b> can minimize divots between the wires <b>14</b> (e.g., over the space <b>14</b><i>a </i>formed between the wires <b>14</b>).
0048<figref idref="DRAWINGS">FIG. 25</figref> shows several topography graphs (i.e., atomic force microscopy data) for silicon divot depth vs. oxide polish of the surface of layer <b>18</b> shown in <figref idref="DRAWINGS">FIG. 8</figref>. These graphs are related to the polishing of the oxide layer <b>24</b> shown, for example, in <figref idref="DRAWINGS">FIG. 8</figref>. In this example, the divot <b>19</b> in the layer <b>18</b> (See, e.g., <figref idref="DRAWINGS">FIGS. 3 and 8</figref>) can be as tall as 250 nm (0.25 μm), which is the thickness of the wires <b>14</b>.
0049The graphs of <figref idref="DRAWINGS">FIG. 25</figref> show CMP of the oxide layer <b>24</b> for 30 seconds, 60 seconds and 90 seconds, with different wiring spacing <b>14</b><i>a </i>of 0.5 μm, 0.8 μm and 5.5 μm. These graphs show the unexpected importance of the wiring spacing <b>14</b><i>a </i>of the wires <b>14</b>, in order to minimize topography variability of the layer <b>18</b>. For example, a slot (spacing) of 0.5 μm and a CMP of the oxide for 30 seconds shows a 2 nm divot depth in the layer <b>18</b>, compared to 5 nm and 10 nm for a CMP of the oxide for 60 seconds and 90 seconds, respectively. Also, a slot of 0.8 μm with a CMP of the oxide for 30 seconds shows a 30 nm divot depth of the layer <b>18</b>, compared to 2 nm and 8 nm for a CMP of oxide for 60 seconds and 90 seconds, respectively. Additionally, a slot of 5.5 μm with a CMP of the oxide for 30 seconds shows a 170 nm divot depth, compared to 40 nm and 10 nm for a CMP of 60 seconds and 90 seconds, respectively. These results were not expected, as a increasing CMP time of the oxide would have been expected to show an optimization, i.e., reduction of the divot depth, of the topography of the layer <b>18</b>. These divots in layer <b>18</b> will replicate under the MEMS beam, resulting in MEMS beam underside topography. In addition, the MEMS beam underside topography, which will consist of both deposited oxide as well as potentially an oxidized seam under the divot, can have poor adhesion to the MEMS beam with resultant flaking during MEMS operation. This flaking can cause catastrophic MEMS capacitor yield or reliability degradation, due to the presence of flaking oxide in the MEMS cavity under or over the MEMS beam.
0050Accordingly, a method of reducing a divot depth or the variability of the silicon layer used for a MEMS structure includes determining a spacing between wires formed on the silicon layer. The method further includes etching an oxide layer for a predetermined amount in order to minimize variability of the silicon layer. The etching for a predetermined amount of time, for each spacing, will result in an optimal structure, e.g., reduce any variability in the silicon layer. The divots over layer <b>18</b>, which form over seams or voids in the silicon due to underlying topography induced by the gap <b>14</b><i>a </i>in layer <b>14</b>, can be the source of residual oxide under the MEMS beam post venting or release. For example, the oxide layers <b>24</b> or <b>34</b> can be deposited using a PECVD process which contains an oxidizing plasma and, optionally, at about 350° C. or 400° C., resulting in oxidization of the divot or seam. This oxidized divot or seam CC, as shown in <figref idref="DRAWINGS">FIG. 33</figref>, can remain on the underside of the MEMS beam post silicon venting, resulting in topography under the MEMS beam, which can either partially block the MEMS beam from contacting the lower capacitor electrode (wire) <b>14</b>, or disintegrate or fall off during MEMS beam actuation or operation, resulting in dielectric damage of the MEMS capacitor. The optional embodiment described in <figref idref="DRAWINGS">FIGS. 4B, 4C, and 4D</figref>, where the layer <b>18</b> is polished and capped with a second silicon layer <b>22</b>, eliminates this problem.
0051As an optional step shown in <figref idref="DRAWINGS">FIG. 9A</figref>, the oxide material <b>24</b> can be deposited to a thickness of about 3.3 μm, compared to the 2.3 μm shown in <figref idref="DRAWINGS">FIG. 5</figref>. For this embodiment, the oxide etch depth is similar to the one described in <figref idref="DRAWINGS">FIG. 7</figref>, but would be approximately 1 um deeper and would need to expose the surface of the underlying silicon layer <b>18</b>. The divot <b>19</b>, e.g., may be formed over the voids <b>20</b> shown in the layer <b>18</b>, between the wires <b>14</b>. As shown in <figref idref="DRAWINGS">FIG. 9A</figref>, the thick oxide material <b>24</b> is deposited on the sides of the layer <b>18</b>, patterned and etched, and polished using CMP. In <figref idref="DRAWINGS">FIG. 9B</figref>, a silicon layer <b>32</b>, for example, is deposited on the thick oxide material <b>24</b> and the layer <b>18</b>. As mentioned, previously, a native (or any) oxide should be avoided on the surface of layer <b>18</b> prior to the deposition of subsequent silicon layer <b>32</b> shown in <figref idref="DRAWINGS">FIG. 9C</figref>.
0052In <figref idref="DRAWINGS">FIG. 9C</figref>, the silicon layer <b>32</b> (and portions of the oxide material <b>24</b>) is planarized using conventional processes such as, for example, CMP, which may eliminate or minimize the divots. In embodiments, this process will advantageously result in a planar cavity structure (e.g., flat or planar surfaces) in subsequent processing steps. These added steps, i.e., silicon deposition, CMP, deposition (<figref idref="DRAWINGS">FIG. 4A-4C</figref>; <figref idref="DRAWINGS">FIG. 9A-9C</figref>) and the reverse damascene oxide CMP overpolish (<figref idref="DRAWINGS">FIG. 6-8</figref>) or non-reverse damascene oxide CMP overpolish (<figref idref="DRAWINGS">FIGS. 5 and 8</figref>) determine both the micro and macro MEMS beam topography. Micro MEMS beam topography due to divots above the silicon voids are further discussed below in relation to <figref idref="DRAWINGS">FIG. 25</figref>.
0053An example of undesirable macro topography are curved silicon surfaces <b>18</b><i>a </i>and <b>18</b><i>b </i>shown in <figref idref="DRAWINGS">FIGS. 9D and 9E</figref>. <figref idref="DRAWINGS">FIG. 9D</figref> shows the silicon surface curvature <b>18</b><i>a </i>due to non-optimized planarization, and more specifically shows an example of undesirable macro topography. This macro topography convex <b>18</b><i>a </i>or concave <b>18</b><i>b </i>curvature in the lower sacrificial cavity material <b>18</b> can cause released MEMS beam ‘frozen-in’ curvature and poor MEMS actuation, i.e., the MEMS beam can be curved around the sacrificial cavity <b>18</b> material, resulting in high post beam release curvature and poor MEMS beam actuation or contact area. The curvature of the silicon surface can be defined by the radius of curvature ROC. A silicon ROC of less than 1 cm is desirable and ROC values greater than 5 cm will result in approximately 50% reduction of MEMS capacitor capacitance due to reduced MEMS capacitor surface contact area and a larger spacing between the two MEMS capacitor plates.
0054In <figref idref="DRAWINGS">FIG. 10A</figref>, starting from the structure of either <figref idref="DRAWINGS">FIG. 8</figref> or <figref idref="DRAWINGS">FIG. 9C</figref>, optional trenches <b>33</b> can be formed in the silicon layer <b>18</b>, over wirings <b>14</b>. To ensure that the silicon is uniformly etched, an optional oxide RIE process can be performed on the resist patterned wafers prior to silicon etch. In addition, with or without the optional oxide RIE process, a HF clean with photoresist on the wafer can be performed to hydrogen passivate the silicon surface prior to etching the silicon. In embodiments, the trenches <b>33</b> are formed to a depth of about 0.3 μm into 2 micron tall layer <b>18</b> (e.g., sacrificial cavity material <b>18</b>); although other dimensions are contemplated by the invention depending on the design parameters and, more particularly, the height of the layer <b>18</b>.
0055As with the oxide pegs <b>16</b><i>a </i>discussed in <figref idref="DRAWINGS">FIG. 3A</figref>, the purpose of these damascene oxide pegs or trenches <b>33</b> is to place a dielectric bumper between the MEMS beam and the lower wire level <b>14</b>, to prevent electrical arcing due to the close proximity of wires in the MEMS beam and the wire <b>14</b> during MEMS operation. Arcing could occur when a high dc voltage, i.e., 5-100V, is applied to the MEMS actuator in, for example, the wire <b>14</b>. To avoid the potential for electrical arcing, the subsequent MEMS beam metal layer in close contact to the bottom of trench <b>33</b> could be removed, as shown in <figref idref="DRAWINGS">FIGS. 10B and 10C</figref>. Oxide peg <b>33</b><i>a </i>has had the subsequent MEMS beam metal layer <b>38</b> taken out of the design while oxide peg <b>33</b><i>b </i>has metal layer <b>38</b> left in the design.
0056The subsequent metal layer <b>38</b>, which is used to form the MEMS beam lower electrode, can be patterned either to cover the oxide peg <b>33</b> or to leave it uncovered. If it is uncovered, then the likelihood of arcing or other dielectric damage between the actuator plates is reduced; if it is covered, i.e. metal extends down into oxide peg <b>33</b>, then the effectiveness of the oxide peg to reduce actuator arcing or dielectric damage may be reduced. If the oxide peg <b>33</b> is not covered by metal layer <b>38</b> and there is a step down into the peg due to process method chosen, then there may be a thin metal spacer left along the sidewall of the oxide peg. Since this metal spacer does not contact the electrode <b>38</b>, it is unimportant.
0057A nearly 90 degree or rounded bottom corner of the oxide peg can be used. To round the peg bottom, which is desirable if the subsequent MEMS beam metal <b>38</b> is present over the peg, the rf bias power on the wafer can be reduced or eliminated during the argon-SF<sub>6</sub>-base silicon etch process and the argon flow can be reduced. The oxide peg <b>33</b> can be patterned and etched either before or after the reverse cavity planarization process. If it is done after, then its depth variability is controlled solely by the silicon etch depth variability and not by the reverse cavity oxide CMP planarization step. Alternatively, if it is done before the reverse cavity oxide planarization oxide deposition step, then it will have an added component of height variability, due to CMP removal variability, but it will be filled or partially filled with planarized oxide, which will increase the separation or spacing of subsequent metal level <b>38</b> from the actuator metal level <b>14</b> if the oxide peg is covered by the metal.
0058In <figref idref="DRAWINGS">FIG. 11</figref>, an upper capacitor dielectric or oxide deposition is performed on the structure of <figref idref="DRAWINGS">FIG. 10A</figref>. More specifically, in this deposition step, oxide material <b>34</b> can be deposited to a height of about 80 nm; although other dimensions are contemplated by the present invention as discussed previously. The MEMS capacitor dielectric, when the MEMS beam is actuated, comprise dielectric layers <b>16</b> and <b>34</b>, which are separated by a small gap, due to the surface roughness and hillocks of the MEMS capacitor electrodes. A tapered via <b>36</b> can be formed in the oxide materials <b>24</b> and <b>34</b> to the underlying wire <b>14</b>′. The tapered via <b>36</b> can be formed using conventional lithographic, etching, and cleaning processes, known to those of skill in the art. Care should be taken with the tapered via not to overly oxidize the underlying TiN, TiAl<sub>3</sub>, or AlCu surface, which can cause high via resistance. Optionally, the post via RIE photoresist strip can be performed at low temperature, i.e., 100° C., to minimize oxidization. Alternatively, a damascene tungsten stud via could be fabricated, as is known in the art. The use of a tapered via <b>36</b> reduces the CMP exposure of the silicon surface, resulting in less silicon <b>18</b> thickness variability, avoiding polishing or damaging the upper MEMS capacitor insulator <b>34</b>, as well as a lower chance of forming a deep divot. Since the silicon layer <b>18</b> thickness determines the pull-in voltage of the MEMS device, minimizing its variability is desirable. Note that the tapered via <b>36</b> should be used outside of the silicon cavity area, because the oxide etch used to fabricate it would be blocked by the silicon layer <b>18</b> if it was placed inside the silicon cavity. If the subsequent metal deposition process used for wire <b>38</b> has poor conformality or side wall coverage, than the aspect ratio of tapered via <b>36</b> needs to be low, e.g., 0.5:1. For a 2 micron thick insulator <b>24</b>, a 4 micron wide tapered via <b>36</b> could be used. Alternatively, if a conformal aluminum process, i.e. a hot reflow PVD or CVD process, was used, than a higher aspect ratio could be used for tapered via <b>36</b>.
0059In <figref idref="DRAWINGS">FIG. 12</figref>, a wire of electrode <b>38</b> is formed and patterned over the oxide material <b>34</b>, and also deposited within the via <b>36</b> to contact the underlying wire <b>14</b>′. The electrode <b>38</b> can also be deposited in the trenches <b>33</b>; however, for illustrative purposes the electrode is not shown in the trench <b>33</b> of <figref idref="DRAWINGS">FIG. 12</figref> (although electrode <b>38</b> is shown formed in trench in subsequent figures). In embodiments, the electrode <b>38</b> can be, for example, AlCu; although other materials are also contemplated by the invention. In embodiments, for example, the electrode <b>38</b> can be TiN, TiN or W, Ru, Pt, Ir, amongst other materials. The thicknesses of this and other electrodes and/or wires can vary depending on the specific design parameters. For example, Ti/AlCu/Ti/TiN layers could be used with 10 nm, 480 nm, 10 nm, and 32 nm thickness, respectively, which would form TiAl<sub>3 </sub>under and over the AlCu after 400 C annealing. To minimize any hillocks, in embodiments, an optional Ti layer may be deposited and/or formed in direct contact with Al, as discussed previously. In this case, the hillocks should be suppressed on the lower surface of the wire (electrode) <b>38</b>, as opposed to the upper surface. Alternatively, the electrode <b>38</b> could be formed from a noble metal, such as Au; or a refractory metal, such as W or Ta; or without a Ti—AlCu interface, e.g., Ti/TiN/AlCu/TiN.
0060In <figref idref="DRAWINGS">FIG. 13</figref>, an insulator material <b>40</b> is conformally deposited over the electrode <b>38</b>. In embodiments, the insulator material <b>40</b> is a deposited oxide using any of the methods discussed above that is deposited to a height of about 0.5 to 5 μm, depending on the beam spring constant and oxide to metal thickness ratio requirements. In one exemplary embodiment, insulator material is 400° C. PECVD 2 μm oxide and has a well controlled residual stress and thickness. In embodiments, tapered vias <b>42</b> are formed in the insulator material <b>40</b>, to expose portions of the underlying electrode <b>38</b> in a fashion similar to the vias <b>36</b> formed previously. Alternatively, tungsten stud vias could be fabricated, at the price of degrading the thickness variability of layer <b>40</b> due to variable CMP erosion of the insulator layer <b>40</b>. Variation in the insulator layer <b>40</b> thickness or residual stress results in spring constant and stress gradient variability in the overall MEMS beam, which can negatively affect the beam curvature and bending.
0061As shown in <figref idref="DRAWINGS">FIG. 14</figref>, an upper electrode <b>44</b> is formed and patterned over the insulator layer <b>40</b>, and also deposited within the vias <b>42</b> to contact the lower electrode <b>38</b>. In embodiments, the upper electrode <b>44</b> is formed from the same materials as the lower electrode <b>38</b>; in one exemplary embodiment, uppers electrode <b>38</b> and <b>44</b> are composed of Ti/AlCu/Ti/TiN. For tungsten stud vias, the prior art teaches that the uppermost TiN layer should be left on the wires post via etch. For the tapered vias used with these MEMS structures, it may be desirable to fully remove the TiN layer prior to depositing the electrode <b>38</b> and <b>44</b> metal, i.e., Ti/AlCu/Ti/TiN, by either etching it using a TiN RIE chemistry, sputter it using an argon sputter, or a combination of both to eliminate the potential for via resistance high flyers. In embodiments, the metal volume of the electrodes <b>38</b> and <b>44</b> should be the same or substantially the same in order to balance the overall volume and stress of the device, and hence not place undue stresses on the beams of the MEM structures. The metal volume is determined by both the metal thickness and the layout. If identical layouts are used for electrodes <b>38</b> and <b>44</b>, then they would have the same volume if their thicknesses were the same. If a slotted or holed layout was used for the lower electrode <b>38</b>, then the upper electrode would need to be thinned to match the metal volume. In embodiments, the thickness of the lower or upper electrode <b>44</b> can be increased or decreased to intentionally place a stress gradient into the beam, which can cause the beam to deflect up or down post release; or to change the beam bending induced by changing temperature, as discussed below. The preceeding discussion assumes that the electrodes <b>38</b> and <b>44</b> are composed of a single, identical metal film. In reality, as discussed above, the electrodes are composed of multiple layers of metal, each with different thermal expansion coefficient (CTE) and other mechanical properties and, if the layout or thickness is varied, it is nearly impossible to exactly match their mechanical properties. If the AlCu portion of the electrodes <b>38</b> and <b>44</b> is much thicker than the refractory and other metal components, then, to first order, the CTE and other mechanical properties can be approximated by those of the AlCu film.
0062Alternatively, if the layout of the upper and lower electrodes <b>38</b> and <b>44</b> are asymmetric or different, then the thickness of the electrode with a lower pattern factor (i.e., less metal) could be thickened to balance the metal volume. One example of an asymmetric upper and lower electrode is shown in <figref idref="DRAWINGS">FIG. 28</figref>. In this representation, there are diamond (or other patterned shapes) shaped shapes removed from the lower MEMS electrode <b>200</b>, which are placed to decrease the likelihood of metal hillocks forming. Because the area of lower MEMS electrode <b>200</b> is less than the area of upper MEMS electrode <b>210</b>, the volume of metal in each electrode would be out of balance if the metal thickness for electrodes <b>200</b> and <b>210</b> were identical. Balancing the metal volume of the lower and upper electrodes is important for both cantilever and bridge MEMS beams because the coefficient of thermal expansion (CTE) of the beam metal, e.g., aluminum, is much greater than the CTE of SiO<sub>2</sub>.
0063In embodiments, MEMS electrodes with different areas could be partially balanced. For example, if the lower MEMS beam electrode had 80% less area than the upper MEMS beam electrode, the lower electrode could be thickened by 10% to partially rebalance the metal volume in the two electrodes. Intentionally unbalancing the metal volume in the two MEMS electrodes can cause MEMS beam bending post release or venting which acts to bend the beam up or down into a desirable position; or can minimize the MEMS beam bending over operational use temperature, e.g., −55° C. to 125° C. or any normal range of packaged chip operational temperatures, as discussed below. The MEMS cavity actuation gap is increased or decreased as the MEMS beam bends up or down; and the curvature of the beam, which can reduce the contact area and decrease the capacitance, can change as the MEMS beam expands or contracts with changing temperature. Minimizing the MEMS beam bending over operational chip temperatures is desirable because the actuation voltage is inverse proportional to the MEMS cavity gap.
0064When the vented MEMS beam movement is constrained by the lid, either because of the lid rivet AA or because the lid is bonded to the lid BB (see, <figref idref="DRAWINGS">FIG. 31</figref>), the MEMS beam will not actuate as expected and will be partially or completely non-functional. The regressive lid oxide profile shown in <figref idref="DRAWINGS">FIG. 16</figref> has the largest regressive extent in the corners of the vias <b>42</b> and <b>48</b>. To reduce this, the vias inside the MEMS cavity <b>42</b> and <b>48</b> corners can be rounded or chamfered, as shown in <figref idref="DRAWINGS">FIG. 32</figref>, which reduces the likelihood that the lid oxide will pin the MEMS beam. <figref idref="DRAWINGS">FIG. 30E</figref> shows a non-regressive silicon deposition with tapered side wall profiles for the upper silicon cavity. This conformal silicon deposition process can be obtained, for example, by performing multiple PVD silicon deposition and rf biased wafer etchback steps preferably in-site, i.e. in the same chamber, or ex-situ, i.e., transferring between a deposition and etch back chamber, during the silicon deposition to achieve an approximate 45 degree angled silicon deposition profile. Once the 45 degree angle is achieved, e.g., after about 0.3 μm of net deposition over a 0.3 μm tall feature (<figref idref="DRAWINGS">FIG. 3</figref>) or after about 1 μm of net deposition over a much deep feature (<figref idref="DRAWINGS">FIG. 16</figref>), the balance of the deposition can consist either of a normal, unbiased, silicon film or a combination of thicker unbiased silicon films with less frequent etch back steps, which may be needed to eliminate an oxidized seam in the silicon due to underlying topography. The goal of these silicon deposition/etch back processes is to both eliminate a regressive overhang structure and also to reduce or eliminate a seam in the deposited silicon due to incoming topography (<figref idref="DRAWINGS">FIG. 35A</figref>). (This is compared to <figref idref="DRAWINGS">FIG. 35B</figref> which shows an oxide seam to the corner of the MEMs structure.) This non-regressive PVD silicon deposition process combines lower chamber pressure deposition for bottom and sidewall deposition, and uses higher chamber pressure etching, where a rf bias is applied to the wafer, to maximize top surface and corner etching. These steps of low pressure deposition and high pressure etchback are repeated sequentially until a desired thickness is achieved. In one exemplary embodiment, the lower pressure deposition, e.g., <6 MTorr, and high pressure, e.g. >10 mTorr, etchback step thickness values are on the order of 10-50 nm for deposition and 5-25 nm for etching, e.g., the etchbacked silicon removal is less than the deposited thickness, and, as mentioned below, the first silicon layer thickness may be increased to, for example, 50 or 100 nm, to avoid sputtering into the corners of features. In addition, this sequence allows for increased film density on the sidewall and tapered surfaces. The surface area of the Si is then minimized, reducing the amount of surface oxidation. Alternatively, a simultaneous PVD silicon deposition and etchback process could be employed, where the sputtering target is biased to sputter the silicon and the wafer is biased to create 45 degree sidewall angles. This is critical to achieve stable venting performance of the Si as any oxidation reduces the venting rate of the Si cavity.
0065The desired 45 degree corner angle is obtained by the repeated argon sputter etch back step and, after it is obtained, the silicon deposition process could revert back to a normal deposition process without argon sputter steps. This biased silicon deposition process could also be applied to the lower silicon cavity layer <b>18</b> to eliminate voids and seams in the silicon. Care should be taken when sputter etching the silicon during the initial film deposition step to avoid sputtering insulator or other materials from the corners of features. The corner <b>405</b> in <figref idref="DRAWINGS">FIG. 30E</figref> could be chamfered to 45 degrees by this in-situ or ex-situ sputtering method, resulting in redeposition of oxide layer <b>46</b> into the silicon with resultant difficulty in silicon venting due to the presence of SiO<sub>2 </sub>in the silicon. To avoid sputtering the exposed corners during the initial silicon deposition, an initial unbiased silicon layer, e.g. 50 or 100 nm, can be deposited.
0066As the released MEMS beam is heated or cooled, it will bend upwards or downwards due to the electrode with the greater volume of metal expanding or contracting more than the electrode with the lesser volume of metal. <figref idref="DRAWINGS">FIG. 29</figref> and Table 2 quantitatively show MEMS bridge beam bending versus temperature for beams using the layout shown in <figref idref="DRAWINGS">FIG. 28</figref>. As mentioned above, the MEMS beam bends because of the CTE mismatch between the oxide and metal in the beam. The dominant metal in the beam, e.g. aluminum, has a yield stress temperature of 150-250° C. The yield stress temperature occurs when the residual stress in the aluminum no longer changes with temperature, as known in the art. At the yield stress temperature, the bending can either flatten out or, more typically, reverse direction (<figref idref="DRAWINGS">FIG. 29</figref> curve B or E). MEMS bridge beams with balanced metal volume have minimal bending vs. temperature; beams with more upper electrode volume bend upwards with increasing temperature; beams with greater lower electrode volume bend downwards vs. temperature. Note that, if the MEMS bridge beam bending is large enough, the beam will be constrained by the lid over the MEMS beam or the fixed electrode under the MEMS beam (<figref idref="DRAWINGS">FIG. 29</figref> curves A or F). The most desirable MEMS beam bending vs. temperature behavior is one where the total bending is minimized, for reasons discussed above. This may be achieved using MEMS beam thicknesses such that the MEMS bending profile initially bends upwards and then bends downwards over the temperature range of interest, i.e. <figref idref="DRAWINGS">FIG. 29</figref> curve C; or vica versa. Achieving a MEMS beam bending curve like this may require intentionally unbalancing the lower and upper electrode volume.
0067In one exemplary embodiment, the ratio of the lower electrode <b>38</b> to upper electrode <b>44</b> pattern factor is 0.8:1; the beam oxide is 2 μm thick, the lower electrode has total thickness of 0.56 μm with unreacted AlCu thickness of 450 nm, and the lower electrode has total thickness of 0.48 μm with unreacted AlCu thickness of 370 nm. This combination results in electrodes <b>38</b> and <b>44</b> with unbalanced volume, i.e., the volume ratio of electrodes <b>38</b> and <b>44</b> is 0.93:1 and minimized beam bending vs. temperature, over the temperature range of interest qualitatively similar to curve C in <figref idref="DRAWINGS">FIG. 29</figref>.
0068<tables id="TABLE-US-00002" num="00002"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="1" colwidth="28pt" align="center" /><colspec colname="2" colwidth="77pt" align="center" /><colspec colname="3" colwidth="42pt" align="center" /><colspec colname="4" colwidth="70pt" align="left" /><thead><row><entry namest="1" nameend="4" rowsep="1">TABLE 2</entry></row><row><entry namest="1" nameend="4" align="center" rowsep="1" /></row><row><entry /><entry>Lower: Upper electrode</entry><entry /><entry /></row><row><entry /><entry>thickness ratio (lower</entry></row><row><entry /><entry>electrode is 20% less</entry><entry>Bending at</entry></row><row><entry /><entry>than upper electrode</entry><entry>metal yield</entry></row><row><entry>Curve</entry><entry>layout area)</entry><entry>stress point</entry><entry>Comment</entry></row><row><entry namest="1" nameend="4" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>A</entry><entry>1:1.5</entry><entry> +3 um</entry><entry>Upwards bending</entry></row><row><entry /><entry /><entry /><entry>constrained by lid</entry></row><row><entry>B</entry><entry>1:1 </entry><entry>+2.2 um</entry></row><row><entry>C</entry><entry>1:0.9</entry><entry>+0.8 um</entry></row><row><entry>D</entry><entry>1:0.8</entry><entry>−0.1 um</entry></row><row><entry>E</entry><entry>1:0.7</entry><entry>−1.0 um</entry></row><row><entry>F</entry><entry>1:0.5</entry><entry> −2 um</entry><entry>Lower bending</entry></row><row><entry /><entry /><entry /><entry>constrained by lower</entry></row><row><entry /><entry /><entry /><entry>fixed electrode</entry></row><row><entry namest="1" nameend="4" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>
0069This MEMS beam bending post release can cause two problems, as mentioned above:
0000a. during normal chip operation, e.g., from about −55° C. to 125° C., MEMS beam bending will increase or decrease the actuation gap resulting in a corresponding change in the actuation voltage; and
0070b. if the released MEMS beam is heated to high temperatures (e.g., >150° C., e.g. 400° C.), which is likely due to normal processing after the sacrificial material is vented or removed, then the released MEMS beam will bend upwards, downwards, or both due to thermal expansion mismatch between the upper and lower MEMS beam electrodes and the beam oxide and, if the bending is large enough, be constrained by the lid over the MEMS beam or the fixed electrode under the MEMS beam. Constraining the MEMS beam during annealing can ‘freeze in’ an undesirable curvature, resulting in a MEMS beam that is curved (i.e., not flat). A curved MEMS beam will have reduced contact area, resulting in reduced capacitance. Additionally, if the force exerted by the MEMS beam pressing against either the fixed electrode under the beam or the lid over the beam is too high, then either the MEMS beam or the lid can crack, resulting in catastrophic failure of the MEMS device.
0071In <figref idref="DRAWINGS">FIG. 15</figref>, an insulator material <b>46</b> is deposited on the upper electrode <b>44</b> and exposed portions of the insulator material <b>40</b>. In embodiments, the insulator material <b>46</b> is deposited to a thickness of about 80 nm; although other dimensions are also contemplated by the present invention. To balance the MEMS beam, insulator material <b>46</b> over the MEMS beam should be substantially the same thickness as insulator material <b>34</b> under the MEMS beam. This thickness balancing of layers <b>34</b> and <b>46</b> should include any additional dielectric deposition on layer <b>46</b> that occurs during the subsequent vent hole dielectric deposition sealing step. A cavity via <b>48</b> is formed through the insulator materials, <b>34</b>, <b>40</b> and <b>46</b> to the underlying layer <b>18</b> by patterning and etching through the insulators. In embodiments, any unwanted oxide, such as a native oxide which is formed by exposing the silicon <b>18</b> to air, on the silicon can be cleaned using, for example, an HF acid, prior to the subsequent silicon deposition. It is desirable but not required that the sidewall angle of the cavity via <b>48</b> be tapered, to improve the subsequent silicon deposition sidewall coverage and reduce the seam or void in the silicon.
0072In <figref idref="DRAWINGS">FIG. 16</figref>, silicon layer <b>50</b> is deposited on the structure of <figref idref="DRAWINGS">FIG. 15</figref>. In embodiments, the silicon layer <b>50</b> can be deposited to a thickness of about 4 μm; although other dimensions are also contemplated by the present invention. As shown in <figref idref="DRAWINGS">FIG. 16</figref>, the silicon layer <b>50</b> is deposited such that the topography of the silicon layer <b>50</b> changes in accordance with the underlying features. The silicon layer <b>50</b> can leave a regressive profile over the vias <b>42</b> and <b>48</b>. During the subsequent oxide deposition, the oxide can fill the regressive structures in a rivet-like fashion so that there is a rivet-shaped oxide peg over the vias <b>42</b> and <b>48</b>. This riveted-shaped oxide feature in the lid can pin the MEMS beam post release. To avoid this MEMS beam pinning, either the silicon layer <b>50</b> deposition process needs to be optimized to avoid this shape (<figref idref="DRAWINGS">FIG. 30E</figref>); or a thick enough silicon <b>50</b> layer to pinch off or partially pinch off the via <b>42</b> and <b>48</b> openings is needed (<figref idref="DRAWINGS">FIG. 30D</figref>); a silicon deposition, CMP, and subsequent silicon deposition is needed similar to the one discussed for silicon layer <b>18</b> previously, or a combination of the above. Also, as shown in <figref idref="DRAWINGS">FIG. 16</figref>, the silicon layer <b>50</b> makes contact with the underlying layer <b>18</b> through the via <b>48</b>. In embodiments, due to the HF acid cleaning, there will be no oxide between the two layers of silicon (e.g., layer <b>18</b> and layer <b>50</b>). In optional embodiments, the silicon layer <b>50</b> has a 3 micron initial thickness, undergoes a 1 micron CMP removal, and has a second silicon deposition to achieve the 4 μm thickness.
0073In an optional embodiment shown in <figref idref="DRAWINGS">FIG. 17</figref>, the silicon layer <b>50</b> can undergo an optional lithographic and RIE process using a reverse mask, similar to that discussed above. This reverse mask would place photoresist over the vias <b>42</b> and <b>48</b> so that, when the silicon <b>50</b> was etched back using a RIE or wet chemical silicon etch process and subsequent resist stripping and cleaning, the topography would be reduced incoming to a subsequent CMP step. The reverse mask shapes need to fully cover the vias <b>42</b> and <b>48</b> openings, so that trenches would not be etched along their sidewalls, as previously discussed regarding <figref idref="DRAWINGS">FIG. 6</figref>.
0074<figref idref="DRAWINGS">FIG. 18A</figref> shows the patterning and etching of the silicon layer <b>50</b> using methods similar to those discussed previously in regards to <figref idref="DRAWINGS">FIG. 3</figref>. In <figref idref="DRAWINGS">FIG. 18A</figref>, the silicon layer <b>50</b> undergoes a CMP process to planarize or partially planarize the silicon surface, and thereafter a cleaning. As mentioned previously, any silicon polish process can be used and, if a process with low or no selectivity to SiO2 is used, then the likelihood of point defects on the silicon surface is eliminated. In this embodiment, the silicon layer <b>50</b> will be patterned such that the silicon layer <b>50</b> remains within the previously formed via <b>48</b> and formed trenches <b>46</b>. In embodiments, the silicon layer <b>50</b> can be planarized using a conventional CMP process with or without a reverse mask patterning and etching process. For either the CMP-only or reverse mask etchback followed by CMP, an optional second silicon deposition, preceded by a HF clean, could be performed. Alternatively, the silicon layer <b>50</b> deposition can be optimized so that it conformally fills the vias <b>42</b> and <b>48</b>; or it pinches off the vias <b>42</b> and <b>48</b>, as discussed above and below. This will ensure that the subsequent lid layer, <b>54</b>, will not extend into a rivet-like feature formed over vias <b>42</b> and <b>48</b>, which can potentially cause rubbing against a MEMS beam, as discussed above. Also, in embodiments, this process will also advantageously result in a planar or substantially planer cavity structure (e.g., flat or planar surfaces) in subsequent processing steps.
0075The optional step of <figref idref="DRAWINGS">FIG. 17</figref> can assist with the subsequent etching/planarization of the silicon layer <b>50</b>. Note that any CMP or other planarization of the silicon layer <b>50</b> cannot completely planarize all features on the wafer if an optical wavelength is used for subsequent lithographic alignment. To avoid complete planarization, the vias <b>42</b> and <b>48</b> could be stacked in areas outside the functional integrated circuit so that, even if the silicon was planarized over the vias <b>42</b> and <b>48</b>, it would not be planarized over stacked <b>42</b> and <b>48</b> via structures.
0076As shown in <figref idref="DRAWINGS">FIG. 19A</figref>, the oxide material <b>52</b> can be planarized such that oxide is left over silicon layer <b>50</b> (<figref idref="DRAWINGS">FIG. 19A</figref>), or can be planar with the underlying silicon layer <b>50</b>, similar to what was previously shown in <figref idref="DRAWINGS">FIG. 8</figref>. Whether or not the oxide layer <b>52</b> is planarized back to the surface of silicon layer <b>50</b>, additional dielectric may need to be deposited to form the required oxide lid thickness over the MEMS cavity, as discussed below. Alternatively, the oxide layer <b>52</b> can be partially planarized, as shown in <figref idref="DRAWINGS">FIG. 19B</figref>; or left unplanarized. As an optional step much like shown in <figref idref="DRAWINGS">FIG. 9A</figref>, the oxide material can be deposited to a thickness of about 5 μm, compared to the 2.3 μm, with a Si layer, for example, deposited on the thick oxide material. The Si layer (and portions of the oxide material <b>52</b>) are planarized using conventional processes such as, for example, CMP. The oxide material <b>52</b> deposition process should sufficiently fill the wire level <b>44</b> spaces such that voids in the oxide do not intersect the CMP planarized oxide surface by, for example, deposition the initial oxide film with HDPCVD oxide to fill the spaces, deposition/etch/deposition oxide, or PECVD TEOS-based oxide, either for the initial oxide deposition or the entire film. With all of these embodiments, the reverse pattern etch back step shown in <figref idref="DRAWINGS">FIG. 18A</figref> is optional.
0077If silicon layer <b>50</b> was not fully planarized, as shown in <figref idref="DRAWINGS">FIG. 16</figref>, then the oxide layer <b>52</b> surface will follow the surface topography of silicon layer <b>50</b>, as shown in <figref idref="DRAWINGS">FIG. 19<i>c</i></figref>. With the incoming topography shown in <figref idref="DRAWINGS">FIG. 19C</figref>, the oxide CMP step, with or without the reverse damascene etch back step, could not fully planarize the surface of oxide layer <b>52</b> due to the presence of vias <b>42</b> and <b>48</b>, with a resulting profile shown in <figref idref="DRAWINGS">FIG. 19D</figref>. Note that the surface profile shown in <figref idref="DRAWINGS">FIG. 19D</figref> could also have the global profile shown in <figref idref="DRAWINGS">FIG. 19B</figref> superimposed on it.
0078Alternatively, if the optional oxide etch back step etched down to the silicon surface of silicon layer <b>50</b>, then the oxide over the vias <b>42</b> and <b>48</b> would extend below the surface of silicon layer <b>50</b>. This topography over vias <b>42</b> and <b>48</b> could result in trenches in the final diced wafer surface, which could cause chip reliability problems due, for example, to water collection in the trenches during humidity-pressure stressing of the packaged chips. To avoid this problem, the oxide layer <b>52</b> could be deposited to a thickness such that the openings over vias <b>42</b> and <b>48</b> pinch off; or the oxide layer <b>52</b> could be planarized such that the final surface is planer as in <figref idref="DRAWINGS">FIG. 19A</figref>.
0079Alternatively, the reverse pattern etchback mask could be modified such that mask openings are removed in areas around the vias <b>42</b> and <b>48</b>. <figref idref="DRAWINGS">FIG. 19E</figref> shows a top view of cavity <b>50</b>, via <b>42</b>, and via <b>48</b>. If a reverse pattern etchback process was used with the vias <b>42</b> and <b>48</b> blocked (<figref idref="DRAWINGS">FIG. 19F</figref>), then the oxide would not be etched around vias <b>42</b> and <b>48</b> (<figref idref="DRAWINGS">FIG. 19G</figref>) and it would be easier to planarize or substantially planarize the surface of the oxide layer <b>52</b>. The optional oxide CMP processes used to planarize or partially planarize oxide layer <b>52</b> can scratch the surface. An example of a surface scratch RR is shown in <figref idref="DRAWINGS">FIG. 19H</figref>. These surface scratches can act as crack nucleation points after the MEMS sacrificial cavity layers <b>18</b> and <b>50</b> are vented or removed. To eliminate this problem, an optional second dielectric or oxide deposition is performed, to deposit the layer <b>400</b> shown in <figref idref="DRAWINGS">FIG. 19H</figref>.
0080In <figref idref="DRAWINGS">FIG. 20</figref>, an oxide material <b>54</b>, which determines the lid thickness before silicon venting, is shown on the surface. The oxide material <b>54</b> can have a thickness before venting of about 3 μm, for example. If the oxide layer <b>52</b> had not been removed or fully removed over silicon layer <b>50</b>, then the total oxide thickness of layers <b>52</b> and <b>54</b> would determine the lid thickness before silicon venting. In embodiments, a vent hole <b>58</b> is patterned, and opened in the oxide lid, exposing a portion of the underlying silicon layer <b>50</b>. It should be understood that more than one vent hole <b>58</b> can be formed in the oxide material <b>54</b>. The vent hole <b>58</b> can be formed using conventional lithographic and etching processes known to those of skill in the art. All of the patterned features discussed in this disclosure are patterned using conventional, e.g. steppers or proximity, lithographic tooling using photomasks, as known in the art. With conventional lithography, extra features on the masks are included to measure feature size, i.e. line width, as well as registration or overlay between the feature currently being imaged and prior level features on the wafer. These extra features are commonly placed in the dicing channel between the active chips, although they can also be placed inside the chips; or active chip features can be used. To match the printed feature to active features inside the active chip, it is important but not required that the prior level features are duplicated. For example, for the vent hole <b>58</b>, if a structure outside of the active chip is used for measuring feature size or overlay, it should be stacked over the upper silicon cavity <b>50</b> and, optionally, the other wires inside the cavity, so that the height off of the wafer and the optical properties (i.e. reflection) of the measured feature are the same as inside the active chip. This is especially important for the vent hole <b>58</b> because it has a relatively small width and, depending on the processing used to planarize the upper cavity, the upper cavity can extend 1 μm or more above the surrounding wafer surface, which can cause problems with resist scumming of vent hole <b>58</b> printed over the cavity if the vent hole resist width is measured outside of the cavity.
0081The width and height of the vent hole <b>58</b> determines the amount of material that should be deposited after silicon venting to pinch off the vent hole. In general, the amount of material that should be deposited to pinch off the vent hole <b>58</b> decreases as the vent hole width decreases; and as the vent hole aspect ratio, which is the ratio of the vent hole height to width, increases. In embodiments, a 3 μm thick pre venting lid would have a 1 μm diameter. In embodiments, the structure, and in particular, the exposed underlying silicon layer <b>50</b>, can be cleaned with an HF solution prior to venting the silicon. If the vent holes <b>58</b> have too high of an aspect ratio or if there are too few vent holes, then it is difficult to vent out the sacrificial cavity material <b>18</b> and <b>50</b>. The vent hole may be circular or nearly circular, to minimize the amount of subsequent material needed to pinch it off. In one exemplary embodiment, the vent hold is shaped in an octagon, which minimized the computational requirement as discussed above.
0082If the lid is too thin with respect to the MEMS cavity area, either post venting or during any subsequent film deposition, the lid over the evacuated or vented cavities can crack or delaminate due to high film stresses or due to MEMS beam bending up against the lid during annealing. For example, a silicon cavity 500 μm by 500 μm capped with a 1 μm oxide lid would be susceptible to cracking or delaminating after venting or after the subsequent sealing film depositions due to the residual stress of the lid oxide or the sealing films; or because the released MEMS beam pushes up against the lid during annealing. In one exemplary embodiment, approximately 1 micron of oxide lid is required per 10,000 μm<sup>2 </sup>of cavity area to avoid lid cracking after venting.
0083In <figref idref="DRAWINGS">FIG. 21A</figref>, the silicon layers <b>50</b> and <b>18</b> are vented or stripped by way of the vent hole <b>58</b>. In embodiments, the stripping (e.g., etching) can be performed using a XeF<sub>2 </sub>etchant through the vent hole <b>58</b>. The etching will strip all of the material (silicon), forming an upper cavity or chamber <b>60</b><i>a </i>and a lower cavity or chamber <b>60</b><i>b</i>, and is selective to many other materials, including SiO<sub>2</sub>. As shown in this representation, the upper cavity <b>60</b><i>a </i>and the lower cavity <b>60</b><i>b </i>have planar or nearly planer walls, due to the previous etching steps of the silicon layers <b>18</b>, <b>50</b>. An optional HF clean can be performed to remove the native oxide and hydrogen passive the exposed silicon surface prior to venting the silicon.
0084As shown in <figref idref="DRAWINGS">FIGS. 21B and 21C</figref>, the vent holes <b>58</b> can be formed at several locations, to portions (expose portions) of the upper silicon layer <b>50</b>, the lower layer <b>18</b> or both the upper and lower silicon layer <b>50</b>, <b>18</b>. For example, as shown in <figref idref="DRAWINGS">FIG. 21B</figref>, the vent holes are formed both inside and outside the cavity vias <b>48</b>. The vent holes <b>58</b> should be either round or nearly round, to minimize the amount of insulator needed to pinch them off post venting. Octagon shapes can be used instead of circles to draw the vent vias, to minimize the computational workload need to process the design data, as discussed above. In this embodiment, the etch rate of the silicon layer <b>50</b> in the upper portion <b>59</b><i>a </i>will etch faster than the silicon layer <b>18</b> in the lower portion <b>59</b><i>b</i>, thus ensuring that no undue stress is placed on the lower portion <b>59</b><i>b</i>, as shown in <figref idref="DRAWINGS">FIG. 21<i>d</i></figref>. (The upper portion <b>59</b><i>a </i>and lower portion <b>59</b><i>b </i>will form the upper cavity and lower cavity of the MEMS structure.)
0085<figref idref="DRAWINGS">FIGS. 21D and 21E</figref> show more detailed cross sectional views of <figref idref="DRAWINGS">FIGS. 21B and 21C</figref>. As shown in <figref idref="DRAWINGS">FIG. 21D</figref>, the vent holes <b>58</b> are formed to portions of both the upper and lower silicon layers <b>50</b>, <b>18</b>. In this embodiment, as seen in <figref idref="DRAWINGS">FIG. 21D</figref>, the lower layer <b>18</b> will actually support the upper portion <b>59</b><i>a</i>, since it etches at a slower rate. In <figref idref="DRAWINGS">FIG. 21E</figref>, the vent holes <b>58</b> can be formed at several locations, but mainly to (expose) the layer <b>18</b>. In this embodiment, the etch rate of the layer <b>18</b> in the lower portion <b>59</b><i>b </i>is faster than the silicon layer <b>50</b> in the upper portion <b>59</b><i>b</i>, resulting in the possibility of added stress on a MEMS beam <b>60</b> (e.g., the MEMS beam <b>60</b> may partially or wholly rip or tear out).
0086If the vent hole layout is such that the lower cavity <b>18</b> vents faster than upper cavity <b>50</b>, for example by placing the vent holes outside of the vias (cavity vias) <b>48</b> as shown in <figref idref="DRAWINGS">FIG. 21<i>c</i></figref>, then the lower cavity may vent before the upper cavity. This can cause stress-related cracking problems, as shown in <figref idref="DRAWINGS">FIG. 21C</figref>. When the lower cavity layer <b>18</b> is almost fully vented but still extends the full height of the cavity and the upper cavity silicon layer <b>50</b> is not fully vented and does extend to the full height of the upper cavity, then stress due to lid and beam upwards bending can rip out oxide <b>60</b> from the lower cavity as shown in <figref idref="DRAWINGS">FIG. 21C</figref>. For these reasons, it is desirable to place vent holes over the upper cavity such that the upper cavity vents before the lower cavity.
0087A chamfered lower cavity A and upper B cavity corner <b>405</b> is shown in <figref idref="DRAWINGS">FIG. 21F</figref> (also see, e.g., <figref idref="DRAWINGS">FIG. 21B</figref>). Chamfering the cavity corner can reduce the stress after silicon venting, resulting in reduced chance of dielectric film cracking due to temperature cycling or other stresses. A 45 degree chamfer <b>405</b> is shown; although any chamfer angle is envisioned, including a rounded corner (also represented by reference numeral <b>405</b>). As mentioned previously, chamfering as opposed to rounding corners reduces the computational complexity associated with verifying that the layout does not violate the minimum line and space rules. The vias <b>42</b> and <b>48</b> inside the cavity can also be chamfered, as discussed below. In <figref idref="DRAWINGS">FIG. 21C</figref>, the vent holes <b>58</b> can be formed at several locations, exposing the lower layer <b>18</b>. In this embodiment, the etch rate of the layer <b>18</b> in the lower portion <b>59</b><i>b </i>will be faster than the silicon layer <b>50</b> in the upper portion <b>59</b><i>b</i>. The corner of any of the wire levels can also be chamfered, <b>14</b>, <b>38</b>, <b>44</b>, as shown in <figref idref="DRAWINGS">FIG. 22</figref> to reduce overall stress.
0088As shown in <figref idref="DRAWINGS">FIG. 22</figref>, the vent hole <b>58</b> can be sealed with a material <b>62</b>, such as a dielectric or metal. If the sealing material <b>62</b> deposits a film inside the cavity on the beam, than it can potentially unbalance the stress of the MEMS beam, and also bond the lid to the beam in regions around vias, as discussed herein and shown by <b>250</b> in <figref idref="DRAWINGS">FIG. 31</figref>. To avoid this problem, in embodiments in which the vent sealing material deposits inside the cavity, the vent holes should be placed far enough away from the vias, e.g., greater than 1 micron or, in an exemplary embodiment, greater than 5 microns, so that released MEMS beam is not bonded to the lid by the vent sealing deposition. Alternatively, the vent holes can be placed in cavity areas away from the MEMS beam, so that no vent hole sealing material is deposited on the released MEMS beam. Optional layer <b>64</b> is deposited next to provide a hermetic seal. The layer <b>64</b> could be, for example, a 500 nm PECVD silicon nitride film or other films known to provide a hermetic seal over oxide layer <b>62</b>.
0089In <figref idref="DRAWINGS">FIG. 23A</figref>, a final via <b>66</b> is opened in the structure of <figref idref="DRAWINGS">FIG. 22</figref>. In embodiments, the via <b>66</b> exposes the underlying electrode <b>44</b>. In embodiments, the via <b>66</b> is formed using conventional lithographic and etching processes. In further embodiments, prior to forming the via, an optional polyimide layer <b>68</b>, for example, can be deposited on the nitride capping layer <b>64</b>. A problem with forming this final via is its height, which can be in the range of 6-12 μm, due to the planarization of the upper silicon cavity. Long dielectric RIE steps cause problems for RIE tools, due to chamber over heating or other issues; or simply because they have low parts per hour process times and are expensive.
0090<figref idref="DRAWINGS">FIGS. 23B and 23C</figref> show alternative processes for forming the via. For example, a partial via <b>66</b><i>a </i>can be formed at the same time as the vent hole <b>58</b>. After formation of the vent hole <b>58</b> (and subsequent cleaning of the silicon layer <b>50</b>, <b>18</b>) the vent hole <b>58</b> can be sealed with a dielectric material <b>62</b> and a nitride cap <b>64</b>. This option, in which the final via <b>66</b> is formed by using two separate patterning and etching steps, reduces the amount of total etch time needed to fabricate the MEMS device and also tapers the angle of the final via, thus improving the Pb-free bumping gap fill. In embodiments, an optional polyimide or other polymer coating as known in the art material <b>68</b> can be deposited on the nitride cap <b>64</b>. The dielectric material, <b>62</b>, nitride cap <b>64</b> and polyimide material <b>68</b> would also be formed in the partial via <b>66</b><i>a</i>. The remaining portion of the via <b>66</b><i>b </i>can then be formed by etching through the dielectric material, <b>62</b>, nitride cap <b>64</b> and optional polyimide material <b>68</b> to the underlying electrode <b>44</b>. As noted in this representation, the partial via <b>66</b><i>a </i>has a larger cross section than the via <b>66</b><i>b</i>. For example, the via <b>66</b><i>a </i>can be about 60 microns across (e.g., diameter); whereas, the via <b>66</b><i>b </i>has a smaller dimension, e.g., 54 microns. Also, the total height of the via (formed from via <b>66</b><i>a </i>and <b>66</b><i>b</i>) can be about 9 microns. In embodiments, the optional polyimide is opening is smaller than the oxide opening, e.g., 48 microns, to cover the corners of the oxide/nitride interface at the wire corner.
0091<figref idref="DRAWINGS">FIGS. 24A-24F</figref> show various top views of the structures fabricated in accordance with the invention. <figref idref="DRAWINGS">FIGS. 24A-24C</figref> show different cross sectional views of a first structure in accordance with the invention; whereas, <figref idref="DRAWINGS">FIGS. 24D-24F</figref> shows different cross sectional views of a second structure in accordance with the invention. More specifically, <figref idref="DRAWINGS">FIG. 24A</figref> shows a top view of cantilever beam structure having an upper cavity <b>200</b><i>a </i>and a lower cavity <b>200</b><i>b</i>. A cavity via <b>210</b> extends between the upper cavity <b>200</b><i>a </i>and the lower cavity <b>200</b><i>b</i>. In embodiments, the cavity via <b>210</b> is a “U” or “| |” shaped via, although other shapes are also contemplated by the present invention. The width of the cavity via <b>210</b> can be, for example, about 0.1 to 100 microns, whereas, a length of the via is about 1 to 1000 microns. In one exemplary embodiment, the cavity via <b>210</b> is 4 microns wide and 100 microns long. As discussed, a narrow cavity via, e.g. 2 μm wide, will pinch off during the upper silicon cavity deposition if it is thick enough, e.g. 5 μm, which reduces the extension of the lid oxide into the via.
0092Upper and lower cavities <b>200</b><i>a </i>and <b>200</b><i>b</i>, as previously described herein, can either be the same size or different sizes. The CMP processing used to form the planer lower cavity, show as <b>200</b><i>b</i>, can cause surface curvature on the cavity edge. To avoid this surface curvature from curving the bottom of the MEMS beam, the cavity via <b>48</b> should be placed so that the inside edge is beyond the curvature and is over the flat portion of the lower cavity.
0093<figref idref="DRAWINGS">FIG. 24B</figref> also shows the cavity via <b>210</b> extending between the upper cavity <b>200</b><i>a </i>and the lower cavity <b>200</b><i>b</i>. In addition, <figref idref="DRAWINGS">FIG. 24B</figref> shows first and second actuators <b>215</b>, in parallel. A capacitor head <b>220</b> is provided in relation to the first and second actuators <b>215</b>, which may be a lower fixed capacitor plate in accordance with aspects of the invention. These wires, i.e., <b>215</b> and <b>220</b>, are formed with layer <b>14</b> as shown in <figref idref="DRAWINGS">FIG. 22</figref>. Those of skill in the art should recognize that the first and second actuators (electrodes) <b>215</b> can be the electrical wires, described above. The first and second actuators (electrodes) <b>215</b> upon actuation, i.e., application of sufficient dc voltage, will cause bending of a MEMS beam.
0094<figref idref="DRAWINGS">FIG. 24C</figref> shows the cavity via <b>210</b> extending between the upper cavity <b>200</b><i>a </i>and the lower cavity <b>200</b><i>b</i>. In addition, <figref idref="DRAWINGS">FIG. 24C</figref> shows first and second actuators <b>215</b><i>a</i>, in parallel. A capacitor arm and head <b>220</b><i>a </i>is provided in relation to the first and second actuators <b>215</b><i>a</i>, which may be a lower fixed capacitor plate in accordance with aspects of the invention. The capacitor arm and head <b>220</b><i>a </i>extends from the edge of the cavity to the capacitor head, between the first and second actuators <b>215</b><i>a</i>. The MEMS capacitor is formed where element <b>220</b>, in <figref idref="DRAWINGS">FIG. 24B</figref>, intersects element <b>220</b><i>a</i>, in <figref idref="DRAWINGS">FIG. 24C</figref>. Actuators <b>215</b><i>a </i>and capacitor arm and head <b>220</b><i>a </i>in <figref idref="DRAWINGS">FIG. 24C</figref> are composed of the wires <b>38</b> and <b>44</b> in <figref idref="DRAWINGS">FIG. 22</figref>, and, as shown, are connected by the vias <b>228</b> discussed below.
0095In addition, <figref idref="DRAWINGS">FIG. 24C</figref> shows electrical vias <b>228</b>, which are connected to the lower and upper wire of the cantilever beam. The electrical vias <b>228</b> can also be connected to the capacitor arm <b>220</b><i>a</i>, extending between the actuators <b>215</b><i>a</i>. These vias are shown as <b>42</b> in <figref idref="DRAWINGS">FIG. 22</figref>.
0096Oxide pegs <b>225</b> are provided under the beam, and can extend to the capacitor arm <b>220</b><i>a</i>, as well as the actuators <b>215</b><i>a</i>. These oxide pegs <b>225</b> could also be above the actuators <b>215</b> in <figref idref="DRAWINGS">FIG. 21B</figref>. <figref idref="DRAWINGS">FIG. 24C</figref> also shows oxide pegs <b>225</b> under the beam. These oxide pegs are element <b>33</b> in <figref idref="DRAWINGS">FIG. 22</figref>. In operation, electrodes <b>215</b><i>a </i>upon actuation, will cause bending of a MEMS beam. In normal MEMS operation, an actuation voltage is applied between actuators <b>215</b> and <b>215</b><i>a</i>. For example, actuator <b>215</b> could be grounded and 50V could be applied to actuator <b>215</b><i>a; −</i>25V could be applied to actuator <b>215</b> and 25V could be applied to actuator <b>215</b><i>a; </i>50V could be applied to actuator <b>215</b> and actuator <b>215</b><i>a </i>could be grounded; etc. These MEMS layouts have four separate inputs: lower capacitor input, upper capacitor output, lower actuator, and upper actuator. These four electrodes could be combined, as known in the art. For example, the upper actuator <b>215</b><i>a </i>and capacitor <b>220</b><i>a </i>could consist of a single connected wire; the lower actuator <b>215</b> and lower capacitor <b>220</b> electrode could consist of a single wire; or both. For these simpler 2 or 3 input devices, ac signal and dc actuation would need to be decoupled by, for example, using inductors wired to ground or dc voltages on the electrodes.
0097<figref idref="DRAWINGS">FIGS. 24D-24F</figref> show different cross sectional views of a second structure in accordance with the invention. More specifically, <figref idref="DRAWINGS">FIG. 24D</figref> shows a top view of cantilever beam structure having an upper cavity <b>300</b><i>a </i>and a lower cavity <b>300</b><i>b</i>. A cavity via <b>310</b> extends between the upper cavity <b>300</b><i>a </i>and the lower cavity <b>300</b><i>b</i>. In embodiments, the cavity via <b>310</b> comprises parallel strips, although other shapes are also contemplated by the present invention. The width of the cavity via <b>310</b> can be, for example, about 0.1 to 100 microns, whereas, a length of the via is about 1 to 1000 microns. In one exemplary embodiment, the via <b>310</b> is 4 microns wide and 100 microns long.
0098<figref idref="DRAWINGS">FIG. 24E</figref> also shows the cavity via <b>310</b> extending between the upper cavity <b>300</b><i>a </i>and the lower cavity <b>300</b><i>b</i>. In addition, <figref idref="DRAWINGS">FIG. 24E</figref> shows first, second and third actuators <b>315</b>. In embodiments, the first and second actuators are in parallel and the third actuator is a lower actuator. A capacitor head <b>320</b> is between the first and second actuators, and the third (lower) actuator. The capacitor head <b>320</b> may be a lower fixed capacitor plate in accordance with aspects of the invention. These wires, i.e., <b>315</b> and <b>320</b>, are formed with layer <b>14</b> as shown in <figref idref="DRAWINGS">FIG. 22</figref>. Those of skill in the art should recognize that the first, second and third actuators (electrodes) <b>315</b> can be the electrical wires, described above. The first, second and third actuators <b>315</b>, upon actuation, will cause bending of a MEMS beam.
0099<figref idref="DRAWINGS">FIG. 24F</figref> shows the cavity via <b>310</b> extending between the upper cavity <b>300</b><i>a </i>and the lower cavity <b>300</b><i>b</i>. In addition, <figref idref="DRAWINGS">FIG. 24F</figref> shows first, second and third actuators (electrodes) <b>315</b><i>a</i>. A is provided in relation to the first, second and third actuators (electrodes) <b>315</b><i>a</i>. The capacitor head and arm <b>320</b><i>a </i>extends between the first and second actuators <b>315</b><i>a</i>. Actuators <b>315</b><i>a </i>and capacitor arm and head <b>320</b><i>a </i>in <figref idref="DRAWINGS">FIG. 24<i>f </i></figref>are composed of the wires <b>38</b> and <b>44</b> in <figref idref="DRAWINGS">FIG. 22</figref>.
0100In addition, <figref idref="DRAWINGS">FIG. 24F</figref> shows electrical vias <b>328</b>, which are connected to the lower and upper wire of the cantilever beam. The electrical vias <b>328</b> can also be connected to the capacitor arm <b>320</b><i>a</i>. Oxide pegs <b>325</b> are provided under the beam, and can extend to the capacitor arm <b>320</b><i>a</i>, as well as the lower actuator <b>315</b><i>c</i>. In operation, the first, second and third actuators (electrodes) <b>315</b>, upon actuation, will cause bending of a MEMS beam. More specifically, the lower actuator will apply the voltage to the actuators (electrodes).
0101In both cases the MEMS beam includes metal/insulator/metal with an added thin insulator layer under and over the stack if the MEMS device is a capacitor. One exemplary embodiment would use 0.5 micron lower and upper metal thickness and 2 micron insulator thickness with 80 nm insulator layer over and under the beam if the device was a capacitor. In addition, the actuators <b>215</b>, (<figref idref="DRAWINGS">FIGS. 24A-24C</figref>) or actuators <b>315</b> (<figref idref="DRAWINGS">FIGS. 24D-24F</figref>) would be connected to ground, so that, when the actuation voltage is applied to the actuators, the MEMS beam would actuate and bend down, as known in the art. Alternatively, the actuation voltage could be applied to the actuation electrodes in <figref idref="DRAWINGS">FIGS. 24C and 24F</figref> and the actuators in <figref idref="DRAWINGS">FIGS. 24B and 24C</figref> would be grounded. In another embodiment, the actuators and capacitor would be connected together and would need to be grounded using a dc ground, such as an inductor.
0102<figref idref="DRAWINGS">FIGS. 30A-30E</figref> show the upper cavity silicon <b>50</b> surface topography after a non-conformal silicon deposition step has been performed that has not pinched off the openings due to the electrical via <b>42</b> and cavity via <b>48</b>. An unbiased PVD silicon deposition would form a ‘bread loaf’ profile, as shown in <figref idref="DRAWINGS">FIG. 30A</figref>, as known in the art. <figref idref="DRAWINGS">FIGS. 30A-30E</figref> also show the oxide pegs <b>16</b><i>a</i>. The silicon layer <b>50</b> regressively, i.e., with an undercut, covers the sidewalls of the vias and, when a MEMS cavity lid material, such as SiO<sub>2 </sub>is deposited, the lid material will fill the regressive opening above the vias <b>42</b> and <b>48</b>, as discussed previously. This regressive lid formation, which is shown after the lid formation, silicon venting, and cavity sealing steps in <figref idref="DRAWINGS">FIG. 16</figref>, can pin the lid to the beam in a rivot-like fashion if the beam bends upwards after venting where the rivet-shaped feature (<b>250</b>) in the lid rubs against the beam and/or bond the rivet-like lid structure to the beam (<b>255</b>) (See, e.g., <figref idref="DRAWINGS">FIG. 31</figref>.)
0103In <figref idref="DRAWINGS">FIGS. 31-33 and 35</figref> an oxide material <b>54</b>, which determines the lid thickness before silicon venting, is shown on the surface. In embodiments, vent holes <b>58</b> are opened in the oxide lid, exposing a portion of the underlying silicon layer <b>50</b>. It should be understood that more than one vent hole <b>58</b> can be formed in the oxide material <b>54</b>. The vent holes <b>58</b> can be formed using conventional lithographic and etching processes known to those of skill in the art. The width and height of the vent holes <b>58</b> determine the amount of material that should be deposited after silicon venting to pinch off the vent hole, as discussed in more detail below. The vent holes <b>58</b> can be sealed with a material <b>62</b>, such as a dielectric or metal, as discussed above.
0104<figref idref="DRAWINGS">FIG. 34</figref> is a flow diagram of a design process used in semiconductor design, manufacture, and/or test. <figref idref="DRAWINGS">FIG. 34</figref> shows a block diagram of an exemplary design flow <b>900</b> used for example, in semiconductor IC logic design, simulation, test, layout, and manufacture. Design flow <b>900</b> includes processes, machines and/or mechanisms for processing design structures or devices to generate logically or otherwise functionally equivalent representations of the design structures and/or devices described above and shown in <figref idref="DRAWINGS">FIGS. 1-24F, 26A-28, 30A-33, 35A, and 35B</figref>. The design structures processed and/or generated by design flow <b>900</b> may be encoded on machine-readable transmission or storage media to include data and/or instructions that when executed or otherwise processed on a data processing system generate a logically, structurally, mechanically, or otherwise functionally equivalent representation of hardware components, circuits, devices, or systems. Machines include, but are not limited to, any machine used in an IC design process, such as designing, manufacturing, or simulating a circuit, component, device, or system. For example, machines may include: lithography machines, machines and/or equipment for generating masks (e.g. e-beam writers), computers or equipment for simulating design structures, any apparatus used in the manufacturing or test process, or any machines for programming functionally equivalent representations of the design structures into any medium (e.g. a machine for programming a programmable gate array).
0105Design flow <b>900</b> may vary depending on the type of representation being designed. For example, a design flow <b>900</b> for building an application specific IC (ASIC) may differ from a design flow <b>900</b> for designing a standard component or from a design flow <b>900</b> for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.
0106<figref idref="DRAWINGS">FIG. 34</figref> illustrates multiple such design structures including an input design structure <b>920</b> that is preferably processed by a design process <b>910</b>. Design structure <b>920</b> may be a logical simulation design structure generated and processed by design process <b>910</b> to produce a logically equivalent functional representation of a hardware device. Design structure <b>920</b> may also or alternatively comprise data and/or program instructions that when processed by design process <b>910</b>, generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features, design structure <b>920</b> may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer. When encoded on a machine-readable data transmission, gate array, or storage medium, design structure <b>920</b> may be accessed and processed by one or more hardware and/or software modules within design process <b>910</b> to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system such as those shown in <figref idref="DRAWINGS">FIGS. 1-24F, 26A-28, 30A-33, 35A</figref>, and <b>35</b>B. As such, design structure <b>920</b> may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer-executable code structures that when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++.
0107Design process <b>910</b> preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures shown in <figref idref="DRAWINGS">FIGS. 1-24F, 26A-28, 30A-33, 35A, and 35B</figref> to generate a netlist <b>980</b> which may contain design structures such as design structure <b>920</b>. Netlist <b>980</b> may comprise, for example, compiled or otherwise processed data structures representing a list of wires, discrete components, logic gates, control circuits, I/O devices, models, etc. that describes the connections to other elements and circuits in an integrated circuit design. Netlist <b>980</b> may be synthesized using an iterative process in which netlist <b>980</b> is resynthesized one or more times depending on design specifications and parameters for the device. As with other design structure types described herein, netlist <b>980</b> may be recorded on a machine-readable data storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium such as a magnetic or optical disk drive, a programmable gate array, a compact flash, or other flash memory. Additionally, or in the alternative, the medium may be a system or cache memory, buffer space, or electrically or optically conductive devices and materials on which data packets may be transmitted and intermediately stored via the Internet, or other networking suitable means.
0108Design process <b>910</b> may include hardware and software modules for processing a variety of input data structure types including netlist <b>980</b>. Such data structure types may reside, for example, within library elements <b>930</b> and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications <b>940</b>, characterization data <b>950</b>, verification data <b>960</b>, design rules <b>970</b>, and test data files <b>985</b> which may include input test patterns, output test results, and other testing information. Design process <b>910</b> may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc. One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process <b>910</b> without deviating from the scope and spirit of the invention. Design process <b>910</b> may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.
0109Design process <b>910</b> employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure <b>920</b> together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure <b>990</b>.
0110Design structure <b>990</b> resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g., information stored in a IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures). Similar to design structure <b>920</b>, design structure <b>990</b> preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more of the embodiments of the invention shown in <figref idref="DRAWINGS">FIGS. 1-24F, 26A-28, 30A-33, 35A, and 35B</figref>. In one embodiment, design structure <b>990</b> may comprise a compiled, executable HDL simulation model that functionally simulates the devices shown in <figref idref="DRAWINGS">FIGS. 1-24F, 26A-28, 30A-33, 35A, and 35B</figref>.
0111Design structure <b>990</b> may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure <b>990</b> may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure as described above and shown in <figref idref="DRAWINGS">FIGS. 1-24F, 26A-28, 30A-33, 35A, and 35B</figref>. Design structure <b>990</b> may then proceed to a stage <b>995</b> where, for example, design structure <b>990</b>: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.
0112The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
0113The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
0114The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims, if applicable, are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principals of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. Accordingly, while the invention has been described in terms of embodiments, those of skill in the art will recognize that the invention can be practiced with modifications and in the spirit and scope of the appended claims.
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77 transactions on the USPTO file
Allowed after 1 non-final rejection and 1 final rejection.
- Non-final rejections
- 1
- Final rejections
- 1
- RCEs
- 0
- Appeals
- 0
Over time
Point at a mark for the transactionTransactions
| Event | Code | |
|---|---|---|
| Expire PatentEXP. | EXP. | |
| Maintenance Fee Reminder MailedREM. | REM. | |
| Payment of Maintenance Fee, 4th Year, Large EntityM1551 | M1551 | |
| Recordation of Patent Grant MailedPGM/ | PGM/ | |
| Patent Issue Date Used in PTA CalculationAllowedPTAC | PTAC | |
| Email NotificationEML_NTR | EML_NTR | |
| Issue Notification MailedAllowedWPIR | WPIR | |
| Dispatch to FDCD1935 | D1935 | |
| Application Is Considered Ready for IssuePILS | PILS | |
| Correspondence Address ChangeC.AD | C.AD | |
| Issue Fee Payment VerifiedN084 | N084 | |
| Issue Fee Payment ReceivedIFEE | IFEE | |
| Email NotificationEML_NTR | EML_NTR | |
| Mail Miscellaneous Communication to ApplicantMM327 | MM327 | |
| Printer Rush- No mailingTCPB | TCPB | |
| Miscellaneous Communication to Applicant - No Action CountM327 | M327 | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Pubs Case Remand to TCPUBTC | PUBTC | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Notice of AllowanceAllowedMN/=. | MN/=. | |
| Notice of Allowance Data Verification CompletedAllowedN/=. | N/=. | |
| After Final Consideration Program Additional Consideration and/or updated searchAFAC | AFAC | |
| Reasons for AllowanceEX.R | EX.R | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| PILOT- Request for After Final Consideration ProgramRAFC | RAFC | |
| Response after Final ActionA.NE | A.NE | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Electronic Information Disclosure StatementEIDS. | EIDS. | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Final Rejection (PTOL - 326)Final rejectionMCTFR | MCTFR | |
| Final RejectionFinal rejectionCTFR | CTFR | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response after Non-Final ActionA... | A... | |
| Electronic Information Disclosure StatementEIDS. | EIDS. | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Mail Interview Summary - Applicant Initiated - TelephonicMEXAT | MEXAT | |
| Interview Summary - Applicant Initiated - TelephonicEXAT | EXAT | |
| Electronic Information Disclosure StatementEIDS. | EIDS. | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Non-Final RejectionNon-final rejectionMCTNF | MCTNF | |
| Non-Final RejectionNon-final rejectionCTNF | CTNF | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Electronic Information Disclosure StatementEIDS. | EIDS. | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Email NotificationEML_NTR | EML_NTR | |
| PG-Pub Issue NotificationPG-ISSUE | PG-ISSUE | |
| Electronic Information Disclosure StatementEIDS. | EIDS. | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Email NotificationEML_NTR | EML_NTR | |
| Application ready for PDX access by participating foreign officesCCRDY | CCRDY | |
| Application Is Now CompleteCOMP | COMP | |
| Filing ReceiptFLRCPT.O | FLRCPT.O | |
| Application Dispatched from OIPEOIPE | OIPE | |
| FITF set to NO - revise initial settingFTFI | FTFI | |
| Cleared by OIPE CSRL194 | L194 | |
| Miscellaneous Incoming LetterLET. | LET. | |
| Electronic Information Disclosure StatementEIDS. | EIDS. | |
| Patent Term Adjustment - Ready for ExaminationPTA.RFE | PTA.RFE | |
| PTO/SB/69-Authorize EPO Access to Search ResultsSREXR141 | SREXR141 | |
| Applicants have given acceptable permission for participating foreignAPPERMS | APPERMS | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| IFW Scan & PACR Auto Security ReviewSCAN | SCAN | |
| Entity Status Set To Undiscounted (Initial Default Setting or Status Change)BIG. | BIG. | |
| Initial Exam Team nnIEXX | IEXX |
7 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Lapsed due to failure to pay maintenance feeLapsedFP | FP | |
| Lapse for failure to pay maintenance feesLapsedPATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYLAPS | LAPS | |
| Information on status: patent discontinuationPATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362STCH | STCH | |
| Fee payment procedureMAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP | FEPP | |
| Maintenance fee paymentMAFP | MAFP | |
| Information on status: patent grantGrantedPATENTED CASESTCF | STCF | |
| AssignmentAS | AS |
Numbers
- Publication
- 09890039
- Publication, DOCDB
- 9890039
- Publication, EPODOC
- US9890039
- Application
- 15212896
- Application, DOCDB
- 201615212896
- Application, EPODOC
- US201615212896
Titles
- English
- Planar cavity MEMS and related structures, methods of manufacture and design structures
Patent term adjustment
- Applicant delay
- −23 days
- Net adjustment
- 0 days
Classification
- CPC, 45
- B81C1/00365
- B81C1/00476
- B81C1/00666
- B81B3/00
- B81B2201/014
- B81B3/0021
- B81B2203/0118
- B81B3/0072
- B81B2203/04
- B81C1/0015
- B81C2201/0109
- B81C1/00619
- B81C2201/0167
- B81C1/00626
- B81C2201/017
- H01H57/00
- G06F17/5068
- H01H2057/006
- G06F17/5072
- Y10T29/435
- H01H1/0036
- Y10T29/49155
- Y10T29/5313
- H01H59/0009
- Y10T29/4913
- H01L41/1136
- Y10T29/42
- B81B2201/01
- Y10T29/49126
- Y10T29/49105
- Y10T29/49121
- B81B2203/0315
- Y10T29/49002
- Y10S438/937
- B81C2201/013
- B81B3/0018
- B81C1/00349
- B81C2203/0136
- B81C2203/0172
- B81C1/00
- H01L2924/0002
- H01H59/00
- H10N30/306
- G06F2115/04
- G06F30/39
- IPC, 9
- H05K3 00
- B81C1 00
- H01L41 113
- H01H57 00
- B81B3 00
- G06F17 50
- H01H1 00
- H01H59 00
- H10N30 30
- USPC, 2
- 200181000
- 001001000