Apparatus and method for sharing function logic between functional units, and reconfigurable processor thereof

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority from Korean Patent Application No. 10-2013-0009327, filed on Jan. 28, 2013, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety for all purposes.

BACKGROUND

1. Field

Apparatuses and methods consistent with the following description relate to an apparatus and method for sharing one or more function logics.

2. Description of the Related Art

A reconfigurable processor generally includes a plurality of functional units and/or a plurality of functional modules, and it is normal that the plurality of functional units commonly perform arithmetic operations and provide output according to a mutually independent given input. However, in some cases of the arithmetic operations, a large function logic of hardware is needed, which may give rise to a difficulty in placing a corresponding arithmetic operation in multiple functional units, in terms of a die size and power consumption, and/or other practical considerations. In a case in which predetermined operations are allocated in a minority of the functional units, because one functional unit performs one arithmetic operation at a time, restrictions can be effectively caused with respect to processing performance for applications that have a plurality of corresponding arithmetic operations. In addition, there is typically a need for routing on a circuit or additional communication that transmits an input to the functional unit which is capable of processing the arithmetic operations for processing the given arithmetic operations and which acquires results. However, if there are not a plurality of the functional units to which the corresponding arithmetic operations are allocated, routing resource efficiency may drop and the performance may decrease, because input/output values must be transmitted very far in many cases. Further, the more routings are increased, the more resource efficiencies are increased, and therefore, scheduling has become increasingly difficult.

SUMMARY

One or more embodiments provide an apparatus and method for sharing a function logic between functional units or modules, and a processor thereof.

Accordingly to an aspect of an embodiment, there is provided an apparatus for sharing a function logic, the apparatus including a storage which is configured to store data which is received from at least two functional units in order to share at least one function logic, and an arbitrator which is configured to transmit the stored data to the at least one function logic, based on a scheduling rule.

The apparatus for sharing a function logic may further include an output device which is configured to transmit at least one result which is obtained by the at least one function logic via processing the data which is transmitted by the arbitrator to each of the at least two functional units.

The output device may include a buffer which is configured to temporarily store the obtained at least one result.

The output device may be further configured to store the obtained at least one result in the buffer for a predetermined amount of time, and then to transmit the at least one result to each of the at least two functional units.

The at least two functional units may be included in at least one reconfigurable processor.

Each respective one of the at least two functional units may belong to a corresponding one of at least two functional unit groups which are configured to concurrently process at least two tasks in one reconfigurable processor.

The storage may include at least two queues which respectively correspond to the at least two functional units, and which are configured to store the data to be transmitted from each of the at least two functional units to the at least one function logic.

The storage may include at least one queue which is configured to store data to be transmitted to the at least one function logic from at least one hardware device that shares the at least one function logic.

Each of the at least one function logic may be configured to perform a same operation.

According to an aspect of another embodiment, there is provided a reconfigurable processor including a plurality of functional units, at least two queues which are respectively configured to store data which is received from a corresponding one of at least two functional units from among the plurality of functional units, the at least two functional units being connected in order to share at least one function logic, an arbitrator which is configured to transmit the stored data to the at least one function logic, based on a scheduling rule, and an output device which is configured to transmit at least one result which is obtained by the at least one function logic via processing the data which is transmitted by the arbitrator to each of the at least two functional units.

The output device may include a buffer which is configured to temporarily store the obtained at least one result and, based on a scheduling rule, to store the obtained at least one result in the buffer for a predetermined amount of time, and to transmit the obtained at least one result to each of the at least two functional units.

Each of the plurality of functional units may be designated as belonging to a respective one of at least two functional unit groups which are configured to concurrently process at least two tasks, and each respective one of the at least two functional units may be included in a corresponding one of the at least two functional unit groups.

According to an aspect of another embodiment, there is provided a method for sharing a function logic, the method including storing data, which is received from at least two functional units in order to share at least one function logic in a respective one of at least two queues which correspond to the at least two functional units, and transmitting the stored data to the at least one function logic based on a scheduling rule.

The method may further include transmitting at least one result which is obtained by the at least one function logic via processing the transmitted data to each of the at least two functional units.

The transmitting the obtained at least one result to each of the at least two functional units may include storing the obtained at least one result in a buffer for a predetermined amount of time.

The at least two functional units may be included in at least one reconfigurable processor.

Each respective one of the at least two functional units may belong to a corresponding one of at least two functional unit groups which are configured to concurrently process at least two tasks in one reconfigurable processor.

Each of the at least one function logic may be configured to perform a same operation.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and/or other aspects will be more apparent by describing in detail exemplary embodiments, with reference to the accompanying drawings, in which:

<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram which illustrates an apparatus for sharing a function logic according to an exemplary embodiment;

<figref idref="DRAWINGS">FIG. 2</figref> is a diagram which illustrates an apparatus for sharing a function logic according to an exemplary embodiment;

<figref idref="DRAWINGS">FIG. 3</figref> is a diagram which illustrates an apparatus for sharing a function logic according to another exemplary embodiment;

<figref idref="DRAWINGS">FIG. 4</figref> is a diagram which illustrates an apparatus for sharing a function logic according to another exemplary embodiment;

<figref idref="DRAWINGS">FIG. 5</figref> is a diagram which illustrates an apparatus for sharing a function logic according to another exemplary embodiment;

<figref idref="DRAWINGS">FIG. 6</figref> is a block diagram which illustrates a reconfigurable processor according to an exemplary embodiment; and

<figref idref="DRAWINGS">FIG. 7</figref> is a flow chart which illustrates a method for sharing a function logic according to an exemplary embodiment.

DETAILED DESCRIPTION

The following description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. Accordingly, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be suggested to those of ordinary skill in the art. Also, descriptions of well-known functions and constructions may be omitted for increased clarity and conciseness. Throughout all descriptions of the specification, an identical reference number refers to an identical component.

Throughout the drawings and the detailed description, unless otherwise described, the same drawing reference numerals will be understood to refer to the same elements, features, and structures. The relative size and depiction of these elements may be exaggerated for clarity, illustration, and convenience.

Examples of an apparatus and method for sharing a function logic, and reconfigurable processor are provided hereafter in detail, referring to figures as illustrated.

<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram which illustrates an apparatus for sharing a function logic according to an exemplary embodiment. In general, when designing a reconfigurable processor, a function logic which is able to perform a predetermined operation may be included only within a range of a predetermined number thereof, because of restrictions relating to practical considerations, such as, for example, a die size. In an exemplary embodiment, an apparatus <b>100</b> for sharing a function logic may enable one or more functional units FU<b>0</b> and FU<b>1</b> to share a function logic <b>140</b> that processes a predetermined operation, as shown in <figref idref="DRAWINGS">FIG. 1</figref>, and thereby allow an increase in the number of functional units that support the predetermined operation, while causing only minimal overhead due to sharing.

Referring to <figref idref="DRAWINGS">FIG. 1</figref>, an apparatus <b>100</b> for sharing a function logic includes a storage unit (also referred to herein as a storage) <b>110</b>, an arbitration unit (also referred to herein as an arbitrator) <b>120</b> and an output unit (also referred to herein as an output device) <b>130</b>.

A storage unit <b>110</b> stores data from two or more functional units FU <b>0</b> and FU <b>1</b> that share a function logic <b>140</b> which processes the data. In particular, the storage unit <b>110</b> may include two or more queues that respectively correspond to two or more functional units FU<b>0</b> and FU<b>1</b>, and data which is received from each functional unit may be stored in the particular queue which corresponds to the particular functional unit. The storage <b>110</b> may be embodied as a storage device, such as, for example, any device or component which is configured for storing data. The functional units are configured to execute a particular function, and may be embodied as hardware modules or components, such as processors or dedicated circuitry, or as software modules or programs.

An arbitration unit <b>120</b> may transmit, to the function logic <b>140</b>, pieces of data which have been inputted to the storage unit <b>110</b> from each of the functional units FU <b>0</b> and FU <b>1</b>, in order to be shared, according to a scheduling rule, and thereby help the function logic <b>140</b> to process the data. In particular, the scheduling rule may include information which relates to an order to transmit data which is received from each functional unit to the function logic <b>140</b> to be shared. The arbitration unit <b>120</b> may transmit data which is inputted to each queue, to the function logic <b>140</b>, based on the information which relates to the order. The arbitrator <b>120</b> is configured to perform an arbitration function, and may be embodied, for example, as a hardware component or module, such as a processor or dedicated circuitry, or as a software module or program.

Further, in an exemplary embodiment, the function logic <b>140</b> to be shared may include two or more function logics, and in case of being designed to share two or more function logics <b>140</b>, each function logic <b>140</b> may process an identical operation. In this aspect, a design which is configured to share two or more function logics <b>140</b>, which process the identical operation, will perform faster processing than a design which is configured to process the identical operation after the arbitration unit <b>120</b> transmits data which has been inputted to each queue to one of the function logics <b>140</b>.

In addition, in an exemplary embodiment, a function logic <b>140</b> which is configured to process a predetermined operation may be connected to an arbitration unit <b>120</b> and an output unit <b>130</b> by being included on the outside of the hardware of an apparatus <b>100</b> for sharing a function logic, as illustrated in <figref idref="DRAWINGS">FIG. 1</figref>. Further, in another exemplary embodiment, a function logic may be designed as one element of the apparatus <b>100</b> for sharing a function logic.

An output unit <b>130</b> transmits one or more results, which are obtained by the function logic <b>140</b> via processing of data which has been transmitted by the arbitration unit <b>120</b>, to a functional unit which has received and stored the data in the storage unit <b>110</b>. For example, when the arbitration unit <b>120</b> transmits data which has been stored by one functional unit FU <b>0</b> to the function logic <b>140</b> according to the scheduling rule, the results, which the function logic <b>140</b> obtains by processing the data, are returned to the functional unit FU <b>0</b>. The output unit <b>130</b> may embodied, for example, as a hardware device or component which is configured to provide an output, or as a software module or program which is configured to provide an output.

The output unit <b>130</b> may include a buffer (not illustrated) which temporarily stores the results obtained via processing performed by the function logic <b>140</b>. If the results obtained from the processing performed by the function logic <b>140</b> are outputted, the output unit <b>130</b> determines whether to transmit the results to the corresponding functional unit after delaying for a predetermined amount of time based on the scheduling rule, and if a predetermined amount of time for delay is required, the output unit <b>130</b> stores the processing results in the buffer. Afterward, if a predetermined amount of time passes, the output unit <b>130</b> may transmit the processing results which are stored in the buffer to the corresponding functional unit.

The functional unit which receives the processing results from the output unit <b>130</b> may use the results for processing the next operation. Further, the functional unit may transmit the received results to a register file or to another functional unit, so that the other functional unit can use the results to process another operation.

In another exemplary embodiment, the apparatus <b>100</b> for sharing a function logic may be designed to have one or more reconfigurable processors and corresponding hardware which facilitates a sharing of the functional unit, by being placed on the outside of a reconfigurable processor. Further, the reconfigurable processor may be embodied as one module.

<figref idref="DRAWINGS">FIG. 2</figref> is a diagram which illustrates an apparatus for sharing a function logic according to an exemplary embodiment.

Referring to <figref idref="DRAWINGS">FIG. 2</figref>, in an exemplary embodiment, one reconfigurable processor <b>20</b> may be designed to share one function logic via an apparatus <b>200</b> for sharing function logic. In particular, two or more functional units FU_0,1, FU_2,3which are included in one reconfigurable processor <b>20</b> may be connected to a storage unit <b>210</b> and an output unit <b>230</b> of the apparatus <b>200</b> for sharing function logic in order to share one function logic <b>240</b>.

A storage unit <b>210</b> may include two or more queues Q<b>1</b> and Q<b>2</b>, each of which stores respective data which received from a corresponding functional unit FU_0,1and FU_2,3, which share a function logic <b>240</b>. The storage unit <b>210</b> stores data which is received from each functional unit FU_0,1, FU_2,3, in each corresponding queue Q<b>1</b> and Q<b>2</b>. The data which is received from each functional unit FU_0,1and FU_2,3may be held temporarily after being stored in the corresponding queue Q<b>1</b> and Q<b>2</b>, until being transmitted to a function logic <b>240</b> after being selected by an arbitration unit <b>220</b>.

The arbitration unit <b>220</b> may include a multiplexer, and may determine the following data to be processed from among data which is being temporarily held in each queue Q<b>1</b> and Q<b>2</b>, according to a scheduling rule. Then, the arbitration unit <b>220</b> may transmit the determined data to the function logic <b>240</b>.

The function logic <b>240</b> performs a predetermined operation by using data which is received from the arbitration unit <b>220</b>, and outputs processed and obtained results.

If the results are outputted from the function logic <b>240</b>, an output unit <b>230</b> transmits the results to a corresponding functional unit, that is, a functional unit which has inputted the data to be transmitted to the function logic <b>240</b> by the arbitration unit <b>220</b> in a queue.

In an exemplary embodiment, the output unit <b>230</b> may include a buffer, which is not illustrated in <figref idref="DRAWINGS">FIG. 2</figref>, and if the processing results are to be transmitted to the corresponding functional unit after a predetermined amount of time passes, the results may be temporarily stored in the buffer.

As illustrated in <figref idref="DRAWINGS">FIG. 2</figref>, if an input of the function logic <b>240</b> is generated in functional unit FU_0,0of one reconfigurable processor <b>20</b>, it is more efficient to transmit the generated input directly to the function logic via FU_0,1, which is relatively close to FU_0,0, than to transmit the generated input to the function logic via FU_2,3, which is relatively further away from the FU_0,0, with respect to a transmission time and a communication resource.

Referring to <figref idref="DRAWINGS">FIG. 2</figref> as mentioned above, in an exemplary embodiment, the apparatus <b>200</b> for sharing a function logic may be designed as a hardware device which is separate from one reconfigurable processor <b>20</b>. Further, in another exemplary embodiment, an apparatus for sharing a function logic is capable of being designed to be included in one reconfigurable processor <b>20</b> as one configuration module.

<figref idref="DRAWINGS">FIG. 3</figref> and <figref idref="DRAWINGS">FIG. 4</figref> are diagrams which illustrate an apparatus for sharing a function logic according to other exemplary embodiments.

As illustrated in <figref idref="DRAWINGS">FIG. 3</figref>, in another exemplary embodiment, two or more reconfigurable processors <b>31</b> and <b>32</b>, and hardware <b>33</b> that processes an additional operation, and the like, may be designed to share one function logic <b>340</b> via an apparatus <b>300</b> for sharing a function logic. In this exemplary embodiment, the apparatus <b>300</b> for sharing a function logic may be designed as separate hardware in order to enable a plurality of reconfigurable processors <b>31</b> and <b>32</b> and/or the hardware <b>33</b> that processes an additional operation, and the like, to share a function logic <b>240</b>.

An apparatus <b>300</b> for sharing a function logic may include a storage unit <b>310</b>, an arbitration unit <b>320</b> and an output unit <b>330</b>. Specific descriptions are omitted hereafter because each component of the apparatus <b>300</b> for sharing a function logic may be understood similarly as described above.

Further, as illustrated in <figref idref="DRAWINGS">FIG. 4</figref>, in another exemplary embodiment, a plurality of functional units FU₀, FU₁, FU₂, FU₃, and FU₄may be designed to share two or more function logics <b>400</b><i>a </i>and <b>400</b><i>b </i>via an apparatus <b>400</b> for sharing a function logic. In particular, the plurality of functional units FU₀to FU₄may be included in one reconfigurable processor, or each in two or more reconfigurable processors. In addition, each of the two or more function logics <b>440</b><i>a </i>and <b>440</b><i>b </i>may include a function logic which is configured to process an identical operation.

As described above, in a case where the two or more function logics <b>440</b><i>a </i>and <b>440</b><i>b </i>are capable of being configured in hardware, a waiting time of data which has been inputted to each queue of a storage unit <b>410</b> may be decreased if the operation is processed by sharing all the two or more function logics <b>440</b><i>a </i>and <b>440</b><i>b</i>. In particular, the data inputted to each queue of the storage unit <b>410</b> may be transmitted to the two or more function logics <b>440</b><i>a </i>and <b>440</b><i>b </i>by an arbitration unit <b>420</b>, and then be processed in the two or more function logics <b>440</b><i>a </i>and <b>440</b><i>b</i>, and because results that are promptly processed by the two or more function logics <b>440</b><i>a </i>and <b>440</b><i>b </i>are transmitted to a corresponding functional unit by an output unit <b>430</b>, a processing performance may be increased as compared with being processed by only one function logic.

<figref idref="DRAWINGS">FIG. 5</figref> is a diagram which illustrates an apparatus for sharing a function logic according to another exemplary embodiment.

Referring to <figref idref="DRAWINGS">FIG. 5</figref>, one reconfigurable processor <b>50</b> may include two or more functional unit groups <b>51</b> and <b>52</b> in order to process two or more threads or tasks at the same time. In particular, a functional unit group <b>51</b> which is configured to process one of threads or tasks, and another functional unit group <b>52</b> which is configured to process other threads or tasks therewith at the same time, may all require results which are processed and obtained from a function logic <b>540</b> which processes predetermined operations. In this case, the function logic <b>540</b> may be shared by connecting predetermined functional units FU_0,1and FU_2,3which are included in each of functional unit groups <b>51</b> and <b>52</b> to an apparatus <b>500</b> for sharing a function logic.

In this exemplary embodiment, the apparatus <b>500</b> for sharing a function logic may include a storage unit <b>510</b>, an arbitration unit <b>520</b>, and an output unit <b>530</b>. The specific description hereafter may be omitted because each component of the apparatus <b>500</b> for sharing a function logic may be understood according to the exemplary embodiments described above.

Generally, a general reconfigurable processor performs one task or one thread at a time. This is because processing several tasks or threads may be difficult due to a limitation of resources, such as a case of only one or a few functional units which process a predetermined operation. However, in the apparatus for sharing a function logic described above, the reconfigurable processor is capable of processing simultaneously by selecting tasks which have low parallelism of a command level, or which is easy or advantageous for scheduling in a relatively small-sized functional unit group. In addition, without assignment of high-cost-of-hardware operations to each functional unit group, such operations can be assigned to only one or a few functional units and be shared among all functional unit groups, and thereby cost reduction can be realized.

<figref idref="DRAWINGS">FIG. 6</figref> is a block diagram which illustrates a reconfigurable processor according to an exemplary embodiment.

Referring to <figref idref="DRAWINGS">FIG. 1</figref>, <figref idref="DRAWINGS">FIG. 2</figref>, <figref idref="DRAWINGS">FIG. 3</figref>, <figref idref="DRAWINGS">FIG. 4</figref>, <figref idref="DRAWINGS">FIG. 5</figref>, and <figref idref="DRAWINGS">FIG. 6</figref>, various exemplary embodiments of an apparatus for sharing a function logic are described above. The apparatus for sharing a function logic may be designed as hardware which is separate from one or more reconfigurable processors. However, in an exemplary embodiment illustrated in <figref idref="DRAWINGS">FIG. 6</figref>, the apparatus may be designed to be included in one reconfigurable processor.

Referring to <figref idref="DRAWINGS">FIG. 6</figref>, a reconfigurable processor may include a plurality of functional units <b>61</b>, two or more queues <b>62</b>, an arbitration unit <b>63</b>, and an output unit <b>64</b>.

Similarly as described above with reference to <figref idref="DRAWINGS">FIG. 2</figref>, a reconfigurable processor <b>60</b> may be designed or configured to have two or more functional units out of a plurality of functional units <b>61</b> share a function logic <b>65</b>, so as to process an operation by sharing the function logic <b>65</b> which processes a predetermined operation.

A predetermined functional unit <b>61</b> or a functional unit which is connected to a function logic of the reconfigurable processor <b>60</b> may transmit data which has been received by the function logic <b>65</b> to a queue <b>62</b> via the connected functional unit, if the predetermined operation is required by the function logic <b>65</b>.

Some of the data transmitted to and stored in the queue <b>62</b> is selected and transmitted by the arbitration unit <b>63</b> to the function logic <b>65</b>, and the function logic <b>65</b> processes the transmitted data. The function logic <b>65</b> performs an operation by using the transmitted data and outputs operation results.

The output unit <b>64</b> transmits the operation results from the function logic <b>65</b> to the original functional unit <b>61</b>. Although not illustrated, the output unit <b>64</b> may include a temporary buffer, and the operation results from the function logic <b>65</b> may be transmitted to the functional unit <b>61</b> after being stored in the temporary buffer for a predetermined amount of time.

Further, similarly as described above with reference to <figref idref="DRAWINGS">FIG. 5</figref>, the reconfigurable processor <b>60</b> may separate a plurality of functional units <b>61</b> into two or more functional unit groups, so as to process two or more threads or tasks at the same time, and may process two or more threads simultaneously by connecting the respective functional unit which is included in each corresponding functional unit group to the function logic <b>61</b>.

<figref idref="DRAWINGS">FIG. 7</figref> is a flow chart which illustrates a method for sharing a function logic according to an exemplary embodiment.

Referring to <figref idref="DRAWINGS">FIG. 7</figref>, a method for sharing a function logic which is performable by using the apparatus <b>100</b> for sharing a function logic as illustrated in <figref idref="DRAWINGS">FIG. 1</figref> is described hereafter.

In operation <b>710</b>, the apparatus <b>100</b> for sharing a function logic stores data which is received from two or more functional units or data which is received from the hardware in two or more corresponding queues. In particular, the two or more functional units may be included in one reconfigurable processor. Alternatively, each of the two or more functional units may be respectively included in a corresponding one of two or more reconfigurable processors. Further, each of the two or more functional units may be included in a respective functional unit group, if separated into two or more functional unit groups in order to process two or more threads or tasks at the same time in one reconfigurable processor.

Then, in operation <b>720</b>, the apparatus <b>100</b> for sharing a function logic may transmit data which is stored in each queue to at least one function logic which processes a predetermined operation, based on a scheduling rule. The scheduling rule may include information which relates to a processing order of data which is received from each functional unit. The at least one function logic may include more than one function logic, and if designed to share two or more function logics, each function logic may perform an identical operation. The apparatus <b>100</b> is capable of processing promptly by processing the predetermined operation by sharing two or more function logics which process the identical operations.

Finally, in operation <b>730</b>, the apparatus transmits processed and obtained results from the at least one function logic to the corresponding functional unit. Further, the processed and obtained results may be transmitted to the corresponding functional unit after being stored in a temporary buffer for a predetermined amount of time.

The methods and/or operations described above may be recorded, stored, or fixed in one or more transitory or non-transitory computer-readable storage media that includes program instructions to be implemented by a computer to cause a processor to execute or perform the program instructions. The media may also include, alone or in combination with the program instructions, data files, data structures, and the like.

Examples of computer-readable storage media include magnetic media, such as hard disks, floppy disks, and magnetic tape; optical media such as compact disk—read-only memory (CD ROM) disks and digital versatile disks (DVDs); magneto-optical media, such as optical disks; and hardware devices that are specially configured to store and perform program instructions, such as read-only memory (ROM), random access memory (RAM), flash memory, and the like. Examples of program instructions include machine code, such as that produced by a compiler, and files containing higher level code that may be executed by the computer by using an interpreter. The described hardware devices may be configured to act as one or more software modules in order to perform the operations and methods described above, or vice versa. In addition, a computer-readable storage medium may be distributed among computer systems connected through a network and computer-readable codes or program instructions may be stored and executed in a decentralized manner. Further, functional programs, codes and code segments to implement those exemplary embodiments may be easily inferred by programmers who are skilled in the related art.

Those who are skilled in the related art may understand that various and specific modifications may be made without modifying the technical ideas or essential characteristics of the present inventive concept. Accordingly, the embodiments disclosed above are exemplary, and should be understandable not to be limited to in all aspects.