Tap dual port router circuitry with gated shiftDR and clockDR

REFERENCE TO RELATED DISCLOSURES

This application is a Divisional of prior application Ser. No. 14/978,752, filed Dec. 22, 2015, now U.S. Pat. No. 9,513,336, issued Dec. 6, 2016;

Which was a divisional of prior application Ser. No. 14/547,830, filed Nov. 19, 2014, now U.S. Pat. No. 9,261,559, issued Apr. 16, 2016;

Which was a divisional of prior application Ser. No. 13/587,522, filed Aug. 16, 2012, now U.S. Pat. No. 8,924,802, issued Dec. 30, 2014;

And claims priority from Provisional Application No. 61/524,632, filed Aug. 17, 2011.

This disclosure is related to pending application Ser. No. 13/188,078 and U.S. Pat. Nos. 7,404,129 and 7,346,821.

FIELD OF THE DISCLOSURE

This disclosure relates generally to three dimensional (3D) stacked die and specifically to a test architecture that supports the testing of die in the 3D stack.

BACKGROUND OF THE DISCLOSURE

Integrated circuit die may be designed such that they may be stacked on top of one another to form a stacked die arrangement for mounting on a system substrate, such as, but not limited to, a printed circuit board. Prior to assembling a stacked die, each die to be stacked must be tested to ensure goodness. After a stacked die is assembled, it must be tested again to ensure the goodness of the assembly.

Testing of the individual die is typically done by a die tester. Testing of the stacked die assembly is typically done by a stacked die assembly tester. The test architecture designed into the die must be capable of supporting both the testing of the individual die on the die tester and the testing of the final stacked die assembly on the stacked die tester. The present disclosure describes a test architecture that supports both individual die testing and final stacked die assembly testing.

BRIEF SUMMARY OF THE DISCLOSURE

This disclosure describes a test architecture that supports the testing of individual die and 3D stacked die arrangements.

BRIEF DESCRIPTIONS OF THE VIEWS OF THE DRAWINGS

<figref idref="DRAWINGS">FIG. 1</figref> illustrates an IEEE Test Access Port (TAP).

<figref idref="DRAWINGS">FIG. 2</figref> illustrates the state diagram of the TAP.

<figref idref="DRAWINGS">FIG. 3</figref> illustrates a TAP capture and shift operation.

<figref idref="DRAWINGS">FIG. 4</figref> illustrates a TAP capture, shift and update operation.

<figref idref="DRAWINGS">FIG. 5</figref> illustrates an improved TAP design of the disclosure.

<figref idref="DRAWINGS">FIG. 6</figref> illustrate a dual port router (DPR) of the disclosure.

<figref idref="DRAWINGS">FIG. 7</figref> illustrate an improved TAP capture and shift operation.

<figref idref="DRAWINGS">FIG. 8</figref> illustrate a DPR of the disclosure.

<figref idref="DRAWINGS">FIG. 9</figref> illustrate an improved TAP capture, shift and update operation.

<figref idref="DRAWINGS">FIG. 10</figref> illustrates a test architecture of the disclosure.

<figref idref="DRAWINGS">FIG. 11</figref> illustrate stacked die using bond wires.

<figref idref="DRAWINGS">FIG. 12</figref> illustrates stacked die using through silicon vias (TSVs).

<figref idref="DRAWINGS">FIG. 13A</figref> illustrates a test architecture of the disclosure.

<figref idref="DRAWINGS">FIGS. 13B-13E</figref> illustrates various test control signal gating circuits of the disclosure.

<figref idref="DRAWINGS">FIG. 14</figref> illustrates a test architecture of the disclosure.

<figref idref="DRAWINGS">FIG. 15</figref> illustrates a die stack according to the disclosure.

<figref idref="DRAWINGS">FIG. 16</figref> illustrates a die stack according to the disclosure.

<figref idref="DRAWINGS">FIG. 17</figref> illustrates a test architecture of the disclosure.

<figref idref="DRAWINGS">FIG. 18</figref> illustrates test circuit of the disclosure.

<figref idref="DRAWINGS">FIG. 19</figref> illustrates a compare circuit of the disclosure.

<figref idref="DRAWINGS">FIG. 20</figref> illustrates a maskable compare circuit of the disclosure.

<figref idref="DRAWINGS">FIG. 21</figref> illustrates a test architecture of the disclosure.

<figref idref="DRAWINGS">FIG. 22</figref> illustrates a die stack according to the disclosure.

<figref idref="DRAWINGS">FIG. 23</figref> illustrates a test architecture of the disclosure.

<figref idref="DRAWINGS">FIG. 24</figref> illustrates a test architecture of the disclosure.

<figref idref="DRAWINGS">FIG. 25</figref> illustrates a test architecture of the disclosure.

<figref idref="DRAWINGS">FIG. 26</figref> illustrates a multiple TAP Domain architecture of the disclosure.

<figref idref="DRAWINGS">FIG. 27</figref> illustrates a die stack according to the disclosure.

DETAILED DESCRIPTION OF THE DISCLOSURE

<figref idref="DRAWINGS">FIG. 1</figref> illustrates a die <b>100</b> including a conventional IEEE 1149.1 test architecture. The architecture includes a TAP State Machine (TSM), an instruction register <b>104</b>, data registers <b>1</b>-N <b>106</b> including a bypass register and boundary register, TDO multiplexer circuitry <b>108</b> and a router for navigating control signals from the TSM to a target data register. The die has inputs for a TDI, TCK and TMS signal and an output for a TDO signal. The TSM inputs the TCK and TMS signals, and outputs data register control (DRC) to the router, instruction register control (IRC) to the instruction register and a Select signal to the TDO multiplexer circuitry. The instruction register inputs the TDI signal and the IRC signals and outputs control on an instruction register output (IRO) bus and a TDO signal to the TDO output via the TDO multiplexer. Each data register inputs the TDI signal, DRC inputs from the router and outputs a TDO signal to the TDO output via the TDO multiplexer. During instruction scan operations, the TSM controls the instruction register to capture instruction data, shift instruction data from TDI to TDO and update the instruction data from the instruction register. During data scan operations the TSM controls a data register selected by the current instruction to capture data, shift data from TDI to TDO and update data from the data register.

<figref idref="DRAWINGS">FIG. 3</figref> illustrates a first example router circuit <b>110</b> that can be enabled by the IRO bus to control capture and shift operations to a data register <b>106</b>. In this example, the router circuit couples ClockDR and ShiftDR signals <b>302</b> from the DRC output bus of TSM <b>102</b> to ClockDR and ShiftDR signals <b>304</b> to the DRC input bus of the data register, via gating circuits <b>308</b> and <b>310</b>. The ClockDR provides the clock input to the data register and the ShiftDR signal provides the capture or shift input to the data register. The repeating TSM state transitions <b>306</b> to access the data register is indicated in <figref idref="DRAWINGS">FIG. 3</figref>. As shown there are dead states (dotted line box states) in the repeating TSM state transitions. For example, there are 3 dead states between the last ShiftDR operation and the CaptureDR operation. This prevents the TSM from being able to perform at speed shift and capture operations. This is a well known TSM testing limitation.

<figref idref="DRAWINGS">FIG. 4</figref> illustrates a second example router circuit <b>110</b> that can be enabled by the IRO bus to control capture, shift and update operations to a data register <b>106</b>. In this example, the router circuit couples ClockDR, ShiftDR and UpdateDR signals <b>402</b> from the DRC output bus of TSM <b>102</b> to ClockDR, ShiftDR and UpdateDR signals <b>404</b> to the DRC input bus of the data register, via gating circuits <b>408</b>-<b>412</b>. The ClockDR provides the clock input to the data register, the ShiftDR signal provides the capture or shift input to the data register and the UpdateDR signal provides the update input to the data register. The repeating TSM state transitions <b>406</b> to access the data register is indicated in <figref idref="DRAWINGS">FIG. 4</figref>. As shown there are dead states (dotted line box states) in the repeating TSM state transitions. For example, there is a dead state between the last ShiftDR operation and the UpdateDR operation and another dead state between the UpdateDR operation and the CaptureDR operation. Thus at speed shift and update operations and at speed update and capture operations cannot be performed using TSM state transitions. This is a well known TSM testing limitation.

The following disclosure provides a die test architecture that includes an improved TAP in combination with a parallel test input and output mechanism for facilitating the testing of functional circuits within the die.

<figref idref="DRAWINGS">FIG. 5</figref> illustrates a die <b>500</b> including the improved TAP architecture of the disclosure. The TAP architecture is identical to the TAP architecture of <figref idref="DRAWINGS">FIG. 1</figref> with the exception that the router <b>102</b> of <figref idref="DRAWINGS">FIG. 1</figref> has been replaced with a dual port router (DPR) <b>502</b>. The TAP architecture of <figref idref="DRAWINGS">FIG. 5</figref> also includes two new inputs, a Capture (CPT) input and an Update (UPD) input. The first input port <b>504</b> of the DPR is coupled to the DRC outputs from the TSM and the second input port <b>506</b> of the DPR is coupled to the CPT and UPD inputs. The DRC outputs of the DPR are coupled to respective data registers <b>106</b>. The DPR inputs IRO signals from the instruction register. During instruction scan operations, the TSM controls the instruction register to capture instruction data, shift instruction data from TDI to TDO and update the instruction data from the instruction register.

During data scan operations when the IRO bus selects the first input port <b>504</b> of the DPR, the TSM controls a data register selected by the current instruction to capture data, shift data from TDI to TDO and update data from the data register. When the first port of the DPR is selected, the TAP architecture of <figref idref="DRAWINGS">FIG. 5</figref> operates exactly like the TAP architecture of <figref idref="DRAWINGS">FIG. 1</figref>. However, during data scan operations when the IRO bus selects the second input port of the DPR, the TSM controls the shifting of a selected data register between TDI and TDO, but the capture and update operations of the data register are controlled by the CPT and UPD inputs, respectively.

<figref idref="DRAWINGS">FIG. 6</figref> illustrates a first example DPR circuit <b>502</b> that can be enabled by the IRO bus to control capture and shift operations to a data register <b>106</b>. As seen, the example DPR circuit is identical to the example router circuit of <figref idref="DRAWINGS">FIG. 3</figref> with the exception that a multiplexer has been placed on ShiftDR input of gate <b>308</b>. When the ShiftDR output signal of bus <b>304</b> is to be controlled by the ShiftDR input signal of bus <b>302</b>, the IRO input will enable the gates and will set the multiplexer to input the ShiftDR signal from the TSM to gate <b>308</b>. When the ShiftDR output signal of bus <b>304</b> is to be controlled by the CPT input signal, the IRO input will enable the gates and will set the multiplexer to input the CPT signal to gate <b>308</b>.

<figref idref="DRAWINGS">FIG. 7</figref> illustrates the timing diagram of performing capture and shift operations using the CPT input. As seen the TSM will go to and remain in the ShiftDR state (TMS=0) to cause data to shift through the data register from TDI to TDO. At appropriate times during the shifting the CPT signal will be asserted, to cause a capture operation to occur, then de-asserted to resume shifting. As seen, there are no dead states in the capture and shift operations when using the CPT signal, as there were in the <figref idref="DRAWINGS">FIG. 3</figref> timing example <b>306</b>.

<figref idref="DRAWINGS">FIG. 8</figref> illustrates a first example DPR circuit <b>502</b> that can be enabled by the IRO bus to control capture, shift and update operations to a data register <b>106</b>. As seen, the example DPR circuit is identical to the example router circuit of <figref idref="DRAWINGS">FIG. 4</figref> with the exception that a multiplexer <b>804</b> has been placed on ShiftDR input of gate <b>410</b> and a multiplexer <b>802</b> has been place on the UpdateDR input of gate <b>408</b>. When the ShiftDR and UpdateDR output signals of bus <b>404</b> are to be controlled by the ShiftDR and UpdateDR inputs of bus <b>402</b>, the IRO input will enable gates <b>408</b>-<b>412</b> and will set the multiplexers to input the ShiftDR and UpdateDR signals from the TSM to gates <b>408</b> and <b>410</b>. When the ShiftDR and UpdateDR output signals of bus <b>404</b> are to be controlled by the CPT and UPD input signals, the IRO input will enable the gates and will set the multiplexers to input the CPT and UPD input signals gates <b>410</b> and <b>408</b>.

<figref idref="DRAWINGS">FIG. 9</figref> illustrates the timing diagram of performing capture, shift and update operations using the CPT and UPD inputs. As seen the TSM will go to and remain in the ShiftDR state to cause data to shift through the data register from TDI to TDO. During the shifting the UPD signal will be asserted to cause an update operation to occur, then the CPT signal will be asserted to cause a capture operation to occur. Shifting resumes following the update and capture operations. As seen, there are no dead states in the capture, shift and update operations when using the CPT and UPD signals, as there were in the <figref idref="DRAWINGS">FIG. 4</figref> timing example <b>306</b>.

<figref idref="DRAWINGS">FIG. 10</figref> illustrates a die <b>1000</b> containing the improved TAP architecture <b>1002</b> of <figref idref="DRAWINGS">FIG. 5</figref> coupled to parallel test circuits <b>1</b>-N <b>1004</b> via the DRC and IRO buses of the improved TAP architecture. As seen in <figref idref="DRAWINGS">FIG. 10</figref>, the DRC and IRO buses of <figref idref="DRAWINGS">FIG. 5</figref> are extended from the improved TAP architecture <b>1002</b> to form connections to the parallel test circuits <b>1004</b>. Each parallel test circuit has a group of Parallel Test Data Inputs (PTDI) and a group of Parallel Test Data Outputs (PTDO). When enabled by the IRO bus, a parallel test circuit may be operated by the DRC signals from the DPR to perform capture and shift operations, or capture, shift and update operations. The IRO inputs to the DPR allow the capture and shift or capture, shift and update operations to be selectively controlled by the TSM, as shown in <figref idref="DRAWINGS">FIGS. 3 and 4</figref>, or by the CPT and UPD signals, as shown in <figref idref="DRAWINGS">FIGS. 6-9</figref>. The advantage of using the CPT and UPD signals to control a parallel test circuit is that the capture and shift and the capture, shift and update operations do not include dead states. During the shifting part of the above mentioned operations, the parallel test circuit inputs parallel test data from PTDI and outputs parallel test data to PTDO. During test, the PTDI and PTDO buses are coupled to external leads of die <b>1000</b>, as will be shown and described in regard to <figref idref="DRAWINGS">FIGS. 13, 14, 16, 17, 21, 22, 23, and 24</figref>.

<figref idref="DRAWINGS">FIG. 11</figref> illustrates an older approach <b>1100</b> of stacking die on top of one another. This example shows the stack including a bottom die, a middle die and a top die. This stacking approach is based on a pyramid arrangement where smaller die are stacked onto larger lower. The die are connected to each other using bond wires <b>1102</b> located between bond pads <b>1104</b> at the periphery of the die. While not shown each die contains functional circuits that are connected to the bond pads. The bottom die of the stack is mounted on a substrate.

<figref idref="DRAWINGS">FIG. 12</figref> illustrates a newer approach <b>1200</b> of stacking die on top of one another. This example shows the stack including a bottom die, a middle die and a top die. This stacking approach, commonly referred to as three dimensional (3D) stacking, is based on vertical connections <b>1202</b>, referred to as through silicon vias (TSV), that are formed from the bottom surface of a die to the top surface of the die. When die are stacked, contact points (micro bumps) <b>1204</b> on the surfaces of each die connect the embedded TSVs of each die together to provide vertical signaling paths up and down the die stack from a substrate. While not shown each die contains functional circuits that are connected to some of the TSVs. There are many advantages of using TSVs, including but not limited too, simplification of connectivity, high bandwidth signaling and the ability to provide an extremely large number of connections between die in a stack.

While the test architecture of this disclosure may be implemented in die that are stacked using the older pyramid approach of <figref idref="DRAWINGS">FIG. 11</figref> or the newer 3D approach of <figref idref="DRAWINGS">FIG. 12</figref>, this disclosure describes the test architecture as it would be implemented in die that are designed to be stacked using the 3D approach of <figref idref="DRAWINGS">FIG. 12</figref>. However, it should be understood that the test architecture of this disclosure is not limited to only being used in die that are stacked according to the 3D approach. Indeed, the test architecture may be implemented in die designed to be stacked in either the pyramid approach, the 3D approach or in various arrangements that may use a mixture of pyramid and 3D approaches. Further, the test architecture may be implemented in die that are not necessarily intended to be stacked, i.e. a standalone die.

<figref idref="DRAWINGS">FIG. 13A</figref> illustrates a test architecture of the disclosure designed into a die <b>1300</b> that is to be used as the bottom die in a 3D stack die arrangement. The test architecture includes the Improved TAP <b>1002</b> and parallel test circuits <b>1004</b> of <figref idref="DRAWINGS">FIG. 10</figref>, gating circuitry <b>1306</b>, 3-state buffers <b>1302</b>, and multiplexer <b>1304</b>. The die includes an N signal wide bus of PTDI TSVs <b>1202</b> extending from contact points <b>1204</b> on the bottom surface of the die to contact points <b>1204</b> on the top surface of the die. The die includes a bus of Test Control Input (TCI) TSVs <b>1202</b>, including the CPT, UPD, TCK and TMS signals of <figref idref="DRAWINGS">FIG. 10</figref>, that are coupled between contact points <b>1204</b> on the bottom surface of the die to contact points <b>1204</b> on the top surface of the die. The die includes a TDI contact point <b>1204</b> on the bottom surface of the die for inputting a TDI signal to the Improved TAP. The die includes a TDO contact point on the bottom surface of the die for outputting a TDO signal from multiplexer <b>1304</b>. The die includes a bus of PTDO TSVs <b>1202</b> extending from contact points <b>1204</b> on the top surface of the die to contact points <b>1204</b> on the bottom top surface of the die. The die includes a TDI contact point <b>1204</b> on the top surface of the die for inputting a TDI signal to multiplexer <b>1304</b>. The die includes a TDO contact point <b>1204</b> on the top surface of the die for outputting a TDO signal from the Improved TAP <b>1002</b>. For the bottom die of <figref idref="DRAWINGS">FIG. 13</figref>, the term “bottom surface” means the die surface to be coupled to a system substrate, and the term “top surface means the die surface to be connected to an upper die in the stack.

Gating circuit <b>1306</b> has inputs coupled to some or all of the TCI contact points on the bottom surface of the die, a Link input from the IRO from the Improved TAP and outputs coupled to some or all the TCI contact points on the top surface of the die. Any TCI signals that are not routed through the gating circuit simply bypass the gating circuit as shown in dotted line.

<figref idref="DRAWINGS">FIG. 13B</figref> illustrates a gating circuit <b>1306</b> that gates all the TCI CPT, UPD, TCK and TMS signals.

<figref idref="DRAWINGS">FIG. 13C</figref> illustrates a gating circuit <b>1306</b> that gates only the TMS and TCK signals.

<figref idref="DRAWINGS">FIG. 13D</figref> illustrates a gating circuit <b>1306</b> that gates only the TMS signal.

<figref idref="DRAWINGS">FIG. 13E</figref> illustrates a gating circuit <b>1306</b> that gates only the TCK signal.

As seen in all gating examples of <figref idref="DRAWINGS">FIGS. 13B-13E</figref>, at least one or both of the TCK and TMS signals may be gated off. When one or both of the TCK and TMS signals are gated off, TAPs in upper die that are connected to the TCI bus are disabled from operating.

The multiplexer <b>1304</b> inputs the TDO from the Improved TAP, the TDI input from the top surface contact point, a control signal from the IRO bus of the Improved TAP and outputs a TDO signal to the bottom surface contact point.

Each Parallel Test Circuit <b>1004</b> inputs a bus of N or less than N PTDI signals from the N wide PTDI TSV bus <b>1202</b> from a tester, the DRC bus from the Improved TAP, optionally the IRO bus from the Improved TAP, and outputs a bus of N or less than N PTDO signals to buffers <b>1302</b>. The buffers, when enabled by the IRO output of the Improved TAP, output the N or less than N PTDO signals to the N wide PTDO TSV bus <b>1202</b> to the tester. The PTDI and PTDO buses may be dedicated for communicating test signals or they may be shared between communicating test signals and function signals. The N width of the PTDI and PTDO buses is established by the Parallel Test Circuit <b>1004</b> having the widest parallel test input and parallel test output. For example, if a Parallel Test Circuit <b>1004</b> has a 32 bit parallel test input and 32 bit parallel test output, N will be set to 32 bits.

The Improved TAP has CPT, UPD, TMS and TCK inputs coupled to the TCI TSV bus, a TDI input coupled to the bottom surface TDI contact point, a TDO output coupled to the multiplexer, DRC outputs coupled to the Parallel Test Circuits and IRO outputs coupled to buffer <b>1302</b> and optionally to some or all of the Parallel Test Circuits.

When access to only the Improved TAP of die <b>1300</b> is required, the Link signal to gating circuit <b>1306</b> is set to gate off the TCI inputs to the top surface TCI contact points, and the control signal to multiplexer <b>1304</b> is set to select the TDO output of the Improved TAP to be output on the bottom surface TDO contact point. In this configuration, a scan path is formed from the bottom surface TDI contact point of die <b>1300</b>, through the Improved TAP of die <b>1300</b> and to the bottom surface TDO contact point of die <b>1300</b>, via multiplexer <b>1304</b>.

When access to the Improved TAP of die <b>1300</b> and a TAP or an Improved TAP of an upper die is required, the Link signal to gating circuit <b>1306</b> is set to gate on the TCI inputs to the top surface TCI contact points, and the control signal to multiplexer <b>1304</b> is set to select the top surface TDI contact point to be output on the bottom surface TDO contact point. In this configuration, a scan path is formed from the bottom surface TDI contact point of die <b>1300</b>, through the Improved TAP to the top surface TDO contact point of die <b>1300</b>, through the TDI to TDO path of the upper die TAP and back to the top surface TDI contact point of die <b>1300</b> and through multiplexer <b>1304</b> to the bottom surface TDO contact point of die <b>1300</b>.

When a Parallel Test Circuit <b>1004</b> is to be tested, the Improved TAP will be loaded with an instruction that enables the buffers <b>1302</b> associated with the Parallel Test Circuit to be tested to drive the PTDO TSV bus. Other buffers <b>1302</b> will not be enabled. Also, and only if required, the instruction will output IRO signals to the Parallel Test Circuit to set up its test operation mode. After this step, the Improved TAP will control the Parallel Test Circuit with the DRC outputs to perform capture and shift type testing or capture, shift and update type testing as described in <figref idref="DRAWINGS">FIG. 10</figref>. When a Parallel Test Circuit is being tested, its PTDO outputs will be the only outputs driving the PTDO TSV bus of a single die or a stack of die.

<figref idref="DRAWINGS">FIG. 14</figref> illustrates a test architecture of the disclosure designed into a die <b>1400</b> that is to be used as a middle or a top die in a 3D stack die arrangement. The test architecture includes the Improved TAP <b>1002</b>, parallel test circuits <b>1004</b>, 3-state buffers <b>1302</b>, and a Fuse <b>1402</b>. The die includes an N signal wide bus of PTDI TSVs <b>1202</b> extending from contact points <b>1204</b> on the bottom surface of the die to contact points <b>1204</b> on the top surface of the die. The die includes a bus of Test Control Input (TCI) TSVs <b>1202</b>, including the CPT, UPD, TCK and TMS signals of <figref idref="DRAWINGS">FIG. 10</figref>, that are coupled between contact points <b>1204</b> on the bottom surface of the die to contact points <b>1204</b> on the top surface of the die. The die includes a TDI contact point <b>1204</b> on the bottom surface of the die for inputting a TDI signal to the Improved TAP. The die includes a TDO contact point on the bottom surface of the die for outputting a TDO signal. The die includes a bus of PTDO TSVs <b>1202</b> extending from contact points <b>1204</b> on the top surface of the die to contact points <b>1204</b> on the bottom top surface of the die. The die includes a TDI contact point <b>1204</b> on the top surface of the die for inputting a TDI signal. The die includes a TDO contact point <b>1204</b> on the top surface of the die for outputting a TDO signal from the Improved TAP <b>1002</b>. The die includes a Fuse <b>1402</b> having a first terminal connected to the TDO output of the Improved TAP and the top surface TDO contact point and a second terminal connected to the top surface TDI contact point and the bottom surface TDO contact point.

For the middle or top die of <figref idref="DRAWINGS">FIG. 14</figref>, the term “bottom surface” means the die surface to be coupled to a lower or the bottom die of the stack, and the term “top surface” means the die surface to be connected to an upper middle or the top die in the stack.

Each Parallel Test Circuit <b>1004</b> inputs a bus of N or less than N PTDI signals from the N wide PTDI TSV bus <b>1202</b>, the DRC bus from the Improved TAP, optionally the IRO bus from the Improved TAP, and outputs a bus of N or less than N PTDO signals to buffers <b>1302</b>. The buffers, when enabled by the IRO output of the Improved TAP, output the N or less than N PTDO signals to the N wide PTDO TSV bus <b>1202</b>. The PTDI and PTDO buses may be dedicated for communicating test signals or they may be shared between communicating test signals and function signals. The N width of the PTDI and PTDO buses is established by the Parallel Test Circuit <b>1004</b> having the widest parallel test input and parallel test output. For example, if a Parallel Test Circuit <b>1004</b> has a 32 bit parallel test input and 32 bit parallel test output, N will be set to 32 bits.

The Improved TAP <b>1002</b> has CPT, UPD, TMS and TCK inputs coupled to the TCI TSV bus, a TDI input coupled to the bottom surface TDI contact point, a TDO output coupled to the Fuse <b>1402</b> and the top surface TDO contact point, DRC outputs coupled to the Parallel Test Circuits and IRO outputs coupled to buffers <b>1302</b> and optionally to some or all of the Parallel Test Circuits.

Fuse <b>1402</b> is an important aspect of the present disclosure, as is allows the die <b>1400</b> to be programmed for use as either a middle die in a stack of die, or as the top die in a stack of die. This allows a die manufacturer to design and manufacture only one version of a die that a customer may purchase and chose to use it as either a middle die in the stack or the top die in the stack. The choosing is simply accomplished by keeping the Fuse <b>1402</b> closed as it was manufactured so that the die could be used as a top die in the customer's die stack, or by opening the Fuse so that the die could be used as a middle die in the customer's die stack. The opening of the Fuse could be done in a myriad of ways, grounding the top surface TDO contact point and apply a voltage sufficient to blow the Fuse at the bottom surface TDO contact point. The opening and closing of Fuse <b>1402</b> could be reversible if an electrically programmable fuse were used. While the word Fuse is used, it should be understood, element <b>1402</b> could be any type of circuit or connection that can pass the TDO signal or not pass the TDO signal. For example, element <b>1402</b> could be a 3-state buffer that is selectively enabled to pass the TDO signal or disabled to not pass the TDO signal.

When a Parallel Test Circuit <b>1004</b> is to be tested, the Improved TAP will be loaded with an instruction that enables the buffers <b>1302</b> associated with the Parallel Test Circuit to be tested to drive the PTDO TSV bus. Other buffers <b>1302</b> will not be enabled. Also, and only if required, the instruction will output IRO signals to the Parallel Test Circuit to set up its test operation mode. After this step, the Improved TAP will control the Parallel Test Circuit with the DRC outputs to perform capture and shift type testing or capture, shift and update type testing as described in <figref idref="DRAWINGS">FIG. 10</figref>. When a Parallel Test Circuit is being tested, its PTDO outputs will be the only outputs driving the PTDO TSV bus of a single die or a stack of die.

When the Improved TAP receives TCK and TMS control from the TCI bus it can shift data from the bottom surface TDI contact point to the top surface TDO contact point. If the Fuse <b>1402</b> is closed, the data shifted to top surface contact point is also present at the top surface TDI contact point and the bottom surface TDO contact point. If the Fuse <b>14021</b> is opened, the data shifted to top surface contact point is not present at the top surface TDI contact point and the bottom surface TDO contact point.

<figref idref="DRAWINGS">FIG. 15</figref> illustrates a stack die example including a bottom die <b>1300</b>, a middle die <b>1400</b> and a top die <b>1400</b>. This example illustrates how the TAPs <b>1002</b> of the die in the stack are accessed, according to the disclosure. As seen, the Fuse <b>1402</b> of the middle die <b>1400</b> has been opened to allow the die to operate as a middle die in the stack, and the Fuse <b>1402</b> of the top die <b>1400</b> remains closed to allow the die to operate as the top die in the stack.

When an instruction is loaded into the bottom die to allow access to the Improved TAP of the bottom die <b>1300</b>, the Improved TAP will respond to the TCK and TMS control signals of the TCI bus to input data from the bottom surface TDI contact point and output data to the bottom surface TDO contact point via multiplexer <b>1304</b>. As described in <figref idref="DRAWINGS">FIG. 14</figref>, the instruction controls the gating circuit to gate off the TCI control signals to the TAPs of the upper die, and also controls multiplexer <b>1304</b> to couple the TDO output of the Improved TAP of the bottom die to the bottom surface TDO contact point.

When an instruction is loaded into the bottom die to allow daisy-chained access to the Improved TAPs of the bottom, middle and top die, the Improved TAPs will respond to the TCK and TMS control signals of the TCI bus to input data from the TDI contact point on the bottom surface of the bottom die and output data to the TDO contact point on the bottom surface of the bottom die via multiplexer <b>1304</b>. As described in <figref idref="DRAWINGS">FIG. 14</figref>, the instruction loaded into the bottom die controls the gating circuit to gate on the TCI control signals to the TAPs of the upper die, and also controls multiplexer <b>1304</b> to couple the TDO output of the top die to the bottom surface TDO contact point of the bottom die, via the TDO TSV signal path in the die stack. As seen in <figref idref="DRAWINGS">FIG. 15</figref>, the Fuse <b>1402</b> of the middle die is opened, allowing the closed Fuse <b>1402</b> of the top die to pass the TDO output of the TAP of the top die to the bottom surface TDO output of the bottom die, via multiplexer <b>1304</b>.

<figref idref="DRAWINGS">FIG. 16</figref> illustrates a stack die example including a bottom die <b>1300</b>, a middle die <b>1400</b> and a top die <b>1400</b>. This example illustrates how the parallel test circuits <b>1004</b> of each die in the stack are accessed, according to the disclosure. This description assumes the die TAPs are daisy-chained as described in <figref idref="DRAWINGS">FIG. 15</figref>, to allow instructions to be loaded in all the die TAPs.

When an instruction is loaded into a TAP <b>1002</b> of one of the die, i.e. the top, middle or bottom die, to enable a parallel test circuit in that die, the buffers <b>1302</b> associated with that parallel test circuit are enabled to drive the PTDO TSV bus of the die stack. The parallel test circuit receives DRC control from the TAP to input parallel data from the PTDI TSV bus of the stack and output parallel data to the PDDO TSV bus of the stack. The parallel test circuit may be controlled to perform capture and shift test operations or it may be controlled to perform capture, shift and update test operations, as previously describe in <figref idref="DRAWINGS">FIGS. 13A and 14</figref>. As seen, only the selected parallel test circuit <b>1004</b> is enabled to drive the PTDO TSV bus. This test process is repeated for each parallel test circuit <b>1004</b> to be tested in each die of the stack.

<figref idref="DRAWINGS">FIG. 17</figref> illustrates an alternate embodiment of the test architecture of the disclosure designed into a die <b>1700</b> that is to be used as the bottom die in a 3D stack die arrangement. The test architecture is identical to the test architecture described in <figref idref="DRAWINGS">FIG. 13A</figref>, with the exceptions that (1) the buffers <b>1302</b> associated with each parallel test circuit in <figref idref="DRAWINGS">FIG. 13A</figref> have been replaced with a test circuit (TC) <b>1702</b> and (2) the N wide PTDO TSV bus of <figref idref="DRAWINGS">FIG. 13A</figref> has been replaced with a N+1 parallel test data input/output (PTDIO) TSV bus.

<figref idref="DRAWINGS">FIG. 18</figref> illustrates an example implementation of TC <b>1702</b>. The TC includes a plurality of buffer <b>1302</b> and comparator <b>1802</b> arrangements <b>1808</b> connected as shown. Each arrangement has an input coupled to a PTDO of a parallel test circuit <b>1004</b> and an input/output coupled to a TSV on the N+1 PTDIO TSV bus. The buffers <b>1302</b> have an input coupled to a PTDO of the parallel test circuit, an ENA1 signal from the TAP IRO bus and an output coupled to a PTDIO of the N+1 PTDIO TSV bus. The comparators <b>1802</b> have an input coupled to a PTDO of the parallel test circuit, an input coupled to a PTDIO of the N+1 PTDIO TSV bus, an ENA2 signal input from the TAP IRO bus and a Fail output signal. Each Fail output signal is input to an OR gate <b>1804</b>. The output of the OR gate is input to a 3-state buffer <b>1806</b> which, when enabled by ENA2, outputs a Compare Fail Output (CFO) signal to a TSV on the N+1 PTDIO TSV bus. Each TC will receive a unique set of ENA1 and ENA2 control signals from the IRO. The TC <b>1702</b> can be enabled to operate in the following two modes.

Mode 1—When the ENA1 signal is asserted, the buffers <b>1302</b> are enabled to output test data from a parallel test circuit to the PTDIO TSV bus exactly as described in regard to <figref idref="DRAWINGS">FIG. 13A</figref>. A tester coupled to the PTDIO contact points of die <b>1700</b> inputs the data for analysis.

Mode 2—When the ENA2 signal is asserted, the comparators <b>1802</b> are enabled to compare the data output from a parallel test circuit to data from the PTDIO TSV bus. A tester coupled to the PTDIO contact points of die <b>1700</b> inputs the compare data. If a mismatch between the data is detected, the comparators output a Fail signal to gate <b>1804</b>, which forwards the Fail signal to the CFO signal in the PTDIO TSV bus, which is coupled to the tester via a PTDIO contact point on die <b>1700</b>.

Testing die <b>1700</b> using Mode 1 requires the tester to have a unique PTDIO bus connection to each die <b>1700</b> being tested in parallel. For example, if the PTDIO bus is 32 bits wide and <b>16</b> die <b>1700</b> are being tested in parallel, the tester has to have 512 PTDIO connections to the die.

Testing die <b>1700</b> using Mode 2 allows the tester to only have one PTDIO connection to each die <b>1700</b> being tested in parallel. Reusing the example above, if the PTDIO bus is 32 bits wide and <b>16</b> die <b>1700</b> are being tested in parallel, the tester only has to have a 32 bit wide PTDIO connection to the die, plus 16 CRO connections, one from each die.

The advantage of Mode 2 therefore is that it reduces the number of connections between a tester and plural die being tested in parallel. This reduction of connections is beneficial at wafer level testing where lower cost testers and probe mechanisms can be used.

<figref idref="DRAWINGS">FIG. 19</figref> is provided to illustrate that comparator <b>1802</b> may include a compare (CMP) circuit that compares PTDO data from a parallel test circuit against expected data from the PTDIO TSV bus.

<figref idref="DRAWINGS">FIG. 20</figref> is provided to illustrate that comparator <b>1802</b> may include a maskable compare (MSK CMP) circuit that only compares PTDO data from a parallel test circuit against unmasked expected data from the PTDIO TSV bus. This comparator <b>1802</b> circuit is useful when the PTDO data from a parallel test circuit contains don't care or unknown data outputs that can generate false Fail signal outputs.

<figref idref="DRAWINGS">FIG. 21</figref> is provided to illustrate TCs <b>1702</b> being used in die <b>2100</b> designed for use as a middle die or top die in a die stack.

<figref idref="DRAWINGS">FIG. 22</figref> is provided to illustrate a stack die example including a bottom die <b>1700</b>, a middle die <b>2100</b> and a top die <b>2100</b>, each die including TCs <b>1702</b>.

<figref idref="DRAWINGS">FIG. 23</figref> illustrates a die <b>2300</b> including the test architecture of the disclosure wherein the parallel test circuit <b>1004</b> is realized as a scan compression circuit having a decompressor (D), parallel scan paths and a compaction circuit (C) controlled by the DRC bus from TAP <b>1002</b>. Dotted line circuit box <b>2302</b> could be either buffers <b>1302</b> or TCs <b>1702</b>.

<figref idref="DRAWINGS">FIG. 24</figref> illustrates a die <b>2400</b> including the test architecture of the disclosure wherein the parallel test circuit <b>1004</b> is realized as parallel scan paths controlled by the DRC bus from TAP <b>1002</b>. Dotted line circuit box <b>2302</b> could be either buffers <b>1302</b> or TCs <b>1702</b>.

<figref idref="DRAWINGS">FIG. 25</figref> illustrates a die <b>2500</b> including the test architecture of the disclosure wherein the parallel test circuit <b>1004</b> is realized as an IEEE 1500 core wrapper having a wrapper boundary register (WBR) and parallel scan paths controlled by the DRC bus of TAP <b>1002</b>. In this example the WBR is connected as one of the TAP data register to allow it to be accessed from TDI to TDO. Dotted line circuit box <b>2302</b> could be either buffers <b>1302</b> or TCs <b>1702</b>.

Today it is very common for a die to include one or more additional TAPs, instead of just the single die TAP <b>1002</b> shown in the previous Figures. For example, there may be a TAP on each embedded intellectual property (IP) circuit or core in the die. <figref idref="DRAWINGS">FIGS. 26 and 27</figref> below illustrate how the disclosure can be expanded to accommodate multiple TAP in a die.

<figref idref="DRAWINGS">FIG. 26</figref> illustrates an example TAP Domain architecture <b>2600</b> that supports access to the die ITAP <b>1002</b> alone or access to the die ITAP <b>1002</b> and multiple embedded IP TAPs <b>2604</b>. The IP TAPs may be conventional TAPs <b>100</b> or they may be Improved TAPs <b>1002</b>. As seen the architecture includes the die ITAP <b>1002</b>, one or more IP TAPs <b>2604</b>, a TDO multiplexer <b>2606</b> and gating circuitry <b>2608</b> all connected as shown. The die ITAP <b>1002</b> outputs the IRO bus from the TAP Domain <b>2600</b> and control signals to multiplexer <b>2606</b> and gating circuit <b>2608</b>. Gating circuit <b>2608</b> may be any of the previously described gating circuits of <figref idref="DRAWINGS">FIG. 13B-13E</figref>. At power up of following a test reset, the IRO bus disables the gating circuit from passing TCI signals to the IP TAPs and controls the multiplexer to select the TDO output of the die ITAP to be output on TDO of the TAP Domain. In this configuration and during instruction and data scan operations, the die ITAP operates alone to shift data from the TDI input of the TAP Domain to the TDO output of the TAP Domain via multiplexer <b>2606</b>. Since the TCI inputs to the IP TAPs are gated off they do not respond to the instruction and data scan operations.

When it is required to access the IP TAPs <b>2604</b>, an instruction is scanned into the die ITAP to output control on the IRO bus to enable the gating circuit <b>2608</b> and control the multiplexer to input the TDO from the one or more IP TAPs. After this instruction is loaded, the die ITAP and the one or more IP TAPs all shift data from the TDI input of the TAP Domain to the TDO output of the TAP Domain during instruction and scan operations. After access to the IP TAPs is complete, another instruction is scanned into the die ITAP to disable the gating circuit and control the multiplexer to select the TDO output of the Die ITAP to be output on the TDO output of the TAP Domain.

<figref idref="DRAWINGS">FIG. 27</figref> illustrates a stack die example including a bottom die <b>2706</b>, a middle die <b>2704</b> and a top die <b>2702</b>. This example illustrates how the TAP Domains <b>2600</b> of the die in the stack are accessed, according to the disclosure. The access is the same as the access described in <figref idref="DRAWINGS">FIG. 15</figref> with the exception that multiple TAPs existing in the TAP Domain <b>2600</b> of each die may be accessed instead of just the single die ITAP <b>1002</b>.

It is important to note that the bottom and top surface test contact points of one die in this disclosure are shown to line up with bottom and top surface test contact points of another other die in this disclosure. This is intentional and facilitates the die stacking process. If they did not line up, an interposer (redistribution layer) would have to be used between each die in the stack to form the connections between the test contact points.

Although the disclosure has been described in detail, it should be understood that various changes, substitutions and alterations may be made without departing from the spirit and scope of the disclosure as defined by the appended claims.