Nanowire semiconductor device partially surrounded by a gate

CROSS-REFERENCE TO RELATED APPLICATION

0001This application is based upon and claims the benefit of priority under 35 U.S.C. §119 from prior French Patent Application No. 14 50079, filed on Jan. 7, 2014, the entire content of which is incorporated herein by reference.

TECHNICAL FIELD AND PRIOR ART

0002A semiconductor device is described here comprising several semiconductor nanowires superimposed or arranged next to one another, spaced one from the other and which are partially surrounded by a gate. This advantageously applies to the carrying out of devices of the FET (Field Effect Transistor) type, in particular for high-performance and low-consumption logic applications in microelectronics. This also applies to the carrying out of MOSFET transistors with nanowires superimposed or arranged next to one another, for example for the carrying out of integrated circuits having improved electrical performance with respect to the circuits of prior art.

0003The semiconductor nanowires are nanostructures with which it is possible to carry out transistors of the FinFET (“Fin-shaped Field Effect Transistor”, or 3D transistor) type. In such a FinFET transistor, instead of having one active zone corresponding to a planar structure as in a conventional MOSFET type transistor, a semiconductor “fin”, or nanowire, is carried out in relief on the substrate in order to form the channel of the transistor. The interest of this adding is to increase, with no detriment to the density with which the transistors are carried out on the substrate, the contact surface between the gate and the channel on an upper face and the sidewalls of the channel (giving the name of “Tri-Gate transistor” also given for this type of transistor). This increase in the contact surface between the gate and the channel makes it possible to reduce leakage currents when the transistor is at the blocked state (OFF state). Such a FinFET structure as such makes it possible to carry out transistors comprising gate lengths that are shorter than those of planar architecture MOSFET transistors without degrading the electrical performance of the transistors. A FinFET transistor can be manufactured on a substrate of the bulk type or of the SOI type.

0004The threshold voltage obtained with such FinFET transistors is adjusted by the metal of the gate (set by its work output). The modulation of the threshold voltage made possible by an adjustment of the geometrical dimensions of the nanowire (width and height) remains however critical and may be incompatible with the constraints linked to good electrostatic control of the transistor, i.e. having a transistor with a low DIBL (“Drain-Induced Barrier Lowering”) and a low slope under the threshold S (“Subthreshold Slope”). The conduction current obtained is directly linked to the circumference of the nanowire defined, in the case of a nanowire with rectangular section, via the value 2(H+W), with H corresponding to the height of the nanowire and W corresponding to the width of the nanowire.

0005With this type of transistor, it is possible to increase the nanowire, or fin, density, on the substrate, and therefore the density of the transistors, in order to create devices with better performance. The technique making it possible to increase the density of the nanowires is referred to as “spacer patterning” or “double patterning” (as it makes it possible to reduce the pitch of the nanowires by two) and consists in carrying out the nanowires via the following steps: <ul id="ul0001" list-style="none"><li id="ul0001-0001" num="0000"><ul id="ul0002" list-style="none"><li id="ul0002-0001" num="0006">a first lithography and an etching are carried out in order to carry out patterns, drawn by a first mask, in a resin film,</li><li id="ul0002-0002" num="0007">a depositing of a material referred to as “spacer” such as silicon oxide or silicon nitride is carried out on the patterns formed during the preceding step,</li><li id="ul0002-0003" num="0008">a third step consists in etching the spacer and in removing the resin in such a way that the remaining spacer material defines new patterns on each side of each initial pattern defined during the first step. The pads formed as such are spacer pads of which the pitch is two times smaller than that of the pads formed during the first lithography,</li><li id="ul0002-0004" num="0009">a fourth step of the method consists in transferring by etching, in the silicon layer, all of the patterns formed in the hard “spacer” mask, as such forming the silicon nanowires,</li><li id="ul0002-0005" num="0010">a second lithography is often required in order to cut the nanowires at their ends,</li><li id="ul0002-0006" num="0011">finally, the spacers are removed then the gate stack is deposited and etched.</li></ul></li></ul>

0012Such a method is for example described in documents U.S. Pat. No. 6,709,982 B1 and WO 2008/059440 A2.

0013However, even with such a method, the circumference of the nanowires generally remains substantial and consequently, the electrostatic control is not optimal.

0014There are also transistors of the GAA-FET or “Gate-All-Around FET” type, wherein the gate entirely wraps, or surrounds, the silicon nanowire or nanowires. With respect to FinFET transistors, the semiconductor nanowires that have a gate that entirely wraps around the GAA-FET transistors make it possible to obtain an excellent electrostatic control of the transistors. This makes it possible in particular to reduce the leakage current when the transistor is in the OFF state (blocked). These devices of the GAA type are as such considered for the most advanced technological nodes for which the gate length is less than 20 nm.

0015However, a disadvantage of this type of transistor is its difficulty in terms of manufacture. Indeed, after the depositing of the gate all around the semiconductor nanowire or nanowires, it is necessary to etch the gate stack which can be comprised of an insulating layer (gate dielectric), of a gate metal and of polycrystalline silicon. However, after the etching of the gate stack, gate metal still remains to be suppressed, in particular under the nanowires in the source-drain extension zones. This removal is difficult to carry out but necessary in order to avoid short-circuiting the transistor. In order to avoid this problem, the gates are often oversized in order to partially overlap the source and drain zones and it is then difficult to reach the dimensions sought for the gate lengths of this type of transistor, for example less than 15 nm.

DISCLOSURE OF THE INVENTION

0016There is therefore a need to propose a semiconductor device that does not have the disadvantages linked to the carrying out of devices of the GAA-FET type while retaining the advantages provided by the structures of devices of the GAA-FET type with respect to other types of FET devices.

0017For this, a semiconductor device is proposed comprising at least: <ul id="ul0003" list-style="none"><li id="ul0003-0001" num="0000"><ul id="ul0004" list-style="none"><li id="ul0004-0001" num="0018">two semiconductor nanowires superimposed one on top of the other, spaced one from the other and intended to form channel regions of the semiconductor device,</li><li id="ul0004-0002" num="0019">a dielectric structure entirely filling a space extending between the two semiconductor nanowires and which is in contact with the two semiconductor nanowires,</li><li id="ul0004-0003" num="0020">a gate dielectric and a gate covering at least a first of the two semiconductor nanowires, sidewalls of the two semiconductor nanowires and sidewalls of the dielectric structure,</li></ul></li></ul>

0021and wherein the dielectric structure comprises at least one portion of dielectric material with a relative permittivity greater than 3.9.

0022A semiconductor device is also proposed comprising at least: <ul id="ul0005" list-style="none"><li id="ul0005-0001" num="0000"><ul id="ul0006" list-style="none"><li id="ul0006-0001" num="0023">two semiconductor nanowires superimposed one on top of the other or arranged next to one another, spaced one from the other and forming channel regions of the semiconductor device,</li><li id="ul0006-0002" num="0024">a dielectric structure entirely filling a space extending between the two semiconductor nanowires and which is in contact with the two semiconductor nanowires,</li><li id="ul0006-0003" num="0025">a gate dielectric and a gate covering at least a first of the two semiconductor nanowires, sidewalls of the two semiconductor nanowires and sidewalls of the dielectric structure when the two semiconductor nanowires are superimposed one on top of the other, or covering a part of the upper faces of the two semiconductor nanowires and a part of an upper face of the dielectric structure when the two semiconductor nanowires are arranged next to one another,</li></ul></li></ul>

0026and wherein the dielectric structure comprises at least one portion of dielectric material with a relative permittivity greater than or equal to 20.

0027With respect to a device of the GAA-FET type that comprises a gate dielectric and a gate entirely surrounding the nanowire or nanowires of the device and which therefore requires the implementing, when it is carried out, of an etching of a portion of the electrically conductive material of the gate located under the portions of the nanowire or of the nanowires that do not form the channel, in particular on source and drain extension zones, the semiconductor device described here comprises a dielectric structure with a strong permittivity interposed between the semiconductor nanowires which makes it possible to avoid the implementation of such an etching due to the fact that the gate surrounds only a portion of the nanowires and is not located under the nanowires. In addition, this semiconductor device does not require carrying out an over-sizing of the gates. As such, the gate dielectric and the gate of the semiconductor device may not cover, even partially, source and drain zones of the semiconductor device.

0028The semiconductor device described here makes it possible to form a transistor of the FET type that retains a structure close to that of a transistor of the FinFET type, i.e. with a channel region, here formed by at least two nanowires superimposed or arranged next to one another, and a gate arranged on two or three sides of the nanowires when the nanowires are superimposed or arranged on a part of the upper faces of the nanowires when the nanowires are arranged next to one another, facilitating the etching of the gate during the carrying out of it while still increasing the drain current and reducing the leakage current of the device via better electrostatic control. This semiconductor device makes it possible to retain the manufacturing simplicity of a FinFET transistor with the implementation of a standard gate etching while still retaining the advantages (in terms of charge transporting properties) of structures with gates surrounding GAA-FET devices. Due to the fact that the portion of dielectric material has a relative permittivity, or dielectric constant, greater than that of the SiO₂, i.e. greater than 3.9, the penetration of the electric field lines (with this field being induced by the gate located on the sidewalls of the nanowires during the operation of the semiconductor device) in the portion of dielectric material, and therefore under the semiconductor nanowires, is therefore favoured. This configuration makes it possible to obtain an electrostatic control close or even identical to that of Gate-All-Around (GAA) devices. The penetration of the electric field lines under the semiconductor nanowires also makes it possible to increase the conduction surface (with respect to a standard FinFET device) and therefore the electrical performance of the semiconductor device.

0029The term “dielectric structure” here designates a structure formed from one or several dielectric materials and not comprising any electrically conductive material or semiconductor such as a metal or polycrystalline silicon.

0030The dielectric structure, and in particular the portion of dielectric material, may extend between the nanowires at least at the channel region formed by the nanowires, and for example also at source and drain extension zones (LDD “Light-Doped Drain” and LDS “Light-Doped Source” regions).

0031The semiconductor device may form a field effect transistor of which the gate length is less than or equal to 20 nm, or 15 nm, or even 10 nm.

0032The semiconductor device may advantageously be used to carry out integrated circuits used to high-performance and low-consumption logical applications in microelectronics such as smartphones, tablets, portable PCs, etc.

0033When the semiconductor nanowires are arranged next to one another, the semiconductor device forms a planar structure which has for advantage to be easy to carry out. This planar structure furthermore improves the electrical performance of the device with respect to the devices of prior art as it makes it possible to have an electrical width that is more substantial, i.e. allow for the carrying out of nanowires of which the circumference is more substantial, which makes it possible to have better electrostatic control while still maintaining an occupation surface that is identical to the planar structures of the FDSOI type.

0034Such a planar structure allows for an improvement in the electrostatic control while still maintaining a fractioning of the total surface of the semiconductor present under the gate into nanowires with an electrical behaviour close to a 3D structure comprising stacked nanowires.

0035The portion of dielectric material may comprise at least one dielectric material with a relative permittivity greater than or equal to 20, or strictly greater than 20. As such, the penetration of the electric field lines in the dielectric structure is improved because the higher the dielectric constant, or relative permittivity, of this dielectric material is, the better the electrostatic coupling is.

0036When the two semiconductor nanowires are arranged one next to the other, a part of the dielectric structure may be arranged under the two semiconductor nanowires and between the two semiconductor nanowires. This portion of the dielectric structure may therefore be arranged on the side of the lower and lateral faces of the semiconductor nanowires. Only the upper face of the nanowires may be in contact with the gate.

0037The semiconductor nanowires may be parallel with respect to one another, i.e. extend according to the same direction.

0038In this case, each semiconductor nanowire may comprise, in a plane perpendicular to a direction according to which the semiconductor nanowires extend, a section of rectangular shape. The direction according to which the nanowires extend corresponds to the orientation of the largest dimension of the nanowires. In this configuration, the gate dielectric and the gate may cover an upper face of the first of the two semiconductor nanowires, as well as the lateral faces of the two semiconductor nanowires and the lateral faces of the dielectric structure. In addition, the portion of dielectric material and the dielectric structure may each comprise, in the plane perpendicular to the direction according to which the semiconductor nanowires extend, a section of rectangular shape. Alternatively, it is possible that the section of the semiconductor nanowires, in the plane perpendicular to the direction according to which the semiconductor nanowires extend, be circular. In addition, the portion of dielectric material and the dielectric structure may each comprise, in the plane perpendicular to the direction according to which the semiconductor nanowires extend, a section of circular shape.

0039Each semiconductor nanowire may be surrounded by a dielectric interface layer, with the dielectric structure able to further comprise portions of the dielectric interface layers arranged between the semiconductor nanowires and in contact with the portion of dielectric material. In the absence of such dielectric interface layers, the portion of dielectric material may be directly in contact with the semiconductor nanowires.

0040In the dielectric structure, the thickness of the portion of dielectric material may be greater than or equal to about ten times the thickness of a dielectric interface layer.

0041The semiconductor device may further comprise, when the semiconductor device comprises more than two semiconductor nanowires superimposed one on top of the other, several dielectric structures such that two of the adjacent semiconductor nanowires may be spaced one from the other by one of the dielectric structures extending between said two adjacent semiconductor nanowires and which is in contact with said two adjacent semiconductor nanowires, and the gate dielectric and the gate may also cover sidewalls of each of the semiconductor nanowires and sidewalls of each of the dielectric structures.

0042The semiconductor device may further comprise source and drain regions between which extend the semiconductor nanowires or formed by parts of the semiconductor nanowires, with the dielectric structure able to be in contact with the source and drain regions and/or juxtaposed with the source and drain regions.

0043A method for carrying out a semiconductor device is also proposed, comprising at least the steps of: <ul id="ul0007" list-style="none"><li id="ul0007-0001" num="0000"><ul id="ul0008" list-style="none"><li id="ul0008-0001" num="0044">carrying out at least two semiconductor nanowires superimposed one on top of the other, spaced one from the other and intended to form channel regions of the semiconductor device,</li><li id="ul0008-0002" num="0045">carrying out at least one dielectric structure entirely filling a space extending between the two semiconductor nanowires and which is in contact with the two semiconductor nanowires,</li><li id="ul0008-0003" num="0046">carrying out a gate dielectric and a gate covering at least a first of the two semiconductor nanowires, sidewalls of the two semiconductor nanowires and sidewalls of the dielectric structure,</li></ul></li></ul>

0047and wherein the dielectric structure comprises at least one portion of dielectric material with a relative permittivity greater than 3.9.

0048A method for carrying out a semiconductor device is also proposed, comprising at least the steps of: <ul id="ul0009" list-style="none"><li id="ul0009-0001" num="0000"><ul id="ul0010" list-style="none"><li id="ul0010-0001" num="0049">carrying out at least two semiconductor nanowires superimposed one on top of the other or arranged next to one another, spaced one from the other and forming channel regions of the semiconductor device,</li><li id="ul0010-0002" num="0050">carrying out of at least one dielectric structure entirely filling a space extending between the two semiconductor nanowires and which is in contact with the two semiconductor nanowires,</li><li id="ul0010-0003" num="0051">carrying out a gate dielectric and a gate covering at least a first of the two semiconductor nanowires, sidewalls of the two semiconductor nanowires and sidewalls of the dielectric structure when the two semiconductor nanowires are superimposed one on top of the other, or covering a part of the upper faces of the two semiconductor nanowires and a part of an upper face of the dielectric structure when the two semiconductor nanowires are arranged next to one another,</li></ul></li></ul>

0052and wherein the dielectric structure comprises at least one portion of dielectric material with a relative permittivity greater than or equal to 20.

0053When the two semiconductor nanowires are superimposed one on top of the other, the carrying out of the two semiconductor nanowires may comprise at least the implementation of the steps of: <ul id="ul0011" list-style="none"><li id="ul0011-0001" num="0000"><ul id="ul0012" list-style="none"><li id="ul0012-0001" num="0054">etching of a stack of at least two semiconductor layers between which is arranged at least one sacrificial layer, such that remaining portions of the two semiconductor layers correspond to the semiconductor nanowires, with a remaining portion of the sacrificial layer being arranged between the semiconductor nanowires,</li><li id="ul0012-0002" num="0055">removal of the remaining portion of the sacrificial layer arranged between the semiconductor nanowires, forming the space extending between the two semiconductor nanowires.</li></ul></li></ul>

0056The two semiconductor layers may comprise silicon, and the sacrificial layer may comprise SiGe.

0057When the two semiconductor nanowires are arranged next to one another, the carrying out of the two semiconductor nanowires may comprise at least the implementation of the steps of: <ul id="ul0013" list-style="none"><li id="ul0013-0001" num="0000"><ul id="ul0014" list-style="none"><li id="ul0014-0001" num="0058">etching a semiconductor layer arranged on a sacrificial layer, forming the space extending between the two semiconductor nanowires and such that remaining portions of the semiconductor layer correspond to the semiconductor nanowires,</li><li id="ul0014-0002" num="0059">removal of the sacrificial layer arranged under the semiconductor nanowires.</li></ul></li></ul>

0060A part of the dielectric structure may be carried out under the two semiconductor nanowires and between the two semiconductor nanowires.

0061The step of carrying out the dielectric structure may comprise at least one depositing of the portion of dielectric material between the semiconductor nanowires.

0062The step of carrying out the dielectric structure may further comprise, between the step of carrying out of the two semiconductor nanowires and the step of depositing of the portion of dielectric material, a step of carrying out an dielectric interface layer around each semiconductor nanowire, the portion of dielectric material then being deposited against the parts of the dielectric interface layers arranged between the semiconductor nanowires.

0063The method may further comprise the carrying out of source and drain regions between which extend the semiconductor nanowires or formed by portions of semiconductor nanowires, with the dielectric structure able to be carried out in contact with the source and drain regions and/or juxtaposed with the source and drain regions.

BRIEF DESCRIPTION OF THE DRAWINGS

0064This invention shall be better understood when reading the description of example embodiments provided solely for the purposes of information and in no way restricted, in reference to the annexed drawings wherein:

0065<figref idref="DRAWINGS">FIG. 1</figref> shows a front cross-section view of several semiconductor devices according to a first embodiment,

0066<figref idref="DRAWINGS">FIGS. 2 to 6B</figref> show the steps of a method for carrying out several semiconductor devices according to the first embodiment,

0067<figref idref="DRAWINGS">FIG. 7</figref> shows the values of the ratio of the concentrations in electrons on the upper and lower faces of a semiconductor nanowire of a semiconductor device according to the relative permittivity of a portion of dielectric material of the semiconductor device and of the width of the semiconductor nanowire,

0068<figref idref="DRAWINGS">FIGS. 8A to 13C</figref> show the steps of a method for carrying out a semiconductor device according to a second embodiment.

0069Identical, similar or equivalent portions of the various figures described hereinafter bear the same numerical references so as to facilitate moving from one figure to another.

0070The different portions represented in the figures are not necessarily represented according to a uniform scale, in order to make the figures easier to read.

0071The various possibilities (alternatives and embodiments) must be understood as not being exclusive from one another and can be combined together.

DETAILED DISCLOSURE OF PARTICULAR EMBODIMENTS

0072Reference is first made to <figref idref="DRAWINGS">FIG. 1</figref> which shows a front cross-section view of several semiconductor devices <b>100</b> according to a first embodiment. In this first embodiment, each one of the semiconductor devices <b>100</b> corresponds to an FET type transistor with superimposed nanowires.

0073The semiconductor devices <b>100</b> are carried out on a dielectric layer <b>102</b> for example comprising an oxide semiconductor such as SiO₂. This dielectric layer <b>102</b> can itself be arranged on a bulk semiconductor substrate (not shown), for example comprising silicon, or correspond to a buried dielectric layer of a substrate of the semiconductor on insulator type, forming for example a BOX (buried oxide) of an SOI (silicon on insulator) substrate. In the first embodiment described here, the dielectric layer <b>102</b> is a thick dielectric layer, with its thickness (dimension according to the axis Z shown in <figref idref="DRAWINGS">FIG. 1</figref>) being for example equal to about 145 nm.

0074Each one of the semiconductor devices <b>100</b> comprises several semiconductor nanowires <b>104</b> (at least two), for example comprising silicon and/or germanium and/or any III-V semiconductor, superimposed one on top of the other and spaced from one another by dielectric structures formed of one or several dielectric materials. In the embodiment shown in <figref idref="DRAWINGS">FIG. 1</figref>, each of the semiconductor devices <b>100</b> comprises three semiconductor nanowires <b>104</b>. Alternatively, each of the semiconductor devices <b>100</b> can comprise two nanowires, or four nanowires, or more than four nanowires, superimposed one on top of the other. The parties of the semiconductor nanowires <b>104</b> shown in <figref idref="DRAWINGS">FIG. 1</figref> form channels of the semiconductor devices <b>100</b> which extend between source and drain regions (cannot be seen in <figref idref="DRAWINGS">FIG. 1</figref>) of the semiconductor devices <b>100</b>, parallel to the Y axis.

0075In the embodiment described here, the sections of semiconductor nanowires <b>104</b> in the plane (X, Z), i.e. in a plane perpendicular to the direction (parallel to the Y axis) according to which the semiconductor nanowires <b>104</b> extend, are of square shape. However, these sections could be of a different shape, for example rectangular or circular. Each one of the semiconductor nanowires <b>104</b> has a height H_NW, or thickness, that corresponds to the dimension according to the axis Z shown in <figref idref="DRAWINGS">FIG. 1</figref>, for example equal to about 10 nm or 12 nm, or more generally between about 5 nm and 30 nm. Each one of the semiconductor nanowires <b>104</b> has a width W_NW, that corresponds to the dimension according to the X axis shown in <figref idref="DRAWINGS">FIG. 1</figref>, for example equal to about 10 nm or 12 nm, or more generally between about 5 nm and 30 nm. Each one of the semiconductor nanowires <b>104</b> can also have a length L_NW, that corresponds to the dimension according to the Y axis shown in <figref idref="DRAWINGS">FIG. 1</figref>, for example between about 5 nm and several hundreds of nanometers. The centres of two adjacent semiconductor nanowires <b>104</b> that are in the same plane parallel to the surface of the dielectric layer <b>102</b> whereon are carried out the semiconductor devices <b>100</b> (parallel to the plane (X, Y)) and which belong to two adjacent devices <b>100</b> are spaced by a distance P_NWfor example equal to about 30 nm (with the space separating these two semiconductor nanowires <b>104</b> being for example equal to about 20 nm), or more generally between about 15 nm and several hundred nanometers.

0076In this first embodiment, each of the semiconductor nanowires <b>104</b> is surrounded by a dielectric interface layer <b>106</b>, for example comprising SiO₂(with relative permittivity equal to 3.9) and a thickness equal to about 0.8 nm or between about 0.7 nm and 10 nm. These dielectric interface layers are here in direct contact with the semiconductor nanowires <b>104</b>. These dielectric interface layers <b>106</b> make it possible to reduce the interface defects and as such to obtain better transporting properties in the semiconductor structure. These interface layers <b>106</b> are for example carried out as finely as possible in order to retain an excellent electrostatic coupling, for example with a thickness less than or equal to about 2 nm.

0077In each of the semiconductor devices <b>100</b>, portions of dielectric material <b>108</b> are arranged between the semiconductor nanowires <b>104</b>, with each one of the portions of dielectric material <b>108</b> being in contact with the dielectric interface layers <b>106</b> surrounding the semiconductor nanowires <b>104</b> between which is located the portion of dielectric material <b>108</b>. As such, in each of the semiconductor devices <b>100</b>, the space between two nanowires <b>104</b> superimposed one on top of the other is entirely filled with a dielectric structure formed of the portions of the dielectric interface layers <b>106</b> surrounding each one of these two semiconductor nanowires <b>104</b> and located between these two semiconductor nanowires <b>104</b> as well as by one of the portions of dielectric material <b>108</b> in contact with these portions of dielectric interface layers <b>106</b>.

0078In the embodiment described here, the sections of the portions of dielectric material <b>108</b> in the plane (X, Z), i.e. in a plane perpendicular to the direction (parallel to the Y axis) according to which the semiconductor nanowires <b>104</b> extend, are of square or rectangular shape. The shape of these sections can however be different as it depends in particular on those of the semiconductor nanowires <b>104</b> (and therefore also on those of the dielectric interface layers <b>106</b>) due to the fact that the portions of dielectric material <b>108</b> are carried out by entirely filling the space located between the semiconductor nanowires <b>104</b> surrounded by the dielectric interface layers <b>106</b>. Each of the dielectric portions <b>108</b> has a height H_HK, or thickness, corresponding to the dimension according to the axis Z shown in <figref idref="DRAWINGS">FIG. 1</figref>, for example equal to about 12 nm, or more generally between about 5 nm and several tens of nanometers. Each one of the portions of dielectric material <b>108</b> here has a width, corresponding to the dimension according to the axis X shown in <figref idref="DRAWINGS">FIG. 1</figref>, equal to the sum of the width W_NWof one of the semiconductor nanowires <b>104</b> and twice the thickness of one of the dielectric interface layers <b>106</b>, and for example equal to about 11.6 nm, or between about (W_NW+2(thickness of one of the layers <b>106</b>)) and (W_NW−6 nm). Alternatively, one or several or each one of the portions of dielectric material <b>108</b> can have a width less than W_NWof a few nanometers, by carrying out for example a slight “recess”, or indentation, of the sidewalls of the portions <b>108</b>, which makes it possible to further improve the electrostatic control of the device.

0079Each one of the portions of dielectric material <b>108</b> can also have a length, corresponding to the dimension according to the axis Y shown in <figref idref="DRAWINGS">FIG. 1</figref>, for example between equal to L_G±10 nm, with L_Gcorresponding to the gate length of the device, which makes it possible to retain this material with a strong permittivity under the gate of the device, i.e. of the FET transistor carried out. The centres of two adjacent portions of dielectric material <b>108</b> located in a same plane parallel to the surface of the dielectric layer <b>102</b> whereon are carried out the semiconductor devices <b>100</b> (parallel to the plane (X, Y)) and which belong to two adjacent semiconductor devices <b>100</b> are spaced by the distance P_NW.

0080The portions of dielectric material <b>108</b> comprise a dielectric material with a strong relative permittivity, i.e. with a relative permittivity greater than that of SiO₂which is equal to 3.9, for example TiO₂(∈_R=80) and/or HfO₂(∈_R=25) and/or ZrO₂(∈_R=25) and/or Ta₂O₅(∈_R=22) and/or Al₂O₃(∈_R=9) and/or Si₃N₄(∈_R=7) and/or HfSiON (∈_R=20) and/or SrTiO3 (∈_R=2000) and/or Y₂O₃(∈_R=15). Advantageously, the dielectric material of the portions <b>108</b> is chosen from among those of which the relative permittivity is between about 20 and 80. As such, in similar environmental conditions, the relative permittivity of the dielectric material of the portions <b>108</b> is greater than that of SiO₂. Other materials of the piezoelectric type of which dielectric permittivity is high (for example PZT of which the permittivity is between 200 and 4000, or BaTiO₃of which the permittivity is equal to about 1700) can be used.

0081The semiconductor nanowires <b>104</b>, surrounded with dielectric interface layers <b>106</b>, and the dielectric portions <b>108</b> form, for each of the semiconductor devices <b>100</b>, an alternating stack of semiconductor nanowires and of dielectric structures. These stacks are covered by gate dielectrics <b>110</b>. In each of the devices <b>100</b>, the gate dielectric <b>110</b> covers the sidewalls of the stack, i.e. the sidewalls of the portions of dielectric material <b>108</b> as well as the portions of the dielectric interface layers <b>106</b> covering the sidewalls of the semiconductor nanowires <b>104</b>. Each gate dielectric <b>110</b> further covers a first of the semiconductor nanowires <b>104</b> of each stack, i.e. an upper face of the stack formed here by the portion of the dielectric interface layer <b>106</b> covering the upper face of the first semiconductor nanowire <b>104</b> (i.e. the semiconductor nanowire <b>104</b> located above the or other semiconductor nanowires <b>104</b> of the semiconductor device <b>100</b>). The gate dielectrics <b>110</b> correspond to layers of dielectric material with a strong relative permittivity (greater than 3.9), for example comprising HfO₂and a thickness equal to about 2.5 nm.

0082Each one of the gate dielectrics <b>110</b> is covered by an electrically conductive gate <b>112</b>, for example comprising metal, corresponding here to a layer of TiN of a thickness for example equal to about 5 nm.

0083Each one of the semiconductor devices <b>100</b> thus forms an FET transistor of which the channel is formed by superimposed semiconductor nanowires <b>104</b> and of which the gate <b>112</b> covers two or three sides of each one of the semiconductor nanowires <b>104</b>, with the other side of the semiconductor nanowires <b>104</b> that are not covered by the gate <b>112</b> and the gate dielectric <b>110</b> being in contact with the dielectric structures which comprise the portions of dielectric material <b>108</b> with strong dielectric permittivity. This strong dielectric permittivity of the portions of dielectric material <b>108</b> favours the penetration of the electric field lines (which is induced, during the operation of the device <b>100</b>, by the gate <b>112</b> located on the sidewalls of the semiconductor nanowires <b>104</b>) in the portions of dielectric material <b>108</b>, and therefore between the semiconductor nanowires <b>104</b> forming the channels, which makes it possible to increase the drain current and to reduce the leakage current via better electrostatic control of the transistors formed by the semiconductor devices <b>100</b> which is close or identical to that of GAA-FET transistors. With respect to a transistor of the FinFET type, the penetration of the electric field lines between the semiconductor nanowires <b>104</b> also make it possible to increase the conduction surface, and therefore the performance of the transistor formed by the semiconductor device <b>100</b>. This structure also provides other advantages linked to the method of carrying out the semiconductor device <b>100</b> which are described hereinafter.

0084In addition, although they cannot be seen in <figref idref="DRAWINGS">FIG. 1</figref>, the semiconductor devices <b>100</b> also comprise source and drain regions between which extend the semiconductor nanowires <b>104</b>. Source and drain extension zones formed by the ends of the semiconductor nanowires <b>104</b> are also in contact with the portions of dielectric material <b>108</b> and therefore are not entirely surrounded by the gate <b>112</b> and the gate dielectric <b>110</b>. In addition, the portions of dielectric material <b>108</b> are juxtaposed with the source and drain regions. Alternatively, it is also possible that the portions of dielectric material <b>108</b> be arranged immediately under the gate and that they not extend in the source and drain regions.

0085According to an alternative of the first embodiment described hereinabove, it is possible for at least one portion of each one of the semiconductor nanowires <b>104</b> or of some of the semiconductor nanowires <b>104</b> to not be surrounded by the dielectric interface layers <b>106</b>. In such an alternative, one of the portions of dielectric material <b>108</b> is directly in contact with the two semiconductor nanowires <b>104</b> between which this portion of dielectric material <b>108</b> is arranged. In addition, in this configuration, the gate dielectric <b>110</b> is also in direct contact with the sidewalls of the semiconductor nanowires <b>104</b>. According to this alternative, the width of at least one or of each one of the portions of dielectric material <b>108</b> can be equal to the width W_NWof each one of the semiconductor nanowires <b>104</b> between which are located the portion of dielectric material <b>108</b>.

0086According to a second alternative, it is possible for the width (dimension according to the X axis) of at least one or of each one of the portions of dielectric material <b>108</b> to be less than that of each one of the semiconductor nanowires <b>104</b> between which are located the portion of dielectric material <b>108</b> or, when the semiconductor nanowires <b>104</b> are surrounded by the dielectric interface layers <b>106</b>, less than the sum of the width of one of the semiconductor nanowires <b>104</b> and twice the thickness of one of the dielectric interface layers <b>106</b>. According to this configuration, the sidewalls of the stacks of the semiconductor nanowires <b>104</b>, of the dielectric interface layers <b>106</b> and of the portions of dielectric material <b>108</b> comprise hollows on portions of dielectric material <b>108</b>. This difference in width is for example between 0 and 6 nm and makes it possible to favour a little further the electrostatic control in such a semiconductor device <b>100</b>. This difference in width is for example equal to about 3 nm. According to this second alternative, the width W_NWof each semiconductor nanowire <b>104</b> is for example between about 5 nm and 10 nm, and the height H_HKof each portion of dielectric material <b>108</b> is for example between about 10 nm and 20 nm. The height H_NWof each semiconductor nanowire <b>104</b> is for example equal to 12 nm. In this configuration, the gate dielectric <b>110</b> and the gate <b>112</b> can be located in one part only of the total space located between two nanowires <b>104</b> superimposed one on top of the other, i.e. at the hollows formed by the portions of dielectric material <b>108</b> on sidewalls of the stacks of the semiconductor nanowires <b>104</b> and of the dielectric structures.

0087Whether the widths of the portions of dielectric material <b>108</b> are equal to or less than those of the semiconductor nanowires <b>104</b>, the semiconductor nanowires <b>104</b> and the portions of dielectric material <b>108</b> of a semiconductor device <b>100</b> can be carried out such that the concentrations in electrons on upper and lower faces of each nanowire <b>104</b> (corresponding to the faces of the nanowires <b>104</b> which are parallel to the surface of the layer <b>102</b> whereon the semiconductor devices <b>100</b> are carried out) are equal to or close to one another, for example such that their ratio R is at least equal to about 0.8. This ratio R, which depends on the parameters of the nanowires <b>104</b> and of the dielectric portion <b>108</b> of the semiconductor device <b>100</b>, can be evaluated according to the following equation: <br /><i>R=</i>0.53933+0.030552·∈_R+147.59613·<i>B−</i>160.12808·<i>W</i>_NW+16.6·<i>H</i>_HK−1.3622·∈_R<i>·B+</i>0.6426·∈_R<i>·W</i>_NW+0.15974·∈_R<i>·μH</i>_HK−10868·<i>B·W</i>_NW−1229.455·<i>B·H</i>_HK+1748.2777·<i>W</i>_NW<i>·H</i>_HK−5.6531·10⁻⁴·∈_R²+6744.84·<i>W</i>_NW²−807.16·<i>H</i>_HK²+167.3184·∈_R<i>·B·W</i>_NW+0.012275·∈_R²<i>·W</i>_NW

0088with ∈_R: relative permittivity of the dielectric material of the portions <b>108</b>,

0089B: difference between the width of one of the nanowires <b>104</b> and the width of one of the portions of dielectric material <b>108</b>.

0090The curves shown in <figref idref="DRAWINGS">FIG. 7</figref> correspond to the values of the ratio R according to the value of ∈_R(in abscissa), which is here between 3.9 and 80 ∈₀, and the value of W_NW(in ordinate), which is here between 0.005 μm and 0.01 μm, by choosing B=3 nm and H_HK=20 nm. The curve bearing the reference <b>50</b> corresponds to the pairs of values (∈_R; W_NW) making it possible to have a ratio R of value equal to 0.8. Likewise, the curves references as <b>52</b>, <b>54</b>, <b>56</b> and <b>58</b> correspond to the pairs of values (∈_R; W_NW) making it possible to have a ratio R of a value respectively equal to 0.2, 0.4, 0.6 and 1. As such, in order to carry out a semiconductor device <b>100</b> that has a ratio R greater than 0.8, the values of ∈_Rand of W_NWcan be chosen in the zone <b>60</b> located to the right of the curve <b>50</b> and which corresponds to the pairs of values (∈_R; W_NW) making it possible to reach a ratio R greater than or equal to 0.8.

0091This <figref idref="DRAWINGS">FIG. 7</figref> shows that the finer the structure of the semiconductor nanowires <b>104</b> is, i.e. the smaller the value of W_NWis (for example equal to 5 nm), the more the dielectric material used for carrying out the portions <b>108</b> can be chosen with a low dielectric permittivity (for example HfO₂of which the relative permittivity is equal to about 25 when W_NW=5 nm). Likewise, the more substantial the structure of the semiconductor nanowires <b>104</b> is, i.e. the higher the value of W_NWis (for example equal to 10 nm), the more the dielectric material used to carry out the portions <b>108</b> can be chosen with a higher dielectric permittivity (for example TiO₂of which the relative permittivity is equal to about 80 when W_NW=10 nm).

0092With such a ratio R close to 1 or between about 0.8 and 1, the electric potential obtained in the semiconductor nanowires <b>104</b> during the operation of the semiconductor device <b>100</b> is relatively homogeneous, i.e. the electric potential on the upper and lower faces of the semiconductor nanowires <b>104</b> is practically equivalent to that on the lateral faces of the semiconductor nanowires <b>104</b> which are covered by the gate dielectric <b>110</b> and the gate <b>112</b> of the semiconductor device <b>100</b>.

0093It is possible for several semiconductor devices <b>100</b> carried out on the same layer or a same substrate to form a single device of the FET type. In this case, the source and drain regions of these devices <b>100</b> are common, i.e. electrically connected together for example by unifying them such that they correspond to a single source region and to a single drain region, and the gates of these devices <b>100</b> are also common such as the device obtained comprises only one gate.

0094In relation with <figref idref="DRAWINGS">FIGS. 2 to 6B</figref>, the steps will now be described of a method of carrying out semiconductor devices <b>100</b> described hereinabove.

0095A stack of several layers is first of all carried out in order to form the semiconductor nanowires <b>104</b> (see <figref idref="DRAWINGS">FIG. 2</figref> corresponding to a profile cross-section view of this stack). This stack of layers rests on a support corresponding here to the dielectric layer <b>102</b>. Several semiconductor layers <b>114</b> intended for the carrying out of semiconductor nanowires <b>104</b> are arranged on the dielectric layer <b>102</b>. The material of the semiconductor layers <b>114</b> corresponds to that of the semiconductor nanowires <b>104</b> intended to be carried out, i.e. for example of the silicon and/or of the germanium and/or any semiconductor of the III-V type. The number of these stacked semiconductor layers <b>114</b> corresponds to the number of superimposed semiconductor nanowires <b>104</b> that each semiconductor device <b>100</b> is intended to comprise (three in the example described here). In addition, the thickness of these semiconductor layers <b>114</b> (dimension according to the axis Z) is here equal to the height, or the thickness, H_NWdesired for the semiconductor nanowires <b>104</b>. Due to the fact that within each semiconductor device <b>100</b> the superimposed semiconductor nanowires <b>104</b> are also spaced from one another, the semiconductor layers <b>114</b> are spaced from one another by sacrificial layers <b>116</b> which comprise at least one material that can be selectively etched with regards to the semiconductor material of the layers <b>114</b>, with the thickness of the sacrificial layers <b>116</b> here being equal to the height, or the thickness, H_HKdesired for the portions of dielectric material <b>108</b>.

0096The stack of layers therefore corresponds here to an alternating stack of N semiconductor layers <b>114</b> and of (N−1) sacrificial layers <b>116</b>, with N an integer greater than or equal to 2. In the example described here, the semiconductor layers <b>114</b> comprise silicon, and the sacrificial layers <b>116</b> comprise SiGe. The concentration of germanium in the SiGe alloy of the sacrificial layers <b>116</b> is for example equal to about 20%, 30% or encore 45%. The higher this concentration in germanium in the SiGe of the sacrificial layers <b>116</b> is, the higher the etching selectivity with regards to the semiconductor layers <b>114</b> will be during the removal of the SiGe in order to form the semiconductor nanowires <b>104</b>. This stack of semiconductor layers <b>114</b> and of sacrificial layers <b>116</b> can be obtained via the implementation of steps of epitaxy.

0097A step of etching, here a dry anisotropic etching, the stack of layers <b>114</b>, <b>116</b> is then implemented so that the remaining portions of the semiconductor layers form the semiconductor nanowires <b>104</b>. The sacrificial layers <b>116</b> and the semiconductor layers <b>114</b> are etched according to the same pattern. As such, the nanowires <b>104</b> superimposed one on top of the other and intended to be a part of the same semiconductor device <b>100</b> are spaced one from the other by remaining portions <b>118</b> of sacrificial layers <b>116</b>, with each of these remaining portions <b>118</b> being in contact with the two semiconductor nanowires <b>104</b> between which the remaining portion <b>118</b> is arranged. This step of etching as such forms empty spaces <b>120</b> in the stack intended to delimit and separate the various semiconductor devices <b>100</b> from one another. <figref idref="DRAWINGS">FIGS. 3A and 3B</figref> show respectively a profile cross-section view and a front cross-section view (according to the axis BB′ shown in <figref idref="DRAWINGS">FIG. 3A</figref>) of the stack after the implementation of this step of etching.

0098This step of etching can be preceded by a step of lithography wherein the pattern to be etched in the stack of layers <b>114</b>, <b>116</b> is defined by a mask formed on this stack of layers <b>114</b>, <b>116</b>. Advantageously and when the semiconductor devices <b>100</b> are intended to be carried out with a high density on the support, this mask can be carried out via the implementation of a “spacer patterning” or “double patterning” method such as described hereinabove in the prior art part.

0099As shown in <figref idref="DRAWINGS">FIGS. 4A and 4B</figref>, the part of the remaining portions <b>118</b> of sacrificial material located between the semiconductor nanowires <b>104</b> are removed via a selective etching with respect to the semiconductor of the nanowires <b>104</b>, for example of the CF₄/N₂/Ar plasma type. Only the sacrificial material of the remaining portions <b>118</b> located at channels intended to be formed by the nanowires <b>104</b> is etched, so that the remaining parts <b>122</b> of the portions <b>118</b> of SiGe provide the maintaining of the nanowires <b>104</b> at the source and drain regions referenced as <b>126</b> and <b>128</b>. This step of etching forms, between the nanowires <b>104</b> superimposed one on top of the other, free spaces <b>124</b> of which the dimensions and the shape correspond to those of the portions of etched sacrificial material and correspond to those of the dielectric structures intended to be carried out between the semiconductor nanowires <b>104</b>.

0100The dielectric interface layers <b>106</b> are then carried out, for example by depositing, around semiconductor nanowires <b>104</b> (see <figref idref="DRAWINGS">FIGS. 5A and 5B</figref>). A part of the free spaces <b>124</b> are filled by a part of the dielectric structures intended to be interposed between the semiconductor nanowires <b>104</b>, with this part of the dielectric structures corresponding to the portions of the dielectric interface layers <b>106</b> arranged between the superimposed semiconductor nanowires <b>104</b>. When these dielectric interface layers <b>106</b> comprise semiconductor oxide, for example SiO₂, these dielectric interface layers <b>106</b> can be carried out by oxidation (for example of the plasma type, forming a deposit) of the semiconductor surface of the semiconductor nanowires <b>104</b>.

0101A dielectric material with strong dielectric permittivity (relative permittivity greater than 3.9) is then deposited in all of the empty spaces formed previously in the stack of layers, i.e. in the free spaces <b>124</b> located between the superimposed semiconductor nanowires <b>104</b> as well as in the free spaces <b>120</b> that separate the semiconductor nanowires <b>104</b> from the various semiconductor devices <b>100</b>. The dielectric material deposited is then etched in order to retain only the portions of dielectric material located between the superimposed semiconductor nanowires <b>104</b> of the same semiconductor device <b>100</b>, as such forming the portions of dielectric material <b>108</b> (see <figref idref="DRAWINGS">FIGS. 6A and 6B</figref>). On their ends, the portions of dielectric material <b>108</b> are juxtaposed with the source and drain regions <b>126</b>, <b>128</b>, and are in contact with source and drain regions extension zones located between the channel regions formed by the semiconductor nanowires <b>104</b> and the source and drain regions <b>126</b>, <b>128</b>. The portions of dielectric material <b>108</b> can also be in contact with the source and drain regions <b>126</b>, <b>128</b>.

0102The gate dielectric <b>110</b> and the gate <b>112</b> are then carried out via depositing on all of the structure obtained previously, then by etching the parts of the materials of the gate dielectric <b>110</b> and of the gate <b>112</b> that do not cover the upper faces and the sidewalls of the stacks of the semiconductor nanowires <b>104</b>, of the dielectric interface layers <b>106</b> and of the portions of dielectric material <b>108</b>. The semiconductor devices <b>100</b> obtained correspond to those shown in <figref idref="DRAWINGS">FIG. 1</figref>.

0103According to an alternative embodiment, when the semiconductor nanowires <b>104</b> are not surrounded by the dielectric interface layers <b>106</b>, the step described previously in relation with <figref idref="DRAWINGS">FIGS. 5A and 5B</figref> is not implemented, the dielectric material deposited and etched during the step described in relation with <figref idref="DRAWINGS">FIGS. 6A and 6B</figref> and intended to form the portions <b>108</b> then being in direct contact with the semiconductor nanowires <b>104</b>.

0104The alternative according to which the portions of dielectric material <b>108</b> are not as wide as the nanowires <b>104</b> can be obtained via the implementation of a slight over-etching, for example of the humid type, of the dielectric portions <b>108</b>, with this over-etching being carried out before the depositing and the etching of the gate dielectric <b>110</b> and of the gate <b>112</b>.

0105In relation with <figref idref="DRAWINGS">FIGS. 8A to 13C</figref>, the steps of a method for carrying out a semiconductor device <b>100</b> according to a second embodiment shall now be described, the device <b>100</b> corresponding here to a transistor of the FET type comprising nanowires arranged next to one another and spaced one from the other.

0106This semiconductor device <b>100</b> is carried out using a substrate of the semiconductor on insulator type, for example SOI (silicon on insulator), i.e. comprising a massive semiconductor layer <b>150</b>, comprising for example silicon and a thickness equal to several hundreds of microns, whereon is arranged a buried dielectric layer <b>152</b> (called BOX or “Buried Oxide”) comprising a dielectric material such as SiO₂and a thickness between a few nanometers and a few tens of nanometers, and a superficial layer <b>154</b>, comprising a semiconductor material such as silicon, germanium, SiGe, or any III-V semiconductor, and arranged on the buried dielectric layer <b>152</b>. The thickness of the superficial layer <b>154</b> (dimension according to the axis Z) is advantageously chosen as being equal to the thickness desired for the nanowires <b>104</b> intended to be carried out using the superficial layer <b>154</b>. This thickness is for example between about 5 nm and 30 nm, or between about 10 nm and 12 nm. <figref idref="DRAWINGS">FIG. 8A</figref> shows a top view of the substrate and <figref idref="DRAWINGS">FIG. 8B</figref> shows a side cross-section view of this substrate. In this second embodiment, the buried dielectric layer <b>152</b> is intended to be used as a sacrificial layer for the carrying out of the nanowires <b>104</b>.

0107As shown in <figref idref="DRAWINGS">FIGS. 9A and 9B</figref> (<figref idref="DRAWINGS">FIG. 9A</figref> shows a top view of the substrate and <figref idref="DRAWINGS">FIG. 9B</figref> shows a side cross-section view of this substrate), shallow isolation trenches <b>156</b>, also referred to as STI for “Shallow Trench Isolation” are carried out through the layers <b>150</b>, <b>152</b> and <b>154</b> of the substrate, as such delimiting the active zone of the device <b>100</b> in the substrate. These trenches <b>156</b> are carried out by etching trenches through the layers <b>154</b> and <b>152</b> and in a part of the thickness of the massive layer <b>150</b>. A dielectric material such as SiO₂is then deposited in the etched trenches.

0108The semiconductor nanowires <b>104</b> are then carried out by etching through the superficial layer <b>154</b>. <figref idref="DRAWINGS">FIG. 10A</figref> shows a top view of the structure obtained, and <figref idref="DRAWINGS">FIGS. 10B and 10C</figref> show cross-section views of the structure obtained respectively according to the axes AA and BB that can be seen in <figref idref="DRAWINGS">FIG. 10A</figref>. The dimensions W_NW, H_NWand L_NWof the nanowires <b>104</b> are for example equal to those described hereinabove in relation with the first embodiment. In addition, the spacing between two nanowires <b>104</b> arranged next to one another is for example similar to the spacing between two nanowires superimposed one on top of the other as described previously in relation with the first embodiment.

0109The buried dielectric layer <b>152</b> is then suppressed, for example by etching (see <figref idref="DRAWINGS">FIGS. 11A to 11C</figref>). The nanowires <b>104</b> are then suspended and maintained at their ends by anchoring to the trenches <b>156</b>.

0110As shown in <figref idref="DRAWINGS">FIGS. 12A to 12C</figref>, the space located under the nanowires <b>104</b>, previously occupied by the buried dielectric layer <b>152</b>, as well as the spaces between the nanowires <b>104</b> are then filled by a deposit of dielectric material <b>158</b>, for example of the oxide and/or a dielectric material with strong permittivity (“High-K”). The dielectric material <b>158</b> can correspond to one of the examples of materials described hereinabove for the portions of dielectric material <b>108</b>.

0111The device <b>100</b> is then completed by carrying out on the previously carried out structure a gate dielectric <b>160</b> and a gate <b>162</b> arranged on the parts of the nanowires <b>104</b> intended to form the channels of the device <b>100</b> (<figref idref="DRAWINGS">FIGS. 13A to 13C</figref>). The gate dielectric <b>160</b> and the gate <b>162</b> are arranged on a part of the upper faces of the nanowires <b>104</b> and on a part of an upper face of the dielectric material <b>158</b>. The ends of the gate dielectric <b>160</b> and of the gate <b>162</b> rest on the trenches <b>156</b>. The portions of the nanowires <b>104</b> that are not covered by the gate dielectric <b>160</b> and the gate <b>162</b> form the source <b>126</b> and drain <b>128</b> regions of the device <b>100</b>. The gate dielectric <b>160</b> correspond for example to a portion of dielectric material with a strong relative permittivity (greater than 3.9), comprising for example HfO₂and a thickness equal to about 2.5 nm. The gate <b>162</b> comprises for example a metal material such as TiN.

0112The various advantages described hereinabove for the first embodiment are also found in the device <b>100</b> according to this second embodiment.

0113The permittivity of the dielectric material <b>158</b> arranged under and between the nanowires <b>104</b> is advantageously greater than or equal to 20. As such, the device <b>100</b> comprises a planar gate <b>162</b> with an electrical behaviour close to a GAA structure car the electric field lines are going to be able to easily penetrate into this dielectric material <b>158</b>.

0114Such a structure makes it possible to obtain an electrostatic behaviour that is close to a transistor of the GAA type while still retaining a gate etching that is simple to carry out.

0115As in the first embodiment described hereinabove, the sections of the nanowires <b>104</b> of the device according to the second embodiment can be of a square shape as in the embodiment described in relation with <figref idref="DRAWINGS">FIGS. 8A to 13C</figref>, or of a different shape.

0116It is also possible that the nanowires <b>104</b>, or some of the nanowires <b>104</b>, of the device <b>100</b> according to the second embodiment each be surrounded by an dielectric interface layer <b>106</b> as described hereinabove for the first embodiment. In this case, the dielectric material <b>158</b> is arranged around the dielectric interface layers <b>106</b> (except on the upper face of the nanowires <b>104</b> which is arranged on the side of the gate dielectric <b>160</b> and of the gate <b>162</b>).

0117The various alternatives and possibilities for carrying out described hereinabove in relation with the first embodiment also apply to this second embodiment.