US9633940B2

Structure and method for a high-K transformer with capacitive coupling

Summary by NHIP

High-K Transformer with Capacitive Coupling

The method forms four conductive features over a semiconductor substrate to create an inductively coupled transformer with capacitive enhancement. Floating ends on the third and fourth features, located in specific metal layers, increase the coupling coefficient through capacitive interaction.

Claim Score by NHIP

Read claim 7, the broadest

Abstract

The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer.

US9633940B2, drawing sheet 1 — Sheet 1 of 19

Term

5.1 yearsleft in the term

Expires 25 October 2031.

20 claims: 3 independent, 17 dependent

1
A method comprising:forming a first conductive feature having first two ports over a semiconductor substrate;forming a second conductive feature having second two ports over the semiconductor substrate, wherein the first and second conductive features are inductively coupled;and forming a third conductive feature over the semiconductor substrate, the third conductive feature being electrically coupled to at least one of the first and second conductive features and having an end that is electrically floating, the third conductive feature being capacitively coupled with at least one of the first and second conductive features.
7
Broadest claimClaim Score 81, broad(NHIP)A method comprising:forming a first conductive feature over a substrate;forming a second conductive feature over the substrate;forming a third conductive feature over the substrate, the third conductive feature being electrically coupled to the first conductive feature and capacitively coupled to the second conductive feature, the third conductive feature having an end that is electrically floating;and forming a via over the first and second conductive features, wherein the via extends continuously from the first conductive feature to the second conductive feature.
14
A method of fabricating a semiconductor device, comprising:forming an interconnect structure over a substrate, the interconnect structure having layers of metal lines and levels of via features interconnecting the layers of metal lines, wherein the forming the interconnect structure includes forming a transformer with a subset of the metal lines and a subset of the via features, the transformer having: a first conductive feature having first two ports;a second conductive feature having second two ports;a third conductive feature electrically connected to the first conductive feature and having at least first two ends that are electrically floating;and a fourth conductive feature electrically connected to the second conductive feature, wherein the first and second conductive features are inductively coupled, and the third and fourth conductive features are capacitively coupled.

Independent claims3

83 paragraphs in 4 sections, as filed

PRIORITY DATA

0001The present application is a divisional application of U.S. application Ser. No. 13/280,786, filed Oct. 25, 2011, which is incorporated herein by reference in its entirety.

BACKGROUND

0002The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.

0003Various active or passive electronic components can be formed on a semiconductor IC. For example, a transformer may be formed as a passive electronic component. As device sizes continue to decrease for even higher frequency applications, traditional transformer structures may encounter problems, such as reduced mutual inductive coefficient K and reduced self-resonant frequency. Particularly, when a transformer is applied with an electrical voltage having a high frequency up to 30 GHz, the mutual inductive coefficient drops to 0.6 or less. The self-resonant frequency also drops down with decreased device size by advancing technology nodes.

0004Therefore, while existing transformer devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

0005Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

0006<figref idref="DRAWINGS">FIG. 1</figref> is a flowchart of method to fabricate a semiconductor device having a transformer with capacitive coupling features in one or more embodiments.

0007<figref idref="DRAWINGS">FIG. 2</figref> is a schematic view of a semiconductor device having a transformer with capacitive coupling features constructed according to aspects of the present disclosure in one or more embodiments.

0008<figref idref="DRAWINGS">FIG. 3</figref> is a sectional view of a semiconductor device having a transformer with capacitive coupling features constructed according to aspects of the present disclosure in other embodiments.

0009<figref idref="DRAWINGS">FIGS. 3a, 3b, 3c and 3d </figref>are top views of various features in the transformer of <figref idref="DRAWINGS">FIG. 3</figref> constructed according to various aspects of the present disclosure in various embodiments.

0010<figref idref="DRAWINGS">FIG. 4</figref> is a perspective view of a transformer with one or more capacitive coupling features according to one or more embodiments.

0011<figref idref="DRAWINGS">FIGS. 4a, 4b and 4c </figref>are perspective views of various features of the transformer in <figref idref="DRAWINGS">FIG. 4</figref> according to various embodiments.

0012<figref idref="DRAWINGS">FIG. 5</figref> is a diagram of various characteristic data of a transformer having one or more capacitive coupling feature.

0013<figref idref="DRAWINGS">FIGS. 6 and 7</figref> are perspective views of a transformer in various embodiments.

0014<figref idref="DRAWINGS">FIG. 8</figref> is a diagram of various characteristic data of the transformer in <figref idref="DRAWINGS">FIG. 7</figref>.

0015<figref idref="DRAWINGS">FIGS. 9-13</figref> are sectional views of a transformer, in portion, with capacitive coupling according to various embodiments.

0016<figref idref="DRAWINGS">FIGS. 14-15</figref> are sectional views of a transformer, in portion, with capacitive coupling according to other embodiments.

0017<figref idref="DRAWINGS">FIGS. 16a and 16b </figref>illustrate another embodiment of a transformer with capacitive coupling in sectional views.

0018<figref idref="DRAWINGS">FIGS. 16c-16e </figref>illustrate various portions of the transformer in <figref idref="DRAWINGS">FIGS. 16a and 16b </figref>in top views.

0019<figref idref="DRAWINGS">FIG. 17</figref> illustrates another embodiment of a transformer with capacitive coupling in a sectional view.

DETAILED DESCRIPTION

0020It is understood that the following disclosure provides many different embodiments, or examples, for implementing different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

0021Illustrated in <figref idref="DRAWINGS">FIG. 1</figref> is a flowchart of a method 20 for fabricating a semiconductor device that includes a transformer structure. <figref idref="DRAWINGS">FIG. 2</figref> is a schematic view of a semiconductor structure 50 having a transformer with capacitive coupling features constructed according to aspects of the present disclosure in other embodiments. The semiconductor structure 50 and the method 20 are collectively described below with reference to <figref idref="DRAWINGS">FIGS. 1 and 2</figref>.

0022The semiconductor structure 50 may include an integrated circuit (IC) chip, system on chip (SoC), or portion thereof, that may include various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, metal-oxide semiconductor field effect transistors (MOSFET), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), laterally diffused MOS (LDMOS) transistors, high power MOS transistors, or other types of transistors. It is understood that the Figures discussed herein have been simplified for a better understanding of the inventive concepts of the present disclosure. Accordingly, it should be noted that additional processes may be provided before, during, and after the method 20 of <figref idref="DRAWINGS">FIG. 1</figref>, and that some other processes may only be briefly described herein.

0023The method 20 begins with block 22 in which a substrate 52 is provided. The substrate 52 includes a surface 53 that defines an axis “Z” perpendicular to the surface 53. The substrate 52 may include a semiconductor substrate, such as silicon substrate, or other suitable substrate. Alternatively or additionally, the substrate 52 includes germanium, silicon germanium or other proper semiconductor materials. The substrate 52 also includes various isolation features, such as shallow trench isolation (STI), formed in the substrate to separate various devices. The semiconductor substrate also includes various doped regions such as n-well, p-wells, light doped drain (LDD) features and heavily doped source and drain (S/D) features. Those doped features and other features (e.g., gate electrode) are configured to form various active and passive devices.

0024The method 20 begins with block 24 in which an interconnect structure 54 is formed on the substrate 52. The interconnect structure 54 includes a plurality of conductive lines interconnected by a plurality of vias (or via features). Particularly, the interconnect structure includes multiple metal layers, such as metal one M1, metal two M2 and so on. The metal layers are perpendicular to the axis Z. The plurality of conductive lines belong to respective metal layers. The conductive lines and via features are configured to provide horizontal and vertical routings, respectively. The conductive lines and via features are couple with the various devices on the substrate, forming one or more functional circuits. Furthermore, the interconnect structure is designed to provide electrical routings between the devices and input/output signals.

0025In another embodiment, each of the metal lines and via features further includes a barrier layer and bulk metal where the barrier layer is disposed to separate the bulk metal from the adjacent dielectric material. In one example, the barrier layer includes titanium nitride, tantalum nitride or other suitable material to prevent inter-diffusion between the bulk metal and the dielectric material. In another example, the bulk metal includes copper, aluminum (or aluminum copper alloy), tungsten or other suitable metal. In yet another example, the dielectric material includes silicon oxide, low k dielectric material or other dielectric material to provide isolation among various metal lines and via features.

0026The interconnect structure 54 is formed in a manner such that a transformer 56 is formed in the interconnect structure. The transformer 56 is formed with at least some of the conductive lines and at least some of the vias of the interconnect structure 54. In one embodiment, the transformer includes a first conductive feature (first inductive coupling feature or inductive conductive feature) 62 and a second conductive feature (second inductive coupling feature or second inductive conductive feature) 64 configured to be inductively coupled. Particularly, the first conductive feature 62 includes a first coil element and the second conductive feature 64 includes a second coil element. The first conductive feature 62 further includes first two ports extended from the first coil element and connected with one of input/output signals. Similarly, the second conductive feature 64 includes second two ports connected with another one of input/output signals. One of the first conductive feature 62 and second conductive feature 64 is configured as a primary coil of the transformer 56 and the another is configured as a secondary coil.

0027The transformer 56 defines a mutual inductance M between the first and second conductive features 62 and 64. A coupling coefficient K is defined to the transformer as well. The coupling coefficient K ranges between 0 and 1. The mutual inductance is related to the coupling coefficient K. In one example wherein the transformer 56 only includes the first and second inductive coupling features 62 and 64, the mutual inductance M is related to the coupling coefficient K by M=K(L1*L2)1/2, wherein L1 is the self-inductance of the first coil element and L2 is the self-inductance of the second coil element.

0028The first and second conductive features 62 and 64 are integrated in one or more metal layers and are approximate from each other such that the mutual inductance is enhanced. In one embodiment, the first and second conductive features 62 and 64 are substantially configured in a same metal layer or same two metal layers. In one embodiment, the first and second conductive features 62 and 64 are configured in two approximate metal layers and each may include metal lines in the two metal layers and via features between the two metal layers. In furtherance of the embodiment, the first and second coil elements are configured one metal layer and the first and second ports are distributed on the two metal layers. In another embodiment, the first conductive feature 62 and second conductive feature 64 each include multiple turns and are configured to be inter-wound with each other to enhance the mutual inductance. In another embodiment, the first conductive feature 62 and second conductive feature 64 each include one turn and are configured such that the second conductive feature 64 surrounds the first conductive feature 62 in a top view. In an alternative embodiment, the first conductive feature 62 and second conductive feature 64 each include one turn and are configured such that the first conductive feature 62 surrounds the second conductive feature 64 in a top view.

0029The transformer 56 further includes a third conductive feature (first capacitive coupling feature or capacitive conductive feature) 66 approximate to the first conductive feature 62 and is electrically connected to the first conductive feature 62 through one or more via feature 67. The third conductive feature 66 is designed and configured to provide a capacitive coupling between the primary coil and the secondary coil. Particularly, the third conductive feature 66 is capacitively coupled with the second conductive feature 64 and thus further increase the mutual inductance M and the coupling coefficient K through the capacitive coupling. In one embodiment, the third conductive feature 66 is substantially aligned with the first and second conductive features 62 and 64 in the top view, enhancing the capacitive coupling effect. In another embodiment, the third conductive feature 66 is configured between the substrate 52 and the conductive features 62/64 to additionally shield the transformer 56 from the substrate 52, reducing the magnetically induced loss on the substrate 52.

0030In another embodiment, the transformer 56 further includes a fourth conductive feature (second capacitive coupling feature or capacitive conductive feature) 68 approximate to the second conductive feature 64 and is electrically connected to the second conductive feature 64 through one or more via feature 69. The fourth conductive feature 68 is designed and configured to provide additional capacitive coupling between the primary coil and the secondary coil. Particularly, the fourth conductive feature 68 is capacitively coupled with the first conductive feature 62 and thus further increase the mutual inductance M and the coupling coefficient K through the respective capacitive coupling. In one embodiment, the fourth conductive feature 68 is substantially aligned with the conductive features 62 and 64 in the top view to enhance the capacitive coupling effect. In another embodiment, the fourth conductive feature 68 is configured overlying the conductive features 62 and 64 to further provide a shielding effect for shielding the transformer 56 from other portions of the interconnect structure 54. Alternatively, the fourth conductive feature 68 is disposed between the third conductive feature 66 and the substrate 52.

0031The third and fourth conductive features 66 and 68 are designed and configured for capacitive coupling effect, increasing the mutual inductance M and the coupling coefficient K of the transformer 56. In one embodiment, each of the third and fourth conductive features 66 and 68 is designed to have a large enough conducive area for capacitive coupling, but each has a geometry that substantially reduces the eddy current (therefore reduced inductive coupling). In furtherance of the embodiment, each of the third and fourth conductive features 66 and 68 has an open structure with at least two floating ends and therefore the eddy current is eliminated or reduced. In another embodiment, the third and fourth conductive features 66 and 68 are disposed within a same region of the substrate 52 and substantially overlap with each other, in the top view, to increase the capacitive coupling area. In yet another embodiment, the third and fourth conductive features 66 and 68 are configured to sandwich the first and the second conductive features (coil elements) 62 and 64. In another embodiment, the third and fourth conductive features 66 and 68 are alternatively configured such that the third conductive feature 66 is coupled with the second conductive feature 64 and the fourth conductive feature 68 is coupled with the first conductive feature 62.

0032In one embodiment, each of the first and second conductive features 62 and 64 is disposed on both first and second metal layers, the third conductive feature 66 is disposed on a third metal layer and the fourth conductive feature 68 is disposed on a fourth metal layer. In one example, the third metal layer is below the first and second metal layers and the fourth metal layer is above the first and second metal layers. In another example, the third metal layer is below the first and second metal layers and the fourth metal layer is below the third metal layer. In another example, at least one of the third and fourth conductive features 66 and 68 is electrically grounded. In another example, at least one of the third and fourth conductive features 66 and 68 is electrically floating. In another embodiment, only one of the third and fourth conductive features is present and another one is eliminated from the transformer.

0033Although not specifically shown for the sake of simplicity, the interconnect structure 54 further includes one or more dielectric material layers such that the various metal features (metal lines and via features) are embedded in. The dielectric material layers provide isolation function to the interconnect structure. The dielectric material layers may include silicon oxide, silicon nitride, silicon oxy-nitride, un-doped silicate (USG), fluoride-doped silicate (FSG), and/or a low-k dielectric material. The various interconnection features may implement various conductive materials including copper, tungsten, aluminum or silicide. In one example, a damascene process is used to form copper related interconnect structure. In another example, a metal etch process may be used to form aluminum related interconnect structure.

0034Various embodiments of the transformer are illustrated below with reference to respective figures and further described. <figref idref="DRAWINGS">FIG. 3</figref> is a sectional view of a semiconductor device 70 having a transformer constructed according to various aspects in one or more embodiments. The semiconductor device 70 includes a transformer 56 integrated in the interconnect structure 54. In the depicted embodiment, the interconnect structure 54 includes three consecutive metal layers 72, 74 and 76. Particularly, the metal layer 74 is disposed on the metal layer 72 and the metal layer 76 is disposed on the metal layer 74. The interconnect structure 54 further includes a first via layer 78 and a second via layer 80. The first via layer 78 includes a plurality of via features between the metal layers 72 and 74, and the second via layer 80 includes a plurality of via features between the metal layers 74 and 76. The transformer 56 is formed in the consecutive metal layers (72, 74 and 76) and the via layers (78 and 80).

0035The transformer 56 includes a first conductive feature 62 and a second conductive feature 64 configured to be inductively coupled. The first conductive feature 62 includes a first coil element. The first conductive feature 62 further includes first two ports extended from the first coil element and connected with one of input/output signals. Particularly, the first conductive feature 62 includes metal lines 62a and 62e in the metal layer 74; metal lines 62c in the metal layer 72; and the via features 62b and 62d in the first via layer 78. The metal lines 62a define a coil structure as the first coil element. The metal lines 62e form two ports of the first conductive feature 62 and are connected to the first coil element through via features 62d, metal lines 62c and via features 62b. <figref idref="DRAWINGS">FIG. 3a </figref>illustrates the metal lines 62e as the first coil element in a top view toward the substrate 52. Two directions (or axis) X and Y are defined on the substrate 52 and are perpendicular to each other. Both directions X and Y are further perpendicular to the axis Z. The axis X and Y define a plane parallel to the surface 53 of the substrate 52.

0036Similarly, the second conductive feature 64 includes a second coil element disposed in the metal layer 74 and is further illustrated in <figref idref="DRAWINGS">FIG. 3b </figref>as a top view. The second conductive feature 64 further includes second two ports extended from the second coil element and connected with another one of input/output signals. In one embodiment, the conductive feature 64 may be connected to a voltage source or a ground line, such as through the central portion 64a of the conductive feature 64. The second coil element and the second two ports include various metal lines properly configured and disposed in the metal layer 74. One of the first and second conductive features 62 and 64 is configured as a primary coil and the another is configured as a secondary coil. The transformer 56 defines a mutual inductance between the primary and secondary coils.

0037The transformer 56 further includes a third conductive feature 66 electrically connected to the first conductive feature 62. The third conductive feature 66 is designed and configured to provide a capacitive coupling to the transformer 56 and to increase the mutual inductance by the capacitive coupling. The third conductive feature 66 is disposed on the metal layer 72 between the substrate 52 and the two coil elements. The third conductive feature 66 includes metal strips 66a in the metal layer 72 and further includes connecting features 66b (such as one or more via features) to connect the metal strips 66a to the first coil element. In one example, the connecting features 66b include conventional via features. In the depicted embodiment, the connecting features 66b include an elongated via feature oriented such that to increase the contact areas with the first coil element and the metal strips 66a.

0038The metal strips 66a as a portion of the third conductive feature 66 is further illustrated in <figref idref="DRAWINGS">FIG. 3c </figref>in a top view. The metal strips 66a do not form a closed path in order to reduce or eliminate eddy currents induced therein, thus enhancing the capacitive coupling. In one embodiment, the metal strips 66a include two or more free (floating) ends. The metal strips are oriented along the direction of the corresponding segments of the first coil element. Furthermore, the via features 66b are oriented in the same direction and are aligned with the corresponding segments of the first coil element and the respective metals trips 66a for connecting the metal strips 66a to the first coil element. In the depicted embodiment, the metal strips 66a include two metal strips oriented along the Y axis. The metal strips 66a may have width similar to the width of other metal lines in the same metal layer or greater than that to increase capacitive coupling area. For example, the metal strips has a width ranging from about 5 times to about 10 times of the width of the other metal lines in the same metal layer. In another example, the metal strips has a width ranging from about 5 times to about 10 times of the width of the metal lines in the first and second coil elements.

0039The transformer 56 further includes a fourth conductive feature 68 electrically connected to the second conductive feature 64. The fourth conductive feature 68 is designed and configured to further provide a capacitive coupling to the transformer 56. The fourth conductive feature 68 is disposed on the metal layer 76 overlying the two coil conductors. The fourth conductive feature 68 includes metal lines in the metal layer 76 and is connected to the second conductive feature 64 through one (or more) via feature 68b. In one example, the via feature 68b includes an elongated via feature oriented to have increased contact areas with the conductive feature 64.

0040The metal strips 68a as a portion of the fourth conductive feature 68 is further illustrated in <figref idref="DRAWINGS">FIG. 3d </figref>in a top view. The metal strips 68a do not form a closed path to reduce or eliminate eddy currents, thus enhancing the capacitive coupling. In one embodiment, the metal strips 68a include two or more free (floating) ends. In another embodiment, the metal strips 68a may be connected to a voltage source or a ground line, such as through a portion 68c of the conductive feature 68a. The metal strips 68a are oriented along the direction of the corresponding segments of the second coil element. Furthermore, the via features 68b are oriented in the same direction and are aligned with the corresponding segments of the second coil element and the respective metals trips 68a for connecting the metal strips 68a to the second coil element. In the depicted embodiment, the metal strips 68a include various segments configured to substantially overlap with the second coil element. In furtherance of the embodiment, the various segments are connected without forming a closed path. The metal strips 68a may have width similar to the width of other metal lines in the same metal layer or greater than that to increase capacitive coupling area. For example, the metal strips has a width ranging from about 5 times to about 10 times of the width of other metal lines in the same metal layer. In another example, the metal strips has a width ranging from about 5 times to about 10 times of the width of the metal lines in the first and second coil elements.

0041In one embodiment, the fourth conductive feature 68 is alternatively disposed under the third conductive feature 66. In another embodiment, the metal strips 66a may be designed differently, such as with a geometry similar to the one in <figref idref="DRAWINGS">FIG. 3d</figref>. In another embodiment, the metal strips 68a may be designed differently, such as with a geometry similar to the one in <figref idref="DRAWINGS">FIG. 3</figref>c.

0042Furthermore, the first, second, third and fourth conductive features are disposed within a same region of the substrate 52 such that they are substantially aligned and overlapped in the top view, enhancing respective inductive coupling and capacitive coupling effects. The third and fourth conductive features 66/68 are configured to sandwich the first and second conductive features 62 and 64 for shielding effect, reducing the magnetically induced loss on the substrate 52 and/or on other portions of the interconnect structure 54.

0043<figref idref="DRAWINGS">FIG. 4</figref> is a diagrammatic view of a transformer 82 as an embodiment of the transformer 56 in <figref idref="DRAWINGS">FIG. 2</figref> or the transformer 70 in <figref idref="DRAWINGS">FIG. 3</figref>, integrated in the interconnect structure 54. The transformer 82 includes a first conductive feature 62 and a second conductive feature 64 configured to be inductively coupled. Particularly, the first conductive feature 62 includes a first coil element and the second conductive feature 64 includes a second coil element. The first conductive feature 62 further includes first two ports 84 connected with one of input/output signals. Similarly, the second conductive feature 64 further includes second two ports 86 connected with another one of input/output signals. The transformer 82 defines a mutual inductance. One of the first conductive feature 62 and second conductive feature 64 is configured as a primary coil for the transformer 56 and the another one is configured as a secondary coil.

0044The transformer 82 further includes a third conductive feature 66 approximate to the first conductive feature 62; underlying the first and second conductive features 62 and 64; and is electrically connected to the first conductive feature 62. The third conductive feature 66 is designed and configured to provide a capacitive coupling between the primary coil and the secondary coil, increasing the mutual inductance by the capacitive coupling.

0045The transformer 82 further includes a fourth conductive feature 68 approximate to the second conductive feature 64 and is electrically connected to the second conductive feature 64 through via feature and metal lines. In the present embodiment, the fourth conductive feature 68 is disposed underlying the third conductive feature 66 and is designed and configured to provide additional capacitive coupling between the primary coil and the secondary coil.

0046The transformer 82, including the first, second, third and fourth conductive features (62, 64, 66 and 68), are formed in three consecutive metal layers. Various via features are formed and configured to connect neighboring metal layers. Various portions of the transformer 82 are further illustrated in <figref idref="DRAWINGS">FIGS. 4a, 4b and 4c</figref>, respectively, as diagrammatic views with further description.

0047<figref idref="DRAWINGS">FIG. 4a </figref>illustrates a first portion of the transformer 82 in a first metal layer 88 including various metal lines 62a, 62e, 64 and 90. The metal lines 62a form a first coil element. The first two ports 84 of the first conductive feature 62 include the metal lines 62e and further include other conductive features (linking features 94) to enable a proper connection to the first coil element. The metal lines 64 form a second coil element. Second two ports 86 are connected to the second coil element. The first coil element is surrounded by the second coil element.

0048<figref idref="DRAWINGS">FIG. 4b </figref>illustrates a second portion 92 of the transformer 82, including metal lines in a second metal layer and via features between the first and second metal layer. The second portion 92 includes the third conductor features 66, two linking features 94 and another linking feature 96. The third conductor feature 68 includes two metal strips and elongated via features landing on respective metal strips. The two linking features 94 include metal lines and via features configured to connect the metal lines 62e to the first coil element. The two linking features 94 and the metal lines 62e form the first two ports 84. The linking feature 96 includes a metal line and a via feature (below and above the respective metal line) configured to connect the fourth conductive feature 68 to the second coil element.

0049<figref idref="DRAWINGS">FIG. 4c </figref>illustrates a third portion of the transformer 82 as the fourth conductive feature 68 electrically connected to the second coil element through the linking feature 96. The fourth conductive feature 68 does not form a closed path. For example, the fourth conductive feature 68 includes two floating ends, defining an opening 98. Alternatively, the fourth conductive feature 68 may be connected with a voltage source or a ground line, such as through a portion 99 of the fourth conductive feature 68.

0050Alternatively, the linking feature 96 is configured to connect the fourth conductive feature 68 to the first coil element and the third conductive feature 66 are connected to the second coil element. In yet another alternative embodiment, each of the first and second may include more than one turns configured in multiple metal layers. In yet another embodiment, each of the third and fourth conductive features may be configured in multiple metal layers but does not form a closed path. In yet another alternative embodiment, the linking feature 96 and the fourth conductive feature 68 may be eliminated from the transformer 82.

0051<figref idref="DRAWINGS">FIG. 5</figref> is a diagram of various characteristic data of a semiconductor device having a transformer with one or more capacitive coupling features in various examples. The horizontal axis represents the frequency (GHz) of a signal applied to the primary coil element. The vertical axis represents the coupling coefficient “K” of a transformer. The various data are from various examples. A first set of data labeled as “A” are from a transformer, such as one embodiment of the transformer 50 in <figref idref="DRAWINGS">FIG. 2</figref>, the transformer 70 in <figref idref="DRAWINGS">FIG. 3</figref> or the transformer 82 in <figref idref="DRAWINGS">FIG. 4</figref>. Particularly, the transformer includes the first, second, third and fourth conductive features 62, 64, 66 and 68. A second set of data labeled as “B” are from a transformer, such as another embodiment of the transformer 50 in <figref idref="DRAWINGS">FIG. 2</figref>. Particularly, the transformer includes the first, second and third conductive features 62, 64 and 66. A third set of data labeled as “C” are from a transformer with only the first and second conductive features 62 and 64. However, the transformer does not include the third and fourth conductive features 66 and 68. From the diagram, the coupling coefficient K is increased (from “C” to “B”) when the third conductive feature 66 is added to a transformer according to one example. The coupling coefficient K is further increased (from “B” to “C”) when both the third conductive feature 66 and the fourth conductive feature 68 are added to a transformer according to anther example. According to the provided example, the coupling coefficient of a transformer may be increased by about 30% (form “C” to “A”) when both the third conductive feature 66 and the fourth conductive feature 68 are added to the transformer.

0052Although various embodiments are described, other embodiments of the transformer with additional capacitive coupling may be used according to the present disclosure. <figref idref="DRAWINGS">FIGS. 6 and 7</figref> are diagrammatic fragmentary perspective views of a transformer 100 in another embodiment. <figref idref="DRAWINGS">FIG. 6</figref> only shows the first and second conductive features 62 and 64 that may be incorporated into the transformer 50, 70 or 82 in <figref idref="DRAWINGS">FIGS. 3, 4 and 5</figref>, respectively. The first and second coil elements are inductively coupled but are differently configured. The first coil element and the second coil element are disposed in a same metal layer. Furthermore, the first two ports 84 and the second two ports 86 are respectively connected to the first and second coil elements in a different configuration. Particularly, the first coil element includes a first portion (P1) and a second portion (P2) and the second coil element includes a third portion (P3) and a fourth portion (P4) configured such that the first portion and the fourth portion substantially surround the second portion and the third portion inside in a top view. The first and second portions are connected through a first linking feature L1 and the third and fourth portions are connected through a second linking feature L2. One of the first two ports 84 is connected to the first coil element through an underlying metal layer and a via feature. One of the second two ports 86 is connected to the second coil element through the underlying metal layer and another via feature. One of the first and second conductive features 62 and 64 is the primary coil element and the another one is the secondary coil element.

0053The semiconductor device 100 in <figref idref="DRAWINGS">FIG. 7</figref> includes the third conductive feature 66 and the fourth conductive feature 68 to provide capacitive coupling to the transformer and increase the mutual inductance thereof through the capacitive coupling. The third conductive feature 66 and the fourth conductive feature 68 are designed and configured similar to the third conductive feature 66 and the fourth conductive feature 68 in <figref idref="DRAWINGS">FIG. 4</figref>. Particularly, the third conductive feature 66 is electrically connected to the first conductive feature 62 and the fourth conductive feature 68 is electrically connected to the second conductive feature 64. In alternative embodiment, the semiconductor device 100 may only include one of the third conductive feature 66 and the fourth conductive feature 68.

0054<figref idref="DRAWINGS">FIG. 8</figref> is a diagram of various characteristic data of the semiconductor device 100 having a transformer with capacitive coupling features according to one or more embodiments. The horizontal axis represents the frequency (GHz) of a signal applied to the primary coil element. The vertical axis represents the coupling coefficient “K” of a transformer. The various data are from various examples. A first set of data labeled as “D” are from the transformer 100 according to one embodiment in which the transformer includes only the third conductive feature 66. Particularly, the transformer includes the first, second and third conductive features 62, 64 and 66. A second set of data labeled as “E” are from a transformer with only the first and second conductive features 62 and 64 without any of the third and fourth conductive features 66 and 68 for capacitive coupling. From the diagram, the coupling coefficient K of the transformer with capacitive coupling feature is increased. According the provided example, the mutual inductance of the transformer 100 with one of third and fourth conductive features 66 and 68 has a coupling coefficient K increased up to about 0.73 at the frequency 60 GHz.

0055<figref idref="DRAWINGS">FIGS. 9 through 13</figref> are fragmental sectional views of a transformer 102 having one or more capacitive coupling features constructed according to various embodiments. The transformer 102 may be incorporated in the semiconductor structure 70 of <figref idref="DRAWINGS">FIG. 3</figref> or the semiconductor structure 50 of <figref idref="DRAWINGS">FIG. 2</figref>, for examples. The transformer 102 in <figref idref="DRAWINGS">FIG. 9</figref> includes the first and second conductive features inductively coupled and further includes one capacitive coupling feature 68. In <figref idref="DRAWINGS">FIG. 9</figref>, the transformer 102 is disposed in two metal layers (Mn and Mn+1) and a layer of via features (Vn) between Mn and Mn+1. The first conductive feature 62 and the second conductive feature 64 are disposed on the metal layer Mn. The capacitive conductive feature 68 is disposed on the metal layer Mn+1 overlying the metal layer Mn. The capacitive conductive feature 68 is electrically connected to the second conductive feature 64 through one or more via feature 103 in the layer of via features Vn.

0056The transformer 102 in <figref idref="DRAWINGS">FIG. 10</figref> includes the first and second conductive features 62 and 64 inductively coupled and further includes the third and fourth conductive features 66 and 68 to provide capacitive coupling and increase the mutual inductance or the coupling coefficient of the transformer 102. In <figref idref="DRAWINGS">FIG. 10</figref>, the transformer 102 is disposed in three metal layers (Mn, Mn+1 and Mn+2) and two via layers (Vn and Vn+1). The first conductive feature 62 and the second conductive feature 64 are disposed on the metal layer Mn+2. The capacitive conductive feature 68 is disposed on the metal layer Mn+1 underlying the metal layer Mn+2. The capacitive conductive feature 68 is electrically connected to the second conductive feature 64 through one or more via feature 103 in the layer of via features. The capacitive conductive feature 66 is disposed on the metal layer Mn underlying the metal layer Mn+1. The capacitive conductive feature 66 may be electrically grounded. The capacitive conductive feature 66 may be further electrically connected to or disconnected from the first conductive feature 62.

0057The transformer 102 in <figref idref="DRAWINGS">FIG. 11</figref> includes the first and second conductive features inductively coupled and further includes one capacitive coupling feature 68. In <figref idref="DRAWINGS">FIG. 11</figref>, the transformer 102 is disposed in two metal layers (Mn and Mn+1) and a layer of via features (Vn) between Mn and Mn+1. The first conductive feature 62 and the second conductive feature 64 are disposed on the metal layer Mn+1. The capacitive conductive feature 68 is disposed on the metal layer Mn underlying the metal layer Mn+1. The capacitive conductive feature 68 is electrically connected to the second conductive feature 64 through one or more via feature 103 in the layer of via features Vn.

0058The transformer 102 in <figref idref="DRAWINGS">FIG. 12</figref> includes the first and second conductive features inductively coupled and further includes the third and fourth conductive features 66 and 68 to provide capacitive coupling and increase the mutual inductance of the transformer 102. In <figref idref="DRAWINGS">FIG. 12</figref>, the transformer 102 is disposed in three metal layers (Mn, Mn+1 and Mn+2) and two layers of via features (Vn and Vn+1). The first conductive feature 62 and the second conductive feature 64 are disposed on the metal layer Mn+1. The capacitive conductive feature 66 is disposed on the metal layer Mn+2 overlying the metal layer Mn+1. The capacitive conductive feature 66 is electrically connected to the first conductive feature 62 through one or more via feature 103 in the layer Vn+1. The capacitive conductive feature 68 is disposed on the metal layer Mn underlying the metal layer Mn+1. The capacitive conductive feature 68 is electrically connected to the second conductive feature 64 through one or more via feature 105 in the layer Vn.

0059The transformer 102 in <figref idref="DRAWINGS">FIG. 13</figref> includes the first and second conductive features inductively coupled and further includes the third and fourth conductive features 66 and 68 to provide capacitive coupling and increase the mutual inductance of the transformer 102. In <figref idref="DRAWINGS">FIG. 13</figref>, the transformer 102 is disposed in three metal layers (Mn, Mn+1 and Mn+2) and two layers of via features (Vn and Vn+1). The first conductive feature 62 and the second conductive feature 64 are disposed on the metal layer Mn+1. The capacitive conductive feature 66 is disposed on the metal layer Mn underlying the metal layer Mn+1. The capacitive conductive feature 66 is electrically connected to the first conductive feature 62 through one or more via feature 105 in the layer Vn. The capacitive conductive feature 68 is disposed on the metal layer Mn+2 overlying the metal layer Mn+1. The capacitive conductive feature 68 is electrically connected to the second conductive feature 64 through one or more via feature 103 in the layer Vn+1.

0060<figref idref="DRAWINGS">FIGS. 14 through 15</figref> illustrate fragmental sectional views of a transformer 104 constructed according to various embodiments. The transformer 104 may be incorporated in the semiconductor structure 70 of <figref idref="DRAWINGS">FIG. 3</figref> or incorporated in a different structure. The transformer 104 in <figref idref="DRAWINGS">FIG. 14</figref> includes the first and second conductive features 62 and 64 inductively coupled. The second conductive feature 64 is configured to be in a same level with the first conductive feature 62, such as in a same metal layer. The second conductive feature 64 is configured to further surrounds the first conductive feature 62. The transformer 104 further includes a third conductive feature 110 disposed underlying the first and second conductive features 62 and 64. The third conductive feature 110 is further connected to the second conductive feature 64 through various conductive linking features 112. The transformer 104 further includes a fourth conductive feature 114 configured underlying the third conductive feature 110. The fourth conductive feature 114 may be configured to be floating or be grounded. Additionally, the fourth conductive feature 104 provides a shielding function to the transformer 104 from environmental circuits and/substrate. The third conductive feature 110 and the fourth conductive feature 114 are designed as a top metal and bottom metal of a capacitor. In one embodiment, the first and second conductive features 62 and 64 are formed on one substrate, such as a silicon substrate while the third and fourth conductive features 110 and 114 are formed on another substrate, such as a packaging substrate or another silicon substrate. The conductive linking features 112 can be formed in a through silicon via (TSV) interposer between the two substrates.

0061The transformer 104 in <figref idref="DRAWINGS">FIG. 15</figref> includes the first and second conductive features 62 and 64 inductively coupled. The first conductive feature 62 and second conductive feature 64 are configured to be in different levels, such as in different metal layers of an interconnect structure. Alternatively, the first conductive feature 62 and second conductive feature 64 are formed on different substrates bonded together through a three-dimensional packaging technique, such as TSV technique. The transformer 104 further includes a third conductive feature 110 and a fourth conductive feature 114 disposed between the first and second conductive features 62 and 64. The third conductive feature 110 is further connected to the first conductive feature 62 through various conductive linking features 112. The fourth conductive feature 114 may be configured to be floating or be grounded. The third conductive feature 110 and the fourth conductive feature 114 are designed as a top metal and bottom metal of a capacitor. The conductive linking features 112 can be formed in a TSV interposer between the two substrates.

0062Another embodiment of a transformer 120 with capacitive coupling is illustrated in <figref idref="DRAWINGS">FIGS. 16a-16e</figref>. Specifically, <figref idref="DRAWINGS">FIGS. 16a and 16b </figref>are sectional views of the transformer 120 from different directions. <figref idref="DRAWINGS">FIGS. 16c, 16d and 16e </figref>are top views of various portions of the transformer 120, respectively. All features are not drawn on scale for simplicity. Particularly, the metal features in a same metal layer are not drawn with same thickness and height such that they can be easily identified and appreciated. Some features are drawn in broken lines for the same purposes. The transformer 120 is another embodiment of the transformer 56 in <figref idref="DRAWINGS">FIG. 2</figref> integrated in the interconnect structure 54. The transformer 120 is described with reference to <figref idref="DRAWINGS">FIGS. 16a through 16e </figref>and <figref idref="DRAWINGS">FIG. 2</figref>. The transformer 120 is formed on the substrate 52 having a top surface 53 defined by X and Y directions. The third direction Z is defined to be perpendicular to both X and Y directions.

0063Referring to <figref idref="DRAWINGS">FIGS. 16a and 16b</figref>, the transformer 120 is formed in two consecutive metal layers interposed by a via layer interconnecting the two metal layers, which are respectively labeled as a first metal layer 122, a via layer 124 and a second metal layer 126, respectively, as illustrated in <figref idref="DRAWINGS">FIGS. 16a and 16b</figref>. Various features in the metal layers and the via layer are described in details with further reference to <figref idref="DRAWINGS">FIGS. 16c, 16d </figref>and 16e.

0064<figref idref="DRAWINGS">FIG. 16c </figref>illustrates a top view of the transformer 120, only the portion in the second metal layer 126. The transformer 120 includes a first coil element 126a, a second coil element 126b and extended conductive lines 126c. The first coil element 126a and second coil element 126b are configured to be inductively coupled.

0065<figref idref="DRAWINGS">FIG. 16d </figref>illustrates a top view of the transformer 120, only the portion in the via layer 124. The transformer 120 includes elongated via features 124a, first via features 124b, second via features 124c and a third via features 124d.

0066<figref idref="DRAWINGS">FIG. 16e </figref>illustrates a top view of the transformer 120, only the portion in the first metal layer 122. The transformer 120 includes first metal lines 122a, second metal lines 122b and a third metal line 122c.

0067Referring back to <figref idref="DRAWINGS">FIG. 16a </figref>as a sectional view of a Y-Z plane and <figref idref="DRAWINGS">FIG. 16b </figref>as a sectional view of a X-Z plane. The metal lines 126c are connected to the second coil element 126b through the via features 124b, the metal lines 122b and the via features 124c. The metal lines 126c serve as two terminals of the second coil element 126b for proper electrical bias. The metal lines 122a are connected to the first coil element 126a through the elongated via features 124a. The metal lines 122a are configured to provide capacitive coupling to the transformer 120. The metal lines 122c is connected to the second coil element 126a through the third via feature 124d. The metal line 122c is configured to provide capacitive coupling to the transformer 120.

0068Other metal features may be may be additionally configured and coupled to provide further capacitive coupling, such as illustrated in <figref idref="DRAWINGS">FIG. 17</figref> as a sectional view of a transformer 130. The transformer 130 is similar to the transformer 120 but further includes a second via layer 132 and a third metal layer 134. Metal lines 134a in the third metal layer 134 are connected to the first coil element 120a through the via features 132a. The metal lines 134a provide additional capacitive coupling to the transformer 130.

0069Although embodiments of the present disclosure have been described in detail, those skilled in the art should understand that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure. For example, the third and fourth conductive features for the capacitive coupling may be formed in sub-metal layers, such as in a level between the neighboring metal layers. In another example, the third and fourth conductive features may be simultaneously formed with integrated capacitors, such as crown capacitors. In another example, the disclosed transformer may be formed by utilizing a TSV interposer when the IC fabrication moves to advanced technology nodes, such as 40 nm or 28 nm. In yet another example, the transformer may includes an additional conductive feature connected to the third or fourth conductive feature to further enhance the capacitive coupling. In yet another example, the transformer may includes an additional conductive feature aligned with the first, second, third and fourth conductive features but are not connected any of those. Particularly, the additional conductive feature is configured to be floating or grounded for shield and/or capacitive coupling effect. The additional conductive feature may be disposed underlying, overlying, or approximate the transformer. In yet another example, one of the conductive features may be connected to a voltage source or a ground line. In furtherance of the example, the second conductive feature 64 (or the fourth conductive feature 68) is connected to a voltage source or a ground line. In various example, one or more ground lines or voltage sources may be connected to different conductive features, respectively.

0070In one example, the dielectric material between the third and fourth conductive features may use a material having a high dielectric constant to increase the capacitive coupling therebetween. In another example, the dielectric material between the first and second conductive features may use a material having a high magnetic permeability to increase capacitive coupling and therefore to increase the coupling coefficient. In yet another example, the present disclosure is not limited to any particular application. For example, the disclosed structure of a transformer and method making the same may be used in any radio frequency integrated circuit (RFIC) applications, such as oscillator, low noise amplifier (LNA) or mixer. In another example, the semiconductor structure having the transformer with capacitive coupling may additionally include other structure, such as a dynamic random access second (DRAM) cell, field programmable gate-array (FPGA) and/or other microelectronic devices (collectively referred to herein as microelectronic devices). Of course, aspects of the present disclosure may be employed in many different applications, including sensor cells, logic cells, and others.

0071In various embodiments of a transformer integrated in a semiconductor structure, the transformer includes two coil elements inductively coupled and further includes one or capacitive coupling features integrated with the first and second coil elements to provide capacitive coupling to the transformer. Various advantages may be present in different examples or embodiments. In one example, the capacitive coupling feature(s) integrated in the transformer increase the mutual inductance M and the coupling coefficient K of the transformer. Therefore the disclosed transformer is referred to as the high-K transformer with capacitive coupling. In another example, the disclosed transformer has a high self-resonance frequency. In another example, the transformer has a application window with much broad frequency range while the mutual inductance is significantly high. In another embodiment, the disclosed transformer may be used for an RFIC application with frequency over 30 GHz with improved mutual inductance. Furthermore, the disclosed transformer with larger frequency window and high mutual inductance may be formed with small dimensions, such as in those advanced technology nodes. In yet another example, the disclosed transformer has reduced loss and a increased quality factor due to the shield functions from the third and/or fourth conductive features.

0072A semiconductor device is disclosed according to one of the broader forms of the present disclosure. In one embodiment, the semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer.

0073In one embodiment of the disclosed semiconductor device, the first conductive feature is electrically connected with first two ports and is further configured to form a first coil element; and the second conductive feature is electrically connected with second two ports and further configured to form a second coil element. In another embodiment, the first coil element includes multiple turns and the second coil element includes multiple turns.

0074In another embodiment, the third conductive feature has at least two ends configured to be electrically floating; and the fourth conductive feature has at least two ends configured to be electrically floating.

0075In yet another embodiment, the interconnect structure includes a plurality of metal layers having a first metal layer, a second metal layer and a third metal layer; the first and second conductive features substantially belong to the first metal layer; the third conductive feature belong to the second metal layer; the fourth conductive feature belong to the third metal layer; and the first, second, third and fourth conductive feature are substantially aligned in a direction perpendicular to the semiconductor substrate to enhance respective inductive and capacitive couplings. The third conductive features may be electrically connected to the first conductive feature through a first via feature between the first and second metal layers. The fourth conductive features may be electrically connected to the second conductive feature though at least second via feature between the first and third metal layers. In one example, the second metal layer is underlying the first metal layer; and the third metal layer is underlying the second metal layer. In another example, the second metal layer is underlying the first metal layer; and the third metal layer is overlying the first metal layer.

0076In another embodiment, the semiconductor device further includes a fifth conductive feature electrically connected to the third conductive feature to further enhance capacitive coupling.

0077The present disclosure also provides another embodiment of an integrated circuit. The integrated circuit includes a transformer disposed on a substrate. The transformer includes a first inductive coupling feature having first two ports; a second inductive coupling feature having second two ports; and a first capacitive coupling feature electrically connected to the first inductive coupling feature and having at least first two ends configured to be floating, wherein the first and second inductive coupling features are configured to be inductively coupled, and the first capacitive coupling feature is configured to be capacitively coupled with the second inductive coupling feature.

0078In one embodiment, the integrated circuit further includes a second capacitive coupling feature electrically connected to the second inductive coupling feature and having at least second two ends configured to be floating, wherein the second capacitive coupling feature is configured to be capacitively coupled with the first inductive coupling feature.

0079In furtherance of the embodiment, the first and second inductive coupling features and the first and second capacitive coupling features are substantially aligned within a same region of the substrate in a top view toward the substrate to enhance corresponding inductive and capacitive couplings. In another embodiment, the integrated circuit further includes an interconnect structure having a plurality of metal layers disposed on the substrate, wherein the transformer is integrated in the interconnect structure. In one example, the first and second inductive coupling features are substantially configured in a same metal layer of the interconnect structure.

0080In another embodiment, the second capacitive coupling feature is underlying the first and second inductive coupling features and the third capacitive coupling features; and the second capacitive coupling feature is further configured to provide a shielding function. In another embodiment, both the first and second capacitive coupling features are underlying the first inductive coupling feature and are overlying the second inductive coupling feature. The integrated circuit may further include an additional substrate configured such that the transformer is distributed between the substrate and the additional substrate; and a through silicon via (TSV) interposer disposed between the substrate and the additional substrate, wherein various features of the transformer are coupled at least partially the TSV interposer. In another embodiment, one of the first inductive feature, the second inductive feature, the first capacitive feature and the second capacitive feature is connected to one of a voltage source and a ground line.

0081The present disclosure also provides an embodiment of a method of fabricating a semiconductor device. The method includes forming an interconnect structure over a substrate, the interconnect structure having layers of metal lines and levels of via features interconnecting the layers of metal lines, wherein the forming the interconnect structure includes forming a transformer with a subset of the metal lines and a subset of the via features, wherein the transformer includes a first conductive feature having first two ports; a second conductive feature having second two ports; a third conductive feature electrically connected to the first conductive feature and having at least first two ends configured to be electrically floating; and a fourth conductive feature electrically connected to the second conductive feature and having at least second two ends configured to be electrically floating. The first and second conductive features are configured to be inductively coupled, and the third and fourth conductive features are configured to be capacitively coupled.

0082In one embodiment, the forming of the interconnect structure includes forming a first metal layer having the first and second conductive features; forming a second metal layer having the third conductive feature; and forming a third metal layer having the fourth conductive feature.

0083The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the detailed description that follows. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Contents4

Every citation, both ways

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201113280786	United States of America	A	2011-10-25

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US2013099352A1	United States of America	A1	2013-04-25
CN103151338A	China	A	2013-06-12
US2013147023A1	United States of America	A1	2013-06-13
CN103187393A	China	A	2013-07-03
US2013168809A1	United States of America	A1	2013-07-04
US8610247B2	United States of America	B2	2013-12-17
US8659126B2	United States of America	B2	2014-02-25
US2014097930A1	United States of America	A1	2014-04-10
US8981526B2	United States of America	B2	2015-03-17
US9087838B2	United States of America	B2	2015-07-21
US2015255207A1	United States of America	A1	2015-09-10
US2015325517A1	United States of America	A1	2015-11-12
CN103187393B	China	B	2015-12-16
US9330830B2	United States of America	B2	2016-05-03
CN103151338B	China	B	2016-12-14
US9633940B2This record	United States of America	B2	2017-04-25

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2016-12-22	Email NotificationEML_NTF	EML_NTF
2016-12-22	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2016-12-19	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2016-12-12	Reasons for AllowanceEX.R	EX.R
2016-08-24	Date Forwarded to ExaminerFWDX	FWDX
2016-08-19	Response after Non-Final ActionA...	A...
2016-06-09	Email NotificationEML_NTR	EML_NTR
2016-06-09	Change in Power of Attorney (May Include Associate POA)PA..	PA..
2016-06-01	Oath or Declaration Filed (Including Supplemental)C602	C602
2016-05-19	Electronic ReviewELC_RVW	ELC_RVW
2016-05-19	Email NotificationEML_NTF	EML_NTF
2016-05-19	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2016-05-11	Non-Final RejectionNon-final rejectionCTNF	CTNF
2016-02-18	Date Forwarded to ExaminerFWDX	FWDX
2016-01-15	Response after Non-Final ActionA...	A...
2016-01-15	Request for Extension of Time - GrantedXT/G	XT/G
2015-11-12	Application ready for PDX access by participating foreign officesCCRDY	CCRDY
2015-11-12	PG-Pub Issue NotificationPG-ISSUE	PG-ISSUE
2015-09-25	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2015-09-21	Non-Final RejectionNon-final rejectionCTNF	CTNF
2015-09-21	Information Disclosure Statement consideredIDSC	IDSC
2015-09-18	Case Docketed to Examiner in GAUDOCK	DOCK
2015-08-07	Application Dispatched from OIPEOIPE	OIPE
2015-08-04	Sent to Classification ContractorPGPC	PGPC
2015-08-04	FITF set to NO - revise initial settingFTFI	FTFI
2015-08-04	Application Is Now CompleteCOMP	COMP
2015-08-04	Application Is Now CompleteCOMP	COMP
2015-08-04	Filing ReceiptFLRCPT.O	FLRCPT.O
2015-07-22	Cleared by OIPE CSRL194	L194
2015-07-20	Patent Term Adjustment - Ready for ExaminationPTA.RFE	PTA.RFE
2015-07-20	Applicants have given acceptable permission for participating foreignAPPERMS	APPERMS
2015-07-20	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2015-07-20	IFW Scan & PACR Auto Security ReviewSCAN	SCAN
2015-07-20	Entity Status Set To Undiscounted (Initial Default Setting or Status Change)BIG.	BIG.
2015-07-20	Initial Exam Team nnIEXX	IEXX

4 legal events, as the office reported them to INPADOC

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Events

Legal events, newest first
	Event	Code
2024-10-09	Maintenance fee paymentMAFP	MAFP
2020-09-30	Maintenance fee paymentMAFP	MAFP
2017-04-05	Information on status: patent grantGrantedPATENTED CASESTCF	STCF
2015-09-10	AssignmentAS	AS