GPU predication

BACKGROUND

Technical Field

This disclosure relates generally to processors, and, more specifically, to graphics processing units that implement predication.

Description of the Related Art

Graphics processing units (GPUs) typically operate on large amounts of graphics data in parallel using multiple execution pipelines or shaders. As modern GPUs are becoming more and more programmable, with less computation done in fixed-function hardware, GPUs are now performing more complicated tasks than ever before. These tasks may include tasks associated with graphics processing as well as tasks that are unrelated to graphics applications through the use of frameworks, such as OpenCL®, to offload workloads from central processing units (CPUs) to GPUs. As GPU complexity has increased, the complexity of their instruction set architectures (ISA) has increased.

Many GPU ISAs now support instructions that affect control flow based on evaluated conditions such as branch instructions. Branch instructions, however, are difficult to implement on a per-instance basis in a single instruction, multiple data (SIMD) machine such as a GPU. GPUs may alternatively use predication as a way to facilitate management of control flow on a per-instance basis.

SUMMARY

In various embodiments, a graphics processing unit is disclosed that implements predication with respect to one or more execution pipelines. In one embodiment, the graphics processing unit may include a first set of architecturally-defined registers and a second set of shadow registers to facilitate implementation of predication. In some embodiments, the shadow registers are located proximal to the outputs of the execution pipelines and are used to store predicate values at writeback. In some embodiments, the shadow registers are used to update the architecturally-defined registers. In one embodiment, the graphics processing unit evaluates predicate values stored in the shadow registers to determine whether to discontinue execution of an instruction sequence.

In some embodiments, multiple instances of an instruction sequence may be executed in parallel. In such an embodiment, a control unit may determine control information relevant to predication (e.g., dependency information, predicate writer information, instance validity information, etc.). In one embodiment, the control unit is configured to minimize the amount of control information that it determines on a per-instance basis.

BRIEF DESCRIPTION OF THE DRAWINGS

<figref idref="DRAWINGS">FIG. 1A</figref> is a block diagram of an exemplary graphics processing pipeline.

<figref idref="DRAWINGS">FIG. 1B</figref> is a block diagram illustrating one embodiment of a graphics processing unit.

<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram illustrating one embodiment of a unified shading cluster.

<figref idref="DRAWINGS">FIG. 3</figref> is a block diagram illustrating one embodiment of an instance execution stack.

<figref idref="DRAWINGS">FIG. 4A</figref> is a block diagram illustrating one embodiment of a table that includes predication information maintained on a per-instruction basis.

<figref idref="DRAWINGS">FIG. 4B</figref> is a block diagram illustrating one embodiment of a table that includes predication information maintained on a per-instance basis.

<figref idref="DRAWINGS">FIG. 5</figref> is a flow diagram illustrating one embodiment of a method for performing predication.

<figref idref="DRAWINGS">FIG. 6</figref> is a block diagram illustrating one embodiment of an exemplary computing system.

This disclosure includes references to “one embodiment” or “an embodiment.” The appearances of the phrases “in one embodiment” or “in an embodiment” do not necessarily refer to the same embodiment. Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

Various units, circuits, or other components may be described or claimed as “configured to” perform a task or tasks. In such contexts, “configured to” is used to connote structure by indicating that the units/circuits/components include structure (e.g., circuitry) that performs those task or tasks during operation. As such, the unit/circuit/component can be said to be configured to perform the task even when the specified unit/circuit/component is not currently operational (e.g., is not on). The units/circuits/components used with the “configured to” language include hardware—for example, circuits, memory storing program instructions executable to implement the operation, etc. Reciting that a unit/circuit/component is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112, sixth paragraph, for that unit/circuit/component. Additionally, “configured to” can include generic structure (e.g., generic circuitry) that is manipulated by software and/or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in a manner that is capable of performing the task(s) at issue. “Configure to” may also include adapting a manufacturing process (e.g., a semiconductor fabrication facility) to fabricate devices (e.g., integrated circuits) that are adapted to implement or perform one or more tasks.

As used herein, the term “based on” is used to describe one or more factors that affect a determination. This term does not foreclose additional factors that may affect a determination. That is, a determination may be solely based on those factors or based, at least in part, on those factors. Consider the phrase “determine A based on B.” While in this case, B is a factor that affects the determination of A, such a phrase does not foreclose the determination of A from also being based on C. In other instances, A may be determined based solely on B.

DETAILED DESCRIPTION

The present disclosure describes embodiments in which a graphics processing unit implements predication. The term “predication” has its ordinary and accepted meaning in the art, and refers to beginning execution of instructions that have a dependency on an instruction (e.g., a predicate writer, discussed below) that affects control flow prior to knowing the outcome of that instruction. More specifically, a sequence of instructions may test a condition (i.e., a predicate) and perform a set of actions based on the outcome of that condition—e.g., an instruction sequence that compares two values and performs a set of operations if the values match. In order to evaluate the condition, the instruction sequence may include an initial set of instructions that help in resolving the predicate (i.e., determining the outcome of the condition). For example, this initial set may include an instruction executable to subtract the two values as a match can be identified if the result is zero. This initial set of instructions may conclude with a final instruction that places a value indicative of the tested condition's outcome (e.g., a Boolean value indicative of a match between the two values) into a register that can be examined by a subsequently executed instruction. As used herein, the term “predicate writer” refers to the instruction that sets a value for an evaluated condition in the register; the value is referred to herein as the “predicate value.” Once a predicate value has been written into a register by a predicate writer, the value may be subsequently examined in order to determine the path of control flow (i.e., whether to perform a set of actions conditional on the predicate value). In the example above, if the two values match, the path of control flow would include performing the set of actions.

As used herein, the term “predicate reader” refers to any instruction that reads a predicate value. In some embodiments, predicate readers include branch instructions, which may affect control flow by changing a program counter based on a predicate value. In the example above, such an instruction may read the predicate value indicative of a match between the two values and adjust the program counter so that the path of control includes (or does not include) performing the set of dependent actions. In some embodiments, predicate readers may, alternatively, include instructions that conditionally execute based on a predicate value. For example, in one embodiment, the graphics processing unit described herein supports multiple versions of an add instruction—i.e., a version that executes independent of any predicate value and a version that executes conditionally on a predicate value having a particular value. In such an embodiment, different versions of the add instruction may have different respective opcodes.

Accordingly, in various embodiments in which predication is implemented, the graphics processing unit may begin execution instructions (i.e., predicate readers) that are dependent on a predicate writer before the predicate value is known. In such an embodiment, if it is later determined that those instructions do not reside in the taken path of control flow (as indicated by the predicate value once it is known), the graphics processing unit does not allow the results of those instructions to be committed updating architectural state. (Note that predication stands in contrast to out-of-order execution used in speculation in that the instructions are still issued in program order.) Continuing with the example above, if the two values do not match, results of the dependent instructions performing the operations may be discarded when predication is implemented.

As discussed below, in various embodiments, the graphics processing unit may implement various techniques to more efficiently implement predication. In one embodiment, a graphics processing unit may include two sets of registers for storing predication information (e.g., predicate values). The first set may be architecturally defined (i.e., the GPU supports ISA-defined instructions for retrieving and/or changing the contents of the registers); however, these registers may be located remotely from the circuitry generating the predicate information. In contrast, the second set of registers may not be architecturally defined, but located proximal to the circuitry determining predication information. In such an embodiment, when a predicate value is determined, it may be initially stored in the second set of registers due to their proximal location before the predicate value is stored in the first set of registers. In some embodiments, the second set of registers feed logic that can disable circuitry (e.g., pipeline stages) executing instructions that reside in the non-taken path (i.e., do not reside in the path of control flow). In various embodiments, disabling the circuitry in this manner can reduce power consumption of the GPU; still further, using the second set of registers to feed logic may allow for the circuitry to be disabled more quickly. In some embodiments, the graphics processing unit is also able to disable circuitry executing the instructions without performing a pipeline stall.

In some embodiments, the graphics processing unit includes multiple execution pipelines to execute instruction streams in parallel. The term “execution pipeline” has its ordinary and accepted meaning in the art, and refers to circuitry that implements performance of operations specified by an instruction. These operations may include fetching, decoding, issuing, executing, committing, etc. (This term is not to be confused with a “graphics pipeline,” discussed below, which refers to a set of operations performed to produce display frames.). As used herein, the term “execution pipeline” may refer to a portion of an execution pipeline or an entire execution pipeline. In such an embodiment, use of multiple execution pipelines may enable the graphics processing unit to execute multiple instances of an instruction sequence in parallel. For example, a first instance of the instruction sequence may be executed in a first execution pipeline to perform operations on pixels in an upper left corner of a frame being displayed while a second instance of the instruction sequence may be executed in a second execution pipeline to perform the same operations on pixels in a lower right corner of the frame. As discussed below, in some embodiments, control information used to facilitate predication may be generated and stored as much as possible on a per-instruction basis, rather than on a per-instance basis. For example, if four instances of the same instruction are being executed, a single set of control information (e.g., dependency information) may be generated, instead of separately generating four copies of the same control information, which is less efficient.

This disclosure initially describes, with reference to <figref idref="DRAWINGS">FIGS. 1A and 1B</figref>, an overview of a graphics pipeline and an exemplary graphics processing unit. The techniques and structures described herein, however, are in no way limited to the graphics pipeline and graphics processing unit shown in <figref idref="DRAWINGS">FIGS. 1A and 1B</figref>; rather, this context is provided only as one possible implementation. Embodiments of a unified shading cluster that implements predication are then described with references to <figref idref="DRAWINGS">FIGS. 2-5</figref>. Finally, an exemplary computing system is described with reference to <figref idref="DRAWINGS">FIG. 6</figref>.

Turning now to <figref idref="DRAWINGS">FIG. 1A</figref>, a block diagram of an exemplary graphics pipeline <b>100</b> for processing graphics data is shown. In one embodiment, transform and lighting step <b>110</b> may involve processing lighting information for vertices received from an application based on defined light source locations, reflectance, etc., assembling the vertices into polygons (e.g., triangles), and/or transforming the polygons to the correct size and orientation based on position in a three-dimensional space. Clip step <b>115</b> may involve discarding polygons or vertices that fall outside of a viewable area. Rasterize step <b>120</b> may involve defining fragments or pixels within each polygon and assigning initial color values for each fragment, e.g., based on texture coordinates of the vertices of the polygon. Shade step <b>130</b> may involve altering pixel components based on lighting, shadows, bump mapping, translucency, etc. Shaded pixels may be assembled in a frame buffer <b>135</b>. As discussed next, graphics processing unit (GPU) <b>150</b> may include programmable shaders that allow customization of shading and other processing steps by application developers. Thus, in various embodiments, the exemplary steps of <figref idref="DRAWINGS">FIG. 1A</figref> may be performed in various orders, performed in parallel, or omitted, and additional processing steps may be implemented.

Turning now to <figref idref="DRAWINGS">FIG. 1B</figref>, a block diagram of a GPU <b>150</b> is shown. In the illustrated embodiment, GPU <b>150</b> includes unified shading cluster (USC) <b>160</b>, vertex pipe <b>185</b>, fragment pipe <b>175</b>, texture processing unit (TPU) <b>165</b>, pixel back end (PBE) <b>170</b>, and memory interface <b>180</b>. In one embodiment, GPU <b>150</b> may be configured to process both vertex and fragment data using USC <b>160</b>, which may be configured to process graphics data in parallel using multiple execution pipelines or instances.

Vertex pipe <b>185</b>, in one embodiment, includes various fixed-function hardware configured to process vertex data. Vertex pipe <b>185</b> may be configured to communicate with USC <b>160</b> in order to coordinate vertex processing. In the illustrated embodiment, vertex pipe <b>185</b> is configured to send processed data to fragment pipe <b>175</b> and/or USC <b>160</b> for further processing.

Fragment pipe <b>175</b>, in one embodiment, includes various fixed-function hardware configured to process pixel data. Fragment pipe <b>175</b> may be configured to communicate with USC <b>160</b> in order to coordinate fragment processing. Fragment pipe <b>175</b> may be configured to perform rasterization on polygons from vertex pipe <b>185</b> and/or USC <b>160</b> to generate fragment data. Vertex pipe <b>185</b> and/or fragment pipe <b>175</b> may be coupled to memory interface <b>180</b> (coupling not shown) in order to access graphics data.

USC <b>160</b>, in one embodiment, is configured to receive vertex data from vertex pipe <b>185</b> and fragment data from fragment pipe <b>175</b> and/or TPU <b>165</b>. USC <b>160</b> may be configured to perform vertex processing tasks on vertex data which may include various transformations and/or adjustments of vertex data. In one embodiment, USC <b>160</b> is also configured to perform fragment processing tasks on pixel data such as texturing and shading, for example. USC <b>160</b> may include multiple execution instances for processing data in parallel. USC <b>160</b> may be referred to as “unified” in the sense that it is configured to process both vertex and fragment data, in some embodiments. In other embodiments, programmable shaders may be configured to process only vertex data or only fragment data.

TPU <b>165</b>, in one embodiment, is configured to schedule fragment processing tasks from USC <b>160</b>. In one embodiment, TPU <b>165</b> may be configured to pre-fetch texture data and assign initial colors to fragments for further processing by USC <b>160</b> (e.g., via memory interface <b>180</b>). TPU <b>165</b> may be configured to provide fragment components in normalized integer formats or floating-point formats, for example. In one embodiment, TPU <b>165</b> may be configured to provide fragments in groups of four (a “fragment quad”) in a 2×2 format to be processed by a group of four execution instances in USC <b>160</b>.

PBE <b>170</b>, in one embodiment, is configured to store processed tiles of an image and may perform final operations to a rendered image before it is transferred to a frame buffer (e.g., in a system memory via memory interface <b>180</b>). Memory interface <b>180</b> may facilitate communications with one or more of various memory hierarchies in various embodiments.

In various embodiments, a programmable shader such as USC <b>160</b> may be coupled in any of various appropriate configurations to other programmable and/or fixed-function elements in a graphics processing unit. The exemplary embodiment of <figref idref="DRAWINGS">FIG. 1B</figref> merely shows one possible configuration of a GPU <b>150</b>.

Turning now to <figref idref="DRAWINGS">FIG. 2</figref>, a block diagram of unified shading cluster (USC) <b>160</b> is depicted. As discussed below, in various embodiments, USC <b>160</b> includes multiple execution pipelines configured to execute instructions. USC <b>160</b> may further implement predication as discussed above. Accordingly, in the illustrated embodiment, USC <b>160</b> includes register store <b>210</b>, instance execution stacks (IESs) <b>220</b>A-N, control unit <b>230</b>, shadow registers <b>240</b>, and predication registers <b>250</b>. In other embodiments, USC <b>160</b> may be configured differently—e.g., in one embodiment, predications registers <b>250</b> may be located within control unit <b>230</b>.

Register store <b>210</b>, in one embodiment, maintains data that is operated on by GPU <b>150</b> including USC <b>160</b>. This data may include, for example, vertex data, pixel data, frame data, etc. for frames being rendered. Register store <b>210</b> may be implemented using any of various appropriate storage structures. In one embodiment, register store <b>210</b> includes a hundred or more registers for each IES <b>220</b>, which may be distributed across multiple banks. In one embodiment, each of these banks may be separately accessed. In one embodiment, each bank of register store <b>210</b> includes registers for multiple IESs <b>220</b>. In other embodiments, register store <b>210</b> may not be split into multiple banks, but may include multiple read ports. In some embodiments, TPU <b>165</b> (discussed above) may be configured to store fragment components in register store <b>210</b> prior to scheduling shader operations on the fragment components.

IESs <b>220</b>, in one embodiment, are execution pipelines, each capable of executing a respective instruction sequence. Accordingly, IESs <b>220</b> may include execution units, such as arithmetic logic units (ALU), that include floating-point units, integer units, shift units, etc. IESs <b>220</b>A-N may be configured to read source operands from register store <b>210</b> and to write execution results to register store <b>210</b> and/or internally forward results back as operands for subsequent instructions. IESs <b>220</b>A-N may include operand cache storage to cache results and/or source operands from register store <b>210</b>. In some embodiments, IESs <b>220</b> may not implement an entire execution pipeline—e.g., in one embodiment, fetch, decode, and issuance stages may be handled by other circuitry (not shown).

In various embodiments, IESs <b>220</b> are configured to execute instances of the same instruction sequence in parallel. For example, IES <b>220</b>A may execute an instruction sequence for a shading operation on a first pixel, while IES <b>220</b>B executes the same instruction sequence on a second pixel. Still further, in some embodiments, IESs <b>220</b> may be multi-threaded. Accordingly, in one embodiment, an IES <b>220</b> may implement thread interleaving such that a stage in the execution pipeline may process an instruction of a first thread during a first cycle, an instruction of a second thread during a second cycle, and so on.

Control unit <b>230</b>, in one embodiment, is configured to manage operation of USC <b>160</b> including register store <b>210</b> and IESs <b>220</b>. Accordingly, in one embodiment, control unit <b>230</b> partially decodes instructions and determines appropriate control information for execution of those instructions. This control information may be used to facilitate routing instructions to the appropriate IESs <b>220</b> and retrieve data from register store <b>210</b>. Control unit <b>230</b> may also be configured to receive commands from a source external to USC <b>160</b> and facilitate implementation of those commands.

In the illustrated embodiment, USC <b>160</b> implements predication through the use of elements <b>220</b>-<b>250</b>.

Shadow registers <b>240</b>, in one embodiment, store the most recent predicate values for resolved predicates. That is, as discussed above, an instruction sequence may include an instruction called a predicate writer that is executable to store a predicate value for a predicate being evaluated. Upon computation of the predicate writer, an IES <b>220</b> may store the predicate value in a shadow register <b>240</b>. This stored value may then be evaluated during execution of a later predicate reader in order to determine control flow. In various embodiments, shadow registers <b>240</b> may support storing predicate values for multiple threads as well as multiple predicate values for a given thread. For example, in one embodiment in which IES <b>220</b>A supports three threads and up to two architecturally-defined predicate registers per thread, shadow registers <b>240</b>A may include six registers. In some embodiments, shadow registers <b>240</b> may store additional metadata about stored predicate values such as initialization bits indicating when predicate values have been stored and dirty bits indicating whether stored predicate values have become stale. In other embodiments, this metadata may be stored elsewhere such as within control unit <b>230</b>. As discussed below in conjunction with <figref idref="DRAWINGS">FIG. 3</figref>, in various embodiments, shadow registers <b>240</b> are configured to provide predicate values to logic configured to evaluate the predicate values in conjunction with control information <b>232</b> in order to determine whether to disable executing instances of instruction sequences. In the illustrated embodiment, registers <b>240</b> are characterized as “shadow” registers because they are not architecturally defined and are configured to mirror predication registers <b>250</b> (i.e., coherence is maintained between with shadow registers <b>240</b> and predication registers <b>250</b>).

Predication registers <b>250</b>, in one embodiment, are architecturally-defined registers that store predicate values. That is, GPU <b>150</b> may support instructions for reading from and/or writing to registers <b>250</b>. In contrast to shadow registers <b>240</b>, in various embodiments, predication registers <b>250</b> are not coupled to control logic configured to disable execution of instructions. Still further, in some embodiments, shadow registers <b>240</b> may be located proximal to control logic and the output stages of IESs <b>220</b>, while predication registers <b>250</b> may be located far away from the control logic and the output stages. As a result, a predicate value may be read from a shadow register <b>240</b> more quickly by IES control logic than if the control logic had read the corresponding predication register <b>250</b>. Thus, the control logic may be able to more quickly discontinue execution of the instruction sequence. Like shadow registers <b>240</b>, in some embodiments, predication registers <b>250</b> may be configured to store predicate values for multiple executing threads, multiple predicate values for each executing instance of a given thread, and even multiple predicate values for a given instance. Predication registers <b>250</b> may also store metadata relevant to predicate values such as initialization bits and dirty bits.

In various embodiments, USC <b>160</b> maintains coherency between shadow registers <b>240</b> and predication registers <b>250</b> by writing resolved predicate values from IESs <b>220</b> to shadow registers <b>240</b> and then using shadow registers <b>240</b> to update predication registers <b>250</b>. For example, as discussed below with <figref idref="DRAWINGS">FIG. 3</figref>, in one embodiment, upon completion of predicate writer, IES <b>220</b>A may write back the predicate value to a shadow register <b>240</b>A, which, in turn, provides the predicate value to the corresponding predication register <b>250</b>. In various embodiments, USC <b>160</b> also maintains coherency by updating shadow registers <b>240</b> with predicate values (referred to as fill-in values) from predication registers <b>250</b>. In one embodiment, such an update may occur responsive to a thread restart. That is, USC <b>116</b> (or more specifically control unit <b>230</b>, in one embodiment) may determine to switch from executing one thread to another thread for various reasons. In performing the switch, predicate values in shadow registers <b>240</b> for the thread may be replaced with predicate values for the new thread (i.e., in such an embodiment, shadow registers <b>240</b> do not store predicate values for non-executing threads; predication registers <b>250</b>, however do. When execution of the original thread is restarted, the predicate values from predication registers <b>250</b> may be written back into shadow registers <b>240</b> in order to main coherency.

In some embodiments, shadow registers <b>240</b> may be updated with predicate values from predication registers <b>250</b> even if the shadow registers <b>240</b> are associated with disabled instances (i.e., instances for which execution has been discontinued). As noted above, an instance of an instruction sequence may be disabled based on a predicate value of a prior predicate writer. An instance of an instruction sequence may also be disabled upon issuance of the instruction sequence to an IES <b>220</b>. This may occur in some embodiments in which the same instruction sequence is issued to all of IESs <b>220</b> regardless whether that many instances need to be executed. That is, for some tasks, it may be appropriate to execute only one or two instances of an instruction sequence. Rather than issue the instruction sequence to merely IES <b>220</b>A and <b>220</b>B, for example, the instruction sequence may be issued, in such an embodiment, to all of IESs <b>220</b>. Instances of the instruction sequence that are not provided to IESs <b>220</b>A and <b>220</b>B, however, may be disabled upon issuance. In some embodiments, maintaining coherence of predicate values for even disabled instances may reduce the overhead for tracking outstanding predicate writers.

In various embodiments, control unit <b>230</b> is further configured to generate control information to facilitate predication—shown in the illustrated embodiment as control information <b>232</b>. In some embodiments, control information <b>232</b> may include information relating to the coherence between registers <b>240</b> and <b>250</b>. Accordingly, in one embodiment, control unit <b>230</b> may write a predicate value to one of predication registers <b>250</b> (e.g., responsive to a thread restart) and, in response to writing the predicate value, issue the predicate value as control information <b>232</b> to the corresponding IES <b>220</b> to cause the predicate value to be stored in a shadow register <b>240</b>. As discussed below with respect to <figref idref="DRAWINGS">FIG. 3</figref>, in such an embodiment, control unit <b>230</b> may use the datapath of an IES <b>220</b> to store the predicate fill-in value in the shadow register <b>240</b>. In some embodiments, control information <b>232</b> may also include dependency information that is used by control logic in evaluating a predicate value to determine whether to disable an instance. As discussed below with respect to <figref idref="DRAWINGS">FIG. 4A</figref>, this dependency information may include an indication of whether an instruction is dependent on a predicate writer and, if so, which particular predicate writer. This dependency information may also include an indication of polarity and an indication of which shadow register <b>240</b> stores the relevant predicate value. In some embodiments, control information <b>232</b> may further identify which instructions are predicate writers as well as specify the registers <b>240</b> to which predicate values are to be written. As discussed below with respect to <figref idref="DRAWINGS">FIG. 4B</figref>, control information <b>232</b> may also include a validity indication specifying whether an instance is still valid (i.e., has not been disabled yet).

In some embodiments, control unit <b>230</b> is configured to determine control information <b>232</b> based on a decode of instructions to be issued to IESs <b>220</b> as well as previously determined predicate values in predication registers <b>250</b>. For example, control unit <b>230</b> may examine opcodes and predicate values to determine general control flow as well as identify which instructions are predicate readers, predicate writers, and instructions dependent on predicate writers. In one embodiment, upon identifying that an instruction sequence includes a predicate writer, control unit <b>230</b> may set a dirty bit for the predication register <b>250</b> relevant to that predicate writer as any stored predicate value in that register <b>250</b> may become stale upon completing execution of the predicate writer.

In various embodiments, control unit <b>230</b> is configured to determine as much control information as possible on a per-instruction basis, rather than a per-instance basis. In one embodiment, this control information includes dependency information as discussed above. Accordingly, control unit <b>230</b> may perform a single determination of dependency information for an instruction executing in IESs <b>220</b>A-N, rather than N determinations for each instance of the instruction. Still further, control unit <b>230</b> may store a single copy of the control information, which it distributes to IESs <b>220</b> (as opposed to storing multiple copies). In some embodiments, this control information also includes predicate writer information as discussed above.

In some embodiments, various ones of the techniques implemented by USC <b>116</b> may improve performance and/or power savings for GPU <b>150</b>. Using shadow registers <b>240</b> proximal to outputs of IESs <b>220</b> may allow for faster disabling of pipeline stages—thus saving power. Still further, as will be discussed with respect to <figref idref="DRAWINGS">FIG. 3</figref>, in some embodiments, execution of an instruction sequence may be disabled in a manner that does not include performing a pipeline stall—thus increasing performance of GPU <b>150</b>. Determining control information on a per-instruction basis may also consume less computational resources and power than determining control information on a per-instance basis.

Turning now to <figref idref="DRAWINGS">FIG. 3</figref>, a block diagram of an IES <b>220</b> is depicted. In the illustrated embodiment, IES <b>220</b> includes shadow registers <b>240</b>, a datapath <b>310</b>, stage control units <b>320</b>, and a control buffer <b>330</b>. In other embodiments, IES <b>220</b> may be configured differently than shown—e.g., in one embodiment, stage control units <b>320</b> and control buffer <b>330</b> may be considered as part of control unit <b>230</b> discussed above.

Datapath <b>310</b>, in one embodiment, is configured to execute received instructions <b>312</b> within pipeline stages e0-eN. In one embodiment, datapath circuitry in stage e0 may receive opcodes, control signals, and data operands from register store <b>210</b> to be processed in subsequent stages. In one embodiment, stage e1 may include circuitry that reads local operand caches and routes information received in stage e0 to appropriate ALUs. In stages e2-eN-1, in one embodiment, ALUs may operate on data for one or more clock cycles to compute instruction results. Finally, in stage eN, instruction results may be written back (i.e., committed) to one or more registers (and forwarded on to register store <b>210</b>, in some embodiments).

In various embodiments, upon completing execution of predicate writers, determined predicate values <b>314</b> are written back to shadow registers <b>240</b>. In some embodiments, shadow registers <b>240</b> may be selected for storing predicate values based on control information <b>232</b> as noted above. As shown, shadow registers <b>240</b> are located near stage eN (i.e., the output of datapath <b>310</b> in the illustrated embodiment). (As noted above, this may allow for a quicker evaluation of predicate values in some embodiments.) In the illustrated embodiment, predicate values <b>314</b> written back to shadow registers <b>240</b> may be subsequently provided to stage control units <b>320</b> and predication registers <b>350</b>. In one embodiment, when data is provided from shadow registers <b>240</b> to predication registers <b>250</b>, the entirety of registers <b>240</b> is written to predication registers <b>250</b> (as opposed to individual bits corresponding to updated ones of predicate values <b>314</b>). In doing so, USC <b>116</b> may forgo implementing a mask to select individual bits for transmission—thus simplifying logic.

Stage control units <b>320</b>, in one embodiment, are configured to evaluate predicate values <b>314</b> and control information <b>232</b> in order to determine whether to disable execution of an instruction sequence at a respective pipeline stage in datapath <b>310</b>. In one embodiment, if a predicate value has already been determined for a dependent instruction at given pipeline stage, stage control unit <b>230</b> may evaluate the predicate value against the polarity (as specified by control information <b>232</b>, in some embodiments). Depending on this evaluation, stage control unit <b>320</b> may disable execution at its respective stage (e.g., stage e0 for stage control unit <b>320</b>A). In one embodiment, a stage control unit <b>320</b> performs disabling by clock gating the pipeline stage (or, at least, a portion of logic within that stage) so that logic is not being driven. In another embodiment, however, stage control unit <b>320</b> may power gate the pipeline stage. As the instruction advances to subsequent stages, stage control units <b>230</b> corresponding to those stages may perform the same evaluation and make a similar determination to enable or disable execution of the instruction. In one embodiment, if a predicate value has not yet been determined for a dependent instruction (i.e., the predicate writer is still being processed in datapath <b>310</b>), a stage control unit <b>320</b> may allow the instruction to continue executing, and evaluation may be postponed. As noted above, control information <b>232</b> may specify which instruction the given instruction is dependent on (e.g., that the given instruction is dependent on a predicate writer one instruction ahead, a predicate writer two instructions ahead, etc.), so that a stage control unit <b>320</b> is aware of when a predicate value will become available for evaluation. Thus, as the instruction advances through stages of datapath <b>310</b>, a subsequent stage control unit <b>320</b> can evaluate the predicate value upon being determined. At which point, the subsequent stage control unit <b>320</b> may determine to disable execution. In various embodiments, being able to evaluate an instruction at each pipeline allows execution of an instruction to be disabled while it is in datapath <b>310</b> (e.g., post issuance) and without stalling the pipeline. That is, an instruction does not need to be held at a particular stage until the corresponding predicate value is determined—thus also preventing it from holding up later instructions in datapath <b>310</b>.

Control buffer <b>330</b>, in one embodiment, is configured to store control information <b>232</b> received from control unit <b>230</b> and relay that information to the appropriate stage control units <b>320</b>. Accordingly, when an instruction <b>312</b> arrives at stage e0, control buffer <b>330</b> may provide the corresponding control information <b>232</b> for that instruction to stage control unit <b>320</b>A. As the instruction advances to later stages of datapath <b>310</b>, control buffer <b>330</b> may provide the control information <b>232</b> for that instruction to subsequent stage control units <b>320</b>. In some embodiments, control buffer <b>330</b> is implemented as a circular buffer. That is, control buffer <b>330</b> may maintain a pointer that, in one embodiment, identifies a next available entry where control information <b>232</b> may be stored for an instruction. As entries are filled, control buffer <b>330</b> may sequentially advance the pointer. Upon reaching a last entry in buffer <b>330</b>, the pointer may be wrapped around to an initial entry—thus giving the buffer its “circular” name. In one embodiment, control buffer <b>330</b> may determine where to route data from buffer entries based on the position of this pointer. In some embodiments, control buffer <b>330</b> may store fill-in values from predication registers <b>250</b> to update shadow registers <b>240</b>. As noted above, in one embodiment, control unit <b>230</b> may update predicate values in this manner in response to a thread restart. In some embodiments, upon doing so, control unit <b>230</b> may provide the predicate values as control information <b>232</b>. In such an embodiment, control buffer <b>330</b> may store received predicate values and provide them to datapath <b>310</b> (e.g., to stage eN) for storage in shadow registers <b>240</b>. Examples of information that may be included within control buffer <b>330</b> are described next with respect to <figref idref="DRAWINGS">FIGS. 4A and 4B</figref>.

Turning now to <figref idref="DRAWINGS">FIG. 4A</figref>, a block diagram of an instruction table <b>400</b> is depicted. Instruction table <b>400</b> is one embodiment of control information that may be generated on a per-instruction basis as discussed above. In some embodiments, data within table <b>400</b> may be determined by control unit <b>230</b> and stored within control buffer <b>330</b>. In the illustrated embodiment, entries <b>410</b> within table <b>400</b> specify an instruction dependency <b>412</b>, predicate dependency <b>414</b>, predicate polarity <b>416</b>, instruction writer flag <b>418</b>, and target register identifier <b>420</b>. In such an embodiment, information <b>412</b>-<b>416</b> may generally be referred to as dependency information, while information <b>418</b> and <b>420</b> may generally be referred to as predicate writer information.

Instruction dependencies <b>412</b>, in one embodiment, specify whether an instruction is dependent on another instruction and, if so, identify the particular instruction. For example, instruction dependency <b>412</b> may specify that the instruction at particular pipeline stage is dependent on a predicate writer that is two instructions ahead in datapath <b>310</b>. As noted above, instruction dependencies <b>412</b> may be used to determine whether a predicate value needs to be evaluated for a given instruction as well as when that predicate value will become available.

Predicate dependencies <b>414</b>, in one embodiment, specify which particular shadow register <b>240</b> includes a predicate value relevant to a given instruction. As noted above, shadow registers <b>240</b> may store multiple predicate values for a given instance, which may be one of several instances, which may correspond to one of several threads. Accordingly, a stage control unit <b>320</b> may use a predicate dependency <b>414</b> to identify the correct register <b>240</b> to read.

Predicate polarity <b>416</b>, in one embodiment, identifies a polarity for predicate value of a predicate reader. That is, in one embodiment, GPU <b>150</b> may support a first type of predicate that dictates taking a particular path (e.g., writing back the predicate reader results) responsive to a predict value being true and a second type of predicate reader that dictates taking the path responsive to the predicate value being false. Accordingly, predicate polarity <b>416</b> may identify whether a predicate reader is the first type or the second type.

Instruction writer flag <b>418</b>, in one embodiment, identifies whether a given instruction is a predicate writer. Accordingly, flag <b>418</b> may be used by datapath <b>310</b> in determining whether a write back is going to be performed to one of shadow registers <b>240</b> for the instruction.

Target register identifier <b>420</b>, in one embodiment, further specifies the shadow register <b>240</b> to which the predicate value of a predicate writer is to be written. Accordingly, datapath <b>310</b> may use target register identifier <b>420</b> to route a predicate value to the appropriate shadow register <b>240</b>.

Turning now to <figref idref="DRAWINGS">FIG. 4B</figref>, a block diagram of an instance table <b>450</b> is depicted. Instance table <b>450</b> is one embodiment of control information that may be generated on a per-instance basis. In some embodiments, data within table <b>450</b> may be determined by control unit <b>230</b> and stored within control buffer <b>330</b>. In the illustrated embodiment, entries <b>460</b> within table <b>450</b> include a respective validity indication <b>462</b> and a fill-in predicate value <b>464</b>.

Validity indications <b>462</b>, in one embodiment, indicate whether a given instance is to be disabled or is to be enabled pending any predicate values. As noted above, in some embodiments, the same instruction sequence may be issued to each of IESs <b>220</b> even if only one or two instances need to be executed for a particular task. Accordingly, in such an embodiment, control unit <b>230</b> may specify at issuance that a given instance does not need to be executed via a validity indication <b>462</b>—thus no evaluation of any predicate value may be warranted for that instance.

Fill-in predicate values <b>464</b>, in one embodiment, are predicate values from predication registers <b>250</b> that are to be written to shadow registers <b>240</b> in order to maintain coherency. Accordingly, fill-in predicate values <b>464</b> may be provided when a thread is being restarted as discussed above, for example.

Turning now to <figref idref="DRAWINGS">FIG. 5</figref>, a flow diagram of a method <b>500</b> is depicted. Method <b>500</b> is one embodiment of a method that may be performed by a graphics processing unit that implements predication such as GPU <b>150</b>. In some embodiments, performance of method <b>500</b> may improve power savings and/or performance of the graphics processing unit.

In step <b>510</b>, a set of shadow registers (e.g., shadow registers <b>240</b>) is maintained for a set of architecturally-defined registers (e.g., predication registers <b>250</b>) in a graphics processing unit. In such an embodiment, the set of architecturally-defined registers stores predicate values (e.g., predicate values <b>314</b>) for instruction sequences. In some embodiments, step <b>510</b> includes executing an instruction that computes a predicate for an instruction sequence and writing back a predicate value of the computed predicate to the set of shadow registers prior to storing the written-back predicate value in the architecturally-defined registers.

In step <b>520</b>, a determination whether to discontinue execution of an instruction sequence is made based on a predicate value in one of the set of shadow registers. In one embodiment, the determining is performed prior to storing the written-back predicate value in the set of architecturally-defined registers. In some embodiments, step <b>520</b> includes executing a plurality of instances of an instruction in separate execution pipelines (e.g., separate IESs <b>220</b>), performing a single determination of control information (e.g., control information <b>232</b>) for the instruction, and distributing the control information to each of the execution pipelines. In various embodiments, in response to determining to discontinue execution of the instruction sequence, execution of the instruction sequence is discontinued without performing a stall in the execution pipeline executing the instruction sequence. In some embodiments, step <b>520</b> further includes control logic (e.g., stage control units <b>320</b>) clock gating one or more stages (e.g., stages e0-eN) of the execution pipeline.

Turning next to <figref idref="DRAWINGS">FIG. 6</figref>, a block diagram illustrating an exemplary embodiment of a computing system <b>600</b> is shown. Computing system <b>600</b> is one embodiment of a computing system that may include graphics processing unit <b>150</b> discussed above. In some embodiments, elements of computing system <b>600</b> may be included within a system on a chip (SoC). In some embodiments, computing system <b>600</b> may be included in a mobile device, which may be battery-powered. Therefore, power consumption by computing system <b>600</b> may be an important design consideration. In the illustrated embodiment, computing system <b>600</b> includes fabric <b>610</b>, central processing unit (CPU) <b>620</b>, input/output (I/O) bridge <b>650</b>, cache/memory controller <b>645</b>, graphics processing unit <b>150</b>, and display unit <b>665</b>.

Fabric <b>610</b> may include various interconnects, buses, MUX's, controllers, etc., and may be configured to facilitate communication between various elements of computing system <b>600</b>. In some embodiments, portions of fabric <b>610</b> may be configured to implement various different communication protocols. In other embodiments, fabric <b>610</b> may implement a single communication protocol and elements coupled to fabric <b>610</b> may convert from the single communication protocol to other communication protocols internally.

In the illustrated embodiment, CPU <b>620</b> includes bus interface unit (BIU) <b>625</b>, cache <b>630</b>, and cores <b>635</b> and <b>640</b>. In various embodiments, CPU <b>620</b> may include various numbers of cores and/or caches. For example, CPU <b>620</b> may include 1, 2, or 4 processor cores, or any other suitable number. In one embodiment, cache <b>630</b> is a set associative L2 cache. In some embodiments, cores <b>635</b> and/or <b>640</b> may include internal instruction and/or data caches. In some embodiments, a coherency unit (not shown) in fabric <b>610</b>, cache <b>630</b>, or elsewhere in computing system <b>600</b> may be configured to maintain coherency between various caches of computing system <b>600</b>. BIU <b>625</b> may be configured to manage communication between CPU <b>620</b> and other elements of computing system <b>600</b>. Processor cores such as cores <b>635</b> and <b>640</b> may be configured to execute instructions of a particular instruction set architecture (ISA), which may include operating system instructions and user application instructions.

Cache/memory controller <b>645</b> may be configured to manage transfer of data between fabric <b>610</b> and one or more caches and/or memories. For example, cache/memory controller <b>645</b> may be coupled to an L3 cache, which may in turn be coupled to a system memory. In other embodiments, cache/memory controller <b>645</b> may be directly coupled to a memory. In some embodiments, cache/memory controller <b>645</b> may include one or more internal caches.

As used herein, the term “coupled to” may indicate one or more connections between elements, and a coupling may include intervening elements. For example, in <figref idref="DRAWINGS">FIG. 6</figref>, graphics processing unit <b>150</b> may be described as “coupled to” a memory through fabric <b>610</b> and cache/memory controller <b>645</b>. In contrast, in the illustrated embodiment of <figref idref="DRAWINGS">FIG. 6</figref>, graphics processing unit <b>150</b> is “directly coupled” to fabric <b>610</b> because there are no intervening elements.

GPU <b>150</b> may receive graphics-oriented instructions, such as OPENGL® or DIRECT3D® instructions, for example. GPU <b>150</b> may execute specialized GPU instructions or perform other operations based on the received graphics-oriented instructions. GPU <b>150</b> may generally be configured to process large blocks of data in parallel and may build images in a frame buffer for output to a display. GPU <b>150</b> may include transform, lighting, triangle, and/or rendering engines in one or more graphics processing pipelines. GPU <b>150</b> may output pixel information for display images. In the illustrated embodiment, GPU <b>150</b> includes USC <b>160</b>; in some embodiments, GPU <b>150</b> may have multiple processing cores each including a respective USC <b>160</b>.

Display unit <b>665</b> may be configured to read data from a frame buffer and provide a stream of pixel values for display. Display unit <b>665</b> may be configured as a display pipeline in some embodiments. Additionally, display unit <b>665</b> may be configured to blend multiple frames to produce an output frame. Further, display unit <b>665</b> may include one or more interfaces (e.g., MIPI® or embedded display port (eDP)) for coupling to a user display (e.g., a touchscreen or an external display).

I/O bridge <b>650</b> may include various elements configured to implement: universal serial bus (USB) communications, security, audio, and/or low-power always-on functionality, for example. I/O bridge <b>650</b> may also include interfaces such as pulse-width modulation (PWM), general-purpose input/output (GPIO), serial peripheral interface (SPI), and/or inter-integrated circuit (I2C), for example. Various types of peripherals and devices may be coupled to computing system <b>600</b> via I/O bridge <b>650</b>.

Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even where only a single embodiment is described with respect to a particular feature. Examples of features provided in the disclosure are intended to be illustrative rather than restrictive unless stated otherwise. The above description is intended to cover such alternatives, modifications, and equivalents as would be apparent to a person skilled in the art having the benefit of this disclosure.

The scope of the present disclosure includes any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations enumerated in the appended claims.