Test system simultaneously testing semiconductor devices

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2014-00133453 filed on Oct. 2, 2014, the subject matter of which is hereby incorporated by reference.

BACKGROUND

Embodiments of the inventive concept relate generally to the testing of semiconductor devices. More particularly, the inventive concept relates to the simultaneous, yet individually tailored, testing of a plurality of memory chips using stress tests respectively associated with corresponding failure attributes.

Many different failure attributes may afflict contemporary memory chips. Yet, memory chips must be tested in an efficient manner that does not overly stress the subject memory chips. As the type and number of failure attributes increases it becomes harder and harder to efficiently test memory chips without overly stressing them.

SUMMARY

Embodiments of the inventive concept provide test systems capable of efficiently and simultaneously testing a plurality of semiconductor devices, such as memory chips without unduly stressing the semiconductor devices. Other embodiments of the inventive concept provide methods of testing semiconductor devices.

According to one embodiment of the inventive concept, a test system includes; a plurality of memory chips including a first memory chip and a second memory chip, and a tester that simultaneously tests the plurality of memory chips, wherein the first memory chip comprises a first memory cell array including memory cells susceptible to a first failure attribute, and first built-in self-test (BIST)/built-in self-stress (BISS) circuitry, the second memory chip comprises a second memory cell array including memory cells susceptible to a second failure attribute, and second BIST/BISS circuitry, the first BIST/BISS circuitry is configured to selectively apply a first stress test associated with the first failure attribute and a second stress test associated with the second failure attribute to the first memory cell array, and the second BIST/BISS circuitry is configured to selectively apply the first stress test and the second stress test to the second memory cell array, and during the simultaneous testing of the plurality of memory cells, the first BIST/BISS applies the first stress test to the first memory cell array and omits the second stress test, while the second BIST/BISS applies omits the first stress test and applies the second stress test to the second memory cell array.

According to another embodiment of the inventive concept, a method of simultaneously testing a plurality of memory chips including a first memory chip and a second memory chip using a tester is provided. The method includes; configuring a first stress module disposed on the first memory chip and including a first stress module that includes first built-in self-test (BIST)/built-in self-stress (BISS) circuitry to selectively apply a first stress test associated with a first failure attribute to a first memory cell array disposed on the first memory chip, and configuring a second stress module disposed on the first memory chip and including second BIST/BISS circuitry to selectively apply a second stress test associated with a second failure attribute to the first memory cell array, and configuring a first stress module disposed on the second memory chip and including a first stress module that includes the first BIST/BISS circuitry to selectively apply the first stress test to a second memory cell array disposed on the second memory chip, and configuring a second stress module disposed on the second memory chip and including the second BIST/BISS circuitry to selectively apply the second stress test to the second memory cell array.

According to another embodiment of the inventive concept, a method of simultaneously testing a plurality of memory chips including a first memory chip and a second memory chip using a tester includes; performing a wafer-level test on the plurality of memory chips during which repair information associated with the first memory chip and second memory chip is acquired, and generating first failure attribute information from repair information associated with the first memory chip, and second failure attribute information from repair information associated with the second memory chip.

The foregoing method may also include running an adaptive burn-in operation during which first built-in self-test (BIST)/built-in self-stress (BISS) circuitry disposed on the first memory chip applies a first stress test associated with the first failure attribute to a first memory cell array of the first memory chip and second BIST/BISS circuitry disposed on the first memory chip omits application of a second stress test associated with the second failure attribute with respect to the first memory cell array, while simultaneously, first BIST/BISS circuitry disposed on the second memory chip omits application of the first stress test with respect to a second memory cell array of the second memory chip and second BIST/BISS circuitry disposed on the second memory chip applies the second stress test to the second memory cell array.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other features and advantages of the inventive concepts will be apparent from the more particular description of preferred embodiments of the inventive concepts, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the inventive concepts. In the drawings:

<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram illustrating a test system according to an embodiment of the inventive concept;

<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram further illustrating in one example the memory of <figref idref="DRAWINGS">FIG. 1</figref>;

<figref idref="DRAWINGS">FIG. 3</figref> is a block diagram illustrating a test system according to another embodiment of the inventive concept;

<figref idref="DRAWINGS">FIG. 4</figref> shows a general package burn-in (BI) operation;

<figref idref="DRAWINGS">FIG. 5</figref> shows types of exemplary failure attributes with respect to memory chips shown in <figref idref="DRAWINGS">FIG. 1</figref>;

<figref idref="DRAWINGS">FIG. 6</figref> shows failure attributes with respect to the memory chips shown in <figref idref="DRAWINGS">FIG. 1</figref> and test time according to the failure attributes;

<figref idref="DRAWINGS">FIG. 7</figref> is a block diagram of a memory system <b>200</b> including memory chips <b>21</b> shown in <figref idref="DRAWINGS">FIG. 1</figref>;

<figref idref="DRAWINGS">FIGS. 8 through 10</figref> are diagrams of memory modules <b>210</b>, <b>220</b>, and <b>230</b> including memory chips <b>21</b> shown in <figref idref="DRAWINGS">FIG. 1</figref>;

<figref idref="DRAWINGS">FIG. 11</figref> is a conceptual diagram illustrating a semiconductor device <b>300</b> which has a stacked structure and includes a plurality of semiconductor layers according to an embodiment of the inventive concept;

<figref idref="DRAWINGS">FIG. 12</figref> is a block diagram of a computer system <b>410</b> including the memory chip <b>21</b> shown in <figref idref="DRAWINGS">FIG. 1</figref>, according to an embodiment of the inventive concept;

<figref idref="DRAWINGS">FIG. 13</figref> is a block diagram of a computer system <b>420</b> including the memory chip <b>21</b> shown in <figref idref="DRAWINGS">FIG. 1</figref>, according to another embodiment of the inventive concept; and

<figref idref="DRAWINGS">FIG. 14</figref> is a block diagram of a computer system <b>430</b> including the memory chip <b>21</b> shown in <figref idref="DRAWINGS">FIG. 1</figref>, according to still another embodiment of the inventive concept;

DETAILED DESCRIPTION

Specific structural and functional details disclosed herein are merely representative for purposes of describing embodiments of the inventive concept. Embodiments of the inventive concept may be implemented in many different forms and the scope of the inventive concept should not be construed as being limited to only the illustrated embodiments presented herein.

It will be understood that, although the terms “first,” “second,” etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another component. Thus, a first component discussed below could be termed a second component and the second component discussed below could be termed the first component without departing from the teachings of the present inventive concept.

It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements. Other words used to describe relationships between elements should be interpreted in a like fashion (i.e., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).

The terminology used herein to describe embodiments of the inventive concept is not intended to limit the scope of the inventive concept. The articles “a,” “an,” and “the” are singular in that they have a single referent, however the use of the singular form in the present document should not preclude the presence of more than one referent. In other words, elements of the inventive concept referred to in singular may number one or more, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used herein, specify the presence of stated features, items, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, items, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as is customary in the art to which this inventive concept belongs. It will be further understood that terms in common usage should also be interpreted as is customary in the relevant art and not in an idealized or overly formal sense unless expressly so defined herein.

Where it is possible to implement any embodiment in any other way, a function or an operation specified in a specific block may be performed differently from a flow specified in a flowchart. For example, consecutive two blocks may actually perform the function or the operation simultaneously, and the two blocks may perform the function or the operation conversely according to a related operation or function.

<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram illustrating a test system <b>100</b> for semiconductor devices according to an embodiment of the inventive concept.

Referring to <figref idref="DRAWINGS">FIG. 1</figref>, the test system <b>100</b> comprises a tester <b>10</b> and a plurality of semiconductor devices (e.g., memory chips <b>20</b>) undergoing testing. <figref idref="DRAWINGS">FIG. 1</figref> shows only ten (10) memory chips being tested by the tester <b>10</b>, but those skilled in the art will recognize that this number is merely an arbitrarily chosen example.

The tester <b>10</b> may include certain automatic test equipment (ATE) capable of variously testing (e.g., selectively stressing) any one of the first through tenth memory chips <b>21</b> to <b>30</b>. For example, the tester <b>10</b> may simultaneously test the first through tenth memory chips <b>21</b> to <b>30</b> during an applied wafer-level test operation or package-level test operation by applying a test data pattern to a respective input port of the first through tenth memory chips <b>21</b> to <b>30</b> and comparing a corresponding output for each of the first through tenth memory chips <b>21</b> to <b>30</b> with an expected value.

Embodiments of the inventive concept, like the one illustrated in <figref idref="DRAWINGS">FIG. 1</figref>, may be applied to many different types of semiconductor devices. For example, the first through tenth memory chips <b>21</b> to <b>30</b> may be dynamic random access memory (DRAM) or similar non-volatile memory devices. In certain embodiments of the inventive concept, the semiconductor devices undergoing testing (e.g., each one of the first through tenth memory chips <b>21</b> to <b>30</b>) may include a Built-In Self Stress (BISS) and/or Built-In SelfTest (BIST) circuitry. Such on-chip BISS/BIST circuitry may be used with good advantage by the tester <b>10</b> to individually, collectively or in-part test the first through tenth memory chips <b>21</b> to <b>30</b>.

For example, the tester <b>10</b> may simultaneously test the respective memory chips <b>21</b> to <b>30</b> in the plurality of memory chips <b>20</b> in respectively different ways using the constituent BISS/BIST circuitry of the memory chips <b>21</b> to <b>30</b>. That is, the tester <b>10</b> may apply different types or levels of stress to respective memory chips <b>21</b> to <b>30</b> using the BISS/BIST circuitry during (e.g.,) a burn-in operation for the memory chips <b>21</b> to <b>30</b>. In this context, the terms “simultaneous” or “simultaneously” mean that the time periods during which testing procedure(s) are applied to two or more semiconductor devices overlap at least in part.

During one or more wafer-level test operation(s), the tester <b>10</b> may identify and collect data associated with one or more failure attribute(s) with respect to each of the first through tenth memory chips <b>21</b> to <b>30</b>. In this manner, failure attribute information may be acquired for each one of the memory chips <b>21</b> to <b>30</b>. Such failure attribute information may be acquired by static or dynamic testing of the memory chips <b>21</b> to <b>30</b>, and/or repair (or mitigation) of identified defects in the memory chips <b>21</b> to <b>30</b>. In this manner, the tester <b>10</b> may acquire “failure attribute information” associated with a number of different failure attributes (e.g., first, second, third, etc., failure attributes), where each one of the memory chip <b>21</b> to <b>30</b> may exhibit none, one, or more than one of these failure attributes.

<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram further illustrating in one example the test system <b>100</b> of <figref idref="DRAWINGS">FIG. 1</figref>. Here, only a single memory chip (e.g., memory chip <b>21</b>) is shown in operative connection to the tester <b>10</b>. The other memory chips (e.g., memory chips <b>22</b> to <b>30</b>) may be similarly tested following the example described with respect to memory chip <b>20</b>.

In <figref idref="DRAWINGS">FIG. 2</figref>, it is assume that the first memory chip <b>21</b> includes first, second and third stress modules (SM<b>1</b>, SM<b>2</b> and SM<b>3</b>), as well as a memory cell array CA. Those skilled in the art will understand that various driving circuitry associated with the memory cell array CA of will also be present in the first memory chip <b>21</b>, but is not specifically illustrated in <figref idref="DRAWINGS">FIG. 2</figref> for purposes of clarity.

The first stress module SM<b>1</b> includes a first storage unit SU<b>1</b>, a first logic control circuit LCC<b>1</b>, a first timer TM<b>1</b>, and a first BISS/BIST circuitry BBL<b>1</b>. The second stress module SM<b>2</b> includes a second storage unit SU<b>2</b>, a second logic control circuit LCC<b>2</b>, a second timer TM<b>2</b>, and a second BISS/BIST circuitry BBL<b>2</b>, and the third stress module SM<b>3</b> includes a third storage unit SU<b>3</b>, a third logic control circuit LCC<b>3</b>, a third timer TM<b>3</b>, and a third BISS/BIST circuitry BBL<b>3</b>.

The first storage unit SU<b>1</b> may be used to store failure attribute information related to a first failure attribute as well as information related to the operation of the first timer TM<b>1</b>. This is similarly so for second and third failure attributes and the second and third storage units SU<b>2</b> and SU<b>3</b>. In certain embodiments of the inventive concept, each one of the first, second and third storage units SU<b>1</b>, SU<b>2</b> and SU<b>3</b> may include circuitry providing laser fuse, e-fuse, and/or anti-fuse elements sufficient to store at least a portion of the failure attribute information. The example of <figref idref="DRAWINGS">FIG. 2</figref> shows only three (3) stress modules (SU) respectively associated with three (3) failure attributes that may be exhibited by the first memory chip <b>21</b>, but the scope of the inventive concept is not limited to this arbitrarily chosen and exemplary number.

Each one of the first, second and third storage units SU<b>1</b>, SU<b>2</b> and SU<b>3</b> respectively disposed in one of the first, second and third stress modules SM<b>1</b>, SM<b>2</b> and SM<b>3</b> corresponds in its use to an associated failure attribute (e.g., a first failure attribute, a second failure attribute, and a third failure attribute).

Using this configuration and during a wafer-level test operation, the tester <b>10</b> will perform one or more test and/or repair operations with respect to the first memory chip <b>21</b>. In this manner, the tester <b>10</b> may acquire repair information associated with the first memory chip <b>21</b>. Thereafter, the tester <b>10</b> may be used to derive (or extract) failure attribute information from the repair information associated with the first memory chip <b>21</b>. For example, given its type, configuration, or series, the first memory chip <b>21</b> may have one or more known failure-mode vulnerabilities (e.g., the first failure attribute, second failure attribute and third failure attribute). Accordingly, the tester <b>10</b> may be used to appropriately stress relevant circuitry of the first memory chip <b>21</b> corresponding to the first failure attribute, second failure attribute, and third failure attribute during (e.g.,) burn-in testing.

With respect to the example shown in <figref idref="DRAWINGS">FIG. 2</figref>, a method of testing the first memory chip <b>21</b> may proceed as follows. The tester <b>10</b> may apply a test mode register set (TMRS) signal (e.g., a type of stress permission start signal) to the first storage unit SU<b>1</b> of the first memory chip <b>21</b>. In response to the TMRS signal, the first storage unit SU<b>1</b> may communicate first failure attribute information including first timing control information associated with the first failure attribute to the first logic control circuit LCC<b>1</b>. The first logic control circuit LCC<b>1</b> may then set the first timer TM<b>1</b> using the first timing control information, and otherwise control the operation of the first BISS/BIST circuitry (BBL<b>1</b>).

Thus, under the control of the first logic control circuit LCC<b>1</b>, the first BISS/BIST circuitry BBL<b>1</b> may be used to apply appropriately defined stress signal(s) (e.g., voltages and/or currents) to the memory cell array CA during a first time period controlled by the first timer TM<b>1</b>. When first failure attribute operation(s) are completed by the first stress module SM<b>1</b>, the first BISS/BIST circuitry BBL<b>1</b> will communicate a first stress operation start signal SOS<b>1</b> to the second storage unit SU<b>2</b>.

Here, if the first memory chip <b>21</b> does not need to be tested for the first failure attribute, the first logic control circuit LCC<b>1</b> may simply set the first timing control information for the first timer TM<b>1</b> to “0”.

In similar manner, and in response to corresponding second and third stress operation start signals (SOS<b>1</b> and SOS<b>2</b>), the second stress module SM<b>2</b> and the third stress module SM<b>3</b> may be used to provide second failure attribute information and third failure attribute information, respectively. Thus, the tester <b>10</b> may selectively and effectively apply different stress tests associated with different failure attributes to a plurality of memory chips being simultaneously tested. One approach to applying different stress tests associated with different failure attributes to a plurality of memory chips being simultaneously tested will be described in some additional detail with respect to <figref idref="DRAWINGS">FIGS. 5 and 6</figref>.

<figref idref="DRAWINGS">FIG. 3</figref> is a block diagram illustrating a test system according to another embodiment of the inventive concept.

Referring to <figref idref="DRAWINGS">FIGS. 1, 2 and 3</figref>, the tester <b>10</b> is now expressly used to simultaneously test the first memory chip <b>21</b> and the second memory chip <b>22</b>. Here again, the first memory chip <b>21</b> includes first, second and third stress modules SM<b>11</b>, SM<b>12</b> and SM<b>13</b>, as well as a first cell array CA<b>1</b>. The first stress module SM<b>11</b>, as an example, includes a first storage unit SU<b>11</b>, a first logic control circuit LCC<b>11</b>, a first timer TM<b>11</b>, and a first BISS/BIST circuitry BBL<b>11</b>. The second stress module SM<b>12</b> and third stress module SM<b>13</b> are similarly configured.

As before, the first storage unit SU<b>11</b> (and by analogous extension, the second storage unit SU<b>12</b> and third storage unit SU<b>13</b>) may be used to store first (second and third) attribute failure information associated with a first (second and third) failure attribute and including timing control information for the first (second and third) timer TM<b>11</b>. In this manner, each of the first, second and third storage units SU<b>11</b> to SU<b>13</b> correspond to a failure attribute that may be exhibited by the first memory chip <b>21</b>.

This exemplary configuration for the first memory chip <b>21</b> is mirrored in <figref idref="DRAWINGS">FIG. 3</figref> with respect to the second memory chip <b>22</b>, and corresponding components are analogously labeled. Accordingly, the first, second and third storage units SU<b>21</b> to SU<b>23</b> of the second memory chip <b>22</b> corresponds to respective failure attributes (e.g., the first stress module SM<b>21</b> corresponds to the first failure attribute, the second stress module SM<b>22</b> corresponds to the second failure attribute, and the third stress module SM<b>23</b> corresponds to the third failure attribute).

As has been previously noted, during a wafer-level test operation, the tester <b>10</b> may simultaneously test the first memory chip <b>21</b> and the second memory chip <b>22</b>, and acquire repair information respectively associated with the first memory chip <b>21</b> and second memory chip <b>22</b>. And from this repair information, the tester <b>10</b> may be used to extract failure attribute information associated with the first memory chip <b>21</b> and the second memory chip <b>22</b>, respectively. For example, using this approach it may be determined that the first memory chip <b>21</b> is vulnerable to a first failure attribute and a third failure attribute, while the second memory chip <b>22</b> is vulnerable to the first failure attribute and a second failure attribute. Accordingly, the tester <b>10</b> may then be used to apply appropriately defined stress signals corresponding to the first failure attribute and third failure attribute to the first memory chip <b>21</b> during burn-in testing, and simultaneously, apply appropriately defined stress signals corresponding to the first failure attribute and second failure attribute to the second memory chip <b>22</b> during burn-in testing.

The foregoing approach may accomplish appropriate stress testing of both memory chips. Thus, assuming that a first, a second and a third stress test respectively associated with the first, second and third failure attributes each require about 20 minutes to perform, the following outcome occurs for the example described above. In the first memory chip <b>21</b>, the first stress module <b>11</b> performs the first stress test with respect to the first memory cell array CA<b>1</b> for 20 minutes, the second stress module <b>12</b> omits a second stress test with respect to the first cell array CA<b>1</b> (i.e., a second stress time is set to 0), and the third stress module <b>13</b> performs the third stress test with respect to the first cell array CA<b>1</b> for an additional 20 minutes.

While the tester <b>10</b> controls execution of the first, second and third stress tests with respect to the first memory chip <b>21</b>, it also controls execution of the first, second and third stress test with respect to the second memory chip <b>22</b>. Thus, under the same assumptions noted above and in relation to the second memory chip <b>22</b>, the first stress module SM<b>21</b> performs the first stress test with respect to the second cell array CA<b>2</b> for 20 minutes, the second stress module SM<b>22</b> performs the second stress test with respect to the second cell array CA<b>2</b> for an additional 20 minutes, and the third stress module SM<b>23</b> omits the third stress test with respect to the second cell array CA<b>2</b> (i.e. a third stress time is set to 0).

In the foregoing approach, the tester <b>10</b> may simultaneously apply the TMRS signal to the first memory chip <b>21</b> and second memory chip <b>22</b>. That is, the first storage unit SU<b>11</b> of the first memory chip <b>21</b> and the first storage unit SU<b>21</b> in the second memory chip <b>22</b> receives the TMRS signal at the same time. Thereafter, the tester <b>10</b> controls the selective application of first, second and/or third stress tests associated with the first, second and/or third failure attributes to each of the first and second memory chips <b>21</b> and <b>22</b>. In this regard, the operation of the respective stress modules SMxx, constituent storage units (SUxx), logic control circuits LCCxx, timers TMxx, and BISS/BIST circuitry BBLxx may be the same as previously described, albeit with respect to both the first memory chip <b>21</b> and second memory chip <b>22</b>. Once a final stress module in a series of stress modules for each memory chip has caused a corresponding stress signal to be applied to a memory cell array, and end signal (e.g., END<b>1</b> and END<b>2</b>) are returned to the tester <b>10</b>.

<figref idref="DRAWINGS">FIG. 4</figref> is a conceptual diagram illustrating a burn-in (BI) operation for semiconductor devices.

Referring to <figref idref="DRAWINGS">FIGS. 1 and 4</figref>, during a period of increasing temperature during a static BI operation, the tester <b>10</b> applies only requisite power supply voltage(s) to the plurality of memory chips <b>20</b>. In this context, the tester <b>10</b> may be said to “run” (i.e., cause, control and/or monitor the execution of) various burn-in operations. Once a high temperature limit of the static BI operation is reached, the tester <b>10</b> may then apply one or more stress signals to the plurality of memory chips <b>20</b> during a main BI operation.

In the context of the inventive concept, the duration of the main BI operation may be reduced from 6 hours to 3 hours, and an adaptive BI operation may be added to essentially pre-detect various failure attributes that are potentially unresolved by the main BI operation. Here, the adaptive BI operation may include the selective application of particular stress signals corresponding to known (or suspected) failure attributes (e.g., the first, second, third, fourth, fifth, and sixth failure attributes suggested in <figref idref="DRAWINGS">FIG. 4</figref>) previously associated with the individual memory chips constituting the plurality of memory chips <b>20</b>. However, the universal inclusion of testing associated with every failure attribute for every memory chip in the plurality of memory chips being tested may result in an unreasonably long test period and may overly stress memory chips.

In contrast to this potential outcome, <figref idref="DRAWINGS">FIG. 5</figref> conceptually illustrates a set of relationships between failure attributes and respective memory chips in the plurality of memory chips being tested by a test system like the one described above in relation to <figref idref="DRAWINGS">FIG. 1</figref>. Referring to <figref idref="DRAWINGS">FIGS. 1 and 5</figref>, incidences of first through sixth failure attributes for first through fourth memory chips <b>21</b> to <b>24</b> is illustrated. Here, it is assumed that each of the first through fourth memory chips <b>21</b> to <b>24</b> includes first through sixth stress modules (SM) respectively corresponding to the first through sixth failure attributes. It is further assumed that based on relevant failure attribute information, the first memory chip <b>21</b> is susceptible to the first, second and third failure attributes; the second memory chip <b>22</b> is susceptible to the fourth, fifth and sixth failure attributes; the third memory chip <b>23</b> is susceptible to the first and sixth failure attributes, and the fourth memory chip <b>24</b> is susceptible to the second and fourth failure attributes.

Here again, assuming for the sake of simplicity that each one of first, second, third, fourth, fifth and sixth stress tests respectively associated with the first, second, third, fourth, fifth and sixth failure attributes takes a minimum of 20 minutes, sequentially applying all of the first through sixth stress tests to each of the first to fourth memory chips would 120 minutes. However, embodiments of the inventive concept are capable of characterizing multiple failure attributes, and more specifically ascribing selected failure attributes to each memory chip being tested. Therefore, unnecessary testing and the resultant stress may omitted from more memory chip-specific testing regimes, as further described with respect to <figref idref="DRAWINGS">FIG. 6</figref>.

<figref idref="DRAWINGS">FIG. 6</figref> conceptually illustrates a set of relationships between selected failure attributes and respective memory chips in the plurality of memory chips being tested by a test system like the one described above in relation to <figref idref="DRAWINGS">FIG. 1</figref>. Referring to <figref idref="DRAWINGS">FIGS. 1, 5 and 6</figref>, markedly reduced total test times (e.g., periods between a start time (TS) and end times (TO)) for the first through fourth memory chips may be achieved.

Instead of applying each one of the first through sixth stress tests using corresponding stress modules, the first memory chip, for example, need only apply the first, second and third stress tests associated with the first, second and third failure attributes. Similarly, the second memory chip need only apply the fourth, fifth and sixth stress tests; the third memory chip need only apply the first and sixth stress test, and the fourth memory chip need only apply the second and fourth stress tests.

Accordingly, instead of the fixed 120 minute testing time for the first through fourth memory chips, a worst case total testing time (i.e., the testing period associated with the testing of the first and second memory chips) may be reduced to 60 minutes, per the example illustrated in <figref idref="DRAWINGS">FIG. 6</figref>. Further, respective time periods for stress testing of the third and fourth memory cells may be expanded as necessary within the total testing time required for the plurality of memory chips being tested. This may also reduce unnecessary or unwanted stress of the memory chips.

<figref idref="DRAWINGS">FIG. 7</figref> is a block diagram illustrating a memory system <b>200</b> comprising a memory module <b>201</b> including a plurality of memory chips and a memory controller <b>202</b>.

The illustrated memory module <b>201</b> is assumed to mechanically mount and electrically connect four (4) memory chips MC, but many other memory module configurations might be used in other embodiments of the inventive concept. For example, memory chips may be mounted on both sides of a primary substrate within a memory module.

The memory controller <b>202</b> may be used to generate command/address signal(s) (C/A) as well as a data signal (DQ). The memory module <b>201</b> and its constituent memory chips operated in response to the command/address signal C/A and/or data signal DQ. In certain embodiments of the inventive concept, the command/address signal C/A will be communicated as packet data combining command data and address data in a defined packet type.

The command/address bus <b>203</b> may have a fly-by structure and electrically connect the four memory chips MC. The data signal DQ may be communicated via the data bus <b>204</b> between the memory controller <b>202</b> and memory module <b>201</b>. Further, each one of the memory chips MC shown in the example of <figref idref="DRAWINGS">FIG. 7</figref> may be similarly configured and operated as the first memory chip <b>21</b> described above with reference to <figref idref="DRAWINGS">FIGS. 1 and 2</figref>.

<figref idref="DRAWINGS">FIGS. 8, 9 and 10</figref> are perspective diagrams respectively illustrating memory modules <b>210</b>, <b>220</b>, and <b>230</b> that may be configured to mount memory chips MC similarly configured and operated as the first memory chip <b>21</b> described above with reference to <figref idref="DRAWINGS">FIGS. 1 and 2</figref>.

Referring to <figref idref="DRAWINGS">FIG. 8</figref>, the memory module <b>210</b> includes memory chips MC mounted on a printed circuit board (PCB) <b>211</b> having a connector <b>212</b>. The memory chips MC may be bonded to top and bottom surfaces of the PCB <b>211</b>, and the connector <b>212</b> may be used to electrically connect the memory chips MC via a multiplicity of conductive lines (not shown). In various configurations, the connector <b>212</b> may be connected to a slot of a host (not shown).

Referring to <figref idref="DRAWINGS">FIG. 9</figref>, the memory module <b>220</b> includes a PCB <b>221</b>, memory chips MC, a connector <b>222</b>, and buffers <b>223</b>. Each of the buffers <b>223</b> is disposed between a memory chip MC and connector <b>222</b>. Each of the buffers <b>233</b> connected to each of the memory chips MC may be provided on top and bottom surfaces of the PCB <b>221</b>. The memory chips MC and buffers <b>223</b> formed on the top and bottom surfaces of the PCB <b>221</b> may be connected via a plurality of via holes.

Referring to <figref idref="DRAWINGS">FIG. 10</figref>, the memory module <b>230</b> includes a memory chips MC, a PCB <b>231</b>, a connector <b>232</b>, buffers <b>233</b>, and a controller <b>234</b>.

Each of the buffers <b>233</b> is connected to a memory chip MC on top and bottom surfaces of the PCB <b>231</b>. The memory chips MC and buffers <b>233</b> formed on the top and bottom surfaces of the PCB <b>231</b> may be connected via a plurality of via holes. The controller <b>234</b> communicates a control signal to each of the memory chips MC and communicates data with each of the memory chips MC.

<figref idref="DRAWINGS">FIG. 11</figref> is a perspective diagram illustrating a semiconductor device <b>300</b> having a stacked structure and including a plurality of semiconductor layers.

In the memory modules <b>210</b>, <b>220</b>, and <b>230</b> shown in <figref idref="DRAWINGS">FIGS. 8, 9 and 10</figref>, each of the memory chips MC may include a plurality of semiconductor layers LA<b>1</b> to LAn.

Referring to <figref idref="DRAWINGS">FIG. 11</figref>, in the semiconductor device <b>300</b>, the plurality of stacked semiconductor layers LA<b>1</b> to LAn may be connected to each other through through-silicon vias (TSVs) <b>301</b>.

<figref idref="DRAWINGS">FIG. 12</figref> is a block diagram illustrating a computer system <b>410</b> comprising one or more memory chips like the first memory chip <b>21</b> shown in <figref idref="DRAWINGS">FIGS. 1 and 2</figref> according to an embodiment of the inventive concept.

Referring to <figref idref="DRAWINGS">FIG. 12</figref>, the computer system <b>410</b> comprises a memory chip <b>411</b>, an application processor (AP) <b>412</b>, a radio transceiver <b>413</b>, an antenna <b>414</b>, an input device <b>415</b>, and a display device <b>416</b>, where the AP <b>412</b> includes a memory controller for controlling the memory chip <b>411</b>.

The radio transceiver <b>413</b> may be used to communicate a wireless signal via the antenna <b>414</b>. For example, the radio transceiver <b>413</b> may modulate a wireless signal to a signal to be processed in the AP <b>412</b>.

Accordingly, the AP <b>412</b> may process a signal output from the radio transceiver <b>413</b> and transmit the processed signal to display device <b>416</b>. Moreover, the radio transceiver <b>413</b> may modulate the signal output from the AP <b>412</b> to a wireless signal and output the modulated wireless signal through the antenna <b>414</b> to an external device.

The input device <b>415</b> is a device capable of inputting a control signal for controlling an operation of the AP <b>412</b> or a data processed by the AP <b>412</b> and may be implemented as a pointing device such as a touch pad and computer mouse, a keypad, or a keyboard.

<figref idref="DRAWINGS">FIG. 13</figref> is a block diagram illustrating a computer system <b>420</b> that may include one or more memory chips like the first memory chip <b>21</b> described in relation to <figref idref="DRAWINGS">FIGS. 1 and 2</figref> according to another embodiment of the inventive concept.

Referring to <figref idref="DRAWINGS">FIG. 13</figref>, the computer system <b>420</b> may be implemented as a personal computer (PC), a network server, a tablet PC, a net-book, e-reader, personal digital assistant (PDA), a portable multimedia player (PMP), a MP3 player, a MP4 player.

The computer system <b>420</b> may include a memory chip <b>421</b>, an AP <b>422</b>, an input device <b>423</b>, and a display device <b>424</b>.

The AP <b>422</b> may include a memory controller for controlling the memory chip <b>421</b>. The AP <b>422</b> may output data stored in the memory chip <b>421</b> through the display device <b>424</b> according to data input through the input device <b>423</b>.

For example, the input device <b>4230</b> may be implemented as a pointing device such as a touch pad or computer mouse, a keypad, or a keyboard. The AP <b>422</b> may control overall operations of the computer system <b>420</b> and control an operation of the memory chip <b>421</b>.

Here, the memory chip <b>421</b> be configured and operated like the first memory chip <b>21</b> of <figref idref="DRAWINGS">FIGS. 1 and 2</figref>.

<figref idref="DRAWINGS">FIG. 14</figref> is a block diagram illustrating a computer system <b>430</b> that may include one or more memory chips like the first memory chip <b>21</b> described in relation to <figref idref="DRAWINGS">FIGS. 1 and 2</figref> according to still another embodiment of the inventive concept.

Referring to <figref idref="DRAWINGS">FIG. 14</figref>, the computer system <b>430</b> may be implemented as an image process device such as a digital camera or a mobile telephone having a digital camera, a smart phone or a tablet PC.

The computer system <b>430</b> may include a memory chip <b>431</b>, an AP <b>432</b>, an input device <b>433</b>, an image sensor <b>434</b>, and a display device <b>435</b>. The AP <b>432</b> may include a memory controller for controlling the memory chip <b>431</b>.

The image sensor <b>434</b> may convert an optical image to a digital signal and transmit the converted digital signal to AP <b>432</b>. According to control of the AP <b>432</b>, the converted digital signal may be displayed through the display device <b>435</b> or stored in the memory chip <b>431</b>.

Further, data stored in the memory chip <b>431</b> may be displayed through display device <b>435</b> according to control of the AP <b>432</b>.

The input device <b>433</b> is a device capable of inputting a control signal for controlling an operation of the AP <b>432</b> or a data processed by the AP <b>432</b> and may be implemented as a pointing device such as a touch pad and computer mouse, a keypad, or a keyboard.

In the embodiment illustrated in <figref idref="DRAWINGS">FIG. 14</figref>, the memory chip <b>431</b> may be configured and operated like the first memory chip <b>21</b> described in relation to <figref idref="DRAWINGS">FIGS. 1 and 2</figref>.

A test system according to embodiments of the inventive concept may be used to reduce the total testing time required to test a plurality of semiconductor devices, such as memory chips. This may be accomplished by differently applying selected stress tests to the individual memory chips, thereby reducing unnecessary testing time and resulting unnecessary stress on the memory chips.

Here, individual memory devices according to embodiments of the inventive concept are capable of operating BISS/BIST circuitry to independently perform selected stress tests based suspected failure attributes for each memory chip.

Certain embodiments of the inventive concept may be applied to mobile devices and/or computer systems includes one or more memory chips.

Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible without materially departing from the novel teachings and advantages. Accordingly, all such modifications are intended to be included within the scope of this inventive concept as defined in the claims.