Drive device for insulated-gate semiconductor element, and power converter

CROSS-REFERENCE TO RELATED APPLICATION

This is a continuation application of International Application number PCT/JP2014/064482, which was filed on May 30, 2014 and designated the United States. Furthermore, this application claims the benefit of foreign priority of Japanese application number 2013-139828, filed on Jul. 3, 2013. The disclosures of both of these earlier applications are incorporated herein by reference.

BACKGROUND OF THE INVENTION

Technical Field

The present invention relates to a drive device for an insulated-gate semiconductor element and a power converter, and particularly to a drive device for an insulated-gate semiconductor element, which is capable of driving in parallel a plurality of parallel-connected insulated-gate semiconductor elements evenly with a constant current, and a power converter.

Background Art

A power converter uses IGBTs (Insulated-Gate Bipolar Transistors) for power control, MOS-FETs (Metal-Oxide-Semiconductor Field-Effect Transistors) or other insulated-gate semiconductor elements as the semiconductor elements for controlling the load. Especially in a power converter for a high power load, generally a plurality of insulated-gate semiconductor elements are connected in parallel and driven in parallel.

<figref idref="DRAWINGS">FIG. 4</figref> is a diagram showing a schematic configuration example of a power converter in which drive devices for a plurality of insulated-gate semiconductor elements are disposed in parallel.

According to this configuration example, a power converter <b>1</b> has a plurality of IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>and a plurality of drive devices <b>3</b><i>a </i>to <b>3</b><i>n </i>for driving the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>respectively. The plurality of IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>are disposed in parallel by connecting the collectors thereof to one another and connecting the emitters of the same to one another, wherein the gates of these IGBTs are connected to the outputs of the drive devices <b>3</b><i>a </i>to <b>3</b><i>n</i>, respectively. The collectors of these IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>that are connected to one another are connected to a high power load <b>4</b>, and the emitters of the same that are connected to one another are connected to a ground line GND.

The plurality of drive devices <b>3</b><i>a </i>to <b>3</b><i>n </i>receive a common drive signal and drives the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>in parallel, respectively. This causes the plurality of IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>to function as a single power switching device that drives the high power load <b>4</b>.

Here, the drive devices <b>3</b><i>a </i>to <b>3</b><i>n </i>control the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>by applying a predetermined voltage to the gates of the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n</i>. On the other hand, there has been proposed a technique for lowering the possibilities of loss and noise that occur in the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>when the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>are turned ON, by supplying a constant current to the gates of the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>to turn the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>ON (see Japanese Patent Application Publication No. 2008-103895, for example).

<figref idref="DRAWINGS">FIG. 5</figref> is a diagram showing a schematic configuration of a drive device for an insulated-gate semiconductor element in a system where the gates of conventional IGBTs are supplied with a constant current. Note that the plurality of drive devices <b>3</b><i>a </i>to <b>3</b><i>n </i>of the power converter <b>1</b> shown in <figref idref="DRAWINGS">FIG. 4</figref> are configured in the same way; thus, <figref idref="DRAWINGS">FIG. 5</figref> shows the configuration of the drive device <b>3</b><i>a </i>as a representative example.

The drive device <b>3</b><i>a </i>has a constant current circuit <b>5</b> for generating a constant current, a discharge circuit <b>6</b> for connecting the gate of the IGBT <b>2</b><i>a </i>to the ground, and a switching circuit <b>7</b> for complementarily turning the constant current circuit <b>5</b> and the discharge circuit <b>6</b> ON and OFF in response to a drive signal.

In the drive device <b>3</b><i>a </i>with the foregoing configuration, when a drive signal for turning the IGBT <b>2</b><i>a </i>ON is input, the switching circuit <b>7</b> turns the IGBT <b>2</b><i>a </i>ON by supplying the gate of the IGBT <b>2</b><i>a </i>with a constant current generated by the constant current circuit <b>5</b>. On the other hand, when a drive signal for turning the IGBT <b>2</b><i>a </i>OFF is input, the switching circuit <b>7</b> activates the discharge circuit <b>6</b> to cause the discharge circuit <b>6</b> to connect the gate of the IGBT <b>2</b><i>a </i>to the ground and discharge the electric charge accumulated in the gate, thereby turning the IGBT <b>2</b><i>a </i>OFF.

In the drive device <b>3</b><i>a </i>with the foregoing configuration, supplying a constant current to the gate of the IGBT <b>2</b><i>a </i>turns the IGBT <b>2</b><i>a </i>ON, achieving a constant speed for charging the electric charge accumulated in the gate of the IGBT <b>2</b><i>a</i>. Therefore, unlike the conventional, typical drive method for turning an IGBT ON/OFF by controlling the gate voltage of the IGBT, the charging speed of the gate of an IGBT is not changed by a change in ON-resistance that depends on the temperature of a semiconductor element (transistor) that drives the gate of the IGBT. Therefore, the IGBT <b>2</b><i>a </i>can be turned ON at constant time regardless of a change in the temperature, lowering the possibilities of loss and noise that occur in the IGBT when the IGBT is turned ON.

Unfortunately, supplying a constant current to each of the plurality of parallel-connected IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>to turn the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>ON raises the possibility that the current flows intensively to an IGBT of low gate threshold voltage due to variations in the gate threshold voltages caused by the individual difference among the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n</i>. Such concentration of current at the time of turning the IGBTs ON has a risk of thermally breaking the IGBTs.

There has conventionally been proposed a technique for measuring and storing the gate current values of the plurality of IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>in advance and controlling the gate currents of the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>based on these gate current values to achieve a current balance (see Japanese Patent Application Publication No. H11-235015, for example).

There has also been proposed a technique for offsetting the drive control voltages and emitter voltages of the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>with an equal potential in response to the difference between a target gate threshold voltage and each of the gate threshold voltages of the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>(see Japanese Patent Application Publication No. 2008-178248, for example). This technique can match the timings for turning the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>ON, achieving a current balance among the plurality of IGBTs <b>2</b><i>a </i>to <b>2</b><i>n. </i>

There has also been proposed a technique for detecting a low-temperature element and a high-temperature element and supplying the high-temperature element with a drive signal with larger delay to interfere with the flow of the current therein, while supplying the low-temperature element with a drive signal with a smaller delay to allow the current to flow easily therein (see Japanese Patent Application Publication No. 2009-159662, for example).

There has also been proposed a technique for detecting a low-temperature element and a high-temperature element, supplying the low-temperature element with a delayed drive signal, increasing the switching loss that arises when turning the element OFF to increase the amount of heat generated, and thereby equalizing the temperature and current between the low-temperature element and the high-temperature element (see Japanese Patent Application Publication No. 2009-135626, for example).

There has also been proposed a technique for comparing the temperatures between two parallel-connected power MOS-FETs and lowering the gate voltage of the power MOS-FET of a higher temperature, to equalize the temperatures of the power MOS-FETs (see Japanese Patent Application Publication No. 2002-142492, for example).

SUMMARY OF THE INVENTION

The techniques disclosed in Japanese Patent Application Publication No. H11-235015 and No. 2008-178248, however, are required to obtain the gate current values or gate threshold voltages of the plurality of IGBTs in advance. Moreover, these techniques need not only to control the gate currents of the IGBTs individually in accordance with the characteristic data of the IGBTs that are obtained beforehand, but also to perform offset control on the drive control voltages and emitter voltages of the IGBTs, and these tasks are time-consuming and lead to a complicated configuration.

On the other hand, the techniques disclosed in Japanese Patent Application Publication No. 2009-159662, No. 2009-135626 and No. 2002-142492 are configured to achieve a temperature balance between two parallel-connected semiconductor elements by comparing the temperatures thereof, which means that these techniques cannot be utilized when there exist three or more semiconductor elements connected in parallel. In addition, one of the two semiconductor elements is operated by the temperature of the other semiconductor element, leading to the potential of causing a hunting operation. Moreover, according to the device described in Japanese Patent Application Publication No. 2002-142492, because the changes in gate voltage are made constant, the temperatures of the two semiconductor elements need to be lowered alternately and repeatedly until the temperatures of the two semiconductor elements become even, resulting in a deterioration in the responsiveness thereof.

The present invention was contrived in view of these circumstances, and an object thereof is to provide a drive device for an insulated-gate semiconductor element, which is simply configured to be able to drive a plurality of parallel-connected insulated-gate semiconductor elements evenly in parallel with a constant current in a balanced manner, and to provide a power converter.

In order to solve the foregoing problems, the present invention provides a drive device for driving one of a plurality of parallel-connected insulated-gate semiconductor elements. This drive device for an insulated-gate semiconductor element has a constant current circuit that supplies a constant current to a gate of the insulated-gate semiconductor element when the insulated-gate semiconductor element is turned ON, to drive the insulated-gate semiconductor element with the constant current. The drive device also has a discharge circuit that discharges an electric charge accumulated in the gate when the insulated-gate semiconductor element is turned OFF, and a switching circuit that receives an input of a drive signal and switches between the execution of constant current drive on the insulated-gate semiconductor element using the constant current circuit and the execution of discharge of the electric charge using the discharge circuit. The drive device of the present invention further has a voltage control circuit that variably controls a power supply voltage of the constant current circuit in response to a temperature that is detected by a temperature detecting element contained in the insulated-gate semiconductor element. In other words, this drive device equalizes the currents flowing in the plurality of insulated-gate semiconductor elements by executing the combination of the constant current drive and the drive voltage control on the insulated-gate semiconductor elements.

The present invention also provides a power converter that has a plurality of parallel-connected insulated-gate semiconductor elements and a plurality of drive devices for driving the insulated-gate semiconductor elements, respectively. The drive devices each have a constant current circuit that supplies a constant current to gates of the insulated-gate semiconductor elements when the insulated-gate semiconductor elements are turned ON. Also, the drive devices each have a discharge circuit that discharges an electric charge accumulated in each of the gates of the insulated-gate semiconductor elements when the insulated-gate semiconductor elements are turned OFF, and a switching circuit that receives an input of a drive signal and switches between the execution of constant current drive on each of the insulated-gate semiconductor elements using the constant current circuit and the execution of discharge of the electric charge using the discharge circuit. Moreover, the drive devices of the present invention each have a voltage control circuit that variably controls a power supply voltage of the constant current circuit in response to the difference between a reference voltage and a detection voltage corresponding to a temperature that is detected by a temperature detecting element contained in each of the insulated-gate semiconductor elements. In other words, in this power converter, the drive devices each equalize the currents flowing in the plurality of insulated-gate semiconductor elements by executing the combination of the constant current drive and the drive voltage control on the insulated-gate semiconductor elements.

The drive device and the power converter for and insulated-gate semiconductor element that are configured as described above regulate the magnitudes of the drive voltages for turning the insulated-gate semiconductor elements ON, in response to the temperature detected by the temperature detecting element. Therefore, regardless of variations in the gate threshold voltages caused by the individual difference among the plurality of insulated-gate semiconductor elements, the timings for turning the insulated-gate semiconductor elements ON can be matched.

Additionally, by supplying a constant current to the gate of each insulated-gate semiconductor element, each of the insulated-gate semiconductor elements can be turned ON without being affected by a change in ON-resistance of a semiconductor element (transistor) that drives the gate of each temperature-dependent insulated-gate semiconductor element, resulting in lowering losses and noise that occur when turning the insulated-gate semiconductor elements ON.

Therefore, based on such a simple configuration of regulating the magnitudes of the drive voltages supplied to the gates of the insulated-gate semiconductor elements in response to the voltages generated from the temperature detecting elements contained in the insulated-gate semiconductor elements, the present invention can bring about a great deal of benefits such as securing a current balance among the plurality of insulated-gate semiconductor elements and preventing thermal breakdown of the insulated-gate semiconductor elements caused by concentration of currents.

The foregoing and other objects, features and advantages of the present invention will become more apparent from the following description associated with the accompanying drawings illustrating preferred embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

<figref idref="DRAWINGS">FIG. 1</figref> is a diagram of a schematic configuration example showing substantial parts of a drive device for an insulated-gate semiconductor element according to a first embodiment;

<figref idref="DRAWINGS">FIG. 2</figref> is a diagram showing turn-on drive voltage characteristics of the insulated-gate semiconductor element;

<figref idref="DRAWINGS">FIG. 3</figref> is a diagram of a schematic configuration example showing substantial parts of a drive device for an insulated-gate semiconductor element according to a second embodiment;

<figref idref="DRAWINGS">FIG. 4</figref> is a diagram of a schematic configuration example showing a power converter in which drive devices for a plurality of insulated-gate semiconductor elements are arranged in parallel; and

<figref idref="DRAWINGS">FIG. 5</figref> is a diagram showing a schematic configuration of a drive device for an insulated-gate semiconductor element based on a system for supplying a constant current to a gate of a conventional IGBT.

DETAILED DESCRIPTION OF THE INVENTION

Examples of using IGBTs as insulated-gate semiconductor elements are described hereinafter in detail as the embodiments of the present invention with reference to the drawings.

<figref idref="DRAWINGS">FIG. 1</figref> is a diagram of a schematic configuration example showing substantial parts of a drive device (driver circuit) for an insulated-gate semiconductor element according to a first embodiment. <figref idref="DRAWINGS">FIG. 2</figref> is a diagram showing turn-on drive voltage characteristics of the insulated-gate semiconductor element. Note that <figref idref="DRAWINGS">FIG. 1</figref> shows a schematic configuration of a drive device <b>3</b><i>a </i>as a representative example, one of drive devices <b>3</b><i>a </i>to <b>3</b><i>n </i>that drive a plurality of IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>(parallel-connected insulated-gate semiconductor elements <b>20</b>) shown in <figref idref="DRAWINGS">FIG. 4</figref>, wherein the other drive devices <b>3</b><i>b </i>to <b>3</b><i>n </i>have the same configuration as the drive device <b>3</b><i>a</i>. The same reference numerals are used to describe the components same as those configuring the drive device <b>3</b><i>a </i>shown in <figref idref="DRAWINGS">FIG. 5</figref>.

The drive device <b>3</b><i>a </i>has a constant current source <b>8</b> and a current mirror circuit <b>9</b>. The constant current source <b>8</b> and the current mirror circuit <b>9</b> configure a constant current circuit <b>5</b> shown in <figref idref="DRAWINGS">FIG. 5</figref>. The drive device <b>3</b><i>a </i>also has a discharge circuit <b>6</b>, a switching circuit <b>7</b>, a voltage control circuit <b>10</b>, and a constant current circuit <b>11</b>. The constant current source <b>8</b>, the current mirror circuit <b>9</b>, and the switching circuit <b>7</b> configure a constant current supply section. The IGBT <b>2</b><i>a </i>and a temperature detecting diode <b>12</b> for detecting heat generated by the IGBT <b>2</b><i>a </i>as a temperature detecting element configure a parallel-connected insulated-gate semiconductor element <b>20</b><i>a. </i>

The constant current source <b>8</b> has an operational amplifier <b>8</b><i>a</i>, an n-channel FET (abbreviated as “n-FET,” hereinafter) <b>8</b><i>b</i>, and a resistor <b>8</b><i>c</i>. A reference voltage Vref is supplied to the non-inverted input terminal (+) of the operational amplifier <b>8</b><i>a</i>, and the output terminal of the operational amplifier <b>8</b><i>a </i>is connected to the gate of the n-FET <b>8</b><i>b</i>. The source of the n-FET <b>8</b><i>b </i>is connected to the inverted input terminal (−) of the operational amplifier <b>8</b><i>a </i>and is also connected to a ground line GND by the resistor <b>8</b><i>c. </i>

In the constant current source <b>8</b>, the two input terminals of the operational amplifier <b>8</b><i>a </i>virtually short-circuit, whereby the reference voltage Vref is applied to the resistor <b>8</b><i>c </i>that is interposed between the source of the n-FET <b>8</b><i>b </i>and the ground line. Therefore, an output current I_Oof the constant current source <b>8</b> (i.e., drain current of the n-FET <b>8</b><i>b</i>) is fixed by a formula, I_O=Vref/Rref, where Rref represents the value of the resistor <b>8</b><i>c. </i>

The current mirror circuit <b>9</b> has a pair of p-channel FETs (abbreviated as “p-FETs,” hereinafter) <b>9</b><i>a</i>, <b>9</b><i>b</i>. The p-FET <b>9</b><i>a </i>has its source connected to a power supply line and has its drain connected to its gate and to the output of the constant current source <b>8</b> (i.e., the drain of the n-FET <b>8</b><i>b</i>). The p-FET <b>9</b><i>b</i>, on the other hand, has its source connected to the power supply line, its drain connected to the gate of the IGBT <b>2</b><i>a</i>, and its gate to the drain and gate of the p-FET <b>9</b><i>a. </i>

In this current mirror circuit <b>9</b>, when the p-FET <b>9</b><i>a </i>is driven by the constant current Io output by the constant current source <b>8</b>, the p-FET <b>9</b><i>b </i>outputs a constant current [k×I_O(k is a constant)] proportional to the constant current I_O. As a result, the current mirror circuit <b>9</b> supplies the constant current [k×I_O] proportional to the current Io to the gate of the IGBT <b>2</b><i>a. </i>

The discharge circuit <b>6</b> has a buffer circuit <b>6</b><i>a </i>and an n-FET <b>6</b><i>b</i>. A drive signal is input to the input terminal of the buffer circuit <b>6</b><i>a</i>, and the gate of the n-FET <b>6</b><i>b </i>is connected to the output terminal of the buffer circuit <b>6</b><i>a</i>. The n-FET <b>6</b><i>b </i>has its drain connected to the gate of the IGBT <b>2</b><i>a </i>and its source connected to the ground line GND.

In this discharge circuit <b>6</b>, when the drive signal input to the buffer circuit <b>6</b><i>a </i>is [H level], the buffer circuit <b>6</b><i>a </i>turns the n-FET <b>6</b><i>b </i>ON and discharges an electric charge accumulated in the gate of the IGBT <b>2</b><i>a </i>to the ground line GND, thereby turning the IGBT <b>2</b><i>a </i>OFF.

The switching circuit <b>7</b> has a p-FET <b>7</b><i>a </i>and a level shift circuit <b>7</b><i>b</i>. The p-FET <b>7</b><i>a </i>has its source connected to the power supply line and its drain connected to the gate of the p-FET <b>9</b><i>b </i>of the current mirror circuit <b>9</b>. A drive signal is input to the input of the level shift circuit <b>7</b><i>b</i>, and the gate of the p-FET <b>7</b><i>a </i>is connected to the output of the level shift circuit <b>7</b><i>b. </i>

In this switching circuit <b>7</b>, the level shift circuit <b>7</b><i>b </i>shifts the level of the drive signal and controls the gate voltage of the p-FET <b>7</b><i>a</i>, thereby turning the p-FETs <b>9</b><i>a</i>, <b>9</b><i>b </i>of the current mirror circuit <b>9</b> ON/OFF.

In other words, in the switching circuit <b>7</b>, when the drive signal is [L level], the level shift circuit <b>7</b><i>b </i>turns the p-FET <b>7</b><i>a </i>OFF and turns the current mirror circuit <b>9</b> ON. As a result, the p-FET <b>9</b><i>b </i>of the current mirror circuit <b>9</b> supplies the constant current [k×I_O] to the gate of the IGBT <b>2</b><i>a</i>. At this moment, the [L level] drive signal is supplied to the discharge circuit <b>6</b> and the n-FET <b>6</b><i>b </i>of the discharge circuit <b>6</b> is turned OFF, turning the IGBT <b>2</b><i>a </i>ON. In other words, the discharge circuit <b>6</b> is controlled so as to be turned ON/OFF by the drive signal directly input or the drive signal input through the switching circuit <b>7</b>.

However, when the drive signal is [H level], the level shift circuit <b>7</b><i>b </i>of the switching circuit <b>7</b> turns the p-FET <b>7</b><i>a </i>ON. As a result, the current mirror circuit <b>9</b> is turned OFF, resulting in stopping the supply of the current from the current mirror circuit <b>9</b> to the gate of the IGBT <b>2</b><i>a</i>. At this moment, because the [H level] drive circuit is input, the n-FET <b>6</b><i>b </i>of the discharge circuit <b>6</b> is turned ON, connecting the gate of the IGBT <b>2</b><i>a </i>to the ground line GND and discharging the electric charge accumulated in the gate of the IGBT <b>2</b><i>a</i>. As a result, the IGBT <b>2</b><i>a </i>is turned OFF.

The parallel-connected insulated-gate semiconductor element <b>20</b><i>a </i>contains the IGBT <b>2</b><i>a </i>and the temperature detecting diode <b>12</b>. The constant current circuit <b>11</b> is connected to the anode of the temperature detecting diode <b>12</b>, and the cathode of the temperature detecting diode <b>12</b> is connected to the ground line GND. A constant current that is output from the constant current circuit <b>11</b> constantly flows in the temperature detecting diode <b>12</b>. The temperature detecting diode <b>12</b> is also configured to output, as a diode voltage Vf, a forward voltage that is changed by the temperature of the IGBT <b>2</b><i>a</i>. Note that the temperature characteristics of the forward voltage of the temperature detecting diode <b>12</b> are, for example, approximately −2.0 to −2.5 mV/° C.

The voltage control circuit <b>10</b> has an operational amplifier <b>10</b><i>a </i>and four resistors <b>10</b><i>b</i>, <b>10</b><i>c</i>, <b>10</b><i>d</i>, <b>10</b><i>e </i>and configures a differential amplifier circuit. In other words, the operational amplifier <b>10</b><i>a </i>is configured to receive a reference voltage Vref<b>0</b> at its inverted input terminal (−) through the resistor <b>10</b><i>b </i>and is connected to its own output by the resistor <b>10</b><i>c</i>. The reference voltage Vref<b>0</b> defines a drive voltage Vo<b>1</b> for the constant current source <b>8</b> and the current mirror circuit <b>9</b> and is set beforehand. The non-inverted input terminal (+) of the operational amplifier <b>10</b><i>a </i>is configured to receive the input of the diode voltage Vf of the temperature detecting diode <b>12</b> through the resistor <b>10</b><i>d </i>and is connected to the ground line GND by the resistor <b>10</b><i>e. </i>

The voltage control circuit <b>10</b> is configured to amplify the voltage difference ΔV between the diode voltage Vf and the reference voltage Vref<b>0</b> and output the drive voltage Vo<b>1</b> for the constant current source <b>8</b> and the current mirror circuit <b>9</b>.

Specifically, the drive voltage Vo<b>1</b> that is output by the voltage control circuit <b>10</b> is defined as follows: <br /><i>Vo</i>1=(<i>R</i>2/<i>R</i>1)×(<i>Vf−Vref</i>0)

where R<b>1</b> represents the value of each of the resistors <b>10</b><i>b</i>, <b>10</b><i>d</i>, which are the input resistors of the operational amplifier <b>10</b><i>a</i>, and R<b>2</b> represents each of the values of the feedback resistor <b>10</b><i>c </i>and the grounding resistor <b>10</b><i>e</i>. In other words, the temperature detecting diode <b>12</b> detects the heat generated in the IGBT <b>2</b><i>a </i>and outputs the diode voltage Vf, and the voltage control circuit <b>10</b> performs feedback control on the drive voltage Vo<b>1</b> for the constant current source <b>8</b> and the current mirror circuit <b>9</b> in response to the diode voltage Vf. Specifically, the following feedback is performed: the temperature of the IGBT <b>2</b><i>a </i>rises (drops)→the diode voltage Vf becomes low (high)→the drive voltage Vo<b>1</b> becomes low (high)→the gate voltage of the IGBT <b>2</b><i>a </i>becomes low (high) because the final gate voltage when the IGBT <b>2</b><i>a </i>is ON is determined based on the drive voltage Vo<b>1</b>→the current flowing to the IGBT <b>2</b><i>a </i>becomes low (high).

In other words, the magnitude of the drive voltage Vo<b>1</b> that drives the gate of the IGBT <b>2</b><i>a </i>can be controlled by controlling the drive voltage Vo<b>1</b> for the constant current source <b>8</b> and the current mirror circuit <b>9</b> in response to variations in the gate threshold voltage that are caused by the individual difference among IGBTs <b>2</b><i>a</i>, or in response to the generated temperature.

Particularly, because the input resistors <b>10</b><i>b </i>and <b>10</b><i>d</i>, the feedback resistor <b>10</b><i>c</i>, and the grounding resistor <b>10</b><i>e </i>that share the same temperature characteristics are used, variations in the resistance values of these resistors can be offset. In addition, in all of the drive devices <b>3</b><i>a </i>to <b>3</b><i>n</i>, the temperature characteristics of the reference voltages Vref<b>0</b> and Vref are kept within ±3% of a standard value in a range of, for example, −20 to 125° C. More specifically, each predetermined reference voltage is maintained a difference from a standard value within 3% of the standard value in a range of −20 to 125° C. as its temperature characteristic. Further, the temperature characteristics of the diode voltage Vf are kept within ±10% thereof. More specifically, each temperature detecting diode <b>12</b> included in the corresponding semiconductor element <b>20</b><i>a </i>outputs a voltage corresponding to a temperature, and a temperature characteristic of each temperature detecting diode <b>12</b> maintains a change of a output voltage level depending on a change of the temperature within 10%. Accordingly, combined with the effect of offsetting variations in the resistance values described above, the temperature characteristics of the drive voltage Vo<b>1</b> for the constant current source <b>8</b> and the current mirror circuit <b>9</b> can be made sufficiently precise in relation to changes in the temperatures of the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n. </i>

As a result, in spite of the variations in the gate threshold voltages of the plurality of parallel-connected IGBTs <b>2</b><i>a </i>to <b>2</b><i>n</i>, the magnitude of the drive voltage Vo<b>1</b> for driving the gate of each IGBT can be subjected to feedback control and optimized in accordance with the temperatures of the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>(diode voltages Vf). In other words, the feedback control is performed in such a manner that the drive voltage Vo<b>1</b> drops continuously as the temperatures of the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>rise (the diode voltages Vf drop), thereby keeping currents Ic that flow to the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>constant, as shown in <figref idref="DRAWINGS">FIG. 2</figref>. Thus, even when the temperature of any of the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>is changed as a result of a change in the current flowing therein due to the variations in the gate threshold voltages, changes in the drive voltage Vo<b>1</b> can keep the flowing currents Ic constant. Consequently, the current Ic that flows in each of the plurality of parallel IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>is effectively prevented from becoming off balance, preventing concentration of current in a certain IGBT and hence thermal breakdown thereof.

In the drive device <b>3</b><i>a </i>according to the first embodiment as described above, the temperature of the IGBT <b>2</b><i>a </i>is detected by the temperature detecting diode <b>12</b> that configures the parallel-connected insulated-gate semiconductor element <b>20</b><i>a </i>together with the IGBT <b>2</b><i>a</i>, and feedback control is performed on the drive voltage Vo<b>1</b> for the constant current source <b>8</b> and the current mirror circuit <b>9</b>. Executing the constant current drive and drive voltage control on the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>converges the current Ic flowing in each of the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>on current values corresponding to the reference voltage Vref<b>0</b> of substantially the same temperature characteristics, making the currents Ic of all the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>even.

<figref idref="DRAWINGS">FIG. 3</figref> is a diagram of a schematic configuration example showing substantial parts of a drive device for an insulated-gate semiconductor element according to a second embodiment. In <figref idref="DRAWINGS">FIG. 3</figref>, the same reference numerals are used to describe the components same as those shown in <figref idref="DRAWINGS">FIG. 1</figref>, omitting the detailed descriptions thereof.

Compared to the drive device <b>3</b><i>a </i>according to the first embodiment, the voltage control circuit <b>10</b> of a drive device <b>3</b><i>a </i>for an insulated-gate semiconductor element according to the second embodiment is replaced with a voltage control circuit <b>13</b> of a different configuration.

In other words, the voltage control circuit <b>13</b> has a plurality of (four, in the example shown in <figref idref="DRAWINGS">FIG. 3</figref>) comparator <b>13</b><i>a</i>, <b>13</b><i>b</i>, <b>13</b><i>c</i>, <b>13</b><i>d</i>, p-FETs <b>13</b><i>f</i>, <b>13</b><i>g</i>, <b>13</b><i>h</i>, <b>13</b><i>i </i>functioning as switch elements, and resistors <b>13</b><i>k</i>, <b>13</b><i>l</i>, <b>13</b><i>m</i>, <b>13</b><i>n</i>, <b>13</b><i>o. </i>

The inverted input terminals (−) of the comparators <b>13</b><i>a</i>, <b>13</b><i>b</i>, <b>13</b><i>c</i>, <b>13</b><i>d </i>are configured to receive the input of the diode voltage Vf of the temperature detecting diode <b>12</b>. The non-inverted input terminals (+) of the comparators <b>13</b><i>a</i>, <b>13</b><i>b</i>, <b>13</b><i>c</i>, <b>13</b><i>d </i>are configured to receive the input of a first threshold voltage Vref<b>1</b>, a second threshold voltage Vref<b>2</b>, a third threshold voltage Vref<b>3</b>, and a fourth threshold voltage Vref<b>4</b>, respectively, whose temperature characteristics are same as the reference voltages of the first embodiment. The outputs of the comparators <b>13</b><i>a</i>, <b>13</b><i>b</i>, <b>13</b><i>c</i>, <b>13</b><i>d </i>are connected to the gates of the p-FETs <b>13</b><i>f</i>, <b>13</b><i>g</i>, <b>13</b><i>h</i>, <b>13</b><i>i</i>, respectively.

The source of the p-FET <b>13</b><i>f </i>is connected to a power supply voltage Vcc that is supplied as a device power supply voltage and is connected to the ground line GND by the serially connected resistors <b>13</b><i>k</i>, <b>13</b><i>l</i>, <b>13</b><i>m</i>, <b>13</b><i>n</i>, <b>13</b><i>o </i>configuring a voltage divider circuit. The connecting point between the resistor <b>13</b><i>k </i>and the resistor <b>13</b><i>l </i>is connected to the source of the p-FET <b>13</b><i>g</i>. The connecting point between the resistor <b>13</b><i>l </i>and the resistor <b>13</b><i>m </i>is connected to the source of the p-FET <b>13</b><i>h</i>. The connecting point between the resistor <b>13</b><i>m </i>and the resistor <b>13</b><i>n </i>is connected to the source of the p-FET <b>13</b><i>i</i>. The drains of the p-FETs <b>13</b><i>f</i>, <b>13</b><i>g</i>, <b>13</b><i>h</i>, <b>13</b><i>i </i>are integrated to output a drive voltage Vo<b>2</b> for the constant current source <b>8</b> and the current mirror circuit <b>9</b>.

In the voltage control circuit <b>13</b>, the comparators <b>13</b><i>a </i>to <b>13</b><i>d </i>compare the diode voltage Vf with the first to fourth threshold voltages Vref<b>1</b> to Vref<b>4</b>, and variably set the drive voltage Vo<b>2</b> for the constant current source <b>8</b> and the current mirror circuit <b>9</b> in response to the comparison results. It should be noted that normally (when the temperature of the IGBT <b>2</b><i>a </i>is equal to or lower than a predetermined temperature) the relationship between the diode voltage Vf and the first to fourth threshold voltages Vref<b>1</b> to Vref<b>4</b> is as follows. <br />Vf&gt;Vref<b>1</b>&gt;Vref<b>2</b>&gt;Vref<b>3</b>&gt;Vref<b>4</b>

Specifically, the power supply voltage Vcc is divided into the five serially connected resistors <b>13</b><i>k</i>(R<b>11</b>), <b>13</b><i>l</i>(R<b>12</b>), <b>13</b><i>m</i>(R<b>13</b>), <b>13</b><i>n</i>(R<b>14</b>), and <b>13</b><i>o</i>(R<b>15</b>), and the divided voltages or the power supply voltage Vcc are selected in accordance with the diode voltage Vf and output as the drive voltage Vo<b>2</b>.

For instance, during the normal operation, because the diode voltage Vf is greater than the first threshold voltage Vref<b>1</b>, all the p-FETs <b>13</b><i>f </i>to <b>13</b><i>i </i>are turned ON, and the drive voltage Vo<b>2</b> becomes equal to the power supply voltage Vcc. Furthermore, when the temperature of the IGBT <b>2</b><i>a </i>rises and the diode voltage Vf becomes lower than the first threshold voltage Vref<b>1</b>, the p-FET <b>13</b><i>f </i>is turned OFF, and the drive voltage Vo<b>2</b> becomes equal to the voltages obtained by dividing the power supply voltage Vcc: Vo<b>2</b>=Vcc×R<b>15</b>/(R<b>11</b>+R<b>15</b>). At this moment, the resistors <b>13</b><i>l</i>(R<b>12</b>), <b>13</b><i>m</i>(R<b>13</b>), and <b>13</b><i>n</i>(R<b>14</b>) are shorted due to the fact that the p-FETs <b>13</b><i>g </i>to <b>13</b><i>i </i>are ON.

When the temperature of the IGBT <b>2</b><i>a </i>further rises and the diode voltage Vf becomes lower than the second threshold voltage Vref<b>2</b>, the drive voltage Vo<b>2</b> becomes as follows. <br /><i>Vo</i>2=<i>Vcc×R</i>15/(<i>R</i>11+<i>R</i>12<i>+R</i>15)

In the drive device <b>3</b><i>a </i>with this voltage control circuit <b>13</b>, the drive voltage Vo<b>2</b> of the IGBT <b>2</b><i>a </i>changes in a stepwise manner (five steps, in this case) in response to the temperature of the IGBT, as shown in <figref idref="DRAWINGS">FIG. 2</figref>. Therefore, although the control according to the second embodiment is not as precise as that of the first embodiment, the magnitude of the drive voltage Vo<b>2</b> supplied to each of the gates of the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>can be configured to conform to the turn-on characteristics of the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>as in the first embodiment. Moreover, the currents Ic that flow through the IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>can be kept constant, effectively preventing the currents Ic that flow through the plurality of parallel-connected IGBTs <b>2</b><i>a </i>to <b>2</b><i>n </i>from becoming off balance. This, as a result, can prevent concentration of current in a certain IGBT and hence thermal breakdown thereof.

Note that the present invention is not limited to the foregoing embodiments. For instance, not only is it possible to change the configuration of the constant current source <b>8</b>, but also the drive voltage Vo<b>2</b> can be variably set with more or less steps in accordance with the diode voltage Vf in the drive device for an insulated-gate semiconductor element according to the second embodiment. The present invention can be applied similarly to a situation in which MOS-FETs are driven in place of the IGBTs described above. Moreover, for the purpose of alleviating the variations among the drive devices <b>3</b><i>a </i>to <b>3</b><i>n</i>, the reference voltages Vref, Vref<b>0</b> and first to fourth threshold voltages Vref<b>1</b> to Vref<b>4</b> of the individual drive devices <b>3</b><i>a </i>to <b>3</b><i>n </i>can be shared by all the drive devices <b>3</b><i>a </i>to <b>3</b><i>n</i>. In addition, various modifications can be made to the present invention without departing from the gist thereof.

The foregoing description is merely an illustration of the principle of the present invention. A number of modifications and changes can be made by those skilled in the art. The present invention is not intended to be limited to the exact configurations and applications described and illustrated above, but is intended to cover all the relevant modifications and equivalents as the accompanying claims and equivalents thereof.