US9607945B2

Semiconductor device comprising power elements in juxtaposition order

Summary by NHIP

Interleaved Power Element Arrangement

The semiconductor device arranges N power elements, each containing M divisional elements, in a repetitive sequential order along a first direction. Output and power supply pads align along a perpendicular second direction at opposite sides of the divisional elements, with wires connecting opposite sides of each element to its respective pad.

Claim Score by NHIP

Read claim 1, the broadest

Abstract

A semiconductor device including a multiplicity of large current power elements with each power element divided into a multiplicity of divisional elements and arranged such that the power elements belonging to different power elements are arranged in a repetitive sequential order. The IC chip of the semiconductor device is formed to have output wires extending from the respective divisional elements connected to corresponding output pads without crossing other output wires. Arranged on the IC chip are output bumps in association with the respective output pads. A rewiring layer is provided having output coupling wires for connecting together the bumps that belong to the same power element and connecting them further to an external output electrode.

US9607945B2, drawing sheet 1 — Sheet 1 of 13

Term

Term ended

Expired 11 November 2024, 1.9 years ago.

10 claims: 1 independent, 9 dependent

1
Broadest claimClaim Score 20, narrow(NHIP)A semiconductor device comprising:N (N≧2) semiconductor power elements each comprising M (M≧2) divisional elements, said semiconductor device thus comprising a total of N×M divisional elements, which are arranged such that divisional elements belonging to different ones of said N semiconductor power elements are arranged in juxtaposition and in a repetitive sequential order;N control circuits each being common to said M divisional elements of said respective N semiconductor power elements;N×M output pads associated with said N×M divisional elements;N×M output wires for connecting each of said N×M divisional elements to associated one of said N×M output pads;N×M power supply pads associated with said N×M divisional elements;and N×M power supply wires for connecting each of said N×M divisional elements to associated one of said N×M power supply pads, wherein said N×M divisional elements are arranged along a first direction, said N×M output pads and said N×M power supply pads are arranged along a second direction perpendicular to the first direction such that said output pads and said power supply pads are located at opposite sides of corresponding ones of said divisional elements respectively, and wherein a first side of one divisional element of two neighboring divisional elements among said N×M divisional elements is connected to a corresponding one of said output pads and a second side of the one divisional element is connected to a corresponding one of said power supply pads such that the first and second sides being opposite sides of the one divisional element along the second direction, and a first side of another divisional element of the two neighboring divisional elements among said N×M divisional elements is connected to a corresponding one of said power supply pads and a second side of the another divisional element is connected to a corresponding one of said output pads such that the first and second sides being opposite sides of the another divisional element along the second direction.

80 paragraphs in 6 sections, as filed

0001This is a divisional of application Ser. No. 11/778,526, filed on Jul. 16, 2007, which is a continuation of application Ser. No. 10/962,162, filed on Oct. 8, 2004, now U.S. Pat. No. 7,265,395, and claims the benefit of priority under 35 USC 119 of Japanese application no. 2003-358599, filed on Oct. 20, 2003, all of which are incorporated herein by reference.

FIELD OF THE INVENTION

0002This invention relates to a semiconductor device equipped with a multiplicity of large current power elements (i.e. large capacity power elements) such as power transistors.

BACKGROUND OF THE INVENTION

0003Some semiconductor devices have a multiplicity of large current power elements such as power transistors arranged in close proximity (see for example Japanese Patent Early Publication No. H7-135299).

0004These multiple large current power elements are often required to have their relative variations in characteristics reduced. One way to reduce the relative variations is shown in <figref idref="DRAWINGS">FIG. 8</figref>.

0005<figref idref="DRAWINGS">FIG. 8</figref> shows an arrangement of a semiconductor integrated circuit 200 having two power transistors 1A and 1B. Operating conditions of the power transistors 1A and 1B are controlled by respective control signals supplied, via signal lines 3A and 3B, from respective control circuits 2A and 2B each having a signal-processing circuit and a pre-drive circuit. The output end of the power transistor 1A is connected to an output pad 5A via an output wire 4A, and the output end of the power transistor 1B to output pad 5B via an output wire 4B. The power input ends of the power transistors 1A and 1B are connected to a common power supply pad 7 via power supply wires 6. The power input end may be alternatively connected to the ground. In this case, the power input ends serve as grounding ends, the power supply wires 6 as grounding wires, and the power supply pad 7 as a grounding pad. This applies to the rest of the examples shown below.

0006In the conventional semiconductor device 200, the power transistors 1A and 1B are arranged as close as possible to each other. However, no matter how closely the power transistors 1A and 1B are arranged to each other, corresponding portions of the power transistors 1A and 1B (indicated by Xa and Xb in <figref idref="DRAWINGS">FIG. 8</figref> for example) will be separated by an appreciable distance, since the power transistors 1A and 1B themselves have large areas. In addition, the semiconductor substrate in which the power transistors 1A and 1B are built has impurity gradient induced during its manufacture. Variations in characteristics of the power transistors 1A and 1B due to the impurity gradient and distance are unavoidable. Similarly, variations in the characteristics due to a temperature gradient created in the semiconductor substrate during operation are unavoidable.

SUMMARY OF THE INVENTION

0007It is therefore an object of the invention to provide a semiconductor device including a multiplicity of large current power elements such as power transistors whose relative variations in characteristics are small.

0008It is another object of the invention to provide a semiconductor device including a multiplicity of large current power elements whose relative variations in characteristics are small and having output wires connecting the power elements without crossing one another to reduce their layout area.

0009A semiconductor device in accordance with one embodiment of the invention includes a multiplicity N (N≧2) of semiconductor power elements adapted to perform N different operations, wherein each of the N power elements is divided into M (M≧2) divisional elements and N×M divisional elements are arranged such that divisional elements belonging to different power elements are sequentially arranged in juxtaposition. The semiconductor device further comprises N output pads in association with the N power elements, and output wires for connecting the divisional elements that belong to a respective semiconductor power element to an output pad associated with power element.

0010The semiconductor device may be provided with power supply wires or grounding wires for connecting the N×M divisional elements to at least one power supply pad or one grounding pad, respectively, wherein the power supply wires and grounding wires are formed using a wiring layer different from the wiring layer for the output wires.

0011A semiconductor device in accordance with another embodiment of the invention comprises:

0012a semiconductor integrated circuit (IC) body including <ul id="ul0001" list-style="none"><li id="ul0001-0001" num="0000"><ul id="ul0002" list-style="none"><li id="ul0002-0001" num="0013">a multiplicity N (N≧2) of semiconductor power elements adapted to perform N different operations with each power element divided into M (M≧2) divisional elements and with N×M divisional elements arranged such that divisional elements belonging to different power elements are sequentially arranged in juxtaposition, and</li><li id="ul0002-0002" num="0014">output wires for connecting the N×M divisional elements to associated N×M output pads without crossing one another; and</li></ul></li></ul>

0015a rewiring layer provided on the IC body and having <ul id="ul0003" list-style="none"><li id="ul0003-0001" num="0000"><ul id="ul0004" list-style="none"><li id="ul0004-0001" num="0016">output bumps electrically connected to the respective N×M output pads to retrieve the outputs of the N×M divisional elements, and</li><li id="ul0004-0002" num="0017">output coupling wires, provided on an insulating layer formed on the IC body, for connecting together the output bumps that belong to the same power element, the output coupling wires further connecting to an external output electrode for connection with an external device.</li></ul></li></ul>

0018The IC body may have power supply wires or grounding wires for connecting the N×M divisional elements to at least one power supply pad or one grounding pad, the power supply wires and grounding wires formed using a wiring layer different from the wiring layer for the output wires.

0019The IC body may have power supply wires or grounding wires for connecting the N×M divisional elements to at least one power supply pad or a grounding pad. The rewiring layer may be provided with a power supply bump or a grounding bump for electrical connection with the power supply pad or the grounding pad. The power supply pad or the grounding pad is connected to an external power supply electrode or external grounding electrode.

0020The power supply wires or grounding wires are arranged not to cross any of the output wires on the same plane.

0021Each of the N×M output pads may be arranged at an angular position relative to the divisional element associated with the output pad, the angular position being unique to the divisional elements that belong to the same power element and different from the angular positions of divisional elements belonging to other power elements.

0022Each of the N×M power supply pads or grounding pads may be arranged at an angular position relative to the divisional element associated with the power supply pad or grounding pad, the angular position being unique to the divisional elements that belong to the same group and different from the angular positions of the output pads.

0023The output coupling wires may be formed of the same material as the output bumps after the output bumps and the insulating layer are formed.

0024The external output electrode may be a ball electrode.

0025As described above, the inventive semiconductor device has a multiplicity of large current power element such as power transistors, with each power element divided into a multiplicity of divisional elements, wherein the divisional elements belonging to different power elements are sequentially arranged in juxtaposition to reduce relative variations of the characteristics of the power elements.

0026According to the invention, in a semiconductor device having a multiplicity of large current power elements such as power transistors with each power element divided into multiple groups of divisional elements and with divisional elements belonging to different power elements are sequentially arranged in juxtaposition, and in such semiconductor device, output wires of the divisional elements are arranged not to cross one another. This arrangement enables reduction of the layout area of the power elements, along with the reduction of the relative variations of the characteristics of the power elements.

0027The IC body of inventive semiconductor device including a multiplicity of semiconductor power elements is provided thereon with a rewiring layer having output coupling wires for connecting together divisional elements belonging to the same power element. Accordingly, the semiconductor device of the invention can be used in the same way as an ordinary semiconductor IC.

BRIEF DESCRIPTION OF THE DRAWINGS

0028<figref idref="DRAWINGS">FIG. 1</figref> shows a structure of the IC chip according to a first embodiment of the invention.

0029<figref idref="DRAWINGS">FIG. 2A</figref> shows a structure of the IC chip body according to a second embodiment of the invention.

0030<figref idref="DRAWINGS">FIG. 2B</figref> shows a structure of the rewiring layer formed on the IC chip body of the second embodiment.

0031<figref idref="DRAWINGS">FIG. 3</figref> shows a schematic sectional view illustrating a structure of the semiconductor device according to the second embodiment.

0032<figref idref="DRAWINGS">FIG. 4</figref> shows a structure of the IC chip body according to a third embodiment of the invention.

0033<figref idref="DRAWINGS">FIG. 5A</figref> shows a structure of the IC chip body according to a fourth embodiment of the invention.

0034<figref idref="DRAWINGS">FIG. 5B</figref> shows a structure of the rewiring layer formed on the IC chip body of the fourth embodiment.

0035<figref idref="DRAWINGS">FIG. 6A</figref> shows a structure of the IC chip body according to a fifth embodiment of the invention.

0036<figref idref="DRAWINGS">FIG. 6B</figref> shows a structure of the rewiring layer formed on IC chip body of the fifth embodiment.

0037<figref idref="DRAWINGS">FIG. 7A</figref> shows a structure of the IC body according to a sixth embodiment of the invention.

0038<figref idref="DRAWINGS">FIG. 7B</figref> show a structure of the rewiring layer formed on the IC chip body of the sixth embodiment.

0039<figref idref="DRAWINGS">FIG. 8</figref> shows a structure of a conventional IC chip.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

0040The inventive semiconductor device will now be described in detail by way of example with reference to the accompanying drawings.

0041<figref idref="DRAWINGS">FIG. 1</figref> shows a structure of the semiconductor device according to a first embodiment of the invention, which includes a multiplicity of power elements adapted to perform different operations and provide their own outputs. To reduce relative variations in characteristics of the power elements, each power element is divided into a multiplicity of divisional elements and arranged in such a way that divisional elements that belong to different power elements are arranged in juxtaposition and in a repetitive sequential order. Of course, the power elements can be configured to operate simultaneously. These features are common in any of the embodiments of the invention described below.

0042<figref idref="DRAWINGS">FIG. 1</figref> shows a structure of a semiconductor integrated circuit (hereinafter referred to as IC chip) 100 having two power transistors 1A and 1B consisting of divisional elements 1A-1 and 1A-2 and divisional elements 1B-1 and 1B-2, respectively. The divisional elements belonging to the power transistors 1A and 1B are arranged in juxtaposition in the order of 1A-1, 1B-1, 1A-2, and 1B-2, as shown.

0043The two divisional elements 1A-1 and 1A-2 are connected together by a signal wire 3A and an output wire 4A to form the power transistor 1A. The two divisional elements 1B-1 and 1B-2 are connected together by a signal wire 3B and an output wire 4B to form the power transistor 1B. Power supply wires 6, shown by phantom lines, are formed using a wiring layer different from the wiring layer for the output wires 4A and 4B, and connected to all the divisional elements 1A-1-1B-2. The output wires 4A and 4B are respectively connected to output pads 5A and 5B, and the power supply wires 6 are connected to a power supply pad 7. Other features of the IC chip of <figref idref="DRAWINGS">FIG. 1</figref> are the same as those of <figref idref="DRAWINGS">FIG. 8</figref>. It should be understood that the power supply wires shown by dashed lines in any other embodiment are also formed using a different wiring layer than the wiring layer for the output wires.

0044In the IC chip 100, the divisional element 1A-1 or 1A-2 belonging to the power transistor 1A and the divisional element 1B-1 or 1B-2 belonging to the power transistor 1B are arranged in juxtaposition. As a result, the distance between two corresponding portions (e.g. between portions Xa-1 and Xb-1, and between Xa-2 and Xb-2 of <figref idref="DRAWINGS">FIG. 1</figref>) becomes approximately one half the conventional distance between them. Now variations in characteristics of the two transistors exist between two correspondence portions of the elements, for example between Xa-1 and Xb-1 and between Xa-2 and Xb-2. Thus, the variations in the characteristics of the power transistors 1A and 1B are reduced accordingly.

0045In the first embodiment, however, although the variations in the characteristics are improved, improvement is not satisfactory regarding the following points. In the first embodiment, the output wires 4A and 4B extending from the divisional elements 1A-1-1B-2 are preferably connected to the output pads 5A and 5B with as small variation in resistance as possible. In doing so, if the output pads arranged in the same angular position relative to the respective divisional elements, the output wires 4A and 4B connected to the output pads will cross each other if the same wiring layer is used. Moreover, if the power supply wires 6 are provided using the same wiring layer, they will cross the output wires 4A and 4B. Furthermore, the output wires 4A and 4B and the power supply wires 6 are required to have sufficient widths in order to suppress on-resistances of the power elements. However, since the wiring distances of the wires increase when such crossing of wires takes place, the widths of the lead wires must be increased to keep the on-resistances suppressed. Hence, when the output wires 4A and 4B and the power supply wires 6 are arranged in the regions between the divisional elements 1A-1-1B-2 and the output pads 5A and 5B, or between the divisional elements 1A-1-1B-2 and the power supply pad 7 as shown in <figref idref="DRAWINGS">FIG. 1</figref>, a large wiring area is needed in the region, thereby lowering the layout efficiency.

0046<figref idref="DRAWINGS">FIGS. 2A and 2B</figref> together show a structure of the semiconductor device according to a second embodiment of the invention configured to reduce the relative variations in characteristics of the power elements while suppressing the layout area therefor. <figref idref="DRAWINGS">FIG. 3</figref> is a schematic sectional view of a semiconductor device of the second embodiment.

0047<figref idref="DRAWINGS">FIG. 2A</figref> particularly shows the structure of a semiconductor integrated circuit (referred to as IC chip body) according to the invention. <figref idref="DRAWINGS">FIG. 2B</figref> particularly shows the structure of a rewiring layer formed on the IC chip body. In the following embodiments, power elements are supposed to be power transistors. However, the invention may be applied to other power elements other than power transistors in reducing their relative variations in characteristics.

0048In the example shown in <figref idref="DRAWINGS">FIG. 2A</figref>, each of the N (N=2) power transistors 11A and 11B consists of two divisional elements (M=2). The multiple divisional elements 11A-1, 11B-1, 11A-2, and 11B-2 of the power transistors 11A and 11B are arranged in juxtaposition in the order mentioned. The two divisional elements 11A-1 and 11A-2 are controlled by the control signal supplied from a control circuit 12A via a signal wire 13A. That is, the divisional elements 11A-1 and 11A-2 are driven together as a unified power transistor 11A. The two divisional elements 11B-1 and 11B-2 are controlled by a control signal supplied from a control circuit 12B via a signal wire 13B. That is, the divisional elements 11B-1 and 11B-2 are driven together as a unified power transistor 11B.

0049The output wires 14A-1, 14B-1, 14A-2, and 14B-2 of the divisional elements 11A-11-B-2 are respectively connected to output pad 15A-1, 15B-1, 15A-2, and 15B-2.

0050Moreover, power supply wires 16 extending from the divisional elements 11A-1-11B-2 are connected to a common power supply pad 17 using a wiring layer different from the wiring layer for the output wires 14A-1-14B-2. Incidentally, the “power supply” can alternatively be replaced by the “ground.” In this case, the power supply pad 17 is grounded, and the power supply wire 16 is rephrased as the grounding wire 16 and the power supply pad 17 as the grounding pad 17. This applies to other embodiments of the invention.

0051In the IC chip body 10, the divisional elements 11A-1 and 11A-2 belonging to the power transistor 11A and the divisional elements 11B-1 and 11B-2 belonging to the power transistor 11B are arranged in close proximity. The corresponding portions (as marked as Xa-1 and Xb-1, and Xa-2 and Xb-2 in <figref idref="DRAWINGS">FIG. 2A</figref>) have short distances. That is, variations in characteristics of the two transistors exist between two correspondence portions of the elements, for example between Xa-1 and Xb-1 and between Xa-2 and Xb-2.

0052In the IC chip 10, output wires 14A-1-14B-2 extending from the divisional elements 11A-1-11B-2 are directly connected to the output pads 15A-1-15B-2. That is, the output wires 14A-1-14B-2 do not cross each other. Thus, on-resistances of the power transistors 11A and 11B including resistances of the wiring resistances can be minimized.

0053It is noted that the output wires 14A-1-14B-2 cross the power supply wires 6. However, in the IC chip body 10, crossing does not matter, since the electric conduction layer for the output wires and that for the power supply wire are formed using different wiring layers.

0054In a rewiring layer 20 formed on the IC chip body shown in <figref idref="DRAWINGS">FIG. 2B</figref>, output bumps (or output posts) 21A-1, 21B-1, 21A-2, 21B-2, and a power supply bump (or power supply post) 23 are provided in contact with corresponding output pads 15A-1, 15B-1, 15A-2, and 15B-2 and with a corresponding power supply pad 17, respectively. An insulating layer of polyimide resin for example is provided on the surface of the IC chip body 10 excluding the areas of the pads. This insulating layer may have a thickness comparable with the heights of the output bumps 21A-1-21B-2 and the power supply bump 23.

0055The output bumps 21A-1-21A-2 associated with the power transistor 11A are connected together by an output coupling wire 22A, which is extended to a position where it is connected to an external output electrode 24A. The bumps 21B-1 and 21B-2 associated with the power transistor 11B are connected together by an output coupling wire 22B, which is extended to a position where it is connected to an external output electrode 24B. The power supply bump 23 is connected to a power supply bump electrode 25. It is noted that in this rewiring layer 20 the output coupling wires 22A and 22B do not cross each other or cross any other lead wires. Therefore, the output coupling wires can be formed with sufficient widths in one layer to minimize their resistances.

0056It is noted that the external output electrodes 24A and 24B can alternatively be provided directly on the respective bumps 21A-1 and 21A-2 or on the respective bumps 21B-1 and 21B-2.

0057The output coupling wires 22A and 22B are formed after the output bumps 21A-21B and the insulating layer are formed. The output coupling wires 22A and 22B are preferably formed of the same material, and formed to have the same thickness and the same length as the bumps. The external output electrodes 24A and 24B and the power supply bump electrode 25 may be provided in the form of, for example, ball electrodes and a bump electrode, respectively.

0058<figref idref="DRAWINGS">FIG. 3</figref> is a schematic sectional view illustrating the structure of the semiconductor device shown in <figref idref="DRAWINGS">FIGS. 2A and 2B</figref>, with alphabets A and B omitted from the symbols.

0059As shown in <figref idref="DRAWINGS">FIG. 3</figref>, each of the constituent elements of <figref idref="DRAWINGS">FIG. 2A</figref> is built in the IC chip body 10. Formed on the surface of the IC chip body 10 are the output pads 15. The bumps (or posts) 21 are formed to be in electrical contact with the output pads 15. An insulating layer 26 is formed on the surface of the IC chip body 10 excluding the areas of the bumps. Next, a predetermined set of the bumps 21 is connected together by an output coupling lead wire 22, to which an external output electrode 24 is connected.

0060In accordance with the second embodiment, each of the multiple power elements 11A and 11B is constituted of a multiplicity of divisional elements 11A-1-11B-2. The divisional elements belonging to different power elements are sequentially arranged in juxtaposition to thereby reduce relative variations in the characteristics of the power elements. Moreover, crossing of the output wires 14A-1-42B-2 is eliminated to suppress their layout area. In addition, only one rewiring layer 20 is used to provide the non-crossing output coupling wires 22A and 22B. Furthermore, since the rewiring layer 20 is formed to have the output coupling wires 22A and 22B that connect together the divisional elements associated with the same power element 11A or 11B, the semiconductor device of the invention can be used as an ordinary IC chip.

0061<figref idref="DRAWINGS">FIG. 4</figref> shows a structure of an IC chip body 10′ of the semiconductor device according to a third embodiment of the invention.

0062In the IC chip body 10′ of <figref idref="DRAWINGS">FIG. 4</figref>, a power supply wire 16′ connecting the divisional elements 11A-1-11B-2 to a power supply pad 17′ is arranged on the same plane without crossing any of the output wires 14A-1-14B-2. Thus, the output wires 14A-1-14B-2 and the power supply wire 16′ can be formed using the same wiring layer. Other features of the arrangement of <figref idref="DRAWINGS">FIG. 4</figref> are the same as for the IC chip body 10 of <figref idref="DRAWINGS">FIG. 2A</figref>.

0063Formed on the IC chip body 10′ is the same rewiring layer 20 as shown in <figref idref="DRAWINGS">FIG. 2B</figref>.

0064In accordance with the third embodiment, although the length of the power supply wire 16′ becomes larger as compared with that of the second embodiment, the power supply wire 16′ can be formed together with the output wires 14A-1-14B-2 using the same wiring layer. The third embodiment can provide the same results as the second embodiment.

0065<figref idref="DRAWINGS">FIGS. 5A and 5B</figref> together show a structure of the semiconductor device according to a fourth embodiment of the invention. Particularly, <figref idref="DRAWINGS">FIG. 5A</figref> illustrates the structure of an IC chip body 30, and <figref idref="DRAWINGS">FIG. 5B</figref> the structure of a rewiring layer 40 formed on the IC chip body 30.

0066<figref idref="DRAWINGS">FIG. 5A</figref> shows an exemplary IC chip body 30 constituted of two power transistors 31A and 31B (N=2) each divided into two divisional elements (M=2). The multiple divisional elements 31A-1, 31B-1, 31A-2, and 31B-2 making up the power transistors 31A and 31B are arranged in juxtaposition in the order mentioned. The two divisional elements 31A-1 and 31A-2 are controlled by a control signal supplied from a control circuit 32A via a signal wire 33A.

0067The output pad 35A-1 and 35A-2 associated with the divisional elements 31A-1 and 31A-2 of the power transistor 31A are provided in proximity to the upper ends of the respective divisional elements, as shown. Power supply pads 37-1 and 37-3 are provided in proximity to the lower ends of the respective divisional elements, as shown. The output pads 35B-1 and 35B-2 associated with the divisional elements 31B-1 and 31B-2 are provided in proximity to the lower ends of the respective divisional elements, as shown. The power supply pads 37-2 and 374 are provided in proximity to the upper ends of the respective divisional elements, as shown. Two sets of the divisional elements 31A-1 and 31A-2 and of divisional elements 31B-1 and 31B-2 are respectively supplied with control signals from control circuits 32A and 32B via signal wires 33A and 33B. Thus, the divisional elements 31A-1 and 31A-2 are driven together as one power transistor 31A, and so are the divisional elements 31B-1 and 31B-2 driven as one transistor 31B.

0068In this manner, the four (N×M) divisional elements 35A-1-35B-2 are provided with respective power supply pads 37-1-374 and output pads 35A-1-35B-2. These power supply pads 37-1-37-4 and output pads 35A-1-35B-2 are connected to the divisional elements by the respective power supply wires and by the respective output wire (reference number omitted in <figref idref="DRAWINGS">FIG. 5A</figref>).

0069The four (N×M) output pads 35A-1-35B-2 are arranged in such a way that two of them associated with the divisional elements 31A-1 and 31A-2 belonging to the same power element 31A are each arranged at an angular position (e.g. upper position) relative to the associated divisional element as shown, while two of them associated with the divisional elements 31B-1 and 31B-2 belonging to the same power element 31B are each arranged at another angular position (e.g. lower position) relative to the associated divisional element as shown.

0070The four (N×M) power supply pads 37-1-37-4 are arranged in such a way that two of them associated with the divisional elements 31A-1 and 31A-2 belonging to the same power element 31A are each arranged at an angular position (e.g. lower position) relative to the associated divisional element as shown, while two of them associated with the divisional elements 31B-1 and 31B-2 belonging to the same power element 31B are each arranged at another angular position (e.g. upper position) relative to the associated divisional element.

0071Thus, the output wires and the power supply wires can be arranged in considerably short length without crossing one another by arranging the output pads 35A-1-35B-2 and the power supply pads 37-1-37-4 in the configuration as described above.

0072In the rewiring layer 40 of <figref idref="DRAWINGS">FIG. 5B</figref> formed on the IC chip body, the output bumps 41A-1, 41B-1, 41A-2, and 41B-2 and the power supply bumps 43-1-43-4 are respectively provided on the IC chip body 30 in electrical contact with the corresponding output pads 35A-1, 35B-1, 35A-2, and 35B-2 and the corresponding power supply pads 37-1 to 37-4. An insulating layer is provided on the surface of the IC chip body 30 excluding the areas of the bumps.

0073The output bumps 41A-1 and 41A-2 associated with the power transistor 31A are connected together by an output coupling lead wire 42A, which is extended to a point where it is connected to an external output electrode 44A. The bumps 41B-1 and 41B-2 associated with the power transistor 31B are connected together by an output coupling wire 42B, which is extended to a point where it is connected to an external output electrode 44B. The power supply bumps 43-1-43-4 are connected together by a power coupling wire 46, which is extended to a point where it is connected to an external device.

0074Power supply electrodes 45-1 and 45-2 are connected to the power coupling wire 46 at two points, which are, in the example shown herein, the power supply bumps 43-1 and 43-4. In this rewiring layer 40, there is no crossing between the output coupling wires 42A and 42B nor between the output coupling wires and the power coupling wire 46. Therefore, the output coupling wires 42A and 42B and the power coupling wire 46 can be implemented by one electric conduction layer. Other features of this semiconductor device are the same as those of the second and the third embodiments described above.

0075It is noted that in the fourth embodiment output wires and power supply wires never cross one another, that their lengths can be very short, and that the same results can be attained as in the second embodiment.

0076<figref idref="DRAWINGS">FIGS. 6A and 6B</figref> together show a structure of the semiconductor device according to a fifth embodiment of the invention. Particularly, <figref idref="DRAWINGS">FIG. 6A</figref> shows an exemplary structure of an IC chip body 50, and <figref idref="DRAWINGS">FIG. 6B</figref> shows an exemplary structure of a rewiring layer 60 formed on the IC chip body 50.

0077The IC chip body 50 shown in <figref idref="DRAWINGS">FIG. 6A</figref> consists of two power transistors 51A and 51B each divided into three divisional elements (N=2, M=3). The rewiring layer 60 of <figref idref="DRAWINGS">FIG. 6B</figref> formed on the IC chip body 50 is structured to correspond to the three divisional elements of the respective power transistors. The IC chip body 50 of <figref idref="DRAWINGS">FIG. 6A</figref> and the rewinding layer 60 of <figref idref="DRAWINGS">FIG. 6B</figref> have the same structures as those of the fourth embodiment shown in <figref idref="DRAWINGS">FIGS. 5A and 5B</figref> except for the power transistors each divided into three divisions. Elements are denoted by numerals of 50′s in <figref idref="DRAWINGS">FIG. 6A and 60</figref>'s in <figref idref="DRAWINGS">FIG. 6B</figref>.

0078More particularly, symbols 51A-1-51B-3 indicate the respective divisional elements of the power transistors 51A and 51B; symbols 52A and 52B, control circuits; symbols 53A and 53B, signal wires; symbols 55A-1-55B-3, output pads; and symbols 57-1-57-6, power supply pads. Further symbols 61A-1-61B-3 indicate output bumps; symbols 62A and 62B, output coupling wires; symbols 63-1-63-6, power supply bumps; symbols 64A and 64B, external output electrodes; symbols 65-1 and 65-2, external power supply electrodes; and symbol 66, power supply coupling wires.

0079In the fifth embodiment, multiplicity M of divisional elements per power element can be increased while attaining the same results as the fourth embodiment.

0080<figref idref="DRAWINGS">FIGS. 7A and 7B</figref> show the structure of a semiconductor device according to a sixth embodiment of the invention. Particularly, <figref idref="DRAWINGS">FIG. 7A</figref> shows the structure of an IC chip body 70, and <figref idref="DRAWINGS">FIG. 7B</figref> shows the structure of a rewiring layer 80 foamed on the IC chip body 70.

0081In the example shown in <figref idref="DRAWINGS">FIG. 7A</figref>, the IC chip body 70 has three power transistors 71A, 71B, and 71C each consisting of two divisional elements (N=3, M=2). The rewiring layer 80 formed on the IC chip body of <figref idref="DRAWINGS">FIG. 7B</figref> is structured to correspond to the two divisional elements of the respective power transistors of the IC chip body 70. The IC chip body 70 and the rewinding layer 80 have the same structures as those of the second embodiment shown in FIGS. 2A and 2B except for the three power transistors each being divided into two divisional elements denoted by numerals of 70's in <figref idref="DRAWINGS">FIG. 7A</figref> and 80's in <figref idref="DRAWINGS">FIG. 7B</figref>.

0082More particularly, symbols 71A-1-71C-2 denote the respective divisional elements of the power transistors 71A, 71B, and 71C; symbols 72A, 72B, and 72C, control circuits; symbols 73A, 73B, and 73C, signal wires; symbols 74A-1-74C-2, output wires; symbols 75A-1-75C-2, output pads; symbols 76, power supply wires; and symbol 77, power supply pad. Further symbols 81A-1-81C-2 denote output bumps; symbols 82A, 82B, and 82C, output coupling wires; symbols 83, a power supply bump; symbols 84A, 84B, and 84C, external output electrodes; and symbols 85, an external power supply electrode.

0083In this sixth embodiment, output wires can connect the respective blocks on the same plane without crossing one another if the number N of power elements is increased, thereby providing the same results as the preceding embodiments.

0084Although the invention has been described above only for the cases with M≦3 or N≦3, it will be apparent that the invention can be extended to cases with M>3 and N>3, facilitating minimization of wiring resistance and a wiring space in a semiconductor device.

Contents6

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Citations
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WO0250898A1	Cites	World Intellectual Property Organization (WIPO)	Applicant
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JPH07135299A	Cites	Japan	Applicant
JPH11168178A	Cites	Japan	Applicant
US20010011768A1	Cites	United States of America	Search report
US20010026008A1	Cites	United States of America	Applicant
US20020149086A1	Cites	United States of America	Applicant
US20020180027A1	Cites	United States of America	Applicant
US20020195286A1	Cites	United States of America	Search report
US20030137861A1	Cites	United States of America	Search report
US20030164738A1	Cites	United States of America	Search report
US20030170934A1	Cites	United States of America	Applicant
US20030218246A1	Cites	United States of America	Applicant
US20040056367A1	Cites	United States of America	Search report
US20050110136A1	Cites	United States of America	Search report
JP7135299	Cites	Japan	Applicant
JP11168178	Cites	Japan	Applicant
WO0250898A1	Cites	World Intellectual Property Organization (WIPO)	Applicant

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Document	Office	Kind	Date
2003358599	Japan	–	2003-10-20
2003358599	Japan	A	2003-10-20
96216204	United States of America	A	2004-10-08
77852607	United States of America	A	2007-07-16

Members13

Family members, oldest first
Document	Office	Kind
KR20050037974A	Republic of Korea	A	2005-04-25
JP2005123486A	Japan	A	2005-05-12
CN1617339A	China	A	2005-05-18
US2005110154A1	United States of America	A1	2005-05-26
TW200520193A	Taiwan Province of China	A	2005-06-16
US7265395B2	United States of America	B2	2007-09-04
US2007262419A1	United States of America	A1	2007-11-15
CN100511679C	China	C	2009-07-08
JP4397210B2	Japan	B2	2010-01-13
TWI348752B	Taiwan Province of China	B	2011-09-11
US2016071798A1	United States of America	A1	2016-03-10
US9607945B2This record	United States of America	B2	2017-03-28
US2017154849A1	United States of America	A1	2017-06-01

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2025-05-05	Expire PatentEXP.	EXP.
2024-11-18	Maintenance Fee Reminder MailedREM.	REM.
2020-09-17	Payment of Maintenance Fee, 4th Year, Large EntityM1551	M1551
2017-03-28	Recordation of Patent Grant MailedPGM/	PGM/
2017-03-28	Patent Issue Date Used in PTA CalculationAllowedPTAC	PTAC
2017-03-10	Email NotificationEML_NTR	EML_NTR
2017-03-08	Issue Notification MailedAllowedWPIR	WPIR
2017-02-15	Dispatch to FDCD1935	D1935
2017-02-15	Application Is Considered Ready for IssuePILS	PILS
2017-02-10	Issue Fee Payment VerifiedN084	N084
2017-02-10	Issue Fee Payment ReceivedIFEE	IFEE
2016-11-28	Email NotificationEML_NTR	EML_NTR
2016-11-28	Printer Rush- No mailingTCPB	TCPB
2016-11-28	Mailing Corrected Notice of AllowabilityMCNOA	MCNOA
2016-11-22	Corrected Notice of AllowabilityCNOA	CNOA
2016-11-21	Pubs Case Remand to TCPUBTC	PUBTC
2016-11-10	Electronic ReviewELC_RVW	ELC_RVW
2016-11-10	Email NotificationEML_NTF	EML_NTF
2016-11-10	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2016-11-08	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2016-10-22	Reasons for AllowanceEX.R	EX.R
2016-10-22	Examiner's Amendment CommunicationEX.A	EX.A
2016-10-20	Interview Summary - Examiner Initiated - TelephonicEXET	EXET
2016-10-06	Information Disclosure Statement consideredIDSC	IDSC
2016-03-11	Email NotificationEML_NTR	EML_NTR
2016-03-10	Application ready for PDX access by participating foreign officesCCRDY	CCRDY
2016-03-10	PG-Pub Issue NotificationPG-ISSUE	PG-ISSUE
2016-01-11	Priority document has successfully retrieved via PDX/DASPD.RECVD	PD.RECVD
2016-01-06	Case Docketed to Examiner in GAUDOCK	DOCK
2015-12-01	Email NotificationEML_NTR	EML_NTR
2015-12-01	Application Is Now CompleteCOMP	COMP
2015-12-01	Filing Receipt - UpdatedFLRCPT.U	FLRCPT.U
2015-11-30	Application Dispatched from OIPEOIPE	OIPE
2015-11-30	FITF set to NO - revise initial settingFTFI	FTFI
2015-11-23	Patent Term Adjustment - Ready for ExaminationPTA.RFE	PTA.RFE
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2015-10-26	Applicant has submitted new drawings to correct Corrected Papers problemsCORRDRW	CORRDRW
2015-10-26	Applicant has submitted a new specification to correct Corrected Papers problemsCORRSPEC	CORRSPEC
2015-08-24	Electronic ReviewELC_RVW	ELC_RVW
2015-08-24	Email NotificationEML_NTF	EML_NTF
2015-08-24	Email NotificationEML_NTR	EML_NTR
2015-08-24	Corrected PaperCPAP	CPAP
2015-08-24	Filing ReceiptFLRCPT.O	FLRCPT.O
2015-08-11	Cleared by OIPE CSRL194	L194
2015-08-07	Reference capture on IDSRCAP	RCAP
2015-08-07	Information Disclosure Statement (IDS) FiledM844	M844
2015-08-07	Preliminary AmendmentA.PE	A.PE
2015-08-07	Applicants have given acceptable permission for participating foreignAPPERMS	APPERMS
2015-08-07	Request from applicant for the USPTO to retrieve the Priority DocumentPDREQUST	PDREQUST
2015-08-07	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2015-08-07	IFW Scan & PACR Auto Security ReviewSCAN	SCAN
2015-08-07	Entity Status Set To Undiscounted (Initial Default Setting or Status Change)BIG.	BIG.
2015-08-07	Initial Exam Team nnIEXX	IEXX

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	Event	Code
2025-05-27	Lapsed due to failure to pay maintenance feeLapsedFP	FP
2025-05-05	Lapse for failure to pay maintenance feesLapsedPATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYLAPS	LAPS
2025-05-05	Information on status: patent discontinuationPATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362STCH	STCH
2024-11-18	Fee payment procedureMAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP	FEPP
2020-09-17	Maintenance fee paymentMAFP	MAFP
2017-03-08	Information on status: patent grantGrantedPATENTED CASESTCF	STCF

Semiconductor device comprising power elements in juxtaposition order

Summary by NHIP

Claim Score by NHIP

Abstract