Methods for uniform imprint pattern transfer of sub-20 nm features
Summary by NHIP
Imprint Lithography Etch Transfer
The method imprints a polymerized layer with protrusions 20 nm or less high and aspect ratios of 1.5:1 to 3:1, then deposits an etch selective material. This material comprises SiO2, Cr, Al2O3, or Si, achieving 50:1 selectivity to preserve sub-20 nm features during substrate etching.
Claim Score by NHIP
Abstract
Methods of increasing etch selectivity in imprint lithography are described which employ material deposition techniques that impart a unique morphology to the multi-layer material stacks, thereby enhancing etch process window and improving etch selectivity. For example, etch selectivity of 50:1 or more between patterned resist layer and deposited metals, metalloids, or non-organic oxides can be achieved, which greatly preserves the pattern feature height prior to the etch process that transfers the pattern into the substrate, allowing for sub-20 nm pattern transfer at high fidelity.

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20 claims: 3 independent, 17 dependent
- 1An imprint lithography method comprising the steps of:imprinting a patterned layer of an organic polymerized material on a substrate, the patterned layer having a residual layer and one or more protrusions and recessions defining features of the patterned layer, with the protrusions extending from the residual layer a height of 20 nm or less and having an aspect ratio of 1.5:1 to 3:1;depositing an etch selective material onto at least the protrusions and the recessions of the patterned layer, the etch selective material comprising a metal, metalloid or non-organic oxide having an etch selectivity of 50:1 or more relative to the organic polymerized material;etching back the deposited etch selective material to reveal the protrusions;etching back the protrusions to reveal the substrate;and etching the substrate to form an inverse pattern of the patterned layer in the substrate at high fidelity.
- 11An imprint lithography method comprising the steps of:imprinting a patterned layer of an organic polymerized material on a substrate, the patterned layer having a residual layer and one or more protrusions and recessions defining features of the patterned layer, with the protrusions extending from the residual layer a height of 20 nm or less and having an aspect ratio of 1.5:1 to 3:1;forming a conformal layer of etch selective material over the patterned layer and filling in the recessions of the patterned layer with the etch selective material, the etch selective material comprising a metal, metalloid or non-organic oxide having an etch selectivity of 50:1 or more relative to the organic polymerized material;etching back the deposited etch selective material to reveal the protrusions;etching back the protrusions to reveal the substrate;and etching the substrate to form an inverse pattern of the patterned layer in the substrate at high fidelity.
- 16Broadest claimClaim Score 61, broad(NHIP)An imprint lithography method comprising the steps of:imprinting a patterned layer of an organic polymerized material on a substrate, the patterned layer having a residual layer and one or more protrusions and recessions defining features of the patterned layer, with the protrusions extending from the residual layer a height of 20 nm or less and having an aspect ratio of 1.5:1 to 3:1;depositing an etch selective material solely on the protrusions of the patterned layer, the etch selective material comprising a metal, metalloid or non-organic oxide having an etch selectivity of 50:1 or more relative to the organic polymerized material;etching back the residual layer to reveal the substrate;and etching the substrate to form a corresponding pattern of the patterned layer in the substrate at high fidelity.
Independent claims3
32 paragraphs in 4 sections, as filed
CROSS-REFERENCE TO RELATED APPLICATION
0001This application claims the benefit under 35 U.S.C. §119(e)(1) of U.S. Provisional Application No. 61/921,647 filed Dec. 30, 2013; which is hereby incorporated by reference herein in its entirety.
BACKGROUND INFORMATION
0002Nano-fabrication includes the fabrication of very small structures that have features on the order of 100 nanometers or smaller. One application in which nano-fabrication has had a sizeable impact is in the processing of integrated circuits. The semiconductor processing industry continues to strive for larger production yields while increasing the circuits per unit area formed on a substrate, therefore nano-fabrication becomes increasingly important. Nano-fabrication provides greater process control while allowing continued reduction of the minimum feature dimensions of the structures formed. Other areas of development in which nano-fabrication has been employed include photovoltaic cells, biotechnology, optical technology, mechanical systems, and the like.
0003An exemplary nano-fabrication technique in use today is commonly referred to as imprint lithography. Exemplary imprint lithography processes are described in detail in numerous publications, such as U.S. Pat. No. 8,349,241, U.S. Patent Publication No. 2004/0065252, and U.S. Pat. No. 6,936,194, all of which are hereby incorporated by reference herein in their entirety.
0004An imprint lithography technique disclosed in each of the aforementioned U.S. patent publication and patents includes formation of a relief pattern in a formable (polymerizable) layer and transferring a pattern corresponding to the relief pattern into an underlying substrate. The substrate may be coupled to a motion stage to obtain a desired positioning to facilitate the patterning process. The patterning process uses a template spaced apart from the substrate and a formable liquid applied between the template and the substrate. The formable liquid is solidified to form a rigid layer that has a pattern conforming to a shape of the surface of the template that contacts the formable liquid. After solidification, the template is separated from the rigid layer such that the template and the substrate are spaced apart. The substrate and the solidified layer are then subjected to additional processes to transfer a relief image into the substrate that corresponds to the pattern in the solidified layer.
BRIEF DESCRIPTION OF DRAWINGS
0005So that features and advantages of the present invention can be understood in detail, a more particular description of embodiments of the invention may be had by reference to the embodiments illustrated in the appended drawings. It is to be noted, however, that the appended drawings only illustrate typical embodiments of the invention, and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
0006<figref idref="DRAWINGS">FIG. 1</figref> illustrates a simplified side view of an exemplary imprint lithography system.
0007<figref idref="DRAWINGS">FIG. 2</figref> illustrates a simplified side view of the substrate illustrated in <figref idref="DRAWINGS">FIG. 1</figref>, having a patterned layer with nanostructures thereon.
0008<figref idref="DRAWINGS">FIGS. 3A-G</figref> illustrate a method of patterning a substrate according to an embodiment of the invention;
0009<figref idref="DRAWINGS">FIGS. 4A-F</figref> illustrate a method of patterning a substrate according to another embodiment of the invention;
0010<figref idref="DRAWINGS">FIGS. 5A-F</figref> illustrate a method of patterning a substrate according to yet another embodiment of the invention;
0011<figref idref="DRAWINGS">FIGS. 6A-E</figref> illustrate a method of patterning a substrate according to further embodiment of the invention.
DETAILED DESCRIPTION
0012Referring to the figures, and particularly to <figref idref="DRAWINGS">FIG. 1</figref>, illustrated therein is a lithographic system <b>10</b> used to form a relief pattern on substrate <b>12</b>. Substrate <b>12</b> may be coupled to substrate chuck <b>14</b>. As illustrated, substrate chuck <b>14</b> is a vacuum chuck. Substrate chuck <b>14</b>, however, may be any chuck including, but not limited to, vacuum, pin-type, groove-type, electrostatic, electromagnetic, and/or the like. Exemplary chucks are described in U.S. Pat. No. 6,873,087, which is hereby incorporated by reference herein.
0013Substrate <b>12</b> and substrate chuck <b>14</b> may be further supported by stage <b>16</b>. Stage <b>16</b> may provide translational and/or rotational motion along the x, y, and z-axes. Stage <b>16</b>, substrate <b>12</b>, and substrate chuck <b>14</b> may also be positioned on a base (not shown).
0014Spaced-apart from substrate <b>12</b> is template <b>18</b>. Template <b>18</b> may include a body having a first side and a second side with one side having a mesa <b>20</b> extending therefrom towards substrate <b>12</b>. Mesa <b>20</b> having a patterning surface <b>22</b> thereon. Further, mesa <b>20</b> may be referred to as mold <b>20</b>. Alternatively, template <b>18</b> may be formed without mesa <b>20</b>.
0015Template <b>18</b> and/or mold <b>20</b> may be formed from such materials including, but not limited to, fused-silica, quartz, silicon, organic polymers, siloxane polymers, borosilicate glass, fluorocarbon polymers, metal, hardened sapphire, and/or the like. As illustrated, patterning surface <b>22</b> comprises features defined by a plurality of spaced-apart recesses <b>24</b> and/or protrusions <b>26</b>, though embodiments of the present invention are not limited to such configurations (e.g., planar surface). Patterning surface <b>22</b> may define any original pattern that forms the basis of a pattern to be formed on substrate <b>12</b>.
0016Template <b>18</b> may be coupled to chuck <b>28</b>. Chuck <b>28</b> may be configured as, but not limited to, vacuum, pin-type, groove-type, electrostatic, electromagnetic, and/or other similar chuck types. Exemplary chucks are further described in U.S. Pat. No. 6,873,087, which is hereby incorporated by reference herein. Further, chuck <b>28</b> may be coupled to imprint head <b>30</b> such that chuck <b>28</b> and/or imprint head <b>30</b> may be configured to facilitate movement of template <b>18</b>.
0017System <b>10</b> may further comprise a fluid dispense system <b>32</b>. Fluid dispense system <b>32</b> may be used to deposit formable material <b>34</b> (e.g., polymerizable material) on substrate <b>12</b>. Formable material <b>34</b> may be positioned upon substrate <b>12</b> using techniques, such as, drop dispense, spin-coating, dip coating, chemical vapor deposition (CVD), physical vapor deposition (PVD), thin film deposition, thick film deposition, and/or the like. Formable material <b>34</b> may be disposed upon substrate <b>12</b> before and/or after a desired volume is defined between mold <b>22</b> and substrate <b>12</b> depending on design considerations. Formable material <b>34</b> may be functional nano-particles having use within the bio-domain, solar cell industry, battery industry, and/or other industries requiring a functional nano-particle. For example, formable material <b>34</b> may comprise a monomer mixture as described in U.S. Pat. No. 7,157,036 and U.S. Patent Publication No. 2005/0187339, both of which are herein incorporated by reference. Alternatively, formable material <b>34</b> may include, but is not limited to, biomaterials (e.g., PEG), solar cell materials (e.g., N-type, P-type materials), and/or the like.
0018Referring to <figref idref="DRAWINGS">FIGS. 1 and 2</figref>, system <b>10</b> may further comprise energy source <b>38</b> coupled to direct energy <b>40</b> along path <b>42</b>. Imprint head <b>30</b> and stage <b>16</b> may be configured to position template <b>18</b> and substrate <b>12</b> in superimposition with path <b>42</b>. System <b>10</b> may be regulated by processor <b>54</b> in communication with stage <b>16</b>, imprint head <b>30</b>, fluid dispense system <b>32</b>, and/or source <b>38</b>, and may operate on a computer readable program stored in memory <b>56</b>.
0019Either imprint head <b>30</b>, stage <b>16</b>, or both vary a distance between mold <b>20</b> and substrate <b>12</b> to define a desired volume therebetween that is filled by formable material <b>34</b>. For example, imprint head <b>30</b> may apply a force to template <b>18</b> such that mold <b>20</b> contacts formable material <b>34</b>. After the desired volume is filled with formable material <b>34</b>, source <b>38</b> produces energy <b>40</b>, e.g., ultraviolet radiation, causing formable material <b>34</b> to solidify and/or cross-link conforming to a shape of surface <b>44</b> of substrate <b>12</b> and patterning surface <b>22</b>, defining patterned layer <b>46</b> on substrate <b>12</b>. Patterned layer <b>46</b> may comprise a residual layer <b>48</b> and a plurality of features shown as protrusions <b>50</b> and recessions <b>52</b>, with protrusions <b>50</b> having a thickness t<sub>1 </sub>and residual layer having a thickness t<sub>2</sub>.
0020The above-mentioned system and process may be further employed in imprint lithography processes and systems referred to in U.S. Pat. No. 6,932,934, U.S. Pat. No. 7,077,992, U.S. Pat. No. 7,179,396, and U.S. Pat. No. 7,396,475, all of which are hereby incorporated by reference in their entirety.
0021As previously noted, imprint lithography processes can pattern features as small as 100 nm or less, and have further proven capable of patterning high fidelity features approaching sub-20 nanometers (i.e., less than 20 nm). The ability to imprint such sub-20 nm features has important implications in a number of applications. For example, imprint lithography can be applied in the hard disk drive (HDD) industry to pattern the underlying media with the magnetic cells (or bits) allowing for greater areal density than would otherwise be possible. Currently, high capacity HD disks have storage capacities of up to 0.5 Tbsi (1 terabit (1 trillion bits) per square inch), but to achieve patterned media with desired storage densities of 1 Tbsi and greater, the pattern feature size necessarily needs to be at least 18 nm or smaller, and preferably as small as about 10 nm or even as small as about 5 nm. The semiconductor industry likewise has the need for such small feature (sub-20 nm) patterning, including imprinting parallel lines or gratings for use in e.g. NAND flash memory. However, with decrease in the feature size, the imprint feature height also must also necessarily decrease, given the aspect ratio constraints imposed by imprint lithography (i.e., the smallest of features can be reliably imprinted at an aspect of ratio of at most up to about 3:1, and in certain applications, such as many applications with feature sizes that are <20 nm, the aspect ratio may necessarily be as low as 1.5:1). This leads to a severely limiting reduction in the etch process window necessary to perform accurate pattern transfer into the substrate. For example, to pattern a 5 nm width feature, the imprint feature height is typically around 10˜15 nm, up to 5 nm of which is associated with the residual layer. The first step in pattern transfer is residual layer removal. A 10-15 nm overall feature height will typically erode or reduce to 3˜8 nm after a 5 nm residual layer etch process. It is extremely difficult to reliably continue the pattern transfer into the substrate with only 3˜8 nm remaining resist feature height, as such a height is too small to ensure uniform pattern transfer with reasonable process control and yield for commercial applications.
0022Alternative reverse tone patterning imprint methods, such as described e.g. in U.S. Pat. Nos. 7,241,395 and 7,186,656, each of which is incorporated by reference in its entirety, can mitigate the effects of feature erosion at larger feature sizes, e.g., 20 nm and above. Such methods typically employ forming a second conformal layer of silicon-containing polymeric resist (e.g. 20% Si-80% polymer) over a first patterned layer of non-silicon-containing organic polymeric resist. The second silicon containing polymeric resist can be formed e.g. by spin coating or imprinting using a no-feature (i.e., blank) template. A blanket etch is performed to etch back the conformal layer to expose protrusions of the patterned layer. A second plasma etch is used to oxidize the silicon-containing polymeric resist while the first patterned layer of non-silicon-containing polymeric resist is removed. By this process, a reverse (or inverse) pattern is created which can then be transferred into the substrate through further etching. However at very small feature heights, the etch selectivity in such methods is at best 3:1 to 4:1 and inadequate to provide high fidelity pattern transfer at the sub-20 nm feature range. This lower selectivity occurs because the organic material in the silicon-containing resist will continue to erode during the etch process even with 100% silicon oxidation. For example, to reliably achieve patterned media with desired storage densities of 1 Tbsi, etch selectivity ideally should approach 7:1 to 8:1. In addition, with certain resist material combinations an intermixing of the first patterned layer of non-silicon-containing polymeric resist and the second conformal layer of silicon-containing polymeric resist was observed. Such intermixing can lead to feature degradation and a significant loss of feature fidelity.
0023For sub 20 nm pattern transfer, the present invention provides approaches that incorporate particular hard mask materials that increase the selectivity during pattern etch into the substrate. That is, the material selected for use after the imprint process greatly increases etch selectivity during the imprint resist etch process and substrate pattern transfer etch process, as compared to processes using silicon-containing polymeric resist as the hard mask. For example, materials such as Chromium (Cr), Silicon (Si), Al<sub>2</sub>O<sub>3</sub>, and SiO<sub>2 </sub>erode very slowly in plasma chemistries used to etch organics, and can be applied over an imprinted patterned layer at a low enough temperature. The method of deposition imparts a unique morphology to the multi-layer material stacks (i.e., substrate/patterned resist layer/deposited material layer), which in turn determines the etch process window (e.g. requirement for over etch, etc.) and results in significant improvement in etch selectivity. For example, etch selectivity of 50:1 or more between a patterned organic resist layer and metals, metalloids, or non-organic oxides (e.g. Cr, Si, Al<sub>2</sub>O<sub>3 </sub>and SiO<sub>2</sub>) can be achieved, which greatly preserves the pattern feature height during the etch process that transfers the pattern into the substrate, allowing for sub 20 nm pattern transfer at high fidelity. In certain aspects of the invention as further described herein, the metal, metalloid, or non-organic oxide (e.g. Cr, Si, Al<sub>2</sub>O<sub>3 </sub>or SiO<sub>2</sub>) can be deposited according to various techniques, such as gap-fill (e.g., F-CVD), conformal (e.g., atomic layer deposition), small-angle sputter deposition, and various types of CVD processes.
0024<figref idref="DRAWINGS">FIGS. 3A-3G</figref> depict an exemplary method of the invention. <figref idref="DRAWINGS">FIGS. 3A-3C</figref> illustrate patterned layer <b>146</b> formed on substrate <b>12</b>, with patterned layer <b>146</b> containing holes <b>152</b> with surrounding, elevated areas (i.e., protrusions) <b>150</b>. A pillar-tone imprint lithography template (not depicted) is used to form patterned layer <b>146</b> from a polymerizable material deposited on substrate <b>12</b>, according to methods described above with respect to <figref idref="DRAWINGS">FIGS. 1-2</figref>, with the template pillars providing for holes <b>152</b> patterned layer <b>146</b> of corresponding size and shape. Once patterned layer <b>146</b> is formed onto substrate <b>12</b>, the substrate is subjected to further processing as shown in <figref idref="DRAWINGS">FIGS. 3D-3G</figref>.
0025First, patterned layer <b>146</b> is subjected to a descum etch to remove residual layer portion at the bottom of each hole <b>152</b>, such that substrate <b>12</b> is exposed at each of holes <b>152</b>, as depicted in <figref idref="DRAWINGS">FIG. 3D</figref>. Methods for removing residual layer from a patterned layer include, but are not limited to, plasma-based (e.g., oxygen plasma) and vacuum ultraviolet (VUV) etching processes. Such processes are capable of directional (i.e., primarily vertical) etching of the solidified polymerizable material, such that the residual layer is removed with minimal alterations to the lateral dimensions of the holes. The patterned layer is then subjected to a gap-fill deposition process to deposit selected material (e.g. Cr, Si, Al<sub>2</sub>O<sub>3 </sub>or SiO<sub>2</sub>) onto patterned layer <b>146</b> such that it forms deposited layer <b>162</b> over exposed substrate <b>12</b> at the bottom of holes <b>152</b>, as shown in <figref idref="DRAWINGS">FIG. 3E</figref>. Exemplary gap-fill deposition processes include, but are not limited to, low temperature FCVD deposition of SiO<sub>2</sub>.
0026Gap-fill deposition likewise results in some deposition of the selected material on protrusions <b>150</b>, forming deposited layer <b>160</b> over such protrusions. A plasma etch process can be used to remove deposition layer <b>160</b> to expose protrusions <b>150</b> while leaving deposited layer <b>162</b> remaining at the bottom of the holes (as shown in <figref idref="DRAWINGS">FIG. 3F</figref>). Protrusions <b>150</b> are then removed by using an oxygen or fluorocarbon based etch process, leaving deposited layer <b>162</b>, as shown in <figref idref="DRAWINGS">FIG. 3G</figref>. Using deposited layer <b>162</b> as a hard mask pattern, substrate <b>12</b> is then etched to form pillars (not shown) in substrate <b>12</b> corresponding to originally patterned holes <b>152</b>, followed by removal of remaining deposited layer <b>162</b> from the tops of such formed pillars.
0027Another exemplary method of the invention is depicted in <figref idref="DRAWINGS">FIGS. 4A-4E</figref>. As above, patterned layer <b>146</b> having holes <b>152</b> is formed onto substrate <b>12</b> (<figref idref="DRAWINGS">FIG. 4A</figref>) and then is likewise subjected to further processing (<figref idref="DRAWINGS">FIGS. 4B-4E</figref>). First, patterned layer <b>146</b> is subjected to a conformal deposition process to deposit selected material (e.g. Cr, Si, or SiO<sub>2</sub>) onto patterned layer <b>146</b> such that it forms deposited layer <b>260</b> over the entirety of patterned layer <b>146</b>, as shown in <figref idref="DRAWINGS">FIG. 4B</figref>. Exemplary conformal deposition processes include, but are not limited to, low temperature atomic layer deposition of SiO<sub>2 </sub>or Al2O<sub>3</sub>.
0028Following the conformal deposition of layer <b>260</b> onto patterned layer <b>146</b>, an additional planarizing layer <b>262</b> is formed over layer <b>260</b>, as shown in <figref idref="DRAWINGS">FIG. 4C</figref>. Planarizing layer <b>262</b> can be formed using imprint lithography processes, such as described above, or through other techniques known in the art, such as spin-on or dip planarization processes. Planarizing layer <b>262</b> is then etched back to expose deposited layer <b>260</b>, as shown in <figref idref="DRAWINGS">FIG. 4D</figref>. Portions of deposited layer <b>260</b> are then etched back, such that protrusions <b>150</b> are exposed while portions <b>264</b> of deposited layer <b>260</b> remain within holes <b>250</b> of patterned layer <b>146</b>, as shown in <figref idref="DRAWINGS">FIG. 4E</figref>. Protrusions <b>150</b> are then removed, leaving portions <b>264</b> of deposited layer <b>260</b>, which correspond to holes <b>152</b> of patterned layer <b>146</b>, remaining, as shown in <figref idref="DRAWINGS">FIG. 4F</figref>. Portions <b>264</b> function as a hard mask pattern for etching substrate <b>12</b> to form pillars (not shown) in substrate <b>12</b>. This is followed by removal of remaining portions <b>264</b> and patterned layer <b>146</b> from the tops of such formed pillars.
0029Yet a further exemplary method of the invention is depicted in <figref idref="DRAWINGS">FIGS. 5A-5F</figref>. <figref idref="DRAWINGS">FIGS. 5A-C</figref> illustrate patterned layer <b>246</b> formed on substrate <b>12</b>, in this instance with with patterned layer <b>246</b> having pillars <b>250</b> extending from surrounding, recessed area <b>252</b>. A hole-tone imprint lithography template (not depicted) is used to form patterned layer <b>246</b> from a polymerizable material deposited on substrate <b>12</b>, according to methods described above with respect to <figref idref="DRAWINGS">FIGS. 1-2</figref>, with the template holes providing for the formation of pillars <b>250</b> of patterned layer <b>246</b> of corresponding size and shape. Once patterned layer <b>246</b> is formed onto substrate <b>12</b>, the substrate is subjected to further processing as shown in <figref idref="DRAWINGS">FIGS. 5D-5F</figref>. First, patterned layer <b>246</b> is subjected to a small angle deposition of selected material (e.g. Cr, Si, or SiO<sub>2</sub>) onto patterned layer <b>246</b> such that it forms deposited layer <b>360</b> capping protrusions <b>250</b>, as shown in <figref idref="DRAWINGS">FIG. 5D</figref>. In particular, the angle of material deposition is controlled such that the material does not accumulate within recesses <b>252</b>. Exemplary small angle deposition processes include, but are not limited to, small angle sputtering. Patterned layer <b>146</b> is then subjected to a descum etch (e.g., O<sub>2 </sub>RIE) to remove residual layer portion (recessed area portion <b>252</b>), such that substrate <b>12</b> is exposed over the areas surrounding pillars <b>250</b>, as depicted in <figref idref="DRAWINGS">FIG. 5E</figref>. Subsequent etching is then done to etch the pattern of pillars into substrate <b>12</b>.
0030<figref idref="DRAWINGS">FIGS. 6A-6E</figref> depict another exemplary method of the invention. Patterned layer <b>146</b> is formed as above with holes <b>152</b> formed over substrate <b>12</b> (<figref idref="DRAWINGS">FIG. 6A</figref>), as above, followed in this instance by PEVCD deposition of the selected material (e.g. Cr, Si, or SiO<sub>2</sub>) onto patterned layer <b>146</b> such that it forms deposited layer <b>460</b> extending over the entirety of patterned layer <b>146</b> (<figref idref="DRAWINGS">FIG. 6B</figref>). Deposited layer <b>460</b> is thick enough such that it completely fills holes <b>152</b> and extends over raised (elevated) area <b>150</b>. Exemplary PEVCD processes include, but are not limited to, atomic layer deposition and FCVD. Alternately, the deposited layer can be applied by a spin-on process (e.g. SOG). This is followed by etching back deposited layer <b>460</b> to expose holes <b>152</b> such that portions <b>462</b> of deposited layer <b>460</b> remain within holes <b>152</b> of patterned layer <b>146</b>, as shown in <figref idref="DRAWINGS">FIG. 6C</figref>. Protrusions <b>150</b> are then etched by e.g. using oxygen or helium based process in a plasma etcher leaving portions <b>462</b> of deposited layer <b>460</b> remaining, which correspond to holes <b>152</b> of patterned layer <b>146</b>, a is as shown in <figref idref="DRAWINGS">FIG. 6D</figref>. Portions <b>462</b> function as a hard mask pattern for etching substrate <b>12</b> to form pillars (not shown) in substrate <b>12</b> corresponding to originally patterned holes <b>152</b>. This is followed by removal of remaining portions <b>462</b> and patterned layer <b>146</b> from the tops of such formed pillars.
0031In further embodiments, the hard mask can consist of more than two materials that have etchants that can achieve high etch selectivity between them. The dual mask layers process can overcome the pattern transfer issue caused by the film surface roughness as a result of certain film deposition techniques.
0032Further modifications and alternative embodiments of various aspects will be apparent to those skilled in the art in view of this description. Accordingly, this description is to be construed as illustrative only. It is to be understood that the forms shown and described herein are to be taken as examples of embodiments. Elements and materials may be substituted for those illustrated and described herein, parts and processes may be reversed, and certain features may be utilized independently, all as would be apparent to one skilled in the art after having the benefit of this description. Changes may be made in the elements described herein without departing from the spirit and scope as described in the following claims.
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| US20130105438A1 | Cites | United States of America | Search report |
| WO2011021573A1 | Cites | World Intellectual Property Organization (WIPO) | Applicant |
15 members in 7 offices; this record represents the family
Priority claims1
| Document | Office | Kind | Date |
|---|---|---|---|
| 201361921647 | United States of America | P |
Members15
| Document | Office | Kind | |
|---|---|---|---|
| US2015187590A1 | United States of America | A1 | |
| WO2015103232A1 | World Intellectual Property Organization (WIPO) | A1 | |
| TW201531799A | Taiwan Province of China | A | |
| SG11201604539QA | Singapore | A | |
| SG11201604539QA | Singapore | A | |
| KR20160103988A | Republic of Korea | A | |
| KR20160103988A | Republic of Korea | A | |
| CN106030406A | China | A | |
| US9514950B2This record | United States of America | B2 | |
| JP2017504201A | Japan | A | |
| JP6496320B2 | Japan | B2 | |
| TWI662359B | Taiwan Province of China | B | |
| CN106030406B | China | B | |
| KR102243630B1 | Republic of Korea | B1 | |
| KR102243630B1 | Republic of Korea | B1 |
40 transactions on the USPTO file
Allowed after 1 non-final rejection.
- Non-final rejections
- 1
- Final rejections
- 0
- RCEs
- 0
- Appeals
- 0
Over time
Point at a mark for the transactionTransactions
| Event | Code | |
|---|---|---|
| Payment of Maintenance Fee, 8th Year, Large EntityM1552 | M1552 | |
| Payment of Maintenance Fee, 4th Year, Large EntityM1551 | M1551 | |
| Recordation of Patent Grant MailedPGM/ | PGM/ | |
| Patent Issue Date Used in PTA CalculationAllowedPTAC | PTAC | |
| Issue Notification MailedAllowedWPIR | WPIR | |
| Dispatch to FDCD1935 | D1935 | |
| Application Is Considered Ready for IssuePILS | PILS | |
| Issue Fee Payment VerifiedN084 | N084 | |
| Issue Fee Payment ReceivedIFEE | IFEE | |
| Mail Notice of AllowanceAllowedMN/=. | MN/=. | |
| Notice of Allowance Data Verification CompletedAllowedN/=. | N/=. | |
| Reasons for AllowanceEX.R | EX.R | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response after Non-Final ActionA... | A... | |
| Request for Extension of Time - GrantedXT/G | XT/G | |
| Mail Non-Final RejectionNon-final rejectionMCTNF | MCTNF | |
| Non-Final RejectionNon-final rejectionCTNF | CTNF | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Electronic Information Disclosure StatementEIDS. | EIDS. | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Application ready for PDX access by participating foreign officesCCRDY | CCRDY | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| PG-Pub Issue NotificationPG-ISSUE | PG-ISSUE | |
| Electronic Information Disclosure StatementEIDS. | EIDS. | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Application Dispatched from OIPEOIPE | OIPE | |
| Sent to Classification ContractorPGPC | PGPC | |
| FITF set to YES - revise initial settingFTFS | FTFS | |
| Application Is Now CompleteCOMP | COMP | |
| Application Is Now CompleteCOMP | COMP | |
| Filing ReceiptFLRCPT.O | FLRCPT.O | |
| Cleared by L&R (LARS)L128 | L128 | |
| Referred to Level 2 (LARS) by OIPE CSRL198 | L198 | |
| IFW Scan & PACR Auto Security ReviewSCAN | SCAN | |
| Patent Term Adjustment - Ready for ExaminationPTA.RFE | PTA.RFE | |
| Applicants have given acceptable permission for participating foreignAPPERMS | APPERMS | |
| Entity status set to undiscounted (initial default setting or status change)BIG. | BIG. | |
| Initial Exam Team nnIEXX | IEXX |
7 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Maintenance fee paymentMAFP | MAFP | |
| Maintenance fee paymentMAFP | MAFP | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| Information on status: patent grantGrantedPATENTED CASESTCF | STCF | |
| Fee payment procedurePAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP | FEPP | |
| AssignmentAS | AS |
Numbers
- Publication
- 9514950
- Application
- 14585247
Titles
- English
- Methods for uniform imprint pattern transfer of sub-20 nm features
Patent term adjustment
- Applicant delay
- −92 days
- Net adjustment
- 0 days
Classification
- CPC, 17
- H01L21/3086
- G03F7/0002
- H10P50/695
- H01L21/02532
- H10P14/26
- H10P14/3411
- H01L21/02623
- H01L21/283
- H10P14/40
- H01L21/31058
- H01L21/31133
- H10P95/08
- H01L21/31144
- H10P50/287
- H01L21/32051
- H10P14/412
- H10P50/73
- IPC, 9
- H01L21 308
- H01L21 311
- H01L21 02
- H01L21 3205
- H01L21 3105
- H01L21 283
- G03F7 00
- H10P14 40
- H10P14 692