Methods of making a monolithic microwave integrated circuit
Summary by NHIP
High Resistivity Substrate IC Fabrication
The method forms a monolithic microwave integrated circuit using a substrate with bulk resistivity equal to or greater than 100 Ohm-cm. Transistors and capacitors sit on the front face while through-substrate vias connect components to a rear ground plane, and low-resistance interconnections overlay the front surface.
Claim Score by NHIP
Abstract
Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face (63) of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC previously unobtainable.
Term
3.9 yearsleft in the term
Expires 12 August 2030.
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22 claims: 4 independent, 18 dependent
- 1A method for forming a monolithic microwave integrated circuit having an input terminal, an output terminal and a reference terminal, the method comprising:providing a high resistivity initial semiconductor substrate having an initial thickness between a first surface and an initial second surface, and having a bulk resistivity equal to or greater than 100 Ohm-cm;forming at least one transistor in and over the initial semiconductor substrate, wherein the at least one transistor has a control terminal, an output terminal, and a source region proximate the first surface;forming a dielectric layer over the first surface and overlying the source region;forming one or more conductor filled substrate vias extending through the dielectric layer and into the initial semiconductor substrate through the first surface;forming an interlayer via in the dielectric layer;forming electrical interconnections overlying the front surface of the semiconductor substrate to electrically couple the interlayer via with at least some of the multiple conductor filled substrate vias so that at least one of the substrate vias is electrically coupled to the source region of the transistor through the interlayer via and at least one of the electrical interconnections;forming one or more planar capacitors over the first surface of the initial substrate, each capacitor having first and second terminals;forming one or more planar inductors over the first surface of the initial substrate, wherein the first terminal or the second terminal of the one or more planar capacitors is coupled to a first terminal or a second terminal of the one or more planar inductors wherein other terminals of the one or more planar inductors are coupled to the substrate vias, to one or more terminals of the transistor or to one or more terminals of the microwave integrated circuit;reducing the initial thickness, thereby creating a new rear surface of a thinned substrate on which inner ends of the substrate vias are exposed;and applying a conductor to the new rear surface of the thinned substrate so that the exposed inner ends of the substrate vias are electrically connected to the conductor, and so that the source region is electrically connected to the conductor through the interlayer via, at least one of the electrical interconnections, and at least one of the substrate vias.
- 7Broadest claimClaim Score 66, broad(NHIP)A method for forming a monolithic microwave integrated circuit, the method comprising:forming portions of a transistor at a front surface of a semiconductor substrate, wherein the transistor has a doped common region, and wherein the semiconductor substrate has a bulk resistivity equal to or greater than 100 Ohm-cm;forming multiple conductive through-substrate vias (TSVs) extending from the front surface of the semiconductor substrate at least partially through the semiconductor substrate;forming electrical interconnections overlying the front surface of the semiconductor substrate to electrically couple the transistor with at least some of the multiple conductive TSVs;and forming a reference node supported by a rear surface of the semiconductor substrate and electrically coupled with at least some of the multiple conductive TSVs.
- 16A method for forming a monolithic microwave integrated circuit, the method comprising:forming a Laterally-Diffused-Metal-Oxide-Semiconductor (LDMOS) transistor at a front surface of a semiconductor substrate, wherein the LDMOS transistor has a gate, a drain region, and a source region, and wherein the semiconductor substrate has a bulk resistivity equal to or greater than 100 Ohm-cm;forming multiple conductive through-substrate vias (TSVs) extending from the front surface of the semiconductor substrate to a rear surface of the semiconductor substrate;forming electrical interconnections overlying the front surface of the semiconductor substrate to electrically couple the transistor with at least some of the multiple conductive TSVs;and forming a reference node supported by the rear surface of the semiconductor substrate and electrically coupled with at least some of the multiple conductive TSVs.
- 20A method for forming a monolithic microwave integrated circuit, the method comprising:forming a transistor in a semiconductor substrate, wherein the transistor includes a doped common region;forming a first dielectric layer over a front surface of the semiconductor substrate;forming a first through-substrate via (“TSV”) extending through the first dielectric layer and the semiconductor substrate, wherein a region of the semiconductor substrate through which the first TSV passes has a bulk resistivity equal to or greater than 1000 Ohm-cm;forming an interlayer via in the first dielectric layer, the first TSV electrically coupled to the doped common region of the transistor through the interlayer via;monolithically forming a passive component over the front surface of the semiconductor substrate;forming planar interconnections overlying the front surface of the semiconductor substrate and coupling the transistor and the passive component;and forming a reference node supported by the rear surface of the semiconductor substrate, which is electrically coupled to the transistor through the first TSV.
Independent claims4
43 paragraphs in 5 sections, as filed
RELATED APPLICATION
0001This application is a divisional of U.S. patent application Ser. No. 12/855,479, filed on Aug. 12, 2010, now issued as U.S. Pat. No. 9,064,712.
FIELD OF THE INVENTION
0002The present invention generally relates to semiconductor devices and circuits and methods for fabricating semiconductor devices and circuits, and more particularly relates to monolithic integrated circuits adapted to operate at very high frequencies, including microwave frequencies.
BACKGROUND OF THE INVENTION
0003As the electronic arts have progressed there is an ongoing need for solid state circuits adapted to operate at higher and higher frequencies, including microwave frequencies. As used herein, the term “microwave” is intended to refer to frequencies at or above about 800 mega-Hertz. Various transistor structures have been created that are capable of providing gain in such frequency ranges. Passive components, e.g., inductors, and capacitors, must often be combined with such solid state amplifiers in order to achieve the desired circuit functions, for example and not intended to be limiting, power amplifiers, modulators, filters, oscillators, etc. However, as the desired operating frequencies have increased, conventional approaches for monolithically forming such active and passive elements on a common substrate have not proved practical for microwave structures and satisfactory performance has so far necessitated assembling separately produced passive and active elements. Thus, there is an ongoing need for monolithic integrated circuits having both passive and active elements, manufactured at substantially the same time on a common monolithic substrate, that are capable of operating at microwave frequencies.
BRIEF DESCRIPTION OF THE DRAWINGS
0004The present invention will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein:
0005<figref idref="DRAWINGS">FIG. 1</figref> is a simplified electrical schematic diagram of an insulated gate field effect transistor combined with capacitors and inductors to form a microwave amplifier, according to the prior art;
0006<figref idref="DRAWINGS">FIG. 2</figref> is a simplified plan view of a physical amplifier structure embodying the circuit of <figref idref="DRAWINGS">FIG. 1</figref>, according to the prior art;
0007<figref idref="DRAWINGS">FIG. 3</figref> is a simplified electrical schematic diagram of an insulated gate field effect transistor combined with capacitors and inductors to form a microwave amplifier, according to an embodiment of the present invention;
0008<figref idref="DRAWINGS">FIG. 4</figref> is a simplified plan view of a physical amplifier structure embodying the circuit of <figref idref="DRAWINGS">FIG. 3</figref>, according to a further embodiment of the present invention;
0009<figref idref="DRAWINGS">FIG. 5</figref> is a simplified cross-sectional view of a lateral (double) diffused metal-oxide-semiconductor (LDMOS) transistor useful in the amplifier of <figref idref="DRAWINGS">FIGS. 3-4</figref>, according to a still further embodiment of the invention;
0010<figref idref="DRAWINGS">FIG. 6</figref> is a simplified cross-sectional view of a portion of the amplifier structure of <figref idref="DRAWINGS">FIG. 4</figref> illustrating how low loss capacitance is provided therein in a monolithic form, coupled to conductors useful for forming low loss inductances or interconnections as a part of the same monolithic structure, according to a yet further embodiment of the invention;
0011<figref idref="DRAWINGS">FIG. 7</figref> is a simplified cross-sectional view of still another portion of the amplifier structure of <figref idref="DRAWINGS">FIG. 4</figref> illustrating how another low loss capacitance is provided therein in a monolithic form, coupled to conductors useful for forming low loss inductances or interconnections as a part of the same monolithic structure, according to a still yet further embodiment of the invention;
0012<figref idref="DRAWINGS">FIG. 8</figref> shows a simplified flow chart illustrating a method for forming part or all of the structures of <figref idref="DRAWINGS">FIGS. 4-7</figref>, according to yet still further embodiments of the invention; and
0013<figref idref="DRAWINGS">FIGS. 9-11</figref> show a simplified flow chart illustrating a method for forming part or all of the structures of <figref idref="DRAWINGS">FIGS. 4-7</figref>, according to yet additional embodiments of the invention.
DETAILED DESCRIPTION OF THE INVENTION
0014The following detailed description is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or the following detailed description.
0015For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the invention. Additionally, elements in the drawing figures are not necessarily drawn to scale. For example, the dimensions of some of the elements or regions in the figures may be exaggerated relative to other elements or regions to help improve understanding of embodiments of the invention.
0016The terms “first,” “second,” “third,” “fourth” and the like in the description and the claims, if any, may be used for distinguishing between similar elements or steps and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms “comprise,” “include,” “have” and any variations thereof, are intended to cover non-exclusive inclusions, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term “coupled,” as used herein, is defined as directly or indirectly connected in an electrical or non-electrical manner. As used herein the terms “substantial” and “substantially” mean sufficient to accomplish the stated purpose in a practical manner and that minor imperfections, if any, are not significant for the stated purpose.
0017As used herein, the term “semiconductor” and the abbreviation “SC” is intended to include any semiconductor whether single crystal, poly-crystalline or amorphous and to include type IV semiconductors, non-type IV semiconductors, compound semiconductors as well as organic and inorganic semiconductors. Further, the terms “substrate” and “semiconductor substrate” and “SC substrate” are intended to include single crystal structures, polycrystalline structures, amorphous structures, thin film structures, layered structures as for example and not intended to be limiting, semiconductor-on-insulator (SOI) structures, and combinations thereof. For convenience of explanation and not intended to be limiting, semiconductor devices and methods of fabrication are described herein for silicon semiconductors, but persons of skill in the art will understand that other semiconductor materials may also be used. Additionally, various device types and/or doped SC regions may be identified as being of N type or P type, but this is merely for convenience of description and not intended to be limiting, and such identification may be replaced by the more general description of being of a “first conductivity type” or a “second, opposite conductivity type” where the first type may be either N or P type and the second type then is either P or N type.
0018For convenience of explanation and not for limitation, various embodiments of the invention will be illustrated using lateral-(double)-diffused-metal-oxide-semiconductor (LDMOS) active devices, which are preferred. However, many other active device types may also be employed and are intended to be included within the scope of the invention, as for example and not intended to be limiting, bipolar devices, junction field effect devices, various insulated gate field effect devices, HBT, and so forth. As used herein, the term metal-oxide-semiconductor and the abbreviation MOS are to be interpreted broadly. In particular, it should be understood that they are not limited merely to structures that use “metal” and “oxide”, but may employ any type of conductor, including “metal”, and any type of dielectric, including “oxide”. The term “field-effect-transistor” is abbreviated as “FET” and the term “insulated-gate-FET” is abbreviated as “IGFET”.
0019<figref idref="DRAWINGS">FIG. 1</figref> shows simplified electrical schematic circuit <b>20</b> of IGFET <b>21</b> combined with capacitances <b>22</b>, <b>23</b> and inductances <b>24</b>, <b>25</b> to form microwave amplifier <b>26</b> having input terminal <b>27</b>, output terminal <b>28</b> and reference terminal or node <b>29</b>, according to the prior art. For convenience of description, terminal or node <b>29</b> may also referred to as “ground” (abbreviated as “GND”), irrespective of whether or not an earth connection is provided. Input terminal <b>27</b> is coupled to node <b>33</b> by connection <b>35</b>. Capacitance <b>22</b> has first electrode <b>22</b>-<b>1</b> coupled to node <b>33</b> and second electrode <b>22</b>-<b>2</b> coupled to reference terminal or node <b>29</b>. Inductance <b>24</b> is coupled between node <b>33</b> and control (e.g., “gate”) terminal <b>30</b> of transistor <b>21</b>. Common (e.g. “source”) terminal <b>31</b> of transistor <b>21</b> is coupled to reference terminal or node <b>29</b>. Output (e.g., “drain”) terminal <b>32</b> of transistor <b>21</b> is coupled to node <b>34</b> which is in turn coupled to output terminal <b>28</b> of amplifier <b>26</b> via connection <b>36</b> and to a first terminal of inductance <b>25</b> via connection <b>37</b>. A second terminal of inductance <b>25</b> is coupled to first terminal <b>23</b>-<b>1</b> of capacitance <b>23</b> whose second terminal <b>23</b>-<b>2</b> is coupled to reference terminal or node <b>29</b>.
0020<figref idref="DRAWINGS">FIG. 2</figref> shows a simplified plan view of physical amplifier structure <b>38</b> corresponding to circuit <b>26</b> of <figref idref="DRAWINGS">FIG. 1</figref>, according to the prior art. To facilitate correlation between structure <b>38</b> and circuit <b>26</b>, the convention is followed of identifying corresponding elements in structure <b>38</b> with the same reference number used for such elements in <figref idref="DRAWINGS">FIG. 1</figref> with a prime (′) added to distinguish between the physical element and its representation in the electrical schematic of <figref idref="DRAWINGS">FIG. 1</figref>. Prior art amplifier structure <b>38</b> is assembled on conductive (e.g., metal) ground plane <b>29</b>′ on circuit board <b>39</b>. Ground plane <b>29</b>′ corresponds to reference node <b>29</b> of <figref idref="DRAWINGS">FIG. 1</figref>. Amplifier structure <b>38</b> comprises separately formed elements, that is, capacitor <b>22</b>′, amplifying semiconductor device <b>21</b>′, capacitor <b>23</b>′ and various wirebonds that provide inductances <b>24</b>, <b>25</b> and connections <b>35</b>, <b>36</b>, <b>37</b>, etc. Capacitor <b>22</b>′, corresponding to capacitance <b>22</b> of <figref idref="DRAWINGS">FIG. 1</figref>, has its lower electrode <b>22</b>-<b>2</b>′ coupled to ground plane <b>29</b>′ and upper electrode <b>22</b>-<b>1</b>′ available to serve as node <b>33</b>. Semiconductor device <b>21</b>′ (e.g., an LDMOS transistor) corresponds to active device <b>21</b> of <figref idref="DRAWINGS">FIG. 1</figref>. The internal structure of semiconductor device <b>21</b>′ is illustrated only schematically in <figref idref="DRAWINGS">FIG. 2</figref> and can comprise for example, multiple parallel coupled source, drain and gate regions, represented schematically by the multiple rectangular regions shown therein. Capacitor <b>23</b>′ corresponding to capacitance <b>23</b> of <figref idref="DRAWINGS">FIG. 1</figref> has lower electrode <b>23</b>-<b>2</b>′ coupled to ground plane <b>29</b>′ and upper electrode <b>23</b>-<b>1</b>′ available to be coupled to wirebonds <b>25</b>′.
0021Wirebonds <b>35</b>′ correspond to connection <b>35</b> between input terminal <b>27</b>′ and node <b>33</b>′ formed by upper electrode <b>22</b>-<b>1</b>′ of capacitor <b>22</b>′. Wirebonds <b>24</b>′ extend between upper terminal <b>22</b>-<b>1</b>′ of capacitor <b>22</b>′ and input (e.g., “gate”) terminal(s) <b>30</b>′ of LDMOS transistor <b>21</b>′ and provide inductance <b>24</b> of <figref idref="DRAWINGS">FIG. 1</figref>. Wirebonds <b>25</b>′ extend between node <b>34</b>′ coupled to drain terminal(s) <b>32</b>′ of transistor <b>21</b>′ and upper electrode <b>23</b>-<b>1</b>′ of capacitance <b>23</b>′, and provide inductance <b>25</b> of <figref idref="DRAWINGS">FIG. 1</figref>. Wirebonds <b>36</b>′ extend between node <b>34</b>′ coupled to drain terminal(s) <b>32</b>′ of transistor <b>21</b>′ and output terminal or bus <b>28</b>′, and correspond to connection <b>36</b> of <figref idref="DRAWINGS">FIG. 1</figref>. Structure <b>38</b> illustrates a physical embodiment of circuit <b>26</b> of <figref idref="DRAWINGS">FIG. 1</figref>, according to the prior art. While structure <b>38</b> is useful, it is formed from separately produced active and passive components (e.g., transistor <b>21</b>′, capacitors <b>22</b>′, <b>23</b> and wirebond inductors <b>24</b>′, <b>25</b>′) and fails to realize economies of manufacture, improved reliability and performance, etc., that might be expected from an entirely monolithic structure formed using a coherent manufacturing technology.
0022It has been found that the failure of prior art structures and manufacturing technologies to provide monolithic implementations of circuit <b>26</b> of adequate performance at microwave frequencies arises, among other things, because of the degraded quality (“Q”) factors associated with the passive components, e.g., the capacitors, inductors and interconnections when they are formed on a common SC substrate. It has been further found that such degraded Q factors arise, among other things, because of the adverse interaction between monolithic planar inductors formed on such SC substrate surface and the underlying SC substrate in or on which the active device(s) are also formed. This occurs because of the significant penetration of the electro-magnetic (EM) fields of such planar inductors and interconnections into the substrate, and merely adding or thickening dielectric layers between such planar inductors and interconnections and the underlying SC substrate and/or providing electrostatic shielding therebetween does not alleviate the problem. It has also been found that in addition to minimizing parasitic substrate inductive coupling effects, it is also important to minimize resistance of the various leads, inductors, and capacitor and ground connections since they can likewise adversely affect the overall Q and circuit performance. These and other problems associated with the prior art are minimized or avoided by the embodiments described below.
0023<figref idref="DRAWINGS">FIG. 3</figref> shows simplified electrical schematic circuit <b>40</b> of IGFET <b>41</b> combined with capacitances <b>42</b>, <b>43</b> and inductances <b>44</b>, <b>45</b> to form microwave amplifier <b>46</b> having input terminal <b>47</b>, output terminal <b>48</b> and reference terminal or node <b>49</b>, according to an embodiment of the present invention. For convenience of description, terminal or node <b>49</b> may also be referred to as “ground” (abbreviated as “GND”), irrespective of whether or not an earth connection is provided. Input terminal <b>47</b> is coupled to node <b>53</b> by connection <b>55</b>. Capacitance <b>42</b> has first electrode <b>42</b>-<b>1</b> coupled to node <b>53</b> and second electrode <b>42</b>-<b>2</b> coupled to reference terminal or node <b>49</b>. Inductance <b>44</b> is coupled between node <b>53</b> and control (e.g., “gate”) terminal <b>50</b> of transistor <b>41</b>. Common (e.g. “source”) terminal <b>51</b> of transistor <b>41</b> is coupled to reference terminal or node <b>49</b>. Output (e.g. “drain”) terminal <b>52</b> of transistor <b>41</b> is coupled to node <b>54</b> which is in turn coupled to first terminal <b>43</b>-<b>1</b> of capacitance <b>43</b> and also to output terminal <b>48</b> of amplifier <b>46</b> via connection <b>56</b>. Second terminal <b>43</b>-<b>2</b> of capacitance <b>43</b> is coupled to a first terminal of inductance <b>45</b> via connection <b>57</b>. A second terminal of inductance <b>45</b> is coupled to reference terminal or node <b>49</b>.
0024<figref idref="DRAWINGS">FIG. 4</figref> is a simplified plan view of physical amplifier structure <b>58</b> embodying circuit <b>46</b> of <figref idref="DRAWINGS">FIG. 3</figref>, according to a further embodiment of the present invention. To facilitate correlation between structure <b>58</b> and circuit <b>46</b>, the convention is followed of identifying corresponding elements in structure <b>58</b> with the same reference number as used for such elements in <figref idref="DRAWINGS">FIG. 3</figref> with a prime (′) added to distinguish between the physical element and its representation in the electrical schematic of <figref idref="DRAWINGS">FIG. 3</figref>. Structure <b>58</b> of <figref idref="DRAWINGS">FIG. 4</figref> illustrates by way of example, monolithic substrate <b>60</b> in or on which are formed: (i) exemplary LDMOS transistor <b>41</b>′ having multiple (e.g., 16) parallel segments, (ii) multiple (e.g., 8) capacitors <b>42</b>′, (iii) multiple (e.g., 3) capacitors <b>43</b>′, (iv) multiple (e.g., 8) inductors <b>44</b>′, and (v) multiple (e.g., 3) inductors <b>45</b>′, all formed on monolithic substrate <b>60</b> prior to being assembled on circuit board or heat sink <b>59</b>. Transistor <b>41</b>′, capacitors <b>42</b>′, <b>43</b>′, and inductors <b>44</b>′, <b>45</b>′ of <figref idref="DRAWINGS">FIG. 4</figref> correspond, respectively, to transistor <b>41</b>, capacitances <b>42</b>, <b>43</b> and inductances <b>44</b>, <b>45</b> of <figref idref="DRAWINGS">FIG. 3</figref>. The combinations of (e.g., 8) capacitors <b>42</b>′ and inductors <b>44</b>′, are arranged substantially in parallel at the input of transistor <b>41</b>′. The combinations of (e.g., 3) capacitors <b>43</b>′ and inductors <b>45</b>′, are arranged substantially in parallel at the output of transistor <b>41</b>′. It will be understood by those of skill in the art, that the number of substantially parallel coupled segments of transistor <b>41</b>′ and/or the number of substantially parallel coupled capacitor-inductor combinations <b>42</b>′, <b>44</b>′, and/or <b>43</b>′, <b>45</b>′ may be varied to achieve different power handling capacities or circuit performance or manufacturing convenience or other reasons, and that the particular representations illustrated here is merely by way of example and not intended to be limiting.
0025Amplifying structure <b>58</b> of <figref idref="DRAWINGS">FIG. 4</figref> differs from amplifying structure <b>38</b> of <figref idref="DRAWINGS">FIG. 2</figref> by, among other things, having its passive and active elements formed on common SC substrate <b>60</b> manufactured using, for example, substantially planar integrated circuit processing technology. It will be understood by those of skill in the art that various insulating layers may be provided between such passive elements and underlying SC substrate <b>60</b> and reference to various elements being “on substrate <b>60</b>” or “on the SC substrate” or equivalent includes having such insulating layers between such elements and underlying SC substrate <b>60</b>. Completed substrate <b>60</b> of <figref idref="DRAWINGS">FIG. 4</figref> is installed as a unit on underlying circuit board or heat sink <b>59</b>, rather than having its passive and active elements produced separately and later assembled and electrically coupled on circuit board <b>39</b> as in <figref idref="DRAWINGS">FIG. 2</figref>. Amplifying structure <b>58</b> of <figref idref="DRAWINGS">FIG. 4</figref> comprises monolithic substrate <b>60</b> in which the desired active (e.g., transistor <b>41</b>′) and passive elements (e.g., capacitors <b>42</b>′, <b>43</b>′ and inductors <b>44</b>′, <b>45</b>′) are already included. It will be understood by those of skill in the art that the active device(s) (e.g., transistor <b>41</b>′) may be formed on or over substrate <b>60</b> or entirely within substrate <b>60</b> or partly within and partly on or over substrate <b>60</b>, depending upon the nature of the device(s). Accordingly, as used herein with respect to the active device(s), the terms “in substrate <b>60</b>”, “in the SC substrate” and equivalents are intended to include all such variations. It has been found, among other things, that when the bulk resistivity of SC substrate <b>60</b> is equal or greater than a predetermined level, that the parasitic inductor-substrate coupling can be substantially reduced and the inductor Q increased enough that satisfactory circuit performance can be obtained, even though the inductors are in the form of planar coils supported by the SC substrate. The desirable predetermined level is usefully equal or greater then about 100 Ohm-cm resistivity, conveniently equal or greater than about 500 Ohm-cm resistivity, more conveniently equal or greater than about 1000 Ohm-cm resistivity and preferably of float zone material of about 1000 Ohm-cm or greater resistivity. As used herein, the term “bulk resistivity” refers to those portions of substrate <b>60</b> that lie outside the device regions, e.g., outside transistor <b>41</b>′ and its associated doped regions. This is a result not taught in the prior art.
0026Monolithic substrate <b>60</b> containing, for example, transistor <b>41</b>′, planar capacitors, <b>42</b>′, <b>43</b>′ and planar inductors <b>44</b>′, <b>45</b>′ is mounted as a unit on underlying circuit board or heat sink <b>59</b>, and the appropriate nodes thereon electrically coupled (e.g., via wirebonds <b>55</b>′) to input bus <b>47</b>′ corresponding to input terminal <b>47</b> of <figref idref="DRAWINGS">FIG. 3</figref> and coupled (e.g., via wirebonds <b>56</b>′) to output bus <b>48</b>′ corresponding to output terminal <b>48</b> of <figref idref="DRAWINGS">FIG. 3</figref>. As will be subsequently explained in more detail in connection with <figref idref="DRAWINGS">FIGS. 5-7</figref>, reference or ground plane <b>49</b>′ corresponding to reference or ground node <b>49</b> of <figref idref="DRAWINGS">FIG. 3</figref> underlies a portion or all of substrate <b>60</b>. Numerous through-substrate-via (TSV) connections (e.g., <b>49</b>-<b>1</b>′, <b>49</b>-<b>2</b>′, <b>49</b>-<b>3</b>′, etc.) are desirably provided in substrate <b>60</b> leading to reference or ground plane <b>49</b>′ to minimize series resistance, reduce losses and enhance overall circuit performance. Exemplary details of such TSV connections are illustrated in <figref idref="DRAWINGS">FIGS. 5-6</figref>. It will also be understood that transistor structure <b>41</b>′ illustrated only schematically in <figref idref="DRAWINGS">FIG. 4</figref>, can comprise many parallel segments. For example, 16 such segments are shown in <figref idref="DRAWINGS">FIG. 4</figref>. In the case of exemplary LDMOS transistor <b>41</b>′ these segments include multiple source regions <b>51</b>′ parallel coupled to reference electrode <b>49</b>′, drain regions <b>52</b>′ parallel coupled to drain bus <b>52</b>-<b>1</b>′, and intervening gate fingers <b>50</b>′ parallel coupled to gate bus <b>50</b>-<b>1</b>′. As is illustrated in more detail in <figref idref="DRAWINGS">FIG. 5</figref>, common (e.g., source) regions <b>51</b>′ of transistor <b>41</b>′ are coupled at multiple locations to ground plane or reference electrode <b>49</b>′ underlying substrate <b>60</b> using various TSVs, indicated symbolically by TSVs <b>49</b>-<b>2</b>′ in <figref idref="DRAWINGS">FIG. 4</figref>.
0027Wirebonds <b>55</b>′ extending from input bus <b>47</b>′ (corresponding to input terminal <b>47</b> of <figref idref="DRAWINGS">FIG. 3</figref>) to bonding pads (e.g., node) <b>53</b>′ correspond to connection <b>55</b> to node <b>53</b> of <figref idref="DRAWINGS">FIG. 3</figref>. Upper terminal <b>42</b>-<b>1</b>′ of (e.g., planar) capacitor <b>42</b>′ is coupled to node <b>53</b>′ and lower terminal <b>42</b>-<b>2</b>′ of capacitor <b>42</b>′ is coupled via TSV <b>49</b>-<b>1</b>′ to ground plane <b>49</b>′ underlying substrate <b>60</b>. Inductor (e.g., planar coil) <b>44</b>′ corresponding to inductance <b>44</b> of <figref idref="DRAWINGS">FIG. 3</figref> has one terminal coupled to node <b>53</b>′ and a second terminal coupled to gate bus <b>50</b>-<b>1</b>′ which ties together multiple gates <b>50</b>′ of exemplary LDMOS transistor <b>41</b>′.
0028Planar capacitor <b>43</b>′ corresponding to capacitance <b>43</b> of <figref idref="DRAWINGS">FIG. 3</figref> has, for example, upper electrode <b>43</b>-<b>1</b>′ coupled to drain bus <b>52</b>-<b>1</b>′ and lower electrode <b>43</b>-<b>2</b>′ coupled to a first lead of planar inductor <b>45</b>′ corresponding to inductance <b>45</b> of <figref idref="DRAWINGS">FIG. 3</figref>, or vice-versa. A second lead of planar inductor <b>45</b>′ is coupled via TSV <b>49</b>-<b>3</b>′ to ground plane <b>49</b>′ underlying all or a portion of substrate <b>60</b>. Drain bus <b>52</b>-<b>1</b>′ is also coupled to bonding pad <b>54</b>′ corresponding, for example, to node <b>54</b> of <figref idref="DRAWINGS">FIG. 3</figref>. Wirebonds <b>56</b>′ corresponding to connection <b>56</b> of <figref idref="DRAWINGS">FIG. 3</figref> couple bonding pad <b>54</b>′ to output bus <b>48</b>′ corresponding to output terminal <b>48</b> of <figref idref="DRAWINGS">FIG. 3</figref>. In the arrangement illustrated in <figref idref="DRAWINGS">FIGS. 3-4</figref>: (i) capacitance <b>43</b> (capacitor <b>43</b>′) and inductance <b>45</b> (inductor <b>45</b>′) are serially coupled, (ii) capacitance electrode <b>43</b>-<b>1</b> (capacitor electrode <b>43</b>-<b>1</b>′) is connected to node <b>54</b>, <b>54</b>′, and (iii) a lead of inductance <b>45</b> (inductor <b>45</b>′) is connected to reference node <b>49</b> (ground plane <b>49</b>′). However, in other embodiments, the order of these elements may be reversed, so that while capacitance <b>43</b> (capacitor <b>43</b>′) and inductance <b>45</b> (inductor <b>45</b>′) are still serially coupled, a lead of inductance <b>45</b> (inductor <b>45</b>′) is connected to node <b>54</b>, <b>54</b>′ and a lead of capacitance <b>43</b> (capacitor <b>43</b>′) is connected to reference node <b>49</b> (ground plane <b>49</b>′). Either arrangement is useful.
0029Among other things, amplifying structure <b>58</b> of <figref idref="DRAWINGS">FIG. 4</figref> has the advantage that the various passive and active devices are provided in monolithic (e.g., planar) form and can be assembled onto circuit board or heat sink <b>59</b> as part of monolithic unit <b>60</b> rather than being manufactured and interconnected separately. This leads to several beneficial results. First: the number of wire-bonds and similar connections needed to implement circuit <b>46</b> is much smaller with the arrangement of <figref idref="DRAWINGS">FIG. 4</figref> versus the arrangement of circuit <b>26</b> of <figref idref="DRAWINGS">FIG. 2</figref>. It is well known in the art that overall reliability improves as the number of separately provided interconnections is reduced. Second: the ability to use substantially planar integrated circuit processing technology to manufacture both passive and active elements on a common substrate means that assembly of the individual passive and active elements can be avoided. This is well known to lead to reduced manufacturing cost and improved overall performance. Thus, the arrangement illustrated in <figref idref="DRAWINGS">FIGS. 3-4</figref> makes it possible to utilize such technologies and overcomes the limitations of the prior art relying on individually manufactured and assembled elements.
0030<figref idref="DRAWINGS">FIG. 5</figref> shows simplified cross-section <b>66</b> though portion <b>67</b> of lateral (double) diffused metal-oxide-semiconductor (LDMOS) transistor <b>41</b>′ useful in the amplifier structure of <figref idref="DRAWINGS">FIGS. 3-4</figref>, according to a still further embodiment of the invention. In a preferred embodiment, portion <b>67</b> is substantially laterally symmetrical around centerline <b>68</b> of portion <b>67</b>, but in other embodiments a non-symmetric structure may also be used. Dashed lines <b>67</b>-<b>1</b> indicate where portion <b>67</b> mates with substantially identical portions on either side thereof to form multi-segment LDMOS transistor <b>41</b>′. <figref idref="DRAWINGS">FIG. 5</figref> depicts initial substrate <b>60</b>-<i>i </i>having initial thickness <b>61</b>-<i>i </i>and initial lower surface <b>62</b>-<i>i </i>(shown dashed) prior to a substrate thinning operation (discussed later) and also shows subsequent substrate <b>60</b> of thickness <b>61</b> and with lower surface <b>62</b> after such thinning operation in which portion <b>61</b>-<b>1</b> of initial substrate <b>61</b>-<i>i </i>has been removed. Portion <b>67</b> comprises (e.g., P type) high resistivity SC substrate <b>60</b>-<i>i</i>, <b>60</b> having a resistivity usefully equal or greater than about 100 Ohm-cm resistivity, conveniently equal or greater than about 500 Ohm-cm resistivity, more conveniently equal or greater than about 1000 Ohm-cm resistivity, and preferably of float zone material of at least about 1000 Ohm-cm resistivity. Finished thickness <b>61</b> of substrate <b>60</b> is usefully in the range of about 10 to 1000 micrometers, conveniently in the range of about 25 to 500 micrometers, and desirably in the range of about 50 to 150 micrometers with about 75 micrometers being preferred, but thicker and thinner substrates may also be used. Lower surface <b>62</b> of substrate <b>60</b> is desirably provided with conductor <b>69</b> of, for example, gold (Au), corresponding to reference node <b>49</b> of <figref idref="DRAWINGS">FIG. 3</figref> and ground plane <b>49</b>′ of <figref idref="DRAWINGS">FIG. 4</figref>. Other relatively conductive materials besides Au may also be used for conductor <b>69</b>, depending upon the die attach method chosen for assembly of substrate <b>60</b> to circuit board or heat sink <b>59</b>. Attachment to a heat sink is preferred. Conductor <b>69</b> may underlie all or part of substrate <b>60</b>. Overlying upper surface <b>63</b> of substrate <b>60</b> are several dielectric and conductor layers and regions, as for example, “first” dielectric layer <b>81</b> overlain in part by “first metal” layer <b>91</b>, “second” dielectric layer <b>82</b> overlain in part by “second metal” layer <b>92</b>, “third” dielectric layer <b>83</b> overlain in part by “third metal” layer <b>93</b> and “fourth” dielectric layer <b>84</b> overlain in part by “fourth metal” layer <b>94</b>. As used herein the term “metal” is intended to include any type of relatively electrically conductive material (e.g., layered conductor structures, metal-SC compounds, semi-metals, etc.) and not be limited merely to simple metals. The structure presented in <figref idref="DRAWINGS">FIG. 5</figref> is intended by way of example and not limitation and depending upon the particular circuit being implemented, more or fewer dielectric-metal layer combinations may be provided.
0031In a symmetric structure, drain region <b>70</b> (e.g., N+) is preferably provided around centerline <b>68</b> adjacent surface <b>63</b> substantially centrally located in portion <b>67</b>, but other locations and non-symmetric arrangements may also be used. Drain region <b>70</b> has doping concentration usefully at least about 5E19 cm<sup>−3</sup>, conveniently at least about 1E20 cm<sup>−3 </sup>and preferably at least about 3E20 cm<sup>−3</sup>, but higher or lower doping concentrations may also be used. Laterally abutting drain region <b>70</b> in a symmetric structure are (e.g., high-voltage-N type (HVN)) carrier drift regions <b>71</b>. Carrier drift regions <b>71</b> have doping concentration usefully in the range of about 1E16 cm<sup>−3 </sup>to 1E18 cm<sup>−3</sup>, conveniently in the range of about 7E16 cm<sup>−3 </sup>to 3E17 cm<sup>−3</sup>, and preferably in the range of about 1E17 cm<sup>−3 </sup>to 2E17 cm<sup>−3</sup>, but higher or lower doping concentrations may also be used. Laterally outboard of drift regions <b>71</b> are (e.g., P type-high-voltage (PHV)) channel regions <b>72</b> underlying at lest a portion of gate dielectric <b>73</b> and conductive gate <b>74</b>. Channel regions <b>72</b> have doping concentration usefully in the range of about 1E17 cm<sup>−3 </sup>to 2E18 cm<sup>−3</sup>, conveniently in the range of about 3E17 cm<sup>−3 </sup>to 1E18 cm<sup>−3</sup>, and preferably in the range of about 5E17 cm<sup>−3 </sup>to 9E17 cm<sup>−3</sup>, but higher or lower doping concentrations may also be used. Laterally outboard of channel regions <b>72</b> are (e.g., N+) source regions <b>76</b>. Source regions <b>76</b> have doping concentration usefully at least about 5E19 cm<sup>−3</sup>, conveniently at least about 1E20 cm<sup>−3 </sup>and preferably at least about 3E20 cm<sup>−3</sup>, but higher or lower doping concentrations may also be used. Laterally outboard of source regions <b>76</b> are (e.g., P type) body contact regions <b>77</b>. Body contact regions <b>77</b> have doping concentration usefully in the range of about 1E18 cm<sup>−3 </sup>to 1E20 cm<sup>−3</sup>, conveniently in the range of about 2E18 cm<sup>−3 </sup>to 7E19 cm<sup>−3</sup>, and preferably in the range of about 5E18 cm<sup>−3 </sup>to 5E19 cm<sup>−3</sup>, but higher or lower doping concentrations may also be used. When gate <b>74</b> is appropriately bias, conductive channel <b>75</b> forms between source region <b>76</b> and drain region <b>70</b>. The exemplary conductivity types presented above are suitable for forming an N-channel structure, but persons of skill in the art will understand that a P-channel structure can also be formed by appropriate interchange of conductivity type of the various doped regions and appropriate modification of the bias on gate <b>74</b>. The thickness of gate dielectric <b>73</b> will depend upon the desired operating voltage, but thicknesses in the range of about 10 to 1000 nanometers are useful, about 100 to 500 nanometers are convenient and about 150 to 400 nano-meters are preferred. WSi is useful for gate conductor <b>74</b>, but other conductive materials may also be used. Persons of skill in the art will understand that gate conductors <b>74</b> are coupled to gate contacts <b>50</b> (see <figref idref="DRAWINGS">FIG. 4</figref>) and gate bus <b>50</b>-<b>1</b> in planes before and/or behind the plane of <figref idref="DRAWINGS">FIG. 5</figref>.
0032Overlying and making Ohmic contact to drain region <b>70</b> is conductor <b>78</b>, for example of cobalt-silicide, but other conductive materials may also be used. Overlying and making Ohmic contact to drain contact region <b>78</b> is interlayer conductive via <b>90</b>-<b>1</b> extending through first dielectric layer <b>81</b> so as to electrically couple drain contact region to portion <b>91</b>-<b>1</b> of first metal <b>91</b>. Overlying and making Ohmic contact to portion <b>91</b>-<b>1</b> of first metal <b>91</b> is interlayer conductive via <b>90</b>-<b>2</b> extending through second dielectric layer <b>82</b> so as to electrically couple portion <b>91</b>-<b>1</b> of first metal <b>91</b> to portion <b>92</b>-<b>1</b> of second metal <b>92</b>. Overlying and making Ohmic contact to portion <b>92</b>-<b>1</b> of second metal <b>92</b> is interlayer conductive via <b>90</b>-<b>3</b> extending through third dielectric layer <b>83</b> so as to electrically couple portion <b>92</b>-<b>1</b> of second metal <b>92</b> to portion <b>93</b>-<b>1</b> of third metal <b>93</b>. Opening <b>84</b>-<b>1</b> is provided in fourth dielectric layer <b>84</b> so as to permit fourth metal <b>94</b> to make Ohmic contact to portion <b>93</b>-<b>1</b> of third metal <b>93</b>. While the multi-layer dielectric-metal arrangement illustrated in <figref idref="DRAWINGS">FIG. 5</figref> is preferred, any means for providing relatively low resistance connection between drain contact <b>78</b> and overlying metal conductor <b>94</b> may be used. Metal layers <b>91</b>, <b>92</b>, <b>93</b>, are conveniently of an aluminum-copper (Al—Cu) alloy, for example and not intended to be limiting, of ˜99.5% Al and ˜0.5% Cu, and with thickness usefully of about 0.1 to 10 micrometers, conveniently in the range of about 0.3 to 3 micrometers and preferably in the range of about 0.5 to 0.7 micrometers, but thinner or thicker layers and other conductive materials may also be used.
0033Overlying and making Ohmic contact to source regions <b>76</b> and body contact regions <b>77</b> are conductors <b>79</b>, for example of cobalt-silicide, but other conductive materials may also be used. Interlayer conductive vias <b>90</b>-<b>4</b> are provided extending through dielectric layer <b>81</b> so as to Ohmically couple source-body contacts <b>79</b> to portions <b>91</b>-<b>2</b> of first metal layer <b>91</b>, which are in turn Ohmically coupled to through-substrate-vias (TSVs) <b>98</b> extending through substrate <b>60</b> to provide comparatively low electrical resistance contact to ground plane layer <b>69</b> underlying substrate <b>60</b>. Tungsten (W) is a suitable material for the conductor of TSVs <b>98</b>. In other embodiments, dielectric liner <b>981</b> provided in TSVs <b>98</b> between the central conductor (e.g., tungsten (W)) and the surrounding SC (e.g., silicon (Si)) may be omitted. Either arrangement is useful. As noted above, “metal” layers <b>91</b>, <b>92</b>, <b>93</b> are conveniently of aluminum-copper (Al—Cu) alloy, but other relatively electrically conductive materials may also be used. Interlayer vias <b>90</b>-<b>1</b>, <b>90</b>-<b>2</b>, <b>90</b>-<b>3</b>, <b>90</b>-<b>4</b> are conveniently also of tungsten (W) but other conductive materials may also be used. Dielectric layers <b>81</b>, <b>82</b>, <b>83</b>, <b>84</b> are conveniently of silicon oxide or silicon nitride or combinations thereof, but other relatively low leakage dielectric material may also be used. Dielectric layers <b>81</b>, <b>82</b>, <b>83</b>, <b>84</b> are usefully of thickness in the range of about 0.1 to 10 micrometers, conveniently in the range of about 0.5- to 5 micrometers and preferably in the range of about 1 to 1.5 micrometers, but thinner or thicker layers may also be used. Conductor <b>94</b> coupled to drain contact <b>78</b> is desirably of copper (Cu), gold (Au), silver (Ag) or combinations thereof, or other high conductivity metal or alloy, with ˜99% pure Cu preferred. Conductor <b>94</b> is conveniently also used to form, for example, inductors <b>45</b>′ of <figref idref="DRAWINGS">FIG. 4</figref> and other top surface interconnections, especially those carrying drain current. For that reason it is desirably that its resistance is low. Accordingly, in a preferred embodiment, thickness is usefully at least about 1 micrometer, conveniently at least about 3 micrometers, more conveniently at least about 6 micrometers and preferably at least about 9 micrometers. Stated another way, it is generally desirable that thickness <b>95</b> of conductor <b>94</b> (and conductors <b>94</b>′, <b>94</b>″ discussed subsequently) be 5 to 10 times the thickness of first, second or third metal layers <b>91</b>-<b>93</b>, but other thicknesses may also be used. Width <b>96</b> of conductor <b>94</b> is desirably chosen to minimize the resistance of conductor <b>94</b> taking into account the available surface area on substrate <b>60</b> for forming, for example, inductors <b>45</b>′ and other (e.g., drain current) interconnections, for example, those leading to bonding pads <b>54</b>′ (see <figref idref="DRAWINGS">FIG. 4</figref>).
0034<figref idref="DRAWINGS">FIG. 6</figref> shows simplified cross-sectional view <b>66</b>′ of portion <b>67</b>′ of amplifier structure <b>58</b> of <figref idref="DRAWINGS">FIG. 4</figref> illustrating how low loss capacitance is provided therein on SC substrate <b>60</b> in a monolithic form, coupled to conductors useful for forming low loss inductances and interconnections on the same monolithic substrate <b>60</b>, according to a yet further embodiment of the invention. Portion <b>67</b>′ depicts the same substrate <b>60</b> as illustrated in <figref idref="DRAWINGS">FIG. 5</figref> but at a different location from transistor <b>41</b>′, for example where capacitances <b>42</b>′ or <b>43</b>′ of <figref idref="DRAWINGS">FIG. 4</figref> are intended to be provided. For convenience of explanation, the cross-sectional structure of capacitor <b>42</b>′ having one electrode coupled to ground plane <b>69</b> (i.e., reference node <b>49</b>, <b>49</b>′ of <figref idref="DRAWINGS">FIGS. 3-4</figref>) is depicted by way of example and not limitation. The same reference numbers are used in <figref idref="DRAWINGS">FIG. 6</figref> as in <figref idref="DRAWINGS">FIG. 5</figref> with the addition of a prime (′) or double-prime (″) followed by “−n”, where n is a number different than used in <figref idref="DRAWINGS">FIG. 5</figref>. This is intended to indicate for example, that the illustrated elements can be formed in the same layers and at the same time as the corresponding elements in <figref idref="DRAWINGS">FIG. 5</figref>, but may be located in different lateral positions and establish different interconnections. Accordingly, the discussion of <figref idref="DRAWINGS">FIG. 5</figref> with respect to the composition and thickness of the various conductor and dielectric layers or regions is incorporated herein by reference.
0035In exemplary structure <b>67</b>′ of <figref idref="DRAWINGS">FIG. 6</figref>, capacitor <b>42</b>′ is formed using portion <b>92</b>-<b>3</b> of “second metal” layer <b>92</b> as lower electrode <b>42</b>-<b>2</b>′ of capacitor <b>42</b>′. Dielectric layer <b>100</b> is provided on conductor portion <b>92</b>-<b>3</b> and upper electrode <b>102</b> corresponding to upper electrode <b>42</b>-<b>1</b>′ of <figref idref="DRAWINGS">FIG. 4</figref> is provided overlying dielectric layer <b>100</b>. Silicon oxide and/or silicon nitride and/or combinations thereof are non-limiting examples of suitable materials for dielectric layer <b>100</b>, but other insulating materials may also be used. Thickness <b>101</b> of dielectric layer <b>100</b> will depend upon the desired capacitance and the voltage required to be sustained by capacitor <b>42</b>′. In many applications, thickness <b>101</b> is usefully in the range of about 0.01 to 1 micrometers, conveniently in the range of about 0.1- to 0.5 micrometers and preferably in the range of about 0.15 to 0.25 micrometers, but thinner or thicker layers may also be used. Upper electrode <b>102</b> is conveniently of TiN and has thickness usefully in the range of about 0.01 to 1 micrometers, conveniently in the range of about 0.1 to 0.5 micrometers and preferably in the range of about 0.15 to 0.25 micrometers, but thinner or thicker layers and other conductors may also be used. Interlayer conductive vias <b>90</b>-<b>2</b> are provided to couple lower electrode <b>42</b>-<b>2</b>′ provided by portion <b>92</b>-<b>3</b> of “second metal” <b>92</b> to portion <b>91</b>-<b>3</b> of “first metal” <b>91</b>, which is coupled to TSVs <b>98</b>′ which are in turn coupled to ground plane or other reference potential conductor <b>69</b> on rear surface <b>62</b> of monolithic SC substrate <b>60</b>. In other embodiments, dielectric liner <b>981</b>′ where TSVs <b>98</b>′ pass through substrate <b>60</b> may be omitted. Either arrangement is useful. Interlayer conductive vias <b>90</b>-<b>3</b> couple upper electrode <b>42</b>-<b>1</b>′ of capacitor <b>42</b> provided by conductor <b>102</b> to portion <b>93</b>-<b>3</b> of “third metal” layer <b>93</b>. Opening <b>84</b>-<b>2</b> is provided in fourth dielectric layer <b>84</b> so that low resistance conductor <b>94</b>′ of thickness <b>95</b>′ and width <b>96</b>′ analogous to conductor <b>94</b> of thickness <b>95</b> and width <b>96</b> of <figref idref="DRAWINGS">FIG. 5</figref> may be provided to couple capacitor <b>42</b>′, for example, to inductor <b>44</b>′ and/or node <b>53</b>′ of <figref idref="DRAWINGS">FIG. 4</figref>. The above-described arrangement allows high quality (e.g., high Q) capacitances to be provided in planar form by minimizing resistive losses associated therewith and the connections thereto.
0036While <figref idref="DRAWINGS">FIG. 6</figref> illustrates capacitor <b>42</b>′ having one electrode coupled to reference potential through low resistance TSVs and another electrode coupled to a non-grounded node, persons of skill in the art will understand that by omitting interlayer conductive vias <b>90</b>-<b>2</b> coupling portion <b>92</b>-<b>3</b> to portion <b>91</b>-<b>3</b> tied to TSVs <b>98</b>′, that capacitor <b>43</b>′ of <figref idref="DRAWINGS">FIG. 4</figref> having both electrodes coupled to non-grounded nodes may be provided. Such an arrangement is illustrated in <figref idref="DRAWINGS">FIG. 7</figref>, showing cross-section <b>66</b>″ of portion <b>67</b>″ wherein capacitor <b>43</b>′ is illustrated. Capacitor <b>43</b> has lower electrode (e.g., <b>43</b>-<b>2</b>′ of <figref idref="DRAWINGS">FIG. 4</figref>) formed by portion <b>92</b>-<b>4</b> of “second metal” <b>92</b>, dielectric <b>103</b> thereon (of thickness similar to that of dielectric <b>100</b> of <figref idref="DRAWINGS">FIG. 6</figref>) and upper electrode (e.g. <b>43</b>-<b>1</b>′ of <figref idref="DRAWINGS">FIG. 4</figref>) <b>104</b> coupled by interlayer vias <b>90</b>-<b>31</b> to portion <b>93</b>-<b>4</b> of “third metal” <b>93</b>, which is in turn coupled to heavier lead <b>94</b>″-<b>1</b> (analogous to lead <b>94</b>, <b>94</b>′ previously described) via opening <b>84</b>-<b>3</b> in dielectric layer <b>84</b>. However, rather than being coupled to TSVs <b>98</b>′ as in <figref idref="DRAWINGS">FIG. 6</figref>, portion <b>92</b>-<b>4</b> of “second metal” layer <b>92</b> is coupled through interlayer vias <b>90</b>-<b>32</b> to portion <b>93</b>-<b>5</b> of “third metal” layer <b>93</b> and heavier lead <b>94</b>″-<b>2</b> via opening <b>84</b>-<b>4</b> in dielectric layer <b>84</b>. As indicated by break <b>106</b>, heavier lead <b>94</b>″-<b>2</b> may be at any distance from and at any orientation with respect to lead <b>94</b>″-<b>1</b>. Thus, the arrangement of <figref idref="DRAWINGS">FIG. 7</figref> may be used to implement, for example, capacitor <b>43</b>″ that is series coupled between drain bus <b>52</b>-<b>1</b>′ and planar inductor <b>45</b>′ in <figref idref="DRAWINGS">FIG. 4</figref>, lead <b>94</b>″-<b>2</b> for example, going to drain bus <b>52</b>-<b>1</b>′ and lead <b>94</b>″-<b>1</b> going to planar inductor <b>45</b>′ or vice versa depending upon the preference of the designer. <figref idref="DRAWINGS">FIG. 7</figref> also illustrates a further embodiment in which portion <b>91</b>-<b>4</b> of “first metal” layer <b>91</b> is provided underlying and coupled by interlayer conductive vias <b>90</b>-<b>2</b> to portion <b>92</b>-<b>4</b> of “second metal” layer <b>92</b>, so that it is electrically in parallel with portion <b>92</b>-<b>4</b>, thereby reducing the resistance between capacitor <b>43</b>″ and lead <b>94</b>″-<b>2</b>. This reduces parasitic resistance and facilitates providing a high Q value for capacitor <b>43</b>″ and for inductor <b>45</b>′.
0037<figref idref="DRAWINGS">FIG. 8</figref> shows a simplified flow chart illustrating method <b>300</b> for forming part or all of the circuit and structures of <figref idref="DRAWINGS">FIGS. 3-7</figref>, according to yet still further embodiments of the invention. It will be understood by those of skill in the art that while method <b>300</b> is useful for forming all or part of the circuit and structures illustrated in <figref idref="DRAWINGS">FIGS. 3-7</figref>, it can also be used to form other circuits and structures containing more or fewer capacitors, inductors and transistors and is not limited merely to implementing the circuit of <figref idref="DRAWINGS">FIG. 3</figref>. Following START <b>301</b>, initial step <b>302</b> comprises providing a high (e.g., preferably ≧10<sup>3 </sup>Ohm-com) resistivity SC substrate having opposed first and second surfaces (<b>63</b>, <b>62</b>-<i>i</i>). This substrate is referred to as initial substrate <b>60</b>-<i>i </i>having initial thickness <b>61</b>-<i>i </i>and initial lower surface <b>62</b>-<i>i </i>(see <figref idref="DRAWINGS">FIG. 5</figref>) to distinguish it from final substrate <b>60</b> of <figref idref="DRAWINGS">FIGS. 4-7</figref> that has smaller thickness <b>61</b> and lower surface <b>62</b>. Substrate <b>60</b>-<i>i </i>has an initial thickness at the beginning of manufacturing usefully in the range of about 500 to 1000 micrometers, conveniently in the range of about 600 to 900 micrometers, and preferably in the range of about 700 to 800 micrometers, but thicker and thinner substrates may also be used. Step <b>303</b> comprises forming a transistor (e.g., transistor <b>41</b>′) in the substrate (e.g., substrate <b>60</b>-<i>i</i>) with input (e.g., gate <b>50</b>, <b>50</b>′, <b>74</b>) terminal, output (e.g., drain <b>52</b>, <b>52</b>′, <b>70</b>, <b>78</b>) terminal and reference or common (e.g., source <b>51</b>, <b>51</b>′, <b>76</b>, <b>79</b>) terminal, proximate the first surface (e.g., surface <b>63</b> of <figref idref="DRAWINGS">FIGS. 4-7</figref>). In step <b>304</b>, one or more conductor filled substrate-vias (e.g., vias <b>49</b>′, <b>98</b>, <b>98</b>′) are formed extending into the initial SC substrate (e.g., substrate <b>60</b>-<i>i</i>) through the first surface (e.g., surface <b>63</b>). Lower surfaces <b>982</b> (see <figref idref="DRAWINGS">FIG. 5</figref>) of such substrate-vias (e.g., vias <b>49</b>′, <b>98</b>, <b>98</b>′) are initially buried within initial substrate (e.g., substrate <b>60</b>-<i>i</i>) and not yet exposed. In step <b>305</b> one or more planar capacitors (e.g., capacitor <b>42</b>′, <b>43</b>′) are provided over the first surface (e.g., surface <b>63</b>) of the initial substrate (e.g., substrate <b>60</b>-<i>i</i>), each capacitor having first and second terminals. In step <b>306</b>, one or more planar inductors (e.g., inductors <b>44</b>′, <b>45</b>′) are provided over the first surface (e.g. surface <b>63</b>), wherein the first terminal (e.g., terminal <b>42</b>-<b>1</b>′, <b>43</b>-<b>1</b>′) or the second terminal (e.g., terminal <b>42</b>-<b>2</b>, <b>43</b>-<b>2</b>) of the one or more planar capacitors (<b>42</b>′, <b>43</b>′) is coupled to the first terminal (e.g., terminal <b>44</b>-<b>1</b>′, <b>45</b>-<b>1</b>′) or the second terminal (e.g., terminal <b>44</b>-<b>2</b>′, <b>45</b>-<b>2</b>′) of the one or more planar inductors (<b>44</b>′, <b>45</b>′), other terminals of which (e.g., terminals <b>44</b>-<b>2</b>′, <b>44</b>-<b>1</b>′) are adapted to be coupled to substrate-vias (e.g., substrate vias <b>49</b>′, <b>98</b>, <b>98</b>′), to one or more terminals of the transistor (e.g., terminals <b>50</b>′, <b>52</b>′ of transistor <b>41</b>′), or to other nodes (e.g., nodes <b>53</b>, <b>54</b>). In subsequent step <b>307</b>, lower surface <b>62</b>-<i>i </i>(see <figref idref="DRAWINGS">FIG. 5</figref>) of the initial substrate (e.g., substrate <b>60</b>-<i>i</i>) is lapped, etched and/or otherwise abraded to remove initial substrate thickness amount <b>61</b>-<b>1</b> (see <figref idref="DRAWINGS">FIG. 5</figref>) and expose lower (inner) ends (e.g., ends <b>982</b>) of the substrate vias (e.g., vias <b>49</b>, <b>98</b>, <b>98</b>′). In step <b>308</b>, a conductor (e.g., ground plane conductor <b>49</b>′, <b>69</b>) is applied to the newly exposed rear face (e.g., face <b>62</b>) of the thinned substrate (e.g., substrate <b>60</b>) so that the substrate vias (e.g., vias <b>49</b>′, <b>98</b>, <b>98</b>′) are electrically connected to the ground plane conductor (e.g., conductor <b>49</b>′, <b>69</b>). Method <b>300</b> then proceeds substantially to END <b>309</b>.
0038According to a still additional embodiment, the preferred embodiment illustrated in <figref idref="DRAWINGS">FIG. 4</figref>, may be formed in steps <b>305</b>-<b>306</b> by: (a) in step <b>305</b> forming first and second planar capacitors (e.g., capacitor <b>42</b>′, <b>43</b>′) over the first surface (e.g., surface <b>63</b>) of initial substrate <b>60</b>-<i>i</i>, each capacitor having first and second terminals; (b) in step <b>306</b>, forming first and second planar inductors (e.g., inductors <b>44</b>′, <b>45</b>′) over the first surface (e.g. surface <b>63</b>), each inductor having first and second terminals; (c) coupling the first terminal (e.g., <b>42</b>-<b>1</b>′) of the first capacitor (e.g., capacitor <b>42</b>′) to a first terminal of the first inductor (e.g., inductor <b>44</b>′) and coupling the second terminal of the first inductor to the transistor input (e.g., gate <b>50</b>′); (d) coupling the first terminal (e.g., terminal <b>43</b>-<b>1</b>′) of the second capacitor (e.g., capacitor <b>43</b>′) to the transistor output (e.g., drain <b>52</b>′) and the second terminal (e.g., terminal <b>43</b>-<b>2</b>′) of the second capacitor (e.g., capacitor <b>43</b>′) to the first terminal of the second inductor (e.g., inductor <b>45</b>′); and (e) coupling the second terminal (<b>42</b>-<b>3</b>′) of the first capacitor (e.g., capacitor <b>42</b>′), the second terminal of the second inductor (e.g., inductor <b>45</b>′) and the common terminal (e.g., source <b>51</b>′) of the transistor (e.g., transistor <b>41</b>′) to the substrate vias (e.g., substrate vias <b>49</b>′, <b>98</b>, <b>98</b>′).
0039<figref idref="DRAWINGS">FIGS. 9-11</figref> show a simplified flow chart illustrating method <b>400</b> for forming part or all of the circuit and structures of <figref idref="DRAWINGS">FIGS. 3-7</figref>, according to yet additional embodiments of the invention. It will be understood by those of skill in the art that while method <b>400</b> is useful for forming all or part of the circuit and structures illustrated in <figref idref="DRAWINGS">FIGS. 3-7</figref>, it can also be used to form other circuits and structures containing more or fewer capacitors, inductors and transistors and is not limited merely to implementing the circuit of <figref idref="DRAWINGS">FIG. 3</figref>. For convenience of presentation, the flow chart of method <b>400</b> is divided into three parts, portion <b>400</b>-<b>1</b> in <figref idref="DRAWINGS">FIG. 9</figref>, portion <b>400</b>-<b>2</b> in <figref idref="DRAWINGS">FIG. 10</figref> and portion <b>400</b>-<b>3</b> in <figref idref="DRAWINGS">FIG. 11</figref>. Following START <b>401</b>, initial step <b>402</b> is performed wherein a high resistivity initial SC substrate (e.g., substrate <b>60</b>-<i>i</i>, see <figref idref="DRAWINGS">FIG. 5</figref> and associated discussion) is provided having opposed first and second surfaces. This substrate is referred to as initial substrate <b>60</b>-<i>i </i>with initial thickness <b>61</b>-<i>i </i>and initial lower surface <b>62</b>-<i>i </i>to distinguish it from thinned substrate <b>60</b> of <figref idref="DRAWINGS">FIGS. 4-7</figref> that has smaller thickness (e.g., thickness <b>61</b>) and lower surface <b>62</b> newly exposed after thinning, as described in connection with <figref idref="DRAWINGS">FIG. 8</figref>, which description is incorporated herein by reference. In step <b>403</b>, one or more transistors (e.g., transistor <b>41</b>, <b>41</b>′, <b>67</b>) is formed in initial SC substrate <b>60</b>-<i>i </i>having an input terminal (e.g., gate <b>50</b>, <b>50</b>′, <b>74</b>), an output terminal (e.g., drain <b>52</b>, <b>52</b>′, <b>70</b>, <b>78</b>) and a reference terminal (e.g., source <b>51</b>, <b>51</b>′, <b>76</b>, <b>79</b>), proximate the first surface (e.g., surface <b>63</b> of <figref idref="DRAWINGS">FIGS. 4-7</figref>). In step <b>404</b> at least a first dielectric layer (e.g., layer <b>81</b>) is provided over the first surface (e.g., surface <b>63</b>). Then steps <b>405</b> and <b>406</b> are provided in either order as indicated by first path <b>405</b>-<b>1</b>, <b>406</b>-<b>1</b>, <b>406</b>-<b>3</b> (which is preferred), or alternate second path <b>405</b>-<b>2</b>,<b>406</b>-<b>2</b>, <b>405</b>-<b>3</b> (which is also useful). In step <b>405</b>, one or more conductor filled substrate-vias (e.g., vias <b>49</b>, <b>98</b>, <b>98</b>′) are formed extending into initial SC substrate <b>60</b>-<i>i </i>through the first surface (e.g., surface <b>63</b>) and having initially buried inner ends <b>982</b> (see <figref idref="DRAWINGS">FIG. 5</figref>). In step <b>406</b>, first interlayer conductive vias (e.g., vias <b>90</b>-<b>1</b>, <b>90</b>-<b>2</b>, <b>90</b>-<b>4</b>) are formed, coupled to at least a first (e.g., terminal <b>76</b>, <b>79</b>) of the terminals (e.g., terminals <b>76</b>, <b>79</b>, <b>74</b>, <b>78</b> of transistor <b>41</b>′). In step <b>407</b> a “first metal” layer (e.g., layer <b>91</b>) is provided over the first dielectric layer (e.g., layer <b>81</b>) and having at least a first portion (e.g., portion <b>91</b>-<b>2</b>) coupling the first terminal (e.g., terminal <b>76</b>, <b>79</b>) to a substrate via (e.g., via <b>49</b>′, <b>98</b>, <b>98</b>′) and another portion (e.g., <b>91</b>-<b>1</b>) coupled to another terminal (e.g., drain terminal <b>78</b>) by another part (e.g., <b>90</b>-<b>1</b>) of the first interlayer via. In step <b>408</b>, a second dielectric layer (e.g. layer <b>82</b>) is formed over the “first metal” (e.g., layer <b>91</b>). In step <b>409</b>, second interlayer conductive vias (e.g., interlayer vias <b>90</b>-<b>2</b>) are provided coupled at least to the another portion (e.g., portion <b>91</b>-<b>1</b>) of the “first metal” (e.g., layer <b>91</b>) and extending through the second dielectric layer (e.g., layer <b>82</b>). In step <b>410</b>, a “second metal” layer (e.g., layer <b>92</b>) is formed overlying the second dielectric layer (e.g., layer <b>82</b>) and having a second portion (e.g., portion <b>92</b>-<b>1</b>) coupled to some of the second interlayer vias (e.g., vias <b>90</b>-<b>2</b>). In step <b>411</b>, a planar capacitor (e.g., capacitor <b>42</b>′, <b>43</b>′) is provided on part (e.g., part <b>92</b>-<b>3</b> and/or <b>92</b>-<b>4</b>) of the second metal layer (e.g., layer <b>92</b>) and having an upper electrode (e.g., electrode <b>102</b>, <b>104</b>). In step <b>412</b>, a third dielectric layer (e.g., layer <b>83</b>) is formed over the upper electrode (e.g., electrode <b>102</b>, <b>104</b>) and otherwise exposed parts of the “second metal” layer (e.g., layer <b>92</b>). In step <b>413</b>, third conductive interlayer vias (e.g., vias <b>90</b>-<b>3</b>) are formed coupled at least to the upper electrode (e.g., electrode <b>102</b>, <b>104</b>) and extending through the third dielectric layer (e.g., layer <b>83</b>). In step <b>414</b>, a “third metal” layer (e.g., layer <b>93</b>) is provided having a third portion (e.g., <b>93</b>-<b>3</b>, <b>93</b>-<b>4</b> and/or <b>93</b>-<b>5</b>) contacting at least part of the third interlayer conductive vias (e.g., vias <b>90</b>-<b>3</b>). In step <b>415</b>, a fourth dielectric layer (e.g., layer <b>84</b>) is provided having one or more openings (e.g., opening <b>84</b>-<b>1</b>, <b>84</b>-<b>2</b>, <b>84</b>-<b>3</b> and/or <b>84</b>-<b>4</b>) extending to the third portion (e.g., portion <b>93</b>-<b>3</b>, <b>93</b>-<b>4</b> and/or <b>93</b>-<b>5</b>). In step <b>416</b>, a planar inductor (e.g., inductor <b>44</b>′, <b>45</b>′) and/or interconnections (e.g., <b>56</b>, <b>57</b>, <b>52</b>-<b>1</b> and/or <b>50</b>-<b>1</b>, etc.) are provided on the fourth dielectric layer (e.g., layer <b>84</b>) coupled to the third portion (e.g., portion <b>93</b>-<b>3</b>, <b>93</b>-<b>4</b> and/or <b>93</b>-<b>5</b>) via the one or more openings (e.g., opening <b>84</b>-<b>1</b>, <b>84</b>-<b>2</b>, <b>84</b>-<b>3</b> and/or <b>84</b>-<b>4</b>). In step <b>417</b>, the second surface (e.g., surface <b>62</b>-<i>i</i>) of the initial substrate (e.g., substrate <b>60</b>-<i>i</i>) is, for example, back-lapped, etched or otherwise abraded, to remove thickness <b>61</b>-<b>1</b> of initial substrate <b>61</b>-<i>i </i>so as to provide a new back-side surface (e.g., surface <b>62</b>) on which inner ends (e.g., ends <b>982</b>) of the substrate vias (e.g., vias <b>49</b>′, <b>98</b>, <b>98</b>′) are newly exposed so that in step <b>418</b>, back-metal or other conductor (e.g., conductor <b>49</b>′, <b>69</b>) can be applied in contact with the newly exposed ends (e.g., ends <b>982</b>) of the substrate vias (e.g., vias <b>49</b>′, <b>98</b>, <b>98</b>′), thereby providing low resistance Ohmic contact with those terminals or leads of the transistor and/or capacitors and/or inductors coupled thereto via the substrate vias, (e.g., TSVs <b>49</b>′, <b>98</b>, <b>98</b>′). Method <b>400</b> then proceeds substantially to END <b>419</b>.
0040According to a first embodiment, there is provided a monolithic microwave integrated circuit (<b>46</b>, <b>58</b>), comprising, a semiconductor substrate (<b>60</b>) having a bulk resistivity equal or greater than about 100 Ohm-cm, and having a front surface (<b>63</b>) and a rear surface (<b>62</b>), at least one transistor (<b>41</b>) formed in the semiconductor substrate (<b>60</b>) and having an input terminal (<b>50</b>), an output terminal (<b>52</b>) and a reference terminal (<b>51</b>), at least one capacitor (<b>42</b>′, <b>43</b>′) monolithically formed over the semiconductor substrate (<b>60</b>), at least one inductor (<b>44</b>′, <b>45</b>′) monolithically formed over the semiconductor substrate (<b>60</b>), and planar interconnections overlying the semiconductor substrate (<b>60</b>) coupling the at least one transistor (<b>41</b>′), capacitor (<b>42</b>′, <b>43</b>′), and inductor (<b>44</b>′, <b>45</b>′) to form the monolithic integrated circuit (<b>46</b>, <b>58</b>). According to a further embodiment, the monolithic microwave integrated circuit (<b>46</b>, <b>58</b>), further comprising an input node (<b>53</b>, <b>53</b>′) thereof and an output node (<b>54</b>, <b>54</b>′) thereof, both supported by the front surface (<b>63</b>) of the semiconductor substrate (<b>60</b>), and a reference node (<b>49</b>, <b>69</b>) thereof supported by the rear surface (<b>62</b>) of the semiconductor substrate (<b>60</b>). According to a still further embodiment, the monolithic microwave integrated circuit (<b>46</b>, <b>58</b>) further comprises multiple conductive through-substrate vias (<b>49</b>′, <b>98</b>, <b>98</b>′) coupling one or more of the at least one transistor (<b>41</b>), the at least one capacitor (<b>42</b>′, <b>43</b>′) and the at least one inductor (<b>44</b>′, <b>45</b>′) to the reference node (<b>49</b>, <b>69</b>, <b>69</b>′). According to a yet further embodiment, a first (<b>49</b>-<b>2</b>′) of the multiple conductive through-substrate vias (<b>49</b>′, <b>98</b>, <b>98</b>′) couples the reference terminal (<b>51</b>′, <b>76</b>) of the at least one transistor (<b>41</b>′) to the reference node (<b>49</b>, <b>69</b>). According to a still yet further embodiment, a second (<b>49</b>-<b>1</b>′) of the multiple through-substrate vias (<b>49</b>′, <b>98</b>, <b>98</b>′) couples a first terminal (<b>42</b>-<b>2</b>′) of the at least one capacitor (<b>42</b>′) to the reference node (<b>49</b>, <b>69</b>). According to a yet still further embodiment, the at least one transistor (<b>41</b>′) is a lateral transistor. According to another embodiment, the at least one capacitor (<b>42</b>′, <b>43</b>′) is a planar capacitor, and the at least one inductor (<b>44</b>′, <b>45</b>′) is a planar inductor. According to still another embodiment, the semiconductor substrate (<b>60</b>) further comprises, multiple conductive through-substrate vias (<b>49</b>′, <b>98</b>, <b>98</b>′) each having a terminal coupled to the reference node (<b>49</b>, <b>69</b>, <b>69</b>′), two monolithic capacitors (<b>42</b>′, <b>43</b>′) formed over the front surface (<b>63</b>) of the semiconductor substrate (<b>60</b>), each having first (<b>42</b>-<b>1</b>′, <b>43</b>-<b>1</b>′) and second (<b>42</b>-<b>1</b>′, <b>43</b>-<b>2</b>′) terminals, two monolithic inductors (<b>44</b>′, <b>45</b>′) formed over the front surface (<b>63</b>) of the semiconductor substrate (<b>60</b>), each having first and second terminals, wherein the first terminal (<b>42</b>-<b>1</b>′) of the first capacitor (<b>42</b>′) is coupled to the first terminal of the first inductor (<b>44</b>′) and the second terminal (<b>42</b>-<b>2</b>′) of the first capacitor (<b>42</b>′) is coupled to a first (<b>49</b>-<b>1</b>′) of the multiple through substrate vias (<b>49</b>′, <b>98</b>, <b>98</b>′), and the second terminal of the first inductor (<b>44</b>′) is coupled to the input terminal (<b>50</b>) of the transistor (<b>41</b>′), wherein the second capacitor (<b>43</b>′) and second inductor (<b>45</b>′) are serially coupled to form a combination (<b>43</b>′, <b>45</b>′), the combination (<b>43</b>′, <b>45</b>′) having first and second terminals, and wherein the first terminal of the combination (<b>43</b>′, <b>45</b>′) is coupled to the output terminal (<b>52</b>′) of the at least one transistor (<b>41</b>′) and the second terminal of the combination (<b>43</b>′, <b>45</b>′) is coupled to a second (<b>49</b>-<b>2</b>′) of the multiple conductive through-substrate vias (<b>49</b>′, <b>98</b>, <b>98</b>′). According to yet another embodiment, the at least one inductor (<b>44</b>′, <b>45</b>′) comprises a high conductivity metal about 0.1-10 micrometers thick.
0041According to a second embodiment, there is provided a method for forming a monolithic microwave integrated circuit (<b>46</b>, <b>58</b>) having an input terminal (<b>47</b>), an output terminal (<b>48</b>) and a reference terminal (<b>49</b>, <b>69</b>, <b>69</b>′), the method comprising, providing a high resistivity initial semiconductor substrate (<b>60</b>-<i>i</i>) having an initial thickness (<b>61</b>-<i>i</i>) between a first surface (<b>63</b>) and an initial second surface (<b>62</b>-<i>i</i>), forming at least one transistor (<b>41</b>′) in the initial semiconductor substrate (<b>60</b>-<i>i</i>) with input terminal (<b>50</b>, <b>50</b>′, <b>74</b>), output terminal (<b>52</b>, <b>52</b>′, <b>70</b>, <b>78</b>) and reference terminal (<b>51</b>, <b>51</b>′, <b>76</b>, <b>79</b>) proximate the first surface (<b>63</b>), forming one or more conductor filled substrate vias (<b>49</b>′, <b>98</b>, <b>98</b>′) extending into the initial semiconductor substrate (<b>60</b>-<i>i</i>) through the first surface (<b>63</b>), forming one or more planar capacitors (<b>42</b>′, <b>43</b>′) over the first surface (<b>63</b>) of the initial substrate (<b>60</b>-<i>i</i>), each capacitor (<b>42</b>′, <b>43</b>′) having first (<b>42</b>-<b>1</b>′, <b>43</b>-<b>1</b>′) and second (<b>42</b>-<b>2</b>′, <b>43</b>-<b>2</b>′) terminals, forming one or more planar inductors (<b>44</b>′, <b>45</b>′) over the first surface (<b>63</b>) of the initial substrate (<b>60</b>-<i>i</i>), wherein the first terminal (<b>42</b>-<b>1</b>′, <b>43</b>-<b>1</b>′) or the second terminal (<b>42</b>-<b>2</b>′, <b>43</b>-<b>2</b>′) of the one or more planar capacitors (<b>42</b>′, <b>43</b>′) is coupled to a first terminal or a second terminal of the one or more planar inductors (<b>44</b>′, <b>45</b>′) wherein other terminals of the one or more planar inductors (<b>44</b>′, <b>45</b>′) are coupled to through substrate vias (<b>49</b>′, <b>98</b>, <b>98</b>′), to one or more terminals (<b>50</b>′, <b>52</b>′) of the transistor (<b>41</b>′) or to one or more terminals (<b>47</b>, <b>48</b>, <b>49</b>) of the microwave integrated circuit (<b>46</b>, <b>58</b>), reducing the initial thickness (<b>61</b>-<i>i</i>), thereby creating a new rear surface (<b>62</b>) of a thinned substrate (<b>60</b>) on which inner ends (<b>982</b>) of the substrate vias (<b>49</b>′, <b>98</b>, <b>98</b>′) are exposed, and applying a conductor (<b>69</b>) to the new rear surface (<b>62</b>) of the thinned substrate (<b>60</b>) so that the exposed inner ends (<b>982</b>) of the substrate vias (<b>49</b>′, <b>98</b>, <b>98</b>′) are electrically connected to the conductor (<b>69</b>). According to a further embodiment, the step of forming one or more planar capacitors (<b>42</b>′, <b>43</b>′) comprises, forming first and second planar capacitors (<b>42</b>′, <b>43</b>′) over the first surface (<b>63</b>) of the initial substrate (<b>60</b>-<i>i</i>), each capacitor (<b>42</b>′, <b>43</b>′) having first (<b>42</b>-<b>1</b>′, <b>43</b>-<b>1</b>′) and second terminals (<b>42</b>-<b>2</b>′, <b>43</b>-<b>2</b>′), the step of forming one or more planar inductors (<b>44</b>′, <b>45</b>′) comprises, forming first and second planar inductors (<b>44</b>′, <b>45</b>′) over the first surface (<b>63</b>), each inductor having first and second terminals, and wherein the first terminal (<b>42</b>-<b>1</b>′) of the first capacitor (<b>42</b>′) is coupled to the first terminal of the first inductor (<b>44</b>′) and the second terminal of the first inductor (<b>44</b>′) is coupled to the transistor input (<b>50</b>′), and wherein the first terminal (<b>43</b>-<b>1</b>′) of the second capacitor (<b>43</b>′) is coupled to the transistor output (<b>52</b>′) and the second terminal (<b>43</b>-<b>2</b>′) of the second capacitor (<b>43</b>′) is coupled to the first terminal of the second inductor (<b>45</b>′), and wherein the second terminal (<b>42</b>-<b>2</b>′) of the first capacitor (<b>42</b>′), the second terminal of the second inductor (<b>45</b>′) and the reference terminal (<b>51</b>′) of the transistor (<b>41</b>′) are coupled to at least one of the conductor filled substrate vias (<b>49</b>′, <b>98</b>, <b>98</b>′). According to a still further embodiment, the initial substrate (<b>60</b>-<i>i</i>) has a resistivity equal or greater than about 100 Ohm-cm. According to a yet further embodiment, initial substrate (<b>60</b>-<i>i</i>) has a resistivity equal or greater than about 500 Ohm-cm. According to a still yet further embodiment, the initial substrate (<b>60</b>-<i>i</i>) has a resistivity equal or greater than about 1000 Ohm-cm. According to a yet still further embodiment, the step of forming one or more planar inductors (<b>44</b>′, <b>45</b>′) comprises, forming the inductors using copper, gold, silver or a combination thereof. According to another embodiment, the copper, gold, silver or combination thereof is at least about 3 micrometers thick.
0042According to a third embodiment, there is provided a monolithic microwave integrated circuit (<b>46</b>, <b>58</b>) having a circuit input terminal (<b>47</b>′), a circuit output terminal (<b>48</b>′) and a circuit reference terminal (<b>49</b>, <b>49</b>′, <b>69</b>, <b>69</b>′), comprising, a semiconductor substrate (<b>60</b>) having a bulk resistivity equal or greater than about 100 Ohm-cm, and having a front surface (<b>63</b>) and a rear surface (<b>62</b>), wherein the rear surface (<b>62</b>) has thereon the circuit reference terminal (<b>49</b>, <b>49</b>′, <b>69</b>, <b>69</b>′), at least one LDMOS transistor (<b>41</b>′) formed in the substrate (<b>60</b>) and having a transistor input terminal (<b>50</b>′), a transistor output terminal (<b>52</b>′) and a transistor reference terminal (<b>51</b>′), wherein the transistor reference terminal (<b>51</b>′) is coupled to the circuit reference terminal (<b>49</b>, <b>49</b>′, <b>69</b>, <b>69</b>′), at least first (<b>42</b>′) and second (<b>43</b>′) monolithic planar capacitors overlying the front surface (<b>63</b>′), at least first (<b>44</b>′) and second (<b>45</b>′) monolithic planar inductors overlying the front surface (<b>63</b>′), and wherein the first capacitor (<b>42</b>′) is coupled between the circuit input terminal (<b>47</b>′) and the circuit reference terminal (<b>49</b>, <b>49</b>′, <b>69</b>, <b>69</b>′), and the first inductor (<b>44</b>′) is coupled between the circuit input terminal (<b>47</b>′) and the transistor input terminal (<b>50</b>′), and wherein the second capacitor (<b>43</b>′) and the second inductor (<b>45</b>′) are coupled in series to from a combination (<b>43</b>′, <b>45</b>′), and a first terminal of the combination (<b>43</b>′, <b>45</b>′) is coupled to the transistor output terminal (<b>52</b>′) and to the circuit output terminal (<b>48</b>′) and a second terminal of the combination (<b>43</b>′, <b>45</b>′) is coupled to the circuit reference terminal (<b>49</b>, <b>49</b>′, <b>69</b>, <b>69</b>′). According to a further embodiment, the substrate (<b>60</b>) substantially comprises float zone silicon. According to a still further embodiment, at least one of the first and second inductors (<b>44</b>′, <b>45</b>′) is formed from substantially high purity copper. According to a yet further embodiment, the high purity copper has a thickness of at least about 0.5 micrometers.
0043While at least one exemplary embodiment and method of fabrication has been presented in the foregoing detailed description of the invention, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the invention, it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the invention as set forth in the appended claims and their legal equivalents.
Contents5
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| IFW Scan & PACR Auto Security ReviewSCAN | SCAN | |
| Entity Status Set To Undiscounted (Initial Default Setting or Status Change)BIG. | BIG. | |
| Initial Exam Team nnIEXX | IEXX |
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Numbers
- Publication
- 9508599
- Application
- 14693781
Titles
- English
- Methods of making a monolithic microwave integrated circuit
Patent term adjustment
- Applicant delay
- −87 days
- Net adjustment
- 0 days
Classification
- CPC, 44
- H01L21/823475
- H10W44/20
- H03F3/195
- H10D1/20
- H01L21/76898
- H10D1/68
- H01L23/481
- H01L23/5223
- H10W20/20
- H01L23/5226
- H10W20/496
- H10W20/497
- H01L23/5227
- H01L23/66
- H01L27/0617
- H10W44/209
- H01L27/0727
- H10W44/234
- H01L28/10
- H10W44/251
- H01L28/40
- H10W72/5445
- H10W20/2134
- H01L24/49
- H10D84/813
- H10D84/80
- H01L2223/6616
- H01L2223/6655
- H01L2223/6683
- H01L2224/48091
- H01L2224/49175
- H10D30/65
- H01L2924/12044
- H10D84/038
- H01L2924/13062
- H10D84/40
- H01L2924/14
- H10D84/0149
- H01L2924/1423
- H10D84/811
- H01L2924/30107
- H10W20/023
- H10W20/42
- H10W90/297
- IPC, 15
- H01L21 8234
- H01L23 522
- H01L23 48
- H01L23 66
- H01L27 06
- H03F3 195
- H01L21 768
- H01L27 07
- H01L49 02
- H01L23 00
- H10D84 03
- H10D84 40
- H10D62 10
- H10D84 80
- H10N97 00