Nonvolatile memory device and a method for fabricating the same

CROSS-REFERENCE TO RELATED APPLICATION

0001This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2012-0090784, filed on Aug. 20, 2012 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

00021. Technical Field

0003The present inventive concept relates to a nonvolatile memory device and a method for fabricating the same, and more particularly to a three-dimensional (3D) flash memory device and a method for fabricating the same.

00042. Discussion of the Related Art

0005A semiconductor memory device is an electronic data storage device that may be implemented using a semiconductor such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). The semiconductor memory device may be classified as a volatile memory device or a nonvolatile memory device.

0006The volatile memory device retains stored data as long as power supply is on, but when the power supply is off or interrupted the stored data is lost. The volatile memory device types may include static random access memory (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). The nonvolatile memory device can retain stored data even when not powered. The nonvolatile memory device types may include a flash memory device, a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), and a resistive memory (for example, a phase-change RAM (PRAM), a ferroelectric RAM (FRAM), and a resistive RAM (RRAM)).

0007To advance the degree of integration of a nonvolatile memory device, a three-dimensional memory device in which unit memory cells are vertically disposed has been developed.

SUMMARY

0008Exemplary embodiments of the present inventive concept provide a three-dimensional (3D) nonvolatile memory device having improved process stability.

0009Exemplary embodiments of the present inventive concept also provide a method for fabricating a 3D nonvolatile memory device having improved process stability.

0010According to an exemplary embodiment of the present inventive concept, there is provided a nonvolatile memory device comprising: a substrate which includes a cell array region and a connection region; an electrode structure formed on the cell array region and the connection region and including a plurality of laminated electrodes; a first recess formed in the electrode structure on the connection region and disposed between the cell array region and a second recess formed in the electrode structure on the connection region; and a plurality of vertical wirings formed on the plurality of electrodes exposed by the first recess.

0011The first recess includes a first side wall surface disposed on a first side of the first recess and a second side wall surface disposed on a second side of the first recess, and the second recess includes a third side wall surface disposed on a first side of the second recess and a fourth side wall surface disposed on a second side of the second recess.

0012The plurality of vertical wirings are formed on the first side wall surface, and the plurality of vertical wirings are not formed on the second side wall surface, the third side wall surface, and the fourth side wall surface.

0013The plurality of electrodes exposed by the first recess have a step shape.

0014The nonvolatile memory device further comprises a plurality of channel patterns that penetrate the electrode structure on the cell array region.

0015According to an exemplary embodiment of the present inventive concept, there is provided a nonvolatile memory device comprising: a substrate which includes a cell array region and a connection region; a mold pattern formed on the substrate and including a trench; a first electrode structure formed on a bottom and a side wall of the trench and an upper surface of the mold pattern, and including a plurality of first laminated electrodes; a second electrode structure formed on the first electrode structure and including a plurality of second laminated electrodes; a first recess formed in the second electrode structure on the connection region; a second recess formed in the second electrode structure on the connection region and disposed between the cell array region and the first recess; and a plurality of first vertical wirings formed on the plurality of second electrodes exposed by the second recess.

0016The second recess includes a first side wall surface disposed on a first side of the second recess and a second side wall surface disposed on a second side of the second recess, and the first recess includes a third side wall surface disposed on a first side of the first recess and a fourth side wall surface disposed on a second side of the first recess.

0017The plurality of first vertical wirings are formed on first side wall surface, and the plurality of first vertical wirings are not formed on the second side wall surface, the third side wall surface, and the fourth side wall surface.

0018The nonvolatile memory further comprises a third recess formed in the first electrode structure on the connection region.

0019The nonvolatile memory device further comprises a fourth recess formed in the first electrode structure on the connection region, wherein the third recess is disposed between the cell array region and the fourth recess.

0020The third recess includes a fifth side wall surface disposed on a first side of the third recess and a sixth side wall surface disposed on a second side of the third recess, and the fourth recess includes a seventh side wall surface disposed on a first side of the fourth recess and an eighth side wall surface disposed on a second side of the fourth recess, and a plurality of second vertical wirings are formed on the plurality of first electrodes exposed by the third recess at the fifth side wall surface, and the plurality of second vertical wirings are not formed on the sixth side wall surface, the seventh side wall surface, and the eighth side wall surface.

0021The third recess and the fourth recess are disposed on the upper surface of the mold pattern.

0022The third recess and the second recess are formed at the substantially same height and with substantially the same depth.

0023The second recess and the first recess are formed with substantially the same depth.

0024An upper surface of the first electrode structure and an upper surface of the second electrode structure are connected to each other.

0025According to an exemplary embodiment of the present inventive concept, there is provided a semiconductor memory device comprising: a first electrode structure formed on a substrate and including a plurality of electrodes; a first recess formed in the first electrode structure; a second recess formed in the first electrode structure adjacent to the first recess; and a plurality of vertical wirings formed on the electrodes in the first recess.

0026The second recess is a dummy recess. The electrodes include word lines. The electrodes have a step shape. The semiconductor memory device is a nonvolatile memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

0027The above and other features of the present inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:

0028<figref idref="DRAWINGS">FIG. 1</figref> is a diagram of a nonvolatile memory device according to an exemplary embodiment of the present inventive concept;

0029<figref idref="DRAWINGS">FIG. 2</figref> is a layout diagram of a nonvolatile memory device according to an exemplary embodiment of the present inventive concept;

0030<figref idref="DRAWINGS">FIG. 3</figref> is a cross-sectional view taken along line A-A of <figref idref="DRAWINGS">FIG. 2</figref>;

0031<figref idref="DRAWINGS">FIG. 4</figref> is a perspective view of a cell array region I in <figref idref="DRAWINGS">FIG. 2</figref>;

0032<figref idref="DRAWINGS">FIG. 5</figref> is an enlarged view of a TS<b>1</b> region in <figref idref="DRAWINGS">FIG. 3</figref>;

0033<figref idref="DRAWINGS">FIG. 6</figref> is a cross-sectional view taken along line B-B of <figref idref="DRAWINGS">FIG. 2</figref>;

0034<figref idref="DRAWINGS">FIG. 7</figref> is a cross-sectional view of a nonvolatile memory device according to an exemplary embodiment of the present inventive concept;

0035<figref idref="DRAWINGS">FIG. 8</figref> is a cross-sectional view of a nonvolatile memory device according to an exemplary embodiment of the present inventive concept;

0036<figref idref="DRAWINGS">FIG. 9</figref> is a cross-sectional view of a nonvolatile memory device according to an exemplary embodiment of the present inventive concept;

0037<figref idref="DRAWINGS">FIG. 10</figref> is a cross-sectional view of a nonvolatile memory device according to an exemplary embodiment of the present inventive concept;

0038<figref idref="DRAWINGS">FIG. 11</figref> is a cross-sectional view of a nonvolatile memory device according to an exemplary embodiment of the present inventive concept;

0039<figref idref="DRAWINGS">FIGS. 12 to 17</figref> are views of intermediate steps of a method for fabricating a nonvolatile memory device according to an exemplary embodiment of the present inventive concept;

0040<figref idref="DRAWINGS">FIGS. 18 to 21</figref> are views of intermediate steps of a recess forming step, according to an exemplary embodiment of the present inventive concept;

0041<figref idref="DRAWINGS">FIG. 22</figref> is a block diagram illustrating a memory system according to an exemplary embodiment of the present inventive concept;

0042<figref idref="DRAWINGS">FIG. 23</figref> is a block diagram illustrating an application example of the memory system of <figref idref="DRAWINGS">FIG. 22</figref>; and

0043<figref idref="DRAWINGS">FIG. 24</figref> is a block diagram illustrating a computing system that includes the memory system of <figref idref="DRAWINGS">FIG. 23</figref>.

DETAILED DESCRIPTION OF THE EMBODIMENTS

0044Exemplary embodiments of the present inventive concept will be described more fully hereinafter with reference to the accompanying drawings. The present inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein.

0045As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

0046<figref idref="DRAWINGS">FIG. 1</figref> is a diagram of a nonvolatile memory device according to an exemplary embodiment of the present inventive concept.

0047Referring to <figref idref="DRAWINGS">FIG. 1</figref>, a memory cell array of a nonvolatile memory device according to an exemplary embodiment of the present inventive concept may include a plurality of memory blocks BLK<b>1</b> to BLKn (where, n is a natural number). The respective memory blocks BLK<b>1</b> to BLKn may extend in first to third directions D<b>1</b>, D<b>2</b>, and D<b>3</b>. As illustrated, the first to third directions D<b>1</b>, D<b>2</b>, and D<b>3</b> may be directions which cross one another, and may be different directions. For example, the first to third directions D<b>1</b>, D<b>2</b>, and D<b>3</b> may be directions which cross one another at right angles, but are not limited thereto.

0048<figref idref="DRAWINGS">FIG. 2</figref> is a layout diagram of a nonvolatile memory device according to an exemplary embodiment of the present inventive concept, and <figref idref="DRAWINGS">FIG. 3</figref> is a cross-sectional view taken along line A-A of <figref idref="DRAWINGS">FIG. 2</figref>. <figref idref="DRAWINGS">FIG. 4</figref> is a perspective view of a cell array region I in <figref idref="DRAWINGS">FIG. 2</figref>. <figref idref="DRAWINGS">FIG. 5</figref> is an enlarged view of a TS<b>1</b> region in <figref idref="DRAWINGS">FIG. 3</figref>. <figref idref="DRAWINGS">FIG. 6</figref> is a cross-sectional view taken along line B-B of <figref idref="DRAWINGS">FIG. 2</figref>.

0049Referring to <figref idref="DRAWINGS">FIG. 2</figref>, in a nonvolatile memory device <b>1</b> according to an exemplary embodiment of the present inventive concept, a cell array region I and a connection region II are defined on a substrate <b>110</b>.

0050The cell array region I is a region where a plurality of nonvolatile memory cells are formed, and the connection region II is a region that is disposed between the cell array region I and a peripheral circuit region (not illustrated). As described later, in the connection region II, a plurality of vertical wirings and pads for routing a plurality of laminated electrodes (in other words, word lines) are formed. Further, the connection region II may include a first recess region for connecting a plurality of gate electrodes, vertical wirings, and pads and a second recess region for stable processing.

0051Referring to <figref idref="DRAWINGS">FIGS. 2 to 5</figref>, the cell array region I will be first described.

0052In the cell array region I of the substrate <b>110</b>, a plurality of insulating patterns <b>112</b>, first electrodes LSL, WL<b>0</b> to WLn, and USL (where, n is a natural number), channel patterns <b>115</b>, tunnel layers <b>121</b>, trap layers <b>122</b>, block layers <b>351</b>, and bit lines BL<b>0</b> to BL<b>2</b> are formed.

0053The plurality of insulating patterns <b>112</b> may be sequentially laminated on the substrate <b>110</b> to be spaced apart from each other in the second direction D<b>2</b>. As illustrated in <figref idref="DRAWINGS">FIG. 4</figref>, the respective insulating patterns <b>112</b> may be formed to extend lengthwise in the first direction D<b>1</b>. The insulating patterns <b>112</b> may be made of, but are not limited to, oxide.

0054The plurality of first electrodes LSL, WL<b>0</b> to WLn, and USL may be deposited between the plurality of insulating patterns <b>112</b>. The plurality of first electrodes LSL, WL<b>0</b> to WLn, and USL may be formed lengthwise in the first direction D<b>1</b>, and may be laminated in the second direction D<b>2</b>. The plurality of first electrodes LSL, WL<b>0</b> to WLn, and USL as laminated above are called a first electrode structure <b>211</b>.

0055A nonvolatile memory cell TS<b>1</b> may be defined in a region where the plurality of channel patterns <b>115</b> and the plurality of first electrodes LSL, WL<b>0</b> to WLn, and USL cross each other.

0056The plurality of channel patterns <b>115</b> are formed to extend lengthwise in the second direction D<b>2</b>, and the plurality of first electrodes LSL, WL<b>0</b> to WLn, and USL are formed to extend lengthwise in the first direction D<b>1</b>. Specifically, the plurality of channel patterns <b>115</b> are disposed on the substrate <b>110</b> in the form of pillars, and are formed to penetrate the plurality of laminated insulating patterns <b>112</b>. The plurality of first electrodes LSL, WL<b>0</b> to WLn, and USL may be formed between the plurality of laminated insulating patterns <b>112</b>. The plurality of first electrodes LSL, WL<b>0</b> to WLn, and USL may be formed to cross the plurality of channel patterns <b>115</b>. Although it is illustrated that the plurality of first electrodes LSL, WL<b>0</b> to WLn, and USL have the same thickness, they may have different thicknesses from each other.

0057For example, the plurality of channel patterns <b>115</b> may be made of, but are not limited to, a semiconductor material such as single crystalline silicon. The plurality of first electrodes LSL, WL<b>0</b> to WLn, and USL may be formed of a conductive material, and for example, may be formed of, but are not limited to, a conductive material, such as tungsten (W), cobalt (Co), and nickel (Ni), or a semiconductor material such as silicon.

0058The tunnel layers <b>121</b> and the trap layers <b>122</b> may be formed on side walls of the channel patterns <b>115</b>. The tunnel layers <b>1</b>.<b>21</b> and the trap layers <b>122</b> may be disposed between the first electrodes LSL, WL<b>0</b> to WLn, and USL and the channel patterns <b>115</b>. Specifically, for example, the tunnel layers <b>121</b> and the trap layers <b>122</b> may be formed to penetrate the plurality of insulating patterns <b>112</b> along the channel patterns <b>115</b>.

0059The tunnel layer <b>121</b> is a portion through which a charge passes, and for example, may be formed of a silicon oxide film or a double layer composed of a silicon oxide film and a silicon nitride film.

0060The trap layer <b>122</b> is a portion in which a charge that has passed through the tunnel layer <b>121</b> is stored. For example, the trap layer <b>122</b> may be formed of a nitride film or a high-k film. The nitride film may include, for example, at least one of silicon nitride, silicon oxynitride, hafnium oxynitride, zirconium oxynitride, hafnium silicon oxynitride, and hafnium aluminum oxynitride. The high-k film may include, for example, at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

0061Further, a block layer <b>351</b> may be disposed between the plurality of channel patterns <b>115</b> and the plurality of first electrodes LSL, WL<b>0</b> to WLn, and USL. The block layer <b>351</b> may be formed to extend lengthwise in the first direction D<b>1</b>. Further, the block layer <b>351</b> may be formed in a zigzag manner in the second direction D<b>2</b>.

0062As illustrated in <figref idref="DRAWINGS">FIG. 5</figref>, the block layer <b>351</b> may be formed between the insulating pattern (<b>112</b><i>a </i>in <figref idref="DRAWINGS">FIG. 5</figref>) disposed on an upper side and the electrode (WL<b>1</b> in <figref idref="DRAWINGS">FIG. 5</figref>), between the insulating pattern (<b>112</b><i>b </i>in <figref idref="DRAWINGS">FIG. 5</figref>) disposed on a lower side and the electrode WL<b>1</b>, and between the channel pattern <b>115</b> (or trap layer <b>122</b>) and the electrode WL<b>1</b>. In other words, the block layer <b>351</b> may be conformally formed depending on the shapes of the insulating patterns <b>112</b><i>a </i>and <b>112</b><i>b </i>and the channel pattern <b>115</b>.

0063The block layer <b>351</b> may be a single layer or a multilayer. The block layer <b>351</b> may include silicon oxide or an insulating metal oxide having a higher dielectric constant than the silicon oxide. For example, the block layer <b>351</b> may be formed of a multi-layer that is laminated by a high-k material, such as aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, or dysprosium scandium oxide, or a combination thereof.

0064The configuration of the tunnel layer <b>121</b>, the trap layer <b>122</b>, and the block layer <b>351</b> as illustrated in <figref idref="DRAWINGS">FIG. 5</figref> is merely exemplary. For example, the tunnel layer <b>121</b>, the trap layer <b>122</b>, and the block layer <b>351</b> may be disposed along the lengthwise direction of the channel pattern <b>115</b>.

0065On the other hand, as illustrated in <figref idref="DRAWINGS">FIGS. 3 and 4</figref>, the plurality of channel patterns <b>115</b> may be disposed to be separate from each other in the first direction D<b>1</b> and in the third direction D<b>3</b>. In other words, the plurality of channel patterns <b>115</b> may be disposed in a matrix form. In <figref idref="DRAWINGS">FIGS. 3 and 4</figref>, the plurality of channel patterns <b>115</b> are illustrated to be disposed 3×3, but are not limited thereto.

0066In the substrate <b>110</b>, a common source line CSL may be formed lengthwise along the first direction D<b>1</b>.

0067Separation spaces T may be formed in the plurality of channel patterns <b>115</b> disposed in the third direction D<b>3</b>. The plurality of channel patterns <b>115</b> disposed in the third direction D<b>3</b> may be electrically connected with each other by the bit lines BL<b>0</b> to BL<b>2</b>.

0068Referring again to <figref idref="DRAWINGS">FIGS. 2 and 6</figref>, the connection region II will be described.

0069In the connection region II, the plurality of first electrodes LSL, WL<b>0</b> to WLn, and USL (in other words, the first electrode structure <b>211</b>), the plurality of insulating patterns <b>112</b>, a first recess R<b>1</b>, a second recess R<b>2</b>, a plurality of vertical wirings <b>171</b>, a plurality of connection pads <b>175</b>, a plurality of supports SP, and interlayer insulating film <b>141</b> may be formed.

0070As illustrated, the plurality of first electrodes LSL, WL<b>0</b> to WLn, and USL, and the plurality of insulating patterns <b>112</b> may extend from the cell array region I.

0071The interlayer insulating film <b>141</b> may be formed to fill the first recess R<b>1</b> and the second recess R<b>2</b> therewith. The interlayer insulating film <b>141</b> may be formed of, but is not limited to, SiO2, SiN, SiON, or a low-k insulating film (for example, SiOF or SiOC).

0072The plurality of supports SP are provided to penetrate the plurality of first electrodes LSL, WL<b>0</b> to WLn, and USL. The supports SP may be formed to extend from the substrate <b>110</b> to the upper side (in other words, extend in the second direction D<b>2</b>). The supports SP may be in a pillar shape formed of an insulating material. The supports SP may be formed to be spaced apart from the plurality of channel patterns <b>115</b>.

0073On the other hand, the first recess R<b>1</b> may be disposed between the cell array region I and the second recess R<b>2</b>. In other words, the first recess R<b>1</b> may be disposed closer to the cell array region I than the second recess R<b>2</b>.

0074The plurality of first electrodes LSL, WL<b>0</b> to WLn, and USL which are exposed by the first recess R<b>1</b> and the second recess R<b>2</b> may be in a step shape. In other words, the electrode disposed on the lower side (for example, WL<b>1</b>) may project further into the recesses R<b>1</b> and R<b>2</b> than the electrode disposed on the upper side (for example, WL<b>2</b>). The length of the electrode WL<b>1</b> disposed on the lower side may be longer than the length of the electrode WL<b>2</b> disposed on the upper side.

0075As illustrated, the first recess R<b>1</b> may have a shape that becomes narrower as it goes from the upper side to the lower side.

0076The second recess R<b>2</b> may also have a shape that becomes narrower as it goes from the upper side to the lower side. For example, the second recess R<b>2</b> may have substantially the same shape as the first recess R<b>1</b>. In other words, the depth D<b>2</b> of the second recess R<b>2</b> may be substantially the same as the depth D<b>1</b> of the first recess R<b>1</b>. The first recess R<b>1</b> and the second recess R<b>2</b> may be formed at the same height and with the same depth D<b>1</b> or D<b>2</b>.

0077Here, the first recess R<b>1</b> may be a real recess, and the second recess R<b>2</b> may be a dummy recess.

0078Specifically, the first recess R<b>1</b> includes a first side wall surface S<b>1</b> and disposed on one side (for example, a left side) and a second side wall surface S<b>2</b> disposed on the other side (for example, a right side). Further, the second recess R<b>2</b> may include a third side wall surface S<b>3</b> disposed on one side and a fourth side wall surface S<b>4</b> disposed on the other side. The plurality of first electrodes LSL, WL<b>0</b> to WLn, and USL, which are exposed by the first side wall surface S<b>1</b>, may be used, but the plurality of first electrodes LSL, WL<b>0</b> to WLn, and USL which are exposed by the second side wall surface S<b>2</b>, the third side wall surface S<b>3</b>, and the fourth side wall surface S<b>4</b>, may not be used. In other words, the plurality of vertical wirings <b>171</b> are formed on the upper surfaces of the plurality of first electrodes LSL, WL<b>0</b> to WLn, and USL exposed by the first side wall surface S<b>1</b>, but the plurality of vertical wirings <b>171</b> are not formed on the upper surfaces of the plurality of first electrodes LSL, WL<b>0</b> to WLn, and USL exposed by the second side wall surface S<b>2</b>, the third side wall surface S<b>3</b>, and the fourth side wall surface S<b>4</b>. The plurality of connection pads <b>175</b> may be formed to be connected to the plurality of vertical wirings <b>171</b>.

0079The reason why the second recess R<b>2</b> is formed adjacent to the first recess R<b>1</b> is as follows. To be described later, if the second recess R<b>2</b> is not formed, the side wall surface S<b>1</b> or S<b>2</b> of the first recess R<b>1</b> may fall down (e.g., collapse) during a planarization process. However, if the second recess R<b>2</b> is disposed adjacent to the first recess R<b>1</b>, the side wall surface S<b>3</b> or S<b>4</b> of the second recess R<b>2</b>, rather than the sidewall surfaces of the first recess R<b>1</b>, may fall down during the planarization process. Thus, the side wall surface S<b>1</b> or S<b>2</b> of the first recess R<b>1</b> may not fall down. In other words, by sacrificing the second recess R<b>2</b>, the first recess R<b>1</b> for forming the plurality of vertical wirings <b>171</b> can be protected. In this way, process stability can be improved in fabricating a three-dimensional (3D) nonvolatile memory device.

0080The unexplained reference numeral <b>111</b> may be a buffer oxide film.

0081<figref idref="DRAWINGS">FIG. 7</figref> is a cross-sectional view of a nonvolatile memory device according to an exemplary embodiment of the present inventive concept. <figref idref="DRAWINGS">FIG. 7</figref> may be used in replacement of the nonvolatile memory cell TS<b>1</b> illustrated in <figref idref="DRAWINGS">FIG. 5</figref>. For convenience, a portion of <figref idref="DRAWINGS">FIG. 7</figref> that is different from <figref idref="DRAWINGS">FIG. 5</figref> will be explained.

0082Referring to <figref idref="DRAWINGS">FIG. 7</figref>, in a nonvolatile memory device according to the current embodiment of the present inventive concept, the tunnel layers <b>121</b>, the trap layers <b>122</b>, and the block layers <b>351</b> may be formed on the side walls of the channel patterns <b>115</b>. The tunnel layers <b>121</b>, the trap layers <b>122</b>, and the block layers <b>351</b> may be disposed along the lengthwise direction of the channel patterns <b>115</b>. More specifically, the tunnel layers <b>121</b>, the trap layers <b>122</b>, and the block layers <b>351</b> may be formed to penetrate the plurality of insulating patterns <b>112</b> along the channel patterns <b>115</b>.

0083<figref idref="DRAWINGS">FIG. 8</figref> is a cross-sectional view of a nonvolatile memory device according to an exemplary embodiment of the present inventive concept. <figref idref="DRAWINGS">FIG. 8</figref> may be used in replacement of the nonvolatile memory cell TS<b>1</b> illustrated in <figref idref="DRAWINGS">FIG. 5</figref>. For convenience, a portion of <figref idref="DRAWINGS">FIG. 8</figref> that is different from <figref idref="DRAWINGS">FIG. 5</figref> will be explained.

0084Referring to <figref idref="DRAWINGS">FIG. 8</figref>, in a nonvolatile memory device according to the current embodiment of the present inventive concept, the tunnel layers <b>121</b>, the trap layers <b>122</b>, and the block layers <b>351</b> may be formed between the insulating pattern <b>112</b><i>a </i>disposed on the upper side and the electrode WL<b>1</b>, between the insulating pattern <b>112</b><i>b </i>disposed on the lower side and the electrode WL<b>1</b>, and between the channel pattern <b>115</b> (or trap layer <b>122</b>) and the electrode WL<b>1</b>. In other words, the block layer <b>351</b> may be conformally formed depending on the shapes of the insulating patterns <b>112</b><i>a </i>and <b>112</b><i>b </i>and the channel pattern <b>115</b>.

0085<figref idref="DRAWINGS">FIG. 9</figref> is a cross-sectional view of a nonvolatile memory device according to an exemplary embodiment of the present inventive concept. For convenience, a portion of <figref idref="DRAWINGS">FIG. 9</figref> that is different from the portion already explained using <figref idref="DRAWINGS">FIGS. 1 to 6</figref> will be explained.

0086Referring to <figref idref="DRAWINGS">FIG. 9</figref>, a nonvolatile memory device <b>4</b> according to the current embodiment of the present inventive concept may include a mold pattern <b>199</b>, a first electrode structure <b>211</b>, a second electrode structure <b>211</b><i>a</i>, a first recess R<b>1</b>, a third recess R<b>3</b>, and a fourth recess R<b>4</b>.

0087The mold pattern <b>199</b> is formed on the substrate <b>110</b>, and includes a trench <b>199</b><i>a</i>. For example, the mold pattern <b>199</b> may include, but is not limited to, at least one of SiO2, SiN, SiON, and a low-k insulating film.

0088The first electrode structure <b>211</b> may include a plurality of first laminated electrodes LSL and WL<b>0</b> to WLn. A plurality of insulating patterns <b>112</b> may be disposed between the plurality of first electrodes LSL and WL<b>0</b> to WLn. The first electrode structure <b>211</b> may be formed along a bottom and a side wall of the trench <b>199</b><i>a </i>and an upper surface of the mold pattern <b>199</b>.

0089The second electrode structure <b>211</b><i>a </i>may include a plurality of second laminated electrodes WLn+1 to WLn+n and USL. The plurality of insulating patterns <b>112</b> may be disposed between the plurality of second electrodes WLn+1 to WLn+n and USL. The second electrode structure <b>211</b><i>a </i>may be formed on an upper surface of the first electrode structure <b>211</b>. Here, it is illustrated that the number of the plurality of first laminated electrodes LSL and WL<b>0</b> to WLn and the number of the plurality of second laminated electrodes WLn+1 to WLn+n and USL are equal to each other, but the numbers of the respective electrodes are not limited thereto.

0090On the other hand, the first electrode structure <b>211</b> and the second electrode structure <b>211</b><i>a </i>may extend from the cell array region I. In other words, in the cell array region I, a nonvolatile memory cell may be defined in the first electrode structure <b>211</b> and the second electrode structure <b>211</b><i>a</i>. In the cell array region I, a plurality of channel patterns (not illustrated) that cross the first electrode structure <b>211</b> and the second electrode structure <b>211</b><i>a </i>may be formed.

0091Further, as illustrated in <figref idref="DRAWINGS">FIG. 9</figref>, the upper surface of the first electrode structure <b>211</b> and the uppermost surface of the second electrode structure <b>211</b><i>a </i>may be connected to each other.

0092The first recess R<b>1</b> may be formed in the first electrode structure <b>211</b>. The first recess R<b>1</b> may be disposed on the upper surface of the mold pattern <b>199</b>. The third recess R<b>3</b> may be formed in the second electrode structure <b>211</b><i>a</i>. The fourth recess R<b>4</b> may be disposed between the first recess R<b>1</b> and the third recess R<b>3</b>. In other words, the third recess R<b>3</b> may be disposed between the cell array region I and the fourth recess R<b>4</b>. In other words, the third recess R<b>3</b> may be disposed closer to the cell array region I than the fourth recess R<b>4</b>.

0093The plurality of first electrodes LSL and WL<b>0</b> to WLn and the plurality of second electrodes WLn+1 to WLn+n and USL, which are exposed by the first recess R<b>1</b>, the third recess R<b>3</b>, and the fourth recess R<b>4</b>, may be in a step shape. For example, the electrode disposed on the lower side (for example, WL<b>1</b>) may project further into the recess R<b>1</b> than the electrode disposed on the upper side (for example, WL<b>2</b>). The length of the electrode WL<b>1</b> disposed on the lower side may be longer than the length of the electrode WL<b>2</b> disposed on the upper side.

0094As illustrated in <figref idref="DRAWINGS">FIG. 9</figref>, the first recess R<b>1</b>, the third recess R<b>3</b>, and the fourth recess R<b>4</b> may have a shape that becomes narrower as they go from the upper side to the lower side. For example, the first recess R<b>1</b>, the third recess R<b>3</b>, and the fourth recess R<b>4</b> may have substantially the same shape. In other words, the depth D<b>1</b> of the first recess R<b>1</b>, the depth D<b>3</b> of the third recess R<b>3</b>, and the depth D<b>4</b> of the fourth recess R<b>4</b> may be substantially equal to each other. The first recess R<b>1</b>, the third recess R<b>3</b>, and the fourth recess R<b>4</b> may be formed at the same height and with the same depth D<b>1</b>, D<b>3</b>, or D<b>4</b>.

0095Here, the first recess R<b>1</b> and the third recess R<b>3</b> may be real recesses, and the second recess R<b>2</b> may be a dummy recess.

0096Specifically, the first recess R<b>1</b> includes a first side wall surface S<b>1</b> disposed on one side (for example, a left side) and a second side wall surface S<b>2</b> disposed on the other side (for example, a right side). Further, the third recess R<b>3</b> may include a fifth side wall surface S<b>5</b> disposed on one side and a sixth side wall surface S<b>6</b> disposed on the other side. The fourth recess R<b>4</b> may include a seventh side wall surface S<b>7</b> disposed on one side and an eighth side wall surface S<b>8</b> disposed on the other side.

0097The plurality of first electrodes LSL and WL<b>0</b> to WLn, which are exposed by the first side wall surface S <b>1</b>, and the plurality of second electrodes WLn+1 to WLn+n and USL, which are exposed by the fifth side wall surface S<b>5</b>, may be used. The plurality of first electrodes LSL and WL<b>0</b> to WLn, which are exposed by the second side wall surface S<b>2</b>, and the plurality of second electrodes WLn+1 to WLn+n and USL, which are exposed by the sixth side wall surface S<b>6</b>, the seventh side wall surface S<b>7</b>, and the eighth side wall surface S<b>8</b>, may not be used. In other words, a plurality of vertical wirings <b>171</b> and <b>171</b><i>a </i>are formed on the upper surfaces of the plurality of first electrodes LSL and WL<b>0</b> to WLn exposed by the first side wall surface Si and the plurality of second electrodes WLn+1 to WLn+n and USL exposed by the fifth side wall surface S<b>5</b>. A plurality of connection pads <b>175</b> and <b>175</b><i>a </i>may be formed to be connected to the plurality of vertical wirings <b>171</b> and <b>171</b><i>a. </i>

0098The reason why the fourth recess R<b>4</b> is formed adjacent to the third recess R<b>3</b> is as follows. To be described later, if the fourth recess R<b>4</b> is not formed, the side wall surface S<b>5</b> or S<b>6</b> of the third recess R<b>3</b> may fall down (e.g., collapse) during a planarization process. However, if the fourth recess R<b>4</b> is disposed adjacent to the third recess R<b>3</b>, the side wall surface S<b>7</b> or S<b>8</b> of the fourth recess R<b>4</b>, rather than the sidewall surfaces of the third recess R<b>3</b>, may fall down during the planarization process. Thus, the side wall surface S<b>5</b> or S<b>6</b> of the third recess R<b>3</b> may not fall down. In other words, by sacrificing the fourth recess R<b>4</b>, the third recess R<b>3</b> for forming the plurality of vertical wirings <b>171</b><i>a </i>can be protected. In this way, process stability can be improved in fabricating a 3D nonvolatile memory device.

0099<figref idref="DRAWINGS">FIG. 10</figref> is a cross-sectional view of a nonvolatile memory device according to an exemplary embodiment of the present inventive concept. For convenience, a portion of <figref idref="DRAWINGS">FIG. 10</figref> that is different from <figref idref="DRAWINGS">FIG. 9</figref> will be described.

0100Referring to <figref idref="DRAWINGS">FIG. 10</figref>, a nonvolatile memory device <b>5</b> according to the current embodiment of the present inventive concept may include a mold pattern <b>199</b>, a first electrode structure <b>211</b>, a second electrode structure <b>211</b><i>a</i>, a first recess R<b>1</b>, a second recess R<b>2</b>, a third recess R<b>3</b>, and a fourth recess R<b>4</b>.

0101The first recess R<b>1</b> and the second recess R<b>2</b> may be formed in the first electrode structure <b>211</b>. The first recess R<b>1</b> and the second recess R<b>2</b> may be disposed on the upper surface of the mold pattern <b>199</b>. The first recess R<b>1</b> may be disposed between the cell array region I and the second recess R<b>2</b>. In other words, the first recess R<b>1</b> may be disposed closer to the cell array region I than the second recess R<b>4</b>.

0102The plurality of first electrodes LSL and WL<b>0</b> to WLn, which are exposed by the first recess R<b>1</b> and the second recess R<b>2</b>, may be in a step shape. In other words, the electrode disposed on the lower side (for example, WL<b>1</b>) may project further into the recesses R<b>1</b> and R<b>2</b> than the electrode disposed on the upper side (for example, WL<b>2</b>).

0103The second recess R<b>2</b> may have a shape that becomes narrower as it goes to the lower side. The first recess R<b>1</b> and the second recess R<b>2</b> may be formed at the same height and with the same depth D<b>1</b> or D<b>2</b>. The second recess R<b>2</b> may include a third side wall surface S<b>3</b> disposed on one side and a fourth side wall surface S<b>4</b> disposed on the other side.

0104By sacrificing the second recess R<b>2</b>, the first recess R<b>1</b> for forming the plurality of vertical wirings <b>171</b> can be protected.

0105<figref idref="DRAWINGS">FIG. 11</figref> is a cross-sectional view of a nonvolatile memory device according to an exemplary embodiment of the present inventive concept. For convenience, a portion of <figref idref="DRAWINGS">FIG. 11</figref> that is different from <figref idref="DRAWINGS">FIG. 9</figref> will be explained.

0106Referring to <figref idref="DRAWINGS">FIG. 11</figref>, a nonvolatile memory device <b>6</b> according to the current embodiment of the present inventive concept may include a mold pattern <b>192</b>, a first electrode structure <b>211</b>, a second electrode structure <b>211</b><i>a</i>, a first recess R<b>1</b>, a second recess R<b>2</b>, and a third recess R<b>3</b>. By sacrificing the second recess R<b>2</b>, the first recess R<b>1</b> for forming the plurality of vertical wirings <b>171</b> can be protected.

0107Hereinafter, using <figref idref="DRAWINGS">FIGS. 12 to 17 and 9</figref>, a method for fabricating a nonvolatile memory device according to an exemplary embodiment of the present inventive concept will be described. <figref idref="DRAWINGS">FIGS. 12 to 17</figref> are views of intermediate steps of the method for fabricating a nonvolatile memory device according to the current embodiment of the to present inventive concept.

0108Referring to <figref idref="DRAWINGS">FIG. 12</figref>, a mold pattern <b>199</b> including a trench <b>199</b><i>a </i>is formed on a substrate <b>110</b>.

0109Then, a first electrode structure <b>211</b> and a second electrode structure <b>211</b><i>a </i>are formed in order on the substrate <b>110</b>. The first electrode structure <b>211</b> may be formed along a bottom and a side wall of the trench <b>199</b><i>a </i>and an upper surface of the mold pattern <b>199</b>. The second electrode structure <b>211</b><i>a </i>may be formed on an upper surface of the first electrode structure <b>211</b>. The first electrode structure <b>211</b> may include a plurality of first laminated electrodes LSL and WL<b>0</b> to WLn. A plurality of insulating patterns <b>112</b> may be disposed between the plurality of first electrodes LSL and WL<b>0</b> to WLn. The second electrode structure <b>211</b><i>a </i>may include a plurality of second laminated electrodes WLn+1 to WLn+n and USL. The plurality of insulating patterns <b>112</b> may be disposed between the plurality of second electrodes WLn+1 to WLn+n and USL.

0110Referring to <figref idref="DRAWINGS">FIG. 13</figref>, a part of the second electrode structure <b>211</b><i>a </i>that is located on the mold pattern <b>199</b> is removed. Accordingly, a part of the first electrode structure <b>211</b> may be exposed.

0111Referring to <figref idref="DRAWINGS">FIG. 14</figref>, a planarization process is performed. As a result, the uppermost surface of the first electrode structure <b>211</b> and the uppermost surface of the second electrode structure <b>211</b><i>a </i>may be connected to each other.

0112Referring to <figref idref="DRAWINGS">FIG. 15</figref>, the first recess R<b>1</b> is formed in the first electrode structure <b>211</b>, and the third recess R<b>3</b> and the fourth recess R<b>4</b> are formed in the second electrode structure <b>211</b><i>a. </i>

0113Specifically, the first recess R<b>1</b> may be disposed on the upper surface of the mold pattern <b>199</b>. The fourth recess R<b>4</b> may be disposed between the first recess R<b>1</b> and the third recess R<b>3</b>. In other words, the third recess R<b>3</b> may be disposed between the cell array region I and the fourth recess R<b>4</b>. In other words, the third recess R<b>3</b> may be disposed closer to the cell array region I than the fourth recess R<b>4</b>.

0114The plurality of first electrodes LSL and WL<b>0</b> to WLn and the plurality of second electrodes WLn+1 to WLn+n and USL, which are exposed by the first recess R<b>1</b>, the third recess R<b>3</b>, and the fourth recess R<b>4</b>, may be in a step shape. For example, the electrode disposed on the lower side (for example, WL<b>1</b>) may project further into the recesses R<b>1</b> and R<b>2</b> than the electrode disposed on the upper side (for example, WL<b>2</b>).

0115A method for forming the first recess R<b>1</b>, the third recess R<b>3</b>, and the fourth recess R<b>4</b> according to an exemplary embodiment of the present inventive concept will be described later with reference to <figref idref="DRAWINGS">FIGS. 18 to 21</figref>.

0116Referring to <figref idref="DRAWINGS">FIG. 16</figref>, an interlayer insulating film <b>141</b> is formed on the first electrode structure <b>211</b> and the second electrode structure <b>211</b><i>a</i>. The interlayer insulating film <b>141</b> may be conformally formed depending on the shapes of the first recess R<b>1</b>, the third recess R<b>3</b>, and the fourth recess R<b>4</b>, but the forming of the interlayer insulating film <b>141</b> is not limited thereto.

0117Referring to <figref idref="DRAWINGS">FIG. 17</figref>, a part of the interlayer insulating film <b>141</b> is removed through a planarization process. Through the planarization process, the upper surface of the first electrode structure <b>211</b> and the upper surface of the second electrode structure <b>211</b><i>a </i>may be exposed. The interlayer insulating film <b>141</b> may remain in the first recess R<b>1</b>, the third recess R<b>3</b>, and the fourth recess R<b>4</b>.

0118As described above, if the fourth recess R<b>4</b> is disposed adjacent to the third recess R<b>3</b>, the side wall surface S<b>7</b> or S<b>8</b> of the fourth recess R<b>4</b>, rather than the sidewall surface of the third recess R<b>3</b>, may fall down (e.g., collapse) during the planarization process. Thus, the side wall surface S<b>5</b> or S<b>6</b> of the third recess R<b>3</b> may not fall down. In other words, by sacrificing the fourth recess R<b>4</b>, the third recess R<b>3</b> for forming the plurality of vertical wirings <b>171</b><i>a </i>can be protected. In this way, process stability can be improved in fabricating a 3D nonvolatile memory device.

0119Referring again to <figref idref="DRAWINGS">FIG. 9</figref>, a plurality of vertical wirings <b>171</b> and <b>171</b><i>a </i>are formed on the upper surfaces of the plurality of first electrodes LSL and WL<b>0</b> to WLn exposed by the first side wall surface S<b>1</b> and the plurality of second electrodes WLn+1 to WLn+n and USL exposed by the fifth side wall surface S<b>5</b>. A plurality of connection pads <b>175</b> and <b>175</b><i>a </i>may be formed to be connected to the plurality of vertical wirings <b>171</b> and <b>171</b><i>a. </i>

0120Referring to <figref idref="DRAWINGS">FIGS. 18 to 21</figref>, a recess forming step (see <figref idref="DRAWINGS">FIG. 15</figref>) will be described in detail. <figref idref="DRAWINGS">FIGS. 18 to 21</figref> are views of intermediate steps of a recess forming step, according to an exemplary embodiment of the present inventive concept. <figref idref="DRAWINGS">FIGS. 18 to 21</figref> show a process of forming the first recess R<b>1</b>.

0121Referring to <figref idref="DRAWINGS">FIG. 18</figref>, the first electrode structure <b>211</b> is formed on the mold pattern <b>199</b>. As described above, the first electrode structure <b>211</b> may include the plurality of first laminated electrodes LSL and WL<b>0</b> to WLn. The plurality of insulating patterns <b>112</b> may be arranged between the plurality of first electrodes LSL and WL<b>0</b> to WLn. The plurality of first electrodes LSL and WL<b>0</b> to WLn and the insulating patterns <b>112</b> may have different wet etching characteristics.

0122A mask pattern <b>200</b> may be formed on the first electrode structure <b>211</b>.

0123Referring to <figref idref="DRAWINGS">FIG. 19</figref>, a first etching process is performed using the mask pattern <b>200</b>. As a result, a part of the region exposed by the mask pattern <b>200</b> may be isotropically etched by the mask pattern <b>200</b> as illustrated. In other words, the plurality of the first electrodes LSL and WL<b>0</b> to WLn and the insulating patterns <b>112</b> may be isotropically etched to expose the substrate <b>110</b>. The first etching process may be a wet etching process having the same etching rate with respect to the plurality of first electrodes LSL and WL<b>0</b> to WLn and the insulating patterns <b>112</b>. The etching rate may include a process error range.

0124Referring to <figref idref="DRAWINGS">FIG. 20</figref>, a second etching process is performed. As a result, the plurality of first electrodes LSL and WL<b>0</b> to WLn may be isotropically etched. The second etching process may include a wet etching process having a higher etch rate with respect to the plurality of first electrodes LSL and WL<b>0</b> to WLn than the insulating patterns <b>112</b>. In <figref idref="DRAWINGS">FIG. 20</figref>, it is illustrated that the insulating patterns <b>112</b> are not etched during the second etching process. In practice, however, a part of the insulating patterns <b>112</b> may be etched.

0125On the other hand, <figref idref="DRAWINGS">FIGS. 19 and 20</figref> illustrate that the first etching process and the second etching process are continuously performed in order. However, the etching order is not limited thereto, and the first etching process and the second etching process may be simultaneously performed.

0126Referring to <figref idref="DRAWINGS">FIG. 21</figref>, the mask pattern <b>200</b> is removed.

0127Then, a third etching process is performed. The insulating patterns <b>112</b> may be anisotropically etched using the etched first electrodes LSL and WL<b>0</b> to WLn as a mask. The third etching process may be an etch-back process.

0128As a result, the electrode disposed on the lower side (for example, WL<b>1</b>) may to project further into the recess R<b>1</b> than the electrode disposed on the upper side (for example, WL<b>2</b>).

0129<figref idref="DRAWINGS">FIG. 22</figref> is a block diagram illustrating a memory system according to an exemplary embodiment of the present inventive concept.

0130Referring to <figref idref="DRAWINGS">FIG. 22</figref>, a memory system <b>1000</b> includes a nonvolatile memory device <b>1100</b> and a controller <b>1200</b>.

0131The nonvolatile memory device <b>1100</b> may be at least one of nonvolatile memory devices according to the exemplary embodiments of the present inventive concept described with reference to <figref idref="DRAWINGS">FIGS. 1 to 11</figref>.

0132The controller <b>1200</b> is connected to a host and the nonvolatile memory device <b>1100</b>. The controller <b>1200</b> may be configured to access the nonvolatile memory device <b>1100</b> in response to a request from the host. For example, the controller <b>1200</b> may be configured to control read, write, erase, and background operations of the nonvolatile memory device <b>1100</b>. The controller <b>1200</b> may be configured to provide an interface between the nonvolatile memory device <b>1100</b> and the host. Further, the controller <b>1200</b> may be configured to drive firmware to control the nonvolatile memory device <b>1100</b>.

0133The controller <b>1200</b> may further include constituent elements, such as a random access memory (RAM), a central processing unit, a host interface, and a memory interface. The RAM is used as at least one of an operating memory of the central processing unit, a cache memory between the nonvolatile memory device <b>1100</b> and the host, and a buffer memory between the nonvolatile memory device <b>1100</b> and the host. The processing unit controls the overall operation of the controller <b>1200</b>.

0134The host interface includes protocols for performing data exchange between the host and the controller <b>1200</b>. Exemplarily, the controller <b>1200</b> is configured to communicate with an external device (e.g., host) through at least one of various interface protocols, such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, and an integrated drive electronics (IDE) protocol. The memory interface interfaces with the nonvolatile memory device <b>1100</b>. For example, the memory interface includes a NAND interface or a NOR interface.

0135The memory system <b>1000</b> may be configured to additionally include an error correction block. The error correction block is configured to detect and correct an error of data read from the nonvolatile memory device <b>1100</b> using an error correction code (ECC). Exemplarily, the error correction block may be provided as a constituent element of the nonvolatile memory device <b>1100</b>.

0136The controller <b>1200</b> and the nonvolatile memory device <b>1100</b> may be integrated into one semiconductor device. For example, the controller <b>1200</b> and the nonvolatile memory device may be integrated into one semiconductor device to configure a memory card, such as a PC card ((e.g., personal computer memory card international association (PCMIA)), a compact flash (CF) card, a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, reduced size (RS)-MMC, MMCmicro), a secure digital card (SD, miniSD, microSD, or secure digital high capacity (SDHC)), a universal flash storage device (UFS), or the like.

0137The controller <b>1200</b> and the nonvolatile memory device <b>1100</b> may be integrated into one semiconductor device to configure a solid state drive (SSD). The SSD includes a storage device that is configured to store data in a semiconductor memory. In the case where the memory system <b>1000</b> is used as the SSD, the operating speed of the host that is connected to the memory system <b>1000</b> can be improved.

0138As another example, the memory system <b>1000</b> may be provided as one of various constituent elements of electronic devices, such as a computer, an ultra mobile PC (UMPC), a work station, a net-book, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box, a digital camera, a 3D television receiver, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device that can transmit and receive information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, a radio frequency identification (RFID) device, or one of various constituent elements constituting a computing system.

0139Exemplarily, the nonvolatile memory device <b>1100</b> or the memory system <b>1000</b> may be mounted as various types of packages. For example, the nonvolatile memory device <b>1100</b> or the memory system <b>1000</b> may be packaged and mounted as package on package (PoP), ball grid array (BGA), chip scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in line package (CERDIP), plastic metric quad flat pack (MQFP), thin quad flat pack (TQFP), small outline integrated circuit (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system in package (SIP), multi chip package (MCP), wafer-level fabricated package (WFP), wafer-level processed stack package (WSP), or the like.

0140<figref idref="DRAWINGS">FIG. 23</figref> is a block diagram illustrating an application example of the memory system of <figref idref="DRAWINGS">FIG. 22</figref>.

0141Referring to <figref idref="DRAWINGS">FIG. 23</figref>, a memory system <b>2000</b> includes a non-volatile memory device <b>2100</b> and a controller <b>2200</b>. The nonvolatile memory device <b>2100</b> includes a plurality of nonvolatile memory chips. The plurality of memory chips are divided into a plurality of groups. The respective groups of the plurality of nonvolatile memory chips are configured to communicate with the controller <b>2200</b> through one common channel. For example, it is illustrated that the plurality of nonvolatile memory chips communicate with the controller <b>2200</b> through first to k-th channels CH<b>1</b> to CHk.

0142The respective nonvolatile memory chips may be configured in the same manner as the nonvolatile memory device as described above with reference to <figref idref="DRAWINGS">FIGS. 1 to 11</figref>.

0143In <figref idref="DRAWINGS">FIG. 23</figref>, it is described that the plurality of nonvolatile memory chips are connected to one channel. However, it is understood that the memory system <b>2000</b> can be modified so that one nonvolatile memory chip is connected to one channel.

0144<figref idref="DRAWINGS">FIG. 24</figref> is a block diagram illustrating a computing system that includes the memory system as described above with reference to <figref idref="DRAWINGS">FIG. 23</figref>.

0145Referring to <figref idref="DRAWINGS">FIG. 24</figref>, a computing system <b>3000</b> includes a central processing unit <b>3100</b>, a RAM <b>3200</b>, a user interface <b>3300</b>, a power supply <b>3400</b>, and a memory system <b>2000</b>.

0146The memory system <b>2000</b> is electrically connected to the central processing unit <b>3100</b>, the RAM <b>3200</b>, the user interface <b>3300</b>, and the power supply <b>3400</b> through a system bus <b>3500</b>. Data which is provided through the user interface <b>3300</b> or is processed by the central processing unit <b>3100</b> is stored in the memory system <b>2000</b>.

0147<figref idref="DRAWINGS">FIG. 24</figref> illustrates that a nonvolatile memory device <b>2100</b> is connected to the system bus <b>3500</b> through the controller <b>2200</b>. However, the nonvolatile memory device <b>2100</b> may be configured to be directly connected to the system bus <b>3500</b>.

0148<figref idref="DRAWINGS">FIG. 24</figref> illustrates that the memory system <b>2000</b> as described above with reference to <figref idref="DRAWINGS">FIG. 23</figref> is provided. However, the memory system <b>2000</b> may be replaced by the memory system <b>1000</b> as described above with reference to <figref idref="DRAWINGS">FIG. 22</figref>.

0149Exemplarily, the computing system <b>3000</b> may be configured to include all the memory systems <b>1000</b> and <b>2000</b> as described above with reference to <figref idref="DRAWINGS">FIGS. 22 and 23</figref>.

0150While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept as defined by the following claims.