Display panel and method of manufacturing the same

CROSS-REFERENCE TO RELATED APPLICATION

0001This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 of Korean Patent Application No. 10-2012-0066249, filed on Jun. 20, 2012, the content of which is herein incorporated by reference.

TECHNICAL FIELD

0002Embodiments of the present disclosure relate to a display panel and a method of manufacturing the same, and more particularly to a display panel that has a reduced pad area connected to an external circuit module and a method of manufacturing the display panel.

DISCUSSION OF THE RELATED ART

0003A display device includes a display panel that displays images and an external circuit module that applies various control signals to the display panel. The display panel and the external circuit module are accommodated in a receiving container, e.g., a chassis. The display panel and the external circuit module are connected to each other by a wiring member, such as a tape carrier package or a flexible printed circuit board.

0004The wiring member is attached to the display panel and the external circuit module. Accordingly, reducing a non-display area of the display panel may be limited due to the presence of the wiring member.

SUMMARY

0005Embodiments of the present disclosure provide a display panel that has a reduced pad area connected to an external circuit module and a method of manufacturing the display panel.

0006An embodiments of the inventive concept provides a display panel includes an array substrate, an opposite substrate facing the array substrate, and a liquid crystal layer disposed between the array substrate and the opposite substrate. The array substrate includes a display area and a non-display area surrounding the display area, and the non-display area including a first non-display area disposed adjacent to a side portion of the display area and a second non-display area other than the first non-display area. The first non-display area overlaps the opposite substrate.

0007The first non-display area includes a wire area adjacent to the display area and a pad area other than the wire area.

0008The array substrate includes a base substrate disposed in the display area, the second non-display area, and the wire area, a thin film transistor disposed on the base substrate in the display area, a pixel electrode connected to the thin film transistor, a signal input pad disposed in the pad area and electrically connected to an external circuit module, a signal wire disposed in the wire area to connect the signal input pad and the thin film transistor. The signal input pad is electrically connected to the external circuit module through a flexible printed circuit board attached on a lower surface of the signal input pad.

0009The array substrate further includes an organic polymer pattern to support the signal input pad, and the signal input pad is disposed on a lower surface of the organic polymer pattern.

0010The display panel further includes a seal pattern disposed between the array substrate and the opposite substrate in the non-display area. At least a portion of the seal pattern overlaps the organic polymer pattern in the first non-display area.

0011The array substrate includes a base substrate disposed in the display area and the non-display area and provided with a thru-hole in the first non-display area, a thin film transistor disposed on the base substrate in the display area, a pixel electrode connected to the thin film transistor, and a signal wire disposed in the first non-display area, electrically connected to the thin film transistor, and filled in the thru-hole. The signal wire is electrically connected to a flexible printed circuit board attached on a lower surface of the array substrate.

0012The array substrate has the same or substantially the same area as the opposite substrate.

0013An embodiment of the inventive concept provides a method of manufacturing a display panel includes forming an array substrate, disposing a liquid crystal layer between the array substrate and an opposite substrate including a common electrode facing the array substrate, and coupling the array substrate to the opposite substrate. The array substrate is formed by at least one of preparing a base substrate that includes a display area and a non-display area surrounding the display area and including a first non-display area disposed adjacent to a side portion of the display area and a second non-display area other than the first non-display area, forming a trench in the first non-display area of the base substrate to be spaced apart from the display area, forming a thin film transistor in the display area of the base substrate and a signal input pad in the trench to be connected to the thin film transistor, and forming a pixel electrode connected to the thin film transistor. After the array substrate is coupled to the opposite substrate, a portion of the base substrate is removed in the first non-display area to expose the signal input pad toward a lower surface of the array substrate.

0014An embodiment of the inventive concept provides a method of manufacturing a display panel includes forming an array substrate, disposing a liquid crystal layer between the array substrate and an opposite substrate including a common electrode facing the array substrate, and coupling the array substrate to the opposite substrate. The array substrate is formed by at least one of preparing a base substrate that includes a display area and a non-display area surrounding the display area and including a first non-display area disposed adjacent to a side portion of the display area and a second non-display area other than the first non-display area, forming a thru-hole in the first non-display area of the base substrate to be spaced apart from the display area, forming a thin film transistor in the display area of the base substrate and a signal wire connected to the thin film transistor and filled in the thru-hole, and forming a pixel electrode connected to the thin film transistor.

0015According to an embodiment, there is provided a display panel comprising an array substrate including a switching element, an opposite substrate parallel with the array substrate, wherein the opposite substrate includes a signal input pad, and a seal pattern between the array substrate and the opposite substrate, wherein the signal input pad connects a driver IC (Integrated Circuit) with the switching element, and wherein the signal input pad is disposed on a bottom surface of the opposite substrate to overlap at least a portion of the seal pattern.

0016The array substrate and the opposite substrate have the same or substantially the same length in a longitudinal direction and overlap each other.

0017According to the embodiments, the array substrate and the opposite substrate have the same or substantially the same area, and the wire member connected to the external circuit module is disposed under the array substrate. Accordingly, the display panel does not need an extra space for the wire member, and thus the non-display area in which no image is displayed may be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

0018The embodiments of the present invention will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:

0019<figref idref="DRAWINGS">FIG. 1</figref> is an exploded perspective view showing a display apparatus according to an exemplary embodiment of the present invention;

0020<figref idref="DRAWINGS">FIG. 2</figref> is a perspective view showing the array substrate of the display panel shown in <figref idref="DRAWINGS">FIG. 1</figref>;

0021<figref idref="DRAWINGS">FIG. 3</figref> is a plan view showing the display panel of <figref idref="DRAWINGS">FIG. 2</figref> before a flexible printed circuit board is attached to the display panel;

0022<figref idref="DRAWINGS">FIG. 4</figref> is an enlarged view showing a portion A of <figref idref="DRAWINGS">FIG. 3</figref>;

0023<figref idref="DRAWINGS">FIG. 5</figref> is an enlarged view showing a portion B of <figref idref="DRAWINGS">FIG. 3</figref>;

0024<figref idref="DRAWINGS">FIG. 6</figref> is a plan view showing a display panel after a flexible printed circuit board is attached to the display panel;

0025<figref idref="DRAWINGS">FIG. 7</figref> is a cross-sectional view taken along a lint I-I′ of <figref idref="DRAWINGS">FIG. 6</figref>;

0026<figref idref="DRAWINGS">FIG. 8</figref> is a cross-sectional view showing the display panel of <figref idref="DRAWINGS">FIG. 7</figref>, wherein a flexible printed circuit board is bent downward;

0027<figref idref="DRAWINGS">FIGS. 9 to 14</figref> are cross-sectional views for describing a method of manufacturing a display apparatus as shown in <figref idref="DRAWINGS">FIGS. 2 and 8</figref>;

0028<figref idref="DRAWINGS">FIG. 15</figref> is a cross-sectional view showing a display panel according to an exemplary embodiment of the present invention;

0029<figref idref="DRAWINGS">FIG. 16</figref> is a cross-sectional view showing a display panel according to an exemplary embodiment of the present invention;

0030<figref idref="DRAWINGS">FIG. 17</figref> is a cross-sectional view showing the display panel of <figref idref="DRAWINGS">FIG. 16</figref>, wherein a flexible printed circuit board is bent downward; and

0031<figref idref="DRAWINGS">FIGS. 18 to 21</figref> are cross-sectional view for describing a method of manufacturing a display panel as shown in <figref idref="DRAWINGS">FIGS. 16 and 17</figref>.

DETAILED DESCRIPTION

0032It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. As used herein, the singular forms, “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

0033Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein the same reference numerals may be used to denote the same or substantially the same elements throughout the specification and the drawings.

0034<figref idref="DRAWINGS">FIG. 1</figref> is an exploded perspective view showing a display apparatus according to an exemplary embodiment of the present invention.

0035Referring to <figref idref="DRAWINGS">FIG. 1</figref>, the display apparatus includes a display panel <b>100</b>, a backlight unit <b>200</b>, an upper cover <b>410</b>, and a lower cover <b>420</b>.

0036According to an embodiment, the display panel <b>100</b> includes various display panels, such as a liquid crystal display panel, an electrophoretic display panel, or an electrowetting display panel. Hereinafter, an example where the display panel <b>100</b> is a liquid crystal display panel is described.

0037The display panel <b>100</b> has a rectangular plate shape with long sides and short sides and includes a display area DA where images are displayed and a non-display area NDA adjacent to the display area DA. The display panel <b>100</b> includes an array substrate <b>110</b>, an opposite substrate <b>120</b> facing the array substrate <b>110</b>, and a liquid crystal layer between the array substrate <b>110</b> and the opposite substrate <b>120</b>. The display panel <b>100</b> further includes polarizing plates that are respectively attached to an outer surface of the array substrate <b>110</b> and an outer surface of the opposite substrate <b>120</b>.

0038The array substrate <b>110</b> includes a plurality of pixels arranged in the display area DA in a matrix form. Each pixel includes a plurality of sub-pixels having different colors from each other. For instance, each sub-pixel has red, green, blue, yellow, or white. Light exiting from each sub-pixel has one of red, green, blue, yellow, and white. Each pixel includes a gate line, a data line insulated from the gate line and crossing the gate line, and a pixel electrode. Each pixel is electrically connected to the gate line and the data line. Each pixel includes a thin film transistor electrically connected to the pixel electrode. The thin film transistor switches on or off a driving signal applied to the pixel electrode.

0039A seal pattern is disposed in the non-display area of the array substrate <b>110</b> and couples the array substrate <b>110</b> to the opposite substrate <b>120</b>.

0040A signal input pad is disposed in the non-display area NDA of the array substrate <b>110</b> and electrically connected to the thin film transistor. The signal input pad is connected to a flexible printed circuit board <b>140</b> on which a driver IC (Integrated Circuit) <b>141</b> is mounted and the flexible printed circuit board <b>140</b> is connected to an external circuit module. The driver IC <b>141</b> receives various control signals from the external circuit module and outputs the driving signal to the thin film transistor in response to the control signals to drive the display panel <b>100</b>.

0041The driver IC <b>141</b> is disposed on a lower surface of the array substrate <b>110</b>, which faces the backlight unit <b>200</b>.

0042The opposite substrate <b>120</b> includes color filters, each of which realizes a predetermined color using light provided from the backlight unit <b>200</b>, and a common electrode disposed on the color filters and facing the pixel electrode. Each color filter has one color of red, green, and blue and is formed by a deposition or coating process. According to an exemplary embodiment, the color filters are disposed on the opposite substrate <b>120</b>, but the embodiments of the present invention should not be limited thereto or thereby. Alternatively, the color filters are disposed on the array substrate <b>110</b>.

0043The liquid crystal layer includes liquid crystal molecules arranged in a specific direction in response to an electric field generated by voltages respectively applied to the pixel electrode and the common electrode. The liquid crystal layer controls a transmittance of light passing through the liquid crystal molecules, thereby displaying desired images.

0044The backlight unit <b>200</b> is disposed under the display panel <b>100</b>. The backlight unit <b>200</b> includes a light guide plate <b>210</b>, a light source unit <b>220</b> including a plurality of light sources, an optical member <b>230</b>, and a reflective sheet <b>240</b>.

0045The light guide plate <b>210</b> is disposed under the display panel <b>100</b> and guides light emitted from the light source unit <b>220</b> to the display panel <b>100</b>. The light guide plate <b>210</b> overlaps at least the display area DA of the display panel <b>100</b>. The light guide plate <b>210</b> includes an exit surface from which light exits, a lower surface facing the exit surface, and side surfaces connecting the exit surface with the lower surface. At least one of the side surfaces faces the light source unit <b>220</b> and functions as a light incident surface into which light emitted from the light source unit <b>220</b> is incident and a side surface facing the light incident surface functions as a light reflective surface that reflects light.

0046The light source unit <b>220</b> includes a printed circuit board <b>222</b> and the light sources <b>221</b>, e.g., light emitting diodes, mounted on the printed circuit board <b>222</b>. According to an embodiment, the light sources <b>221</b> emit light of different colors from each other. For example, some of the light sources <b>221</b> emit red light, some of the light sources <b>221</b> emit green light, and some of the light sources <b>221</b> emit blue light.

0047The light source unit <b>220</b> is disposed to face at least one side surface of the light guide plate <b>210</b> and provides light to the display panel <b>100</b> through the light guide plate <b>210</b>.

0048The optical member <b>230</b> is disposed between the light guide plate <b>210</b> and the display panel <b>100</b>. The optical member <b>230</b> controls light exiting through the light guide plate <b>210</b> from the light source unit <b>220</b>. The optical member <b>230</b> includes a diffusion sheet <b>236</b>, a prism sheet <b>234</b>, and a protective sheet <b>232</b>, which are sequentially stacked one on another.

0049The diffusion sheet <b>236</b> diffuses light exiting from the light guide plate <b>210</b>. The prism sheet <b>234</b> condenses light diffused by the diffusion sheet <b>236</b> to allow the light to travel in a direction perpendicular or substantially perpendicular to the display panel <b>100</b>. Light exiting from the prism sheet <b>234</b> is vertically incident into the display panel <b>100</b>. The protective sheet <b>232</b> is disposed on the prism sheet <b>234</b> and protects the prism sheet <b>234</b> from external impacts.

0050According to an exemplary embodiment, the optical member <b>230</b> includes one diffusion sheet <b>236</b>, one prism sheet <b>234</b>, and one protective sheet <b>232</b>, but it should not be limited thereto or thereby. Alternatively, a plurality of diffusion sheets <b>236</b>, a plurality of prism sheets <b>234</b>, or a plurality of protective sheets <b>232</b> may be included in the optical member <b>230</b>, or one of the diffusion sheet <b>236</b>, the prism sheet <b>234</b>, and the protective sheet <b>232</b> may be removed from the optical member <b>230</b>.

0051The reflective sheet <b>240</b> is disposed under the light guide plate <b>210</b> and reflects light that leaks from the light guide plate and is not directed to the display panel <b>100</b>. The reflective sheet <b>240</b> includes a light reflective material to reflect light. The reflective sheet <b>240</b> is disposed on the lower cover <b>420</b> and reflects light emitted from the light source unit <b>220</b>. As a result, the reflective sheet <b>240</b> increases the amount of light provided to the display panel <b>100</b>.

0052According to an exemplary embodiment, the light source unit <b>220</b> is disposed to provide light to a side surface of the light guide plate <b>210</b>, but it should not be limited thereto or thereby. Alternatively, the light source unit <b>220</b> is disposed to provide light to a lower surface of the light guide plate <b>210</b>. According to an embodiment, when the light guide plate <b>210</b> is omitted from the backlight unit <b>200</b>, the light source unit <b>220</b> is disposed under the display panel <b>100</b>, so that light emitted from the light source unit <b>220</b> may be directly provided to the display panel <b>100</b>.

0053The upper cover <b>410</b> is disposed on the display panel <b>100</b>. The upper cover <b>410</b> is provided with a display window <b>411</b> that exposes the display area DA of the display panel <b>100</b>. The upper cover <b>410</b> is coupled with the lower cover <b>420</b> to support a front edge portion of the display panel <b>100</b>.

0054The lower cover <b>420</b> is disposed under the backlight unit <b>200</b>. The lower cover <b>420</b> provides a space to accommodate the display panel <b>100</b> and the backlight unit <b>200</b>. The lower cover <b>420</b> is coupled with the upper cover <b>410</b> to accommodate the display panel <b>100</b> and the backlight unit <b>200</b> therein.

0055<figref idref="DRAWINGS">FIG. 2</figref> is a perspective view showing the array substrate of the display panel shown in <figref idref="DRAWINGS">FIG. 1</figref>, <figref idref="DRAWINGS">FIG. 3</figref> is a plan view showing a display panel before a flexible printed circuit board is attached to the display panel according to an embodiment of the present invention, <figref idref="DRAWINGS">FIG. 4</figref> is an enlarged view showing a portion A of <figref idref="DRAWINGS">FIG. 3</figref>, <figref idref="DRAWINGS">FIG. 5</figref> is an enlarged view showing a portion B of <figref idref="DRAWINGS">FIG. 3</figref>, <figref idref="DRAWINGS">FIG. 6</figref> is a plan view showing a display panel after a flexible printed circuit board is attached to the display panel, <figref idref="DRAWINGS">FIG. 7</figref> is a cross-sectional view taken along a lint I-I′ of <figref idref="DRAWINGS">FIG. 6</figref>, and <figref idref="DRAWINGS">FIG. 8</figref> is a cross-sectional view showing a flexible printed circuit board bent downward of the display panel of <figref idref="DRAWINGS">FIG. 7</figref>.

0056Referring to <figref idref="DRAWINGS">FIGS. 2 to 8</figref>, the display panel <b>100</b> includes the display area DA and the non-display area NDA surrounding the display area DA. The non-display area NDA includes a first non-display area NDA-<b>1</b> including the pad area PA and a second non-display area NDA-<b>2</b> other than the first non-display area NDA-<b>1</b>.

0057The display panel <b>100</b> includes the array substrate <b>110</b>, the opposite substrate <b>120</b> facing the array substrate <b>110</b>, and the liquid crystal layer <b>130</b> disposed between the array substrate <b>110</b> and the opposite substrate <b>120</b>.

0058The array substrate <b>110</b> has a shape corresponding to a shape of the display panel <b>100</b>, and includes the display area DA and the non-display area NDA including the first and second non-display areas NDA-<b>1</b> and NDA-<b>2</b>. The array substrate <b>110</b> includes an upper surface facing the opposite substrate and a lower surface opposite to the upper surface.

0059The pixels are arranged in the display area DA of the array substrate <b>110</b> in the matrix form. Each pixel includes the thin film transistor TFT and the pixel electrode <b>115</b>.

0060The seal pattern SP is disposed in the non-display area NDA of the array substrate <b>110</b>. The seal pattern SP is disposed to surround the display area DA and couples the array substrate <b>110</b> to the opposite substrate <b>120</b> to prevent leakage of the liquid crystal molecules of the liquid crystal layer <b>130</b>. The seal pattern SP has conductivity to allow a common voltage to be applied to the common electrode <b>125</b> of the opposite substrate <b>120</b>.

0061The first non-display area NDA-<b>1</b> of the array substrate <b>110</b> overlaps the opposite substrate <b>120</b> and includes a wire area SA adjacent to the display area DA and a pad area PA other than the wire area SA. The pad area PA and the wire area SA of the array substrate <b>110</b> overlap the opposite substrate <b>120</b>.

0062Signal input pads SIP are disposed in the pad area PA of the array substrate <b>110</b> and electrically connected to corresponding ones of the thin film transistors TFT. The signal input pads SIP are disposed on the lower surface of the array substrate <b>110</b> in the pad area PA.

0063The signal input pads SIP are supported by an organic polymer pattern <b>116</b>. For instance, the signal input pads SIP are disposed on the lower surface of the organic polymer pattern <b>116</b> and supported by a cohesive force between the signal input pads SIP and the organic polymer pattern <b>116</b>.

0064A common voltage pad <b>117</b> is disposed on the upper surface of the organic polymer pattern <b>116</b>. The common voltage pad <b>117</b> contacts the seal pattern SP and applies a common voltage to the common electrode <b>125</b>. The common voltage pad <b>117</b> includes a transparent conductive oxide, e.g., indium tin oxide (ITO) or indium zinc oxide (IZO).

0065The organic polymer pattern <b>116</b> is positioned in the pad area PA and is extended to a portion of the wire area SA. According to an embodiment, the organic polymer pattern <b>116</b> includes a photosensitive resin, e.g., photoresist. The organic polymer pattern <b>116</b> is cured by light to support the signal input pad SIP. According to an embodiment, the organic polymer pattern <b>116</b> includes an organic polymer material, e.g., polyethyleneterephthalate (PET), polyethylenenapthalate (PEN), polycarbonate (PC), polyetherimide (PEI), polyethersulfone (PES), polyetheretherketon (PEEK), or polyimide (PI).

0066Signal wires SL are disposed in the wire area SA of the array substrate <b>110</b> and connect corresponding thin film transistors TFT to corresponding signal input pads SIP.

0067The seal pattern SP overlaps at least a portion of the organic polymer pattern <b>116</b>. Accordingly, a contact area between the signal input pads SIP and the flexible printed circuit boards <b>140</b> on which the driver ICs <b>141</b> are mounted increases. As a contact area or width between the seal pattern SP and the organic polymer pattern <b>116</b> decreases, the area or width of the pad area PA is reduced in the first non-display area NDA-<b>1</b>. Accordingly, the exposed area or width of the signal input pad SIP is reduced, and thus the contact area or width between the signal input pad SIP and the flexible printed circuit boards <b>140</b> on which the drivers IC <b>141</b> are mounted may be decreased. As the contact area or width between the seal pattern SP and the organic polymer pattern <b>116</b> increases, the area or width of the pad area PA is increased in the first non-display area NDA-<b>1</b>. Accordingly, the exposed area or width of the signal input pad SIP is increased, and thus the contact area or width between the signal input pad SIP and the flexible printed circuit boards <b>140</b> on which the driver ICs <b>141</b> are mounted may be increased.

0068The array substrate <b>110</b> includes a first base substrate <b>111</b>, the thin film transistor TFT disposed on the first base substrate <b>111</b> in the display area DA, and the pixel electrode <b>115</b> connected to the thin film transistor TFT.

0069The first base substrate <b>111</b> corresponds to the display area DA and a portion of the non-display area NDA. For instance, the first base substrate <b>111</b> corresponds to the display area DA, the second non-display area NDA-<b>2</b>, and the wire area SA and has a rectangular plate shape with long sides and short sides. The first base substrate <b>111</b> does not overlap the pad area PA.

0070The first base substrate <b>111</b> is formed of a transparent insulating material to transmit light. According to an embodiment, the first base substrate <b>111</b> includes a rigid substrate, such as a glass substrate, a quartz substrate, a glass ceramic substrate, or a crystalline glass substrate, or a flexible substrate, such as a film substrate containing an organic polymer layer, or a plastic substrate. According to an embodiment, material used to form the first base substrate <b>111</b> has high heat-resistance when the first base substrate <b>111</b> is formed.

0071The thin film transistor TFT is disposed on the first base substrate <b>111</b> and includes a semiconductor layer SCL, a gate electrode GE, a source electrode SE, and a drain electrode DE. The gate electrode GE is disposed on the first base substrate <b>111</b>. The thin film transistor TFT further includes a gate insulating layer <b>112</b> that covers the gate electrode GE. The semiconductor layer SCL is disposed on the gate insulating layer <b>112</b>. The source and drain electrodes SE and DE are respectively connected to two ends of the semiconductor layer SCL. According to an exemplary embodiment, the semiconductor layer SCL includes a channel area overlapping the gate electrode GE when viewed in a plan view, a source area contacting the source electrode SE, and a drain area contacting the drain electrode DE. The gate electrode GE of the thin film transistor TFT is connected to the gate line GL through which a scan signal or a gate signal is transmitted to the thin film transistor TFT. The source electrode SE is connected to the data line DL through which the data voltage is supplied to the thin film transistor TFT.

0072The above-described thin film transistor TFT is a bottom gate thin film transistor in which the gate electrode GE is disposed under the semiconductor layer SCL, but the thin film transistor TFT should not be limited to the bottom gate thin film transistor. Alternatively, a top gate thin film transistor in which the gate electrode GE is disposed on the semiconductor layer SCL may be used as the thin film transistor TFT.

0073The protective layer <b>114</b> is disposed on the thin film transistor TFT. The protective layer <b>114</b> is provided with a contact hole CH to expose a portion of the drain electrode DE. According to an embodiment, the protective layer <b>114</b> has a multi-layered structure. For instance, according to an embodiment, the protective layer <b>114</b> includes an inorganic protective layer, which covers the thin film transistor TFT and the gate insulating layer <b>112</b>, and an organic protective layer disposed on the inorganic protective layer. According to an embodiment, the organic protective layer removes and planarizes steps that occur due to the thin film transistor TFT.

0074The pixel electrode <b>115</b> is disposed on the protective layer <b>114</b> and electrically connected to the drain electrode DE through the contact hole CH. The pixel electrode <b>115</b> includes a transparent conductive oxide, such as iridium tin oxide (ITO) or indium zinc oxide (IZO).

0075At least one of the gate line GL and the data line DL, for example, the data line. DL is connected to the signal input pad SIP through the signal wire SL.

0076The flexible printed circuit boards <b>140</b> on which the driver ICs <b>141</b> are mounted contact the lower surfaces of the signal input pads SIP. Since the signal input pads SIP are disposed on the lower surface of the organic polymer pattern <b>116</b>, the flexible printed circuit board <b>141</b> receives various control signals from the external circuit module and outputs driving signals to the thin film transistors TFT through the signal input pads SIP in response to the control signals, thereby resulting in driving the display panel <b>100</b>.

0077The opposite substrate <b>120</b> is disposed in the display area DA and the non-display area NDA. The opposite substrate <b>120</b> includes a second base substrate <b>121</b> and a common electrode <b>125</b> disposed on the second base substrate <b>121</b>. According to an embodiment, the second base substrate <b>121</b> includes a rigid substrate or a flexible substrate similar to the first base substrate <b>111</b>. The common electrode <b>125</b> includes a transparent conductive oxide as the pixel electrode <b>115</b>. The common electrode <b>125</b> applies a common voltage from an external source to each pixel.

0078The liquid crystal layer <b>130</b> includes the liquid crystal molecules. The liquid crystal molecules are arranged in a specific direction by an electric field generated between the pixel electrode <b>115</b> and the common electrode <b>125</b> to control the transmittance of light passing through the liquid crystal layer <b>130</b>. Accordingly, the liquid crystal layer <b>130</b> transmits light provided from the backlight unit <b>200</b> in response to the electric field, and thus the display panel <b>110</b> displays desired images.

0079As described above, the array substrate <b>110</b> and the opposite substrate <b>120</b> have the same or substantially the same size, and the flexible printed circuit boards <b>140</b>, on which the driver ICs <b>141</b> are mounted which output driving signals to drive the display panel <b>100</b>, are attached onto the lower surface of the array substrate <b>110</b> in the pad area PA. Thus, the display apparatus does not need to prepare an extra space for the flexible printed circuit board <b>140</b> in the upper and lower covers. As a consequence, the size of the upper and lower covers may be reduced.

0080<figref idref="DRAWINGS">FIGS. 9 to 14</figref> are cross-sectional views for describing a method of manufacturing a display apparatus as shown in <figref idref="DRAWINGS">FIGS. 2 and 8</figref>. <figref idref="DRAWINGS">FIGS. 9 to 14</figref> show the first non-display area and the display area of the display panel.

0081The array substrate <b>110</b> is prepared. The array substrate <b>110</b> includes the display area DA and the non-display area NDA surrounding the display area DA. The non-display area NDA includes the first non-display area NDA-<b>1</b> adjacent to a side portion of the display area DA and the second non-display area NDA-<b>2</b> other than the first non-display area NDA-<b>1</b>.

0082The array substrate <b>110</b> includes the first base substrate <b>111</b>, the organic polymer pattern <b>116</b> disposed adjacent to a side portion of the first base substrate <b>111</b>, the thin film transistor TFT disposed on the first base substrate <b>111</b>, and the pixel electrode <b>115</b> connected to the thin film transistor TFT.

0083Referring to <figref idref="DRAWINGS">FIG. 9</figref>, the first base substrate <b>111</b> is prepared. The first base substrate <b>111</b> transmits light. The first base substrate <b>111</b> has a rectangular plate shape with long sides and short sides. The first base substrate <b>111</b> is divided into the display area DA and the non-display area NDA.

0084A trench T is formed in the first non-display area NDA-<b>1</b> of the first base substrate <b>111</b>. The trench T is parallel or substantially parallel to one of the long side or the short side, e.g., the long side. The trench T is formed by various methods. For example, according to an embodiment, the trench T is formed by removing a portion of the first base substrate <b>111</b> in the first non-display area NDA-<b>1</b> using a laser. Alternatively, the trench T is formed by forming a photoresist pattern on the first base substrate <b>111</b> in the first non-display area NDA-<b>1</b> to expose a portion of first base substrate <b>111</b> in the first non-display area NDA-<b>1</b> and by etching the portion of the first base substrate <b>111</b> in the first non-display area NDA-<b>1</b> using the photoresist pattern as a mask.

0085Referring to <figref idref="DRAWINGS">FIG. 10</figref>, after forming the trench T, the thin film transistor TFT is formed on the first base substrate <b>111</b> in the display area DA. The thin film transistor TFT includes the gate electrode GE, the semiconductor layer SCL, the source electrode SE, and the drain electrode DE.

0086According to an embodiment, the gate electrode GE is formed on the first base substrate <b>111</b>, and the gate insulating layer <b>112</b> is formed on the first base substrate <b>111</b> to cover the gate electrode GE. Then, the semiconductor layer SCL is formed on the gate insulating layer <b>112</b>, and the source electrode SE and the drain electrode DE are respectively formed in the source area and the drain area of the semiconductor layer SCL. The channel area is disposed between the source area and the drain area.

0087According to an embodiment, the data line DL connected to the source electrode SE, the signal input pad SIP electrically connected to the data line DL and disposed in the trench T of the pad area PA, and the signal wire SL that connects the data line DL with the signal input pad SIP and is disposed in the wire area SA are simultaneously or substantially simultaneously formed when the source electrode SE and the drain electrode DE are formed. According to an embodiment, the signal input pad SIP is disposed in the trench T.

0088After the thin film transistor TFT is formed, an organic polymer material is filled in the trench T to form the organic polymer pattern <b>116</b>. According to an embodiment, the organic polymer pattern <b>116</b> is formed of at least one of transparent materials, such as polyethyleneterephthalate (PET), polyethylenenapthalate (PEN), polycarbonate (PC), polyetherimide (PEI), polyethersulfone (PES), polyetheretherketon (PEEK), or polyimide (PI).

0089After forming the organic polymer pattern <b>116</b>, the protective layer <b>114</b> is formed to cover the thin film transistor TFT and the organic polymer pattern <b>116</b>. The protective layer <b>114</b> is formed of an inorganic material, an organic material, or a combination thereof.

0090Then, a portion of the protective layer <b>114</b> is removed to form the contact hole CH through which a portion of the drain electrode DE is exposed.

0091A transparent conductive oxide is deposited on the protective layer <b>114</b> and patterned. Accordingly, the pixel electrode <b>115</b> is formed to be electrically connected to the drain electrode DE of the thin film transistor TFT through the contact hole CH. The common voltage pad <b>117</b> is formed in the first non-display area NDA-<b>1</b> by a patterning process.

0092Referring to <figref idref="DRAWINGS">FIG. 11</figref>, after the array substrate <b>110</b> is prepared, the seal pattern SP is formed in the non-display area NDA to surround the display area DA.

0093The seal pattern SP has conductivity. The seal pattern P contacts the common electrode <b>125</b> and applies a common voltage to each pixel. For instance, according to an embodiment, the seal pattern SP includes a mixture of a polymer resin including at least one of an epoxy-containing resin, a phenol-containing resin, or an acryl-containing resin, a conductive particle including at least one of gold, silver, copper, or aluminum, and an organic binder. According to an embodiment, the seal pattern SP is cured by heat or light.

0094After the seal pattern SP is formed, the liquid crystal layer <b>130</b> including liquid crystal molecules is disposed in the display area DA.

0095The opposite substrate <b>120</b> that includes the second base substrate <b>121</b> and the common electrode <b>125</b> disposed on the second base substrate <b>121</b> is prepared. According to an exemplary embodiment, the opposite substrate <b>120</b> is divided into the display area DA and the non-display area NDA.

0096The opposite substrate <b>120</b> is disposed such that the common electrode <b>125</b> faces the array substrate <b>110</b>. The array substrate <b>110</b> and the opposite substrate <b>120</b> are coupled to each other by the seal pattern SP. The seal pattern SP, which is disposed to surround the display area DA and couples the array substrate <b>110</b> to the opposite substrate <b>120</b>, prevents leakage of the liquid crystal of the liquid crystal layer <b>130</b>.

0097After the seal pattern SP is formed and the liquid crystal layer <b>130</b> is disposed, the array substrate <b>110</b> and the opposite substrate <b>120</b> are coupled to each other, but it should not be limited thereto or thereby. For instance, alternatively, the liquid crystal is injected into between the array substrate <b>110</b> and the opposite substrate <b>120</b> to form the liquid crystal layer <b>130</b> after the seal pattern SP is formed and the array substrate <b>110</b> and the opposite substrate <b>120</b> are coupled to each other.

0098When heat or light is irradiated to the seal pattern SP after the array substrate <b>110</b> and the opposite substrate <b>120</b> are coupled to each other, the seal pattern SP is cured.

0099Referring to <figref idref="DRAWINGS">FIG. 12</figref>, after the seal pattern SP is cured, a portion of the array substrate, which protrudes beyond the opposite substrate <b>120</b> in the pad area PA, is removed.

0100The first base substrate <b>111</b> and the gate insulating layer <b>112</b> are removed in the pad area PA. When the first base substrate <b>111</b> and the gate insulating layer <b>112</b> are removed in the pad area PA, the signal input pad SIP is exposed under the array substrate <b>110</b>. According to an embodiment, the first base substrate <b>111</b> is removed by using a laser cutting method or a wet etch method.

0101Referring to <figref idref="DRAWINGS">FIG. 13</figref>, after removing the first base substrate <b>111</b>, the flexible printed circuit board <b>140</b> connected to the external circuit module is attached to the signal input pad SIP of the pad area PA to electrically connect the signal input pad SIP to the driver IC <b>141</b>.

0102Referring to <figref idref="DRAWINGS">FIG. 14</figref>, the signal input pad SIP is connected to the flexible printed circuit board <b>140</b>, and the flexible printed circuit board <b>140</b> is bent to the backlight unit <b>200</b> at the pad area PA.

0103The display panel <b>100</b> and the backlight unit <b>200</b> are accommodated in the space between the upper cover and the lower cover.

0104According to the display panel <b>100</b> manufactured by the above-described processes, the pad area PA, where the signal input pad SIP and the flexible circuit board <b>140</b> are connected to each other, does not protrude beyond the opposite substrate <b>120</b>. Thus, no space for the pad area PA is needed in the upper and lower covers of in the display panel <b>100</b>.

0105Hereinafter, display panels according to exemplary embodiments are described with reference to <figref idref="DRAWINGS">FIGS. 15 to 21</figref>.

0106<figref idref="DRAWINGS">FIG. 15</figref> is a cross-sectional view showing a display panel according to an exemplary embodiment of the present invention.

0107The display panel shown in <figref idref="DRAWINGS">FIG. 15</figref> has a similar structure to the display panel <b>100</b> shown in <figref idref="DRAWINGS">FIGS. 2 to 14</figref> except that in the display panel shown in <figref idref="DRAWINGS">FIG. 15</figref>, the first base substrate <b>111</b> of the array substrate <b>110</b> is even with the exposed surface of the signal input pad SIP. Accordingly, a thickness of the first base substrate <b>111</b> of the array substrate <b>110</b> decreases, thereby resulting in a decrease in a total thickness of the display panel.

0108According to an embodiment, the display panel shown in <figref idref="DRAWINGS">FIG. 15</figref> is manufactured by additionally performing a process of removing a portion of the first base substrate <b>111</b> so that a thickness of the first base substrate <b>111</b> is reduced before the flexible printed circuit board <b>140</b> on which the driver IC <b>141</b> is mounted is attached to the signal input pad SIP. For instance, according to an embodiment, a grinding process or an etching process is performed on the lower surface of the first base substrate <b>111</b>, so that the surface of the first base substrate <b>111</b> may be even with the surface of the signal input pad SIP.

0109According to an embodiment, the grinding process or the etching process is performed on the lower surface of the first base substrate <b>111</b> after the seal pattern SP is cured without separately performing a removing process of the first base substrate <b>111</b> of the pad area PA, and thus the surface of the first base substrate <b>111</b> may be even with the surface of the signal input pad SIP. According to an embodiment, the process of removing the first base substrate <b>111</b> is performed until the signal input pad SIP is exposed by removing the gate insulating layer <b>112</b> in the pad area PA. Accordingly, the first base substrate <b>111</b> is removed in the pad area PA, so that the total thickness of the display panel may be reduced.

0110<figref idref="DRAWINGS">FIG. 16</figref> is a cross-sectional view showing a display panel according to an exemplary embodiment of the present invention, and <figref idref="DRAWINGS">FIG. 17</figref> is a cross-sectional view showing the display panel of <figref idref="DRAWINGS">FIG. 16</figref>, wherein the flexible printed circuit board is bent downward.

0111Referring to <figref idref="DRAWINGS">FIGS. 16 and 17</figref>, the display panel <b>100</b> includes the display area DA and the non-display area NDA surrounding the display area DA. The non-display area NDA includes the first non-display area NDA-<b>1</b> adjacent to an side portion of the display area DA and the second non-display area NDA-<b>2</b> other than the first non-display area NDA-<b>1</b>.

0112The display panel <b>100</b> includes the array substrate <b>110</b>, the opposite substrate <b>120</b> facing the array substrate <b>110</b>, and the liquid crystal layer <b>130</b> disposed between the array substrate <b>110</b> and the opposite substrate <b>120</b>.

0113The array substrate <b>110</b> includes the display area DA and the non-display area NDA and has a rectangular plate shape with long sides and short sides. The first base substrate <b>111</b> is provided with a thru-hole TH formed in the first non-display area NDA-<b>1</b>.

0114The thin film transistor TFT is disposed on the first base substrate <b>111</b> and includes the semiconductor layer SCL, the gate electrode GE, the source electrode SE, and the drain electrode DE. The source electrode SE contacts the data line DL that transmits a data voltage to the thin film transistor TFT.

0115The protective layer <b>114</b> is disposed on the thin film transistor TFT. The protective layer <b>114</b> is provided with the contact hole CH to expose a portion of the drain electrode DE.

0116The pixel electrode <b>115</b> is disposed on the protective layer <b>114</b> and electrically connected to the drain electrode DE through the contact hole CH.

0117The seal pattern SP is disposed between the array substrate <b>110</b> and the opposite substrate <b>120</b> in the non-display area NDA. The seal pattern SP has conductivity. The seal pattern SP contacts the common voltage pad <b>117</b> to allow a common voltage to be applied to the common electrode <b>125</b> of the opposite substrate <b>120</b>.

0118The source electrode SE is connected to the data line DL, and the data line DL is connected to the signal input pad SIP through the signal wire SL. The signal wire SL is disposed on the first base substrate <b>111</b> in the first non-display area NDA-<b>1</b>, and the signal input pad SIP is disposed on the lower surface of the first base substrate <b>111</b>. The signal wire SL contacts the signal input pad SIP through the thru-hole TH.

0119<figref idref="DRAWINGS">FIGS. 18 to 21</figref> are cross-sectional views for describing a method of manufacturing a display panel as shown in <figref idref="DRAWINGS">FIGS. 16 and 17</figref>.

0120The array substrate <b>110</b> is prepared. The array substrate <b>110</b> includes the display area DA and the non-display area NDA. The non-display area NDA includes the first non-display area NDA-<b>1</b> adjacent to a side portion of the display area DA and the second non-display area NDA-<b>2</b> other than the first non-display area NDA-<b>1</b>. The array substrate <b>110</b> includes the first base substrate <b>111</b>, the thin film transistor TFT disposed on the first base substrate <b>111</b> in the display area DA, the pixel electrode <b>115</b> connected to the thin film transistor TFT, and the signal input pad SIP electrically connected to the thin film transistor TFT in the first non-display area NDA-<b>1</b> and disposed on the lower surface of the first base substrate <b>111</b>.

0121Referring to <figref idref="DRAWINGS">FIG. 18</figref>, the first base substrate <b>111</b> is prepared. The first base substrate <b>111</b> transmits light. The first base substrate has a rectangular plate shape with long sides and short sides.

0122A conductive material is deposited on the upper surface of the first base substrate <b>111</b> and is patterned to form the gate electrode GE and the gate line.

0123After forming the gate electrode GE and the gate line, the gate insulating layer <b>112</b> is formed to cover the gate electrode GE and the gate line.

0124Portions of the gate insulating layer <b>112</b> and the first base substrate <b>111</b> are removed in the first non-display area NDA-<b>1</b> to form the thru-hole TH passing through the first base substrate <b>111</b> and the gate insulating layer <b>112</b>.

0125When the thru-hole TH is formed, amorphous silicon is deposited on the gate insulating layer <b>112</b> and patterned to form the semiconductor layer SCL. Part of the semiconductor layer SCL overlaps the gate electrode GE.

0126A conductive material is deposited on the semiconductor layer SCL and the gate insulating layer <b>112</b> and patterned to form the source electrode SE, the drain electrode DE, the data line DL, and the signal wire SL. The source electrode SE and the drain electrode DE form the thin film transistor TFT together with the gate electrode GE and the semiconductor layer SCL. The source electrode SE and the drain electrode DE are spaced apart from each other and contact the semiconductor layer SCL. The source electrode SE is connected to the data line DL, and the data line DL is connected to the signal wire SL. The signal wire SL is filled in the thru-hole TH and exposed through the lower surface of the first base substrate <b>111</b>.

0127A conductive material is deposited on the lower surface of the first base substrate <b>111</b> and patterned to form the signal input pad SIP in the first non-display area NDA-<b>1</b>. The signal input pad SIP contacts the signal wire SL.

0128The signal input pad SIP is separately formed, but it should not be limited thereto or thereby. Alternatively, no separate signal input pad SIP is provided. For example, according to an embodiment, when the signal wire SL is filled in the thru-hole TH and exposed through the lower surface of the first base substrate <b>111</b>, the exposed portion of the signal wire SL may function as the signal input pad SIP.

0129The protective layer <b>114</b> is formed to cover the thin film transistor TFT. Part of the protective layer <b>114</b> is removed to form the contact hole CH through which a portion of the drain electrode DE is exposed.

0130The pixel electrode <b>115</b> is formed to be electrically connected to the drain electrode DE of the thin film transistor TFT through the contact hole CH, so that the array substrate <b>110</b> is formed.

0131Referring to <figref idref="DRAWINGS">FIG. 19</figref>, after the array substrate <b>110</b> is formed, the seal pattern SP is formed in the non-display area NDA. The seal pattern SP has conductivity and is cured by heat or light.

0132After the seal pattern SP is formed, the liquid crystal layer <b>130</b> is disposed in the display area DA.

0133The opposite substrate <b>120</b> that includes the second base substrate <b>121</b> and the common electrode <b>125</b> disposed on the second base substrate <b>121</b> is prepared. The opposite substrate <b>120</b> is disposed such that the common electrode <b>125</b> faces the array substrate <b>110</b>. The array substrate <b>110</b> and the opposite substrate <b>120</b> are coupled to each other by the seal pattern SP.

0134When heat or light is irradiated to the seal pattern SP after the array substrate <b>110</b> and the opposite substrate <b>120</b> are coupled to each other, the seal pattern SP is cured.

0135Referring to <figref idref="DRAWINGS">FIG. 20</figref>, after the seal pattern SP is cured, a portion of the array substrate <b>110</b>, which protrudes beyond the opposite substrate <b>120</b> in the pad area PA, is removed.

0136Referring to <figref idref="DRAWINGS">FIG. 21</figref>, after removing the portion of the first base substrate <b>110</b>, the flexible printed circuit board <b>140</b> is attached to the signal input pad SIP, and thus the signal input pad SIP is electrically connected to the driver IC <b>141</b>.

0137The flexible printed circuit board <b>140</b> is bent after the signal input pad SIP is connected to the flexible printed circuit board <b>140</b>.

0138The display panel <b>100</b> and the backlight unit <b>200</b> are accommodated in the space between the upper cover and the lower cover, thereby forming the display apparatus.

0139Although the exemplary embodiments of the present invention have been described, it is understood that the present invention should not be limited to these exemplary embodiments but various changes and modifications can be made by one ordinary skilled in the art within the spirit and scope of the present invention as hereinafter claimed.