Semiconductor device and method of forming RDL using UV-cured conductive ink over wafer level package

CLAIM TO DOMESTIC PRIORITY

0001The present application claims the benefit of U.S. Provisional Application No. 61/691,651, filed Aug. 21, 2012, which application is incorporated herein by reference.

FIELD OF THE INVENTION

0002The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming an RDL using UV-cured conductive ink over wafer level package.

BACKGROUND OF THE INVENTION

0003Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).

0004Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.

0005Semiconductor devices exploit the electrical properties of semiconductor materials. The structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.

0006A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed operations and other useful functions.

0007Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each semiconductor die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual semiconductor die from the finished wafer and packaging the die to provide structural support and environmental isolation. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.

0008One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller semiconductor die size can be achieved by improvements in the front-end process resulting in semiconductor die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.

0009<figref idref="DRAWINGS">FIG. 1<i>a </i></figref>shows a portion of a reconstituted semiconductor wafer <b>10</b> including semiconductor die <b>12</b>. A contact pad <b>14</b> is formed over an active surface of semiconductor die <b>12</b> with electrical connection to circuits in the active surface. An insulating or passivation layer <b>16</b> is formed over semiconductor die <b>12</b>. An encapsulant <b>18</b> is deposited around semiconductor die <b>12</b> as part of reconstituted wafer <b>10</b>. In <figref idref="DRAWINGS">FIG. 1<i>b</i></figref>, a dielectric layer <b>20</b> is formed over insulating layer <b>16</b> and encapsulant <b>18</b>. An opening <b>22</b> is formed in dielectric layer <b>20</b> to expose contact pad <b>14</b>. In <figref idref="DRAWINGS">FIG. 1<i>c</i></figref>, a multi-layer redistribution layer (RDL) is formed over dielectric layer <b>20</b> and into opening <b>22</b> to contact pad <b>14</b>. The RDL includes conductive layer <b>24</b> conformally applied to dielectric layer <b>20</b> and into opening <b>22</b> to contact pad <b>14</b>, and conductive layer <b>26</b> conformally applied to conductive layer <b>24</b>. In <figref idref="DRAWINGS">FIG. 1<i>d</i></figref>, a dielectric layer <b>28</b> is formed over dielectric layer <b>20</b> and conductive layers <b>24</b> and <b>26</b>.

0010As described in <figref idref="DRAWINGS">FIGS. 1<i>a</i>-1<i>d</i></figref>, the RDL requires several processes, including spin coating to form the dielectric layers and plating to form the conductive layers in accordance with standard photoresist procedures. The formation of the dielectric layers and conductive layers is time consuming and requires access to expensive and complex semiconductor processing equipment, such as a plating tool. In addition, the formation of the dielectric layers and conductive layers is difficult to achieve over a large semiconductor die area or large portion of the reconstituted wafer.

SUMMARY OF THE INVENTION

0011A need exists for a simple and cost effective way to form RDLs over a semiconductor die, substrate, or reconstituted wafer. Accordingly, in one embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a semiconductor die, forming a first insulating layer over the semiconductor die, forming a patterned trench in the first insulating layer, depositing a conductive ink in the patterned trench, and curing the conductive ink by ultraviolet light.

0012In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a substrate, forming a first insulating layer over the substrate, forming a trench in the first insulating layer, depositing a conductive ink in the trench, and curing the conductive ink.

0013In another embodiment, the present invention is a semiconductor device comprising a semiconductor die and first insulating layer formed over the semiconductor die. A patterned trench is formed in the first insulating layer. A conductive ink is deposited in the patterned trench. The conductive ink is cured by ultraviolet light.

0014In another embodiment, the present invention is a semiconductor device comprising a substrate and first insulating layer formed over the substrate. A trench is formed in the first insulating layer. A conductive ink is deposited in the trench. The conductive ink is cured.

BRIEF DESCRIPTION OF THE DRAWINGS

0015<figref idref="DRAWINGS">FIGS. 1<i>a</i>-1<i>d </i></figref>illustrate a conventional process of forming an RDL over a reconstituted wafer;

0016<figref idref="DRAWINGS">FIG. 2</figref> illustrates a printed circuit board (PCB) with different types of packages mounted to its surface;

0017<figref idref="DRAWINGS">FIGS. 3<i>a</i>-3<i>c </i></figref>illustrate further detail of the representative semiconductor packages mounted to the PCB;

0018<figref idref="DRAWINGS">FIGS. 4<i>a</i>-4<i>c </i></figref>illustrate a semiconductor wafer with a plurality of semiconductor die separated by a saw street;

0019<figref idref="DRAWINGS">FIGS. 5<i>a</i>-5<i>b </i></figref>illustrate mounting the semiconductor die to a carrier to form a reconstituted wafer;

0020<figref idref="DRAWINGS">FIGS. 6<i>a</i>-6<i>i </i></figref>illustrate a process of forming an RDL over a semiconductor die using UV-cured conductive ink;

0021<figref idref="DRAWINGS">FIGS. 7<i>a</i>-7<i>b </i></figref>illustrate an eWLB having an RDL formed in the encapsulant by UV-cured conductive ink; and

0022<figref idref="DRAWINGS">FIGS. 8<i>a</i>-8<i>d </i></figref>illustrate a process of forming a wiring trace or RDL over a substrate using UV-cured conductive ink.

DETAILED DESCRIPTION OF THE DRAWINGS

0023The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings.

0024Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, and resistors, create a relationship between voltage and current necessary to perform electrical circuit functions.

0025Passive and active components are formed over the surface of the semiconductor wafer by a series of process steps including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process modifies the electrical conductivity of semiconductor material in active devices by dynamically changing the semiconductor material conductivity in response to an electric field or base current. Transistors contain regions of varying types and degrees of doping arranged as necessary to enable the transistor to promote or restrict the flow of electrical current upon the application of the electric field or base current.

0026Active and passive components are formed by layers of materials with different electrical properties. The layers can be formed by a variety of deposition techniques determined in part by the type of material being deposited. For example, thin film deposition can involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes. Each layer is generally patterned to form portions of active components, passive components, or electrical connections between components.

0027Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and then packaging the semiconductor die for structural support and environmental isolation. To singulate the semiconductor die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with solder bumps, stud bumps, conductive paste, or wirebonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.

0028<figref idref="DRAWINGS">FIG. 2</figref> illustrates electronic device <b>50</b> having a chip carrier substrate or printed circuit board (PCB) <b>52</b> with a plurality of semiconductor packages mounted on its surface. Electronic device <b>50</b> can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown in <figref idref="DRAWINGS">FIG. 2</figref> for purposes of illustration.

0029Electronic device <b>50</b> can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device <b>50</b> can be a subcomponent of a larger system. For example, electronic device <b>50</b> can be part of a cellular phone, personal digital assistant (PDA), digital video camera (DVC), or other electronic communication device. Alternatively, electronic device <b>50</b> can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for the products to be accepted by the market. The distance between semiconductor devices must be decreased to achieve higher density.

0030In <figref idref="DRAWINGS">FIG. 2</figref>, PCB <b>52</b> provides a general substrate for structural support and electrical interconnect of the semiconductor packages mounted on the PCB. Conductive signal traces <b>54</b> are formed over a surface or within layers of PCB <b>52</b> using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces <b>54</b> provide for electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces <b>54</b> also provide power and ground connections to each of the semiconductor packages.

0031In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate carrier. Second level packaging involves mechanically and electrically attaching the intermediate carrier to the PCB. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to the PCB.

0032For the purpose of illustration, several types of first level packaging, including bond wire package <b>56</b> and flipchip <b>58</b>, are shown on PCB <b>52</b>. Additionally, several types of second level packaging, including ball grid array (BGA) <b>60</b>, bump chip carrier (BCC) <b>62</b>, dual in-line package (DIP) <b>64</b>, land grid array (LGA) <b>66</b>, multi-chip module (MCM) <b>68</b>, quad flat non-leaded package (QFN) <b>70</b>, and quad flat package <b>72</b>, are shown mounted on PCB <b>52</b>. Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB <b>52</b>. In some embodiments, electronic device <b>50</b> includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.

0033<figref idref="DRAWINGS">FIGS. 3<i>a</i>-3<i>c </i></figref>show exemplary semiconductor packages. <figref idref="DRAWINGS">FIG. 3<i>a </i></figref>illustrates further detail of DIP <b>64</b> mounted on PCB <b>52</b>. Semiconductor die <b>74</b> includes an active region containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and are electrically interconnected according to the electrical design of the die. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active region of semiconductor die <b>74</b>. Contact pads <b>76</b> are one or more layers of conductive material, such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and are electrically connected to the circuit elements formed within semiconductor die <b>74</b>. During assembly of DIP <b>64</b>, semiconductor die <b>74</b> is mounted to an intermediate carrier <b>78</b> using a gold-silicon eutectic layer or adhesive material such as thermal epoxy or epoxy resin. The package body includes an insulative packaging material such as polymer or ceramic. Conductor leads <b>80</b> and bond wires <b>82</b> provide electrical interconnect between semiconductor die <b>74</b> and PCB <b>52</b>. Encapsulant <b>84</b> is deposited over the package for environmental protection by preventing moisture and particles from entering the package and contaminating semiconductor die <b>74</b> or bond wires <b>82</b>.

0034<figref idref="DRAWINGS">FIG. 3<i>b </i></figref>illustrates further detail of BCC <b>62</b> mounted on PCB <b>52</b>. Semiconductor die <b>88</b> is mounted over carrier <b>90</b> using an underfill or epoxy-resin adhesive material <b>92</b>. Bond wires <b>94</b> provide first level packaging interconnect between contact pads <b>96</b> and <b>98</b>. Molding compound or encapsulant <b>100</b> is deposited over semiconductor die <b>88</b> and bond wires <b>94</b> to provide physical support and electrical isolation for the device. Contact pads <b>102</b> are formed over a surface of PCB <b>52</b> using a suitable metal deposition process such as electrolytic plating or electroless plating to prevent oxidation. Contact pads <b>102</b> are electrically connected to one or more conductive signal traces <b>54</b> in PCB <b>52</b>. Bumps <b>104</b> are formed between contact pads <b>98</b> of BCC <b>62</b> and contact pads <b>102</b> of PCB <b>52</b>.

0035In <figref idref="DRAWINGS">FIG. 3<i>c</i></figref>, semiconductor die <b>58</b> is mounted face down to intermediate carrier <b>106</b> with a flipchip style first level packaging. Active region <b>108</b> of semiconductor die <b>58</b> contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed according to the electrical design of the die. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements within active region <b>108</b>. Semiconductor die <b>58</b> is electrically and mechanically connected to carrier <b>106</b> through bumps <b>110</b>.

0036BGA <b>60</b> is electrically and mechanically connected to PCB <b>52</b> with a BGA style second level packaging using bumps <b>112</b>. Semiconductor die <b>58</b> is electrically connected to conductive signal traces <b>54</b> in PCB <b>52</b> through bumps <b>110</b>, signal lines <b>114</b>, and bumps <b>112</b>. A molding compound or encapsulant <b>116</b> is deposited over semiconductor die <b>58</b> and carrier <b>106</b> to provide physical support and electrical isolation for the device. The flipchip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die <b>58</b> to conduction tracks on PCB <b>52</b> in order to reduce signal propagation distance, lower capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die <b>58</b> can be mechanically and electrically connected directly to PCB <b>52</b> using flipchip style first level packaging without intermediate carrier <b>106</b>.

0037<figref idref="DRAWINGS">FIG. 4<i>a </i></figref>shows a semiconductor wafer <b>120</b> with a base substrate material <b>122</b>, such as silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide, for structural support. A plurality of semiconductor die or components <b>124</b> is formed on wafer <b>120</b> separated by a non-active, inter-die wafer area or saw street <b>126</b> as described above. Saw street <b>126</b> provides cutting areas to singulate semiconductor wafer <b>120</b> into individual semiconductor die <b>124</b>.

0038<figref idref="DRAWINGS">FIG. 4<i>b </i></figref>shows a cross-sectional view of a portion of semiconductor wafer <b>120</b>. Each semiconductor die <b>124</b> has a back surface <b>128</b> and active surface <b>130</b> containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface <b>130</b> to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, memory, or other signal processing circuit. Semiconductor die <b>124</b> may also contain integrated passive devices (IPDs), such as inductors, capacitors, and resistors, for RF signal processing.

0039An electrically conductive layer <b>132</b> is formed over active surface <b>130</b> using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer <b>132</b> can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer <b>132</b> operates as contact pads electrically connected to the circuits on active surface <b>130</b>. Conductive layer <b>132</b> can be formed as contact pads disposed side-by-side a first distance from the edge of semiconductor die <b>124</b>, as shown in <figref idref="DRAWINGS">FIG. 4<i>b</i></figref>. Alternatively, conductive layer <b>132</b> can be formed as contact pads that are offset in multiple rows such that a first row of contact pads is disposed a first distance from the edge of the die, and a second row of contact pads alternating with the first row is disposed a second distance from the edge of the die.

0040In <figref idref="DRAWINGS">FIG. 4<i>c</i></figref>, semiconductor wafer <b>120</b> is singulated through saw street <b>126</b> using a saw blade or laser cutting tool <b>134</b> into individual semiconductor die <b>124</b>.

0041<figref idref="DRAWINGS">FIG. 5<i>a </i></figref>shows a cross-sectional view of substrate or carrier <b>140</b> containing temporary or sacrificial base material such as silicon, germanium, gallium arsenide, indium phosphide, silicon carbide, resin, beryllium oxide, glass, or other suitable low-cost, rigid material for structural support. An interface layer or double-sided tape <b>142</b> is formed over carrier <b>140</b> as a temporary adhesive bonding film, etch-stop layer, or release layer. Semiconductor die <b>124</b> from <figref idref="DRAWINGS">FIGS. 3<i>a</i>-3<i>c </i></figref>are positioned over and mounted to interface layer <b>142</b> and carrier <b>140</b> using, for example, a pick and place operation with back surface <b>128</b> oriented toward the carrier. <figref idref="DRAWINGS">FIG. 5<i>b </i></figref>shows a plurality of semiconductor die <b>124</b>, potentially hundreds of die, mounted to carrier <b>140</b> as reconstituted wafer <b>144</b> to fabricate high density embedded wafer level ball grid array (eWLB) packages.

0042<figref idref="DRAWINGS">FIGS. 6<i>a</i>-6<i>i </i></figref>illustrate, in relation to <figref idref="DRAWINGS">FIGS. 2 and 3</figref><i>a</i>-<b>3</b><i>c</i>, a processing of forming an RDL or wiring trace over a semiconductor die using UV-cured conductive ink. <figref idref="DRAWINGS">FIG. 6<i>a </i></figref>shows a portion of reconstituted wafer <b>144</b> associated with one semiconductor die <b>124</b>. In <figref idref="DRAWINGS">FIG. 6<i>b</i></figref>, an insulating or dielectric layer <b>146</b> is formed over active surface <b>130</b> and conductive layer <b>132</b> of semiconductor die <b>124</b> using PVD, CVD, laminating, printing, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer <b>146</b> includes one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), hafnium oxide (HfO2), benzocyclobutene (BCB), polyimide (PI), polybenzoxazoles (PBO), or other material having similar structural and insulating properties. The insulating layer <b>146</b> can be organic or inorganic base material. The insulating layer <b>146</b> is cured at 180-200° C. for 1.5-2.0 hours.

0043In <figref idref="DRAWINGS">FIG. 6<i>c</i></figref>, a portion of insulating layer <b>146</b> is removed by laser direct ablation (LDA) using infrared (IR) or ultraviolet (UV) laser <b>148</b> to expose conductive layer <b>132</b> and define pattern cavity or trench <b>150</b> into the insulating layer for a later formed RDL. Alternatively, a portion of insulating layer <b>146</b> is removed by an etching process through a patterned photoresist layer to expose conductive layer <b>132</b> and define a pattern or path <b>150</b> into the insulating layer for the later RDL formation.

0044In <figref idref="DRAWINGS">FIG. 6<i>d</i></figref>, a screen or stencil <b>152</b> is disposed over insulating layer <b>146</b> with one or more openings in the stencil aligned to patterned trench <b>150</b>. A volume of conductive ink <b>154</b> is deposited over stencil <b>152</b> and insulating layer <b>146</b> in a printing process. In one embodiment, conductive ink <b>154</b> contains powdered or flaked silver or carbon conductive materials applied as a thin layer in patterned trench <b>150</b>. A conductive ink distribution tool or squeegee <b>156</b> distributes conductive ink <b>154</b> across stencil <b>152</b> and into patterned trench <b>150</b>. During the printing operation, conductive ink distribution tool <b>156</b> moves left to right across stencil <b>152</b> as shown by arrow <b>158</b> to press conductive ink <b>154</b> through the openings in the stencil into patterned trench <b>150</b> in insulating layer <b>146</b>.

0045In another embodiment, a volume of conductive ink <b>154</b> is deposited directly into patterned trench <b>150</b> in insulating layer <b>146</b> using dispensing nozzle or jet <b>160</b>, as shown in <figref idref="DRAWINGS">FIG. 6<i>e</i></figref>. During the jetting operation, conductive ink <b>154</b> flows from dispensing nozzle <b>160</b> as droplets or steady stream in the proper volume to fill patterned trench <b>150</b>. The volume of conductive ink <b>154</b> is measured according to the space requirements of patterned trench <b>150</b>.

0046<figref idref="DRAWINGS">FIG. 6<i>f </i></figref>shows conductive ink <b>154</b> deposited into patterned trench <b>150</b> in insulating layer <b>146</b> by operation of conductive ink distribution tool <b>156</b>, dispensing nozzle <b>160</b>, or other suitable applicator for dispensing or distributing the conductive ink. Conductive ink <b>154</b> is evenly dispensed and uniformly distributed within patterned trench <b>150</b> in insulating layer <b>146</b>. Excess conductive ink <b>154</b> can be removed by a planarizing operation on insulating layer <b>146</b> to make the conductive ink planar with the insulating layer.

0047An ultraviolet (UV) light source <b>162</b> radiates UV light <b>164</b> onto conductive ink <b>154</b> at room temperature (15-25° C.) causing a chemical crosslinking reaction to cure the conductive ink. An elevated temperature is not required for the UV cure of conductive ink <b>154</b>.

0048<figref idref="DRAWINGS">FIG. 6<i>g </i></figref>shows a plan view of conductive ink <b>154</b> deposited into patterned trench <b>150</b> in insulating layer <b>146</b> as RDLs. The radiation curable conductive ink <b>154</b> can be applied at the wafer level, i.e., either at the manufacturing step of <figref idref="DRAWINGS">FIG. 4<i>a </i></figref>(semiconductor wafer) or <figref idref="DRAWINGS">FIG. 5<i>b </i></figref>(reconstituted wafer). Conductive ink <b>154</b> is disposed in patterned trench <b>150</b> of insulating layer <b>146</b> by screen printing, ink jetting, or other suitable dispensing process and then cured by UV light at room temperature.

0049In <figref idref="DRAWINGS">FIG. 6<i>h</i></figref>, an insulating or passivation layer <b>170</b> is formed over insulating layer <b>146</b> and conductive ink <b>154</b> using PVD, CVD, laminating, printing, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer <b>170</b> includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, HfO2, or other material having similar structural and insulating properties. A portion of insulating layer <b>170</b> is removed by LDA using laser <b>172</b> to expose conductive ink <b>154</b>. Alternatively, a portion of insulating layer <b>170</b> is removed by an etching process through a patterned photoresist layer to expose conductive ink <b>154</b>.

0050In <figref idref="DRAWINGS">FIG. 6<i>i</i></figref>, an electrically conductive bump material is deposited over conductive ink <b>154</b> using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive ink <b>154</b> using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps <b>174</b>. In some applications, bumps <b>174</b> are reflowed a second time to improve electrical contact to conductive ink <b>154</b>. In one embodiment, bumps <b>174</b> are formed over a UBM having a wetting layer, barrier layer, and adhesive layer. The bumps can also be compression bonded or thermocompression bonded to conductive ink <b>154</b>. Bumps <b>174</b> represent one type of interconnect structure that can be formed over conductive ink <b>154</b>. The interconnect structure can also use bond wires, conductive paste, stud bump, micro bump, or other electrical interconnect.

0051Carrier <b>140</b> and interface layer <b>142</b> are removed by chemical etching, mechanical peeling, chemical mechanical planarization (CMP), mechanical grinding, thermal bake, UV light, laser scanning, or wet stripping.

0052The description of <figref idref="DRAWINGS">FIGS. 6<i>a</i>-6<i>i </i></figref>is simple, fast, low cost, and applies to a portion of semiconductor wafer <b>120</b> or reconstituted wafer <b>144</b>, or a large area, e.g., the entirety, of the semiconductor wafer or reconstituted wafer. The cured conductive ink <b>154</b> provides RDL or wiring traces to electrically connect electronic circuits within active surface <b>130</b> of semiconductor die <b>124</b>, as well as external devices. In one embodiment, the cured RDL <b>154</b> has electrical resistivity of 10-3 ohms centimeters (Ωcm).

0053<figref idref="DRAWINGS">FIGS. 7<i>a</i>-7<i>b </i></figref>illustrate an embodiment including RDL formed with conductive ink for eWLB <b>180</b>, shown as a portion of reconstituted wafer <b>144</b> associated with one semiconductor die <b>124</b>. In <figref idref="DRAWINGS">FIG. 7<i>a</i></figref>, an encapsulant or molding compound <b>182</b> is deposited around semiconductor die <b>124</b> over carrier <b>140</b> using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant <b>182</b> can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant <b>182</b> is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.

0054An insulating or dielectric layer <b>186</b> is formed over active surface <b>130</b> and conductive layer <b>132</b> of semiconductor die <b>124</b> using PVD, CVD, laminating, printing, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer <b>186</b> includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, HfO2, BCB, PI, PBO, or other material having similar structural and insulating properties. The insulating layer <b>186</b> can be organic or inorganic base material. The insulating layer <b>186</b> is cured at 180-200° C. for 1.5-2.0 hours.

0055A portion of encapsulant <b>182</b> and insulating layer <b>186</b> is removed by LDA to expose conductive layer <b>132</b> and define the patterned trench into the insulating layer for a later formed RDL, similar to <figref idref="DRAWINGS">FIG. 6<i>c</i></figref>. Alternatively, a portion of encapsulant <b>182</b> and insulating layer <b>186</b> is removed by an etching process through a patterned photoresist layer to expose conductive layer <b>132</b> and define a pattern or path into the insulating layer for the later RDL formation.

0056A volume of conductive ink <b>188</b> is deposited into the patterned trench in encapsulant <b>182</b> and insulating layer <b>186</b> using a printing or jetting process, similar to <figref idref="DRAWINGS">FIGS. 6<i>d </i>and 6<i>e</i></figref>, or other suitable application process. In one embodiment, conductive ink <b>188</b> contains powdered or flaked silver or carbon conductive materials applied as a thin layer in the patterned trench. The volume of conductive ink <b>188</b> is measured according to the space requirements of the patterned trench. The radiation curable conductive ink <b>188</b> can be applied at the wafer level. Excess conductive ink <b>188</b> can be removed by a planarizing operation on encapsulant <b>182</b> and insulating layer <b>186</b> to make the conductive ink planar with the encapsulant and insulating layer. Conductive ink <b>188</b> is radiated with UV light at room temperature causing a chemical crosslinking reaction to cure the conductive ink as RDL. An elevated temperature is not required for the UV cure of conductive ink <b>188</b>.

0057An insulating or passivation layer <b>190</b> is formed over encapsulant <b>182</b>, insulating layer <b>186</b>, and conductive ink <b>188</b> using PVD, CVD, laminating, printing, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer <b>190</b> includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, HfO2, or other material having similar structural and insulating properties. A portion of insulating layer <b>190</b> is removed by LDA to expose conductive ink <b>188</b>. Alternatively, a portion of insulating layer <b>190</b> is removed by an etching process through a patterned photoresist layer to expose conductive ink <b>188</b>.

0058An electrically conductive bump material is deposited over conductive ink <b>188</b> using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive ink <b>188</b> using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps <b>192</b>. In some applications, bumps <b>192</b> are reflowed a second time to improve electrical contact to conductive ink <b>188</b>. In one embodiment, bumps <b>192</b> are formed over a UBM having a wetting layer, barrier layer, and adhesive layer. The bumps can also be compression bonded or thermocompression bonded to conductive ink <b>188</b>. Bumps <b>192</b> represent one type of interconnect structure that can be formed over conductive ink <b>188</b>. The interconnect structure can also use bond wires, conductive paste, stud bump, micro bump, or other electrical interconnect.

0059In <figref idref="DRAWINGS">FIG. 7<i>b</i></figref>, carrier <b>140</b> and interface layer <b>142</b> are removed by chemical etching, mechanical peeling, chemical mechanical planarization (CMP), mechanical grinding, thermal bake, UV light, laser scanning, or wet stripping.

0060The formation of RDL using conductive ink <b>188</b> is simple, fast, low cost, and applies to a portion of reconstituted wafer <b>144</b> or a large area, e.g., the entirety, of the reconstituted wafer. The cured conductive ink <b>188</b> provides RDL or wiring traces to electrically connect electronic circuits within active surface <b>130</b> of semiconductor die <b>124</b>, as well as external devices.

0061<figref idref="DRAWINGS">FIGS. 8<i>a</i>-8<i>d </i></figref>illustrate, in relation to <figref idref="DRAWINGS">FIGS. 2 and 3</figref><i>a</i>-<b>3</b><i>c</i>, a processing of forming an RDL or wiring trace over a substrate using UV-cured conductive ink. <figref idref="DRAWINGS">FIG. 8<i>a </i></figref>shows a substrate <b>200</b> including an interconnect structure <b>202</b> comprising one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material enabling vertical and lateral conduction through the substrate. In another embodiment, substrate <b>200</b> has a back surface <b>204</b> and active surface <b>206</b> containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface <b>206</b> to implement analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuit. Substrate <b>200</b> may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing.

0062An electrically conductive layer <b>208</b> is formed over substrate <b>200</b> using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer <b>208</b> can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer <b>208</b> operates as contact pads electrically connected to interconnect structure <b>202</b> and/or the circuits on active surface <b>206</b>.

0063A screen or stencil <b>210</b> is disposed over substrate <b>200</b> with openings <b>212</b> in the stencil. A volume of conductive ink <b>214</b> is deposited over stencil <b>210</b> in a printing process. In one embodiment, conductive ink <b>214</b> contains powdered or flaked silver or carbon conductive materials applied as a thin layer. A conductive ink distribution tool or squeegee <b>216</b> distributes conductive ink <b>214</b> across stencil <b>210</b> and into openings <b>212</b>. During the printing operation, conductive ink distribution tool <b>216</b> moves left to right across stencil <b>210</b> as shown by arrow <b>218</b> to press conductive ink <b>214</b> through openings <b>212</b> in the stencil to contact conductive layer <b>208</b>. Conductive ink <b>214</b> is evenly dispensed and uniformly distributed within openings <b>212</b>, as shown in <figref idref="DRAWINGS">FIG. 8<i>b</i></figref>. Excess conductive ink <b>214</b> can be removed to planarize the conductive ink. Stencil <b>210</b> is removed.

0064In another embodiment, a volume of conductive ink <b>214</b> is deposited directly into openings <b>212</b> using dispensing nozzle or jet <b>218</b>, as shown in <figref idref="DRAWINGS">FIG. 8<i>c</i></figref>. During the jetting operation, conductive ink <b>214</b> flows from dispensing nozzle <b>218</b> as droplets or steady stream over conductive layer <b>208</b>.

0065<figref idref="DRAWINGS">FIG. 8<i>d </i></figref>shows conductive ink <b>214</b> deposited over conductive layer <b>208</b> by operation of conductive ink distribution tool <b>216</b>, dispensing nozzle <b>218</b>, or other suitable applicator for dispensing or distributing the conductive ink. Conductive ink <b>214</b> is evenly dispensed and uniformly distributed over conductive layer <b>208</b>.

0066UV light source <b>220</b> radiates UV light <b>222</b> onto conductive ink <b>214</b> at room temperature (15-25° C.) causing a chemical crosslinking reaction to cure the conductive ink. An elevated temperature is not required for the UV cure. The radiation curable conductive ink <b>214</b> can be applied at the wafer level to form wiring traces or RDL over substrate <b>200</b>. The formation of wiring traces or RDL using conductive ink <b>214</b> is simple, fast, low cost, and applies to a portion of substrate <b>200</b> or a large area, e.g., the entirety, of the substrate.

0067While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.