US9268708B2

Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence

Summary by NHIP

Multi-Level Cache Coherence Protocol

The method maintains cache coherence during victim eviction and DMA writes by comparing addresses against victim buffers. A first victim buffer stores evicted data, while a second buffer holds data passing to the next level for retirement upon commitment.

Claim Score by NHIP

Read claim 1, the broadest

Abstract

This invention assures cache coherence in a multi-level cache system upon eviction of a higher level cache line. A victim buffer stored data on evicted lines. On a DMA access that may be cached in the higher level cache the lower level cache sends a snoop write. The address of this snoop write is compared with the victim buffer. On a hit in the victim buffer the write completes in the victim buffer. When the victim data passes to the next cache level it is written into a second victim buffer to be retired when the data is committed to cache. DMA write addresses are compared to addresses in this second victim buffer. On a match the write takes place in the second victim buffer. On a failure to match the controller sends a snoop write.

US9268708B2, drawing sheet 1 — Sheet 1 of 9

Term

5 yearsleft in the term

Expires 28 September 2031.

2 claims: 1 independent, 1 dependent

1
Broadest claimClaim Score 10, narrow(NHIP)In a data processing system including a central processing unit executing program instructions to manipulate data, a first level data cache temporarily storing in a plurality of first cache lines data for manipulation by the central processing unit, a second level memory including second level cache temporarily storing in a plurality of second cache lines data for manipulation by the central processing unit and a second level local memory directly addressable by the central processing unit and a direct memory access unit operating under control of the central processing unit to control data transfers including transferring data into and out of the second level local memory, a method of data processing operation comprising the steps of:initiating a victim entry in a first victim buffer upon selection of a first cache line in the first level data cache for replacement, storing a first victim address corresponding to data stored in a first cache line selected for replacement and data stored in said first cache line selected for replacement in the victim entry of the first victim buffer;receiving snoop write data and a corresponding snoop write address;comparing the first victim address of each entry in the first victim buffer to the snoop write address;writing the snoop write data into a corresponding entry in said first victim buffer upon a match between a snoop write address and a first victim address in said first victim buffer;retiring a victim entry of the first victim buffer upon committing said first cache line selected for replacement to the second level memory;initiating a victim entry in a second victim buffer upon selection of a first cache line in the first level data cache for replacement;storing a second victim address corresponding to data stored in said first cache line selected for replacement and the data stored in the first cache line selected for replacement in a victim entry in the second victim buffer;receiving direct memory access write data and a corresponding direct memory access write address of a direct memory access unit controlled data transfer;comparing the second victim address of each entry in said second victim buffer to the direct memory access write address;writing the direct memory access write data into a corresponding entry in said second victim buffer upon a match between a direct memory access write address and a second victim address in said second victim buffer;forwarding a snoop write to the first level cache if there is no match between the direct memory access write address and the second victim address in said second victim buffer, stalling the snoop write if there is a pending read from the first cache line of the first level data cache and committing the snoop write if no pending read from the first cache line of the first level data cache;and retiring a victim entry of the second victim buffer upon committing said first cache line selected for replacement to the second level memory.

68 paragraphs in 6 sections, as filed

CLAIM OF PRIORITY

0001This application: is a divisional of U.S. patent application Ser. No. 13/247,209 filed Sep. 28, 2011.

TECHNICAL FIELD OF THE INVENTION

0002The technical field of this invention is cache for digital data processors.

BACKGROUND OF THE INVENTION

0003This invention is applicable to data processing systems with multi-level memory where the second level (L2) memory used for both unified (code and instructions) level two cache and flat (L2 SRAM) memory used to hold critical data and instructions. The second level memory (L2) is used for multiple purposes including unified instruction and data level two cache, directly addressable SRAM memory used to hold critical data and code accessible by both external and internal direct memory access (DMA) units.

0004When the level one data cache controller is granted access to the level one data cache, this access could force an existing line to be evicted. The CPU can also force the level one data cache to evict lines though the block writeback operation. At the same time, the level two cache could be receiving a DMA access to the same line. This situation could break coherency, if DMA data were committed incorrectly. This could occur by writing to the level two memory then overwriting that data with the level one cache victim. This could also occur by sending the DMA data as a snoop write to the level one data cache. This forces the level one data cache to write the DMA data to its cache after the victim has been evicted. This effectively, drops the DMA write. Thus when a victim is in progress, a DMA write sent as snoop could miss the victim.

SUMMARY OF THE INVENTION

0005This invention assures cache coherence in a multi-level cache system upon eviction of a higher level cache line. Data identifying an evicted cache line is entered into an entry within a victim buffer when selected for eviction. An entry is retired from the victim buffer when the corresponding cache line data reaches the next cache level. On a DMA access that may be cached in the higher level cache the lower level cache sends a snoop write. The address of this snoop write is compared with cached data and cache lines in the victim buffer. On a hit in the victim buffer the write completes in the victim buffer. When the victim data passes to the next cache level it is written into a second victim buffer. An entry in this second victim buffer is retired when the data is committed to cache. DMA write addresses are compared to addresses in this second victim buffer. On a match the write takes place in the second victim buffer. On a failure to match the controller sends a snoop write. In the preferred embodiment the next cache level uses shadow tags to determine whether the data is cached in higher level cache before sending the snoop write.

BRIEF DESCRIPTION OF THE DRAWINGS

0006These and other aspects of this invention are illustrated in the drawings, in which:

0007<figref idref="DRAWINGS">FIG. 1</figref> illustrates the organization of a typical digital signal processor to which this invention is applicable (prior art);

0008<figref idref="DRAWINGS">FIG. 2</figref> illustrates details of a very long instruction word digital signal processor core suitable for use in Figure (prior art);

0009<figref idref="DRAWINGS">FIG. 3</figref> illustrates the pipeline stages of the very long instruction word digital signal processor core illustrated in <figref idref="DRAWINGS">FIG. 2</figref> (prior art);

0010<figref idref="DRAWINGS">FIG. 4</figref> illustrates the instruction syntax of the very long instruction word digital signal processor core illustrated in <figref idref="DRAWINGS">FIG. 2</figref> (prior art);

0011<figref idref="DRAWINGS">FIG. 5</figref> illustrates the details of a set of typical prior art cache lines (prior art);

0012<figref idref="DRAWINGS">FIG. 6</figref> illustrates a computing system including a local memory arbiter according to an embodiment of the invention;

0013<figref idref="DRAWINGS">FIG. 7</figref> is a further view of the digital signal processor system of this invention illustrating the various cache controllers;

0014<figref idref="DRAWINGS">FIG. 8</figref> is a flow chart illustrating action when a CPU loads misses level one cache 123;

0015<figref idref="DRAWINGS">FIG. 9</figref> is a flow chart illustrating action on a DMA read;

0016<figref idref="DRAWINGS">FIG. 10</figref> is a flow chart illustrating action on a DMA write; and

0017<figref idref="DRAWINGS">FIG. 11</figref> illustrates hardware in the level one data cache controller and the level two memory controller handling interlocks on victim eviction from the level one cache.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

0018<figref idref="DRAWINGS">FIG. 1</figref> illustrates the organization of a typical digital signal processor system 100 to which this invention is applicable (prior art). Digital signal processor system 100 includes central processing unit core 110. Central processing unit core 110 includes the data processing portion of digital signal processor system 100. Central processing unit core 110 could be constructed as known in the art and would typically includes a register file, an integer arithmetic logic unit, an integer multiplier and program flow control units. An example of an appropriate central processing unit core is described below in conjunction with <figref idref="DRAWINGS">FIGS. 2 to 4</figref>.

0019Digital signal processor system 100 includes a number of cache memories. <figref idref="DRAWINGS">FIG. 1</figref> illustrates a pair of first level caches. Level one instruction cache (L1I) 121 stores instructions used by central processing unit core 110.

0020Central processing unit core 110 first attempts to access any instruction from level one instruction cache 121. Level one data cache (L1D) 123 stores data used by central processing unit core 110. Central processing unit core 110 first attempts to access any required data from level one data cache 123. The two level one caches are backed by a level two unified cache (L2) 130. In the event of a cache miss to level one instruction cache 121 or to level one data cache 123, the requested instruction or data is sought from level two unified cache 130. If the requested instruction or data is stored in level two unified cache 130, then it is supplied to the requesting level one cache for supply to central processing unit core 110. As is known in the art, the requested instruction or data may be simultaneously supplied to both the requesting cache and central processing unit core 110 to speed use.

0021Level two unified cache 130 is further coupled to higher level memory systems. Digital signal processor system 100 may be a part of a multiprocessor system. The other processors of the multiprocessor system are coupled to level two unified cache 130 via a transfer request bus 141 and a data transfer bus 143. A direct memory access unit 150 provides the connection of digital signal processor system 100 to external memory 161 and external peripherals 169.

0022<figref idref="DRAWINGS">FIG. 1</figref> illustrates several data/instruction movements within the digital signal processor system 100. These include: (1) instructions move from L2 cache 130 to L1I cache 121 to fill in response to a L1I cache miss; (2) data moves from L2 cache 130 to L1D cache 123 to fill in response to a L1D cache miss; (3) data moves from L1D cache 123 to L2 cache 130 in response to a write miss in L1D cache 123, in response to a L1D cache 123 victim eviction and in response to a snoop from L2 cache 130; (4) data moves from external memory 161 to L2 cache 130 to fill in response to L2 cache miss or a direct memory access (DMA) data transfer into L2 cache 130; (5) data moves from L2 cache 130 to external memory 161 in response to a L2 cache victim eviction or writeback and in response to a DMA transfer out of L2 cache 130; (6) data moves from peripherals 169 to L2 cache 130 in response to a DMA transfer into L2 cache 130; and (7) data moves from L2 cache 130 to peripherals 169 is response to a DMA transfer out of L2 cache 130.

0023<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram illustrating details of a digital signal processor integrated circuit 200 suitable but not essential for use in this invention (prior art). The digital signal processor integrated circuit 200 includes central processing unit 1, which is a 32-bit eight-way VLIW pipelined processor. Central processing unit 1 is coupled to level one instruction cache 121 included in digital signal processor integrated circuit 200. Digital signal processor integrated circuit 200 also includes level one data cache 123. Digital signal processor integrated circuit 200 also includes peripherals 4 to 9. These peripherals preferably include an external memory interface (EMIF) 4 and a direct memory access (DMA) controller 5. External memory interface (EMIF) 4 preferably supports access to supports synchronous and asynchronous SRAM and synchronous DRAM. Direct memory access (DMA) controller 5 preferably provides 2-channel auto-boot loading direct memory access. These peripherals include power-down logic 6. Power-down logic 6 preferably can halt central processing unit activity, peripheral activity, and phase lock loop (PLL) clock synchronization activity to reduce power consumption. These peripherals also include host ports 7, serial ports 8 and programmable timers 9.

0024Central processing unit 1 has a 32-bit, byte addressable address space. Internal memory on the same integrated circuit is preferably organized in a data space including level one data cache 123 and a program space including level one instruction cache 121. When off-chip memory is used, preferably these two spaces are unified into a single memory space via the external memory interface (EMIF) 4.

0025Level one data cache 123 may be internally accessed by central processing unit 1 via two internal ports 3a and 3b. Each internal port 3a and 3b preferably has 32 bits of data and a 32-bit byte address reach. Level one instruction cache 121 may be internally accessed by central processing unit 1 via a single port 2a. Port 2a of level one instruction cache 121 preferably has an instruction-fetch width of 256 bits and a 30-bit word (four bytes) address, equivalent to a 32-bit byte address.

0026Central processing unit 1 includes program fetch unit 10, instruction dispatch unit 11, instruction decode unit 12 and two data paths 20 and 30. First data path 20 includes four functional units designated L1 unit 22, S1 unit 23, M1 unit 24 and D1 unit 25 and 16 32-bit A registers forming register file 21. Second data path 30 likewise includes four functional units designated L2 unit 32, S2 unit 33, M2 unit 34 and D2 unit 35 and 16 32-bit B registers forming register file 31. The functional units of each data path access the corresponding register file for their operands. There are two cross paths 27 and 37 permitting access to one register in the opposite register file each pipeline stage. Central processing unit 1 includes control registers 13, control logic 14, and test logic 15, emulation logic 16 and interrupt logic 17.

0027Program fetch unit 10, instruction dispatch unit 11 and instruction decode unit 12 recall instructions from level one instruction cache 121 and deliver up to eight 32-bit instructions to the functional units every instruction cycle. Processing occurs simultaneously in each of the two data paths 20 and 30. As previously described each data path has four corresponding functional units (L, S, M and D) and a corresponding register file containing 16 32-bit registers. Each functional unit is controlled by a 32-bit instruction. The data paths are further described below. A control register file 13 provides the means to configure and control various processor operations.

0028<figref idref="DRAWINGS">FIG. 3</figref> illustrates the pipeline stages 300 of digital signal processor core 110 (prior art). These pipeline stages are divided into three groups: fetch group 310; decode group 320; and execute group 330. All instructions in the instruction set flow through the fetch, decode, and execute stages of the pipeline. Fetch group 310 has four phases for all instructions, and decode group 320 has two phases for all instructions. Execute group 330 requires a varying number of phases depending on the type of instruction.

0029The fetch phases of the fetch group 310 are: Program address generate phase 311 (PG); Program address send phase 312 (PS); Program access ready wait stage 313 (PW); and Program fetch packet receive stage 314 (PR). Digital signal processor core 110 uses a fetch packet (FP) of eight instructions. All eight of the instructions proceed through fetch group 310 together. During PG phase 311, the program address is generated in program fetch unit 10. During PS phase 312, this program address is sent to memory. During PW phase 313, the memory read occurs. Finally during PR phase 314, the fetch packet is received at CPU 1.

0030The decode phases of decode group 320 are: Instruction dispatch (DP) 321; and Instruction decode (DC) 322. During the DP phase 321, the fetch packets are split into execute packets. Execute packets consist of one or more instructions which are coded to execute in parallel. During DP phase 322, the instructions in an execute packet are assigned to the appropriate functional units. Also during DC phase 322, the source registers, destination registers and associated paths are decoded for the execution of the instructions in the respective functional units.

0031The execute phases of the execute group 330 are: Execute 1 (E1) 331; Execute 2 (E2) 332; Execute 3 (E3) 333; Execute 4 (E4) 334; and Execute 5 (E5) 335. Different types of instructions require different numbers of these phases to complete. These phases of the pipeline play an important role in understanding the device state at CPU cycle boundaries.

0032During E1 phase 331, the conditions for the instructions are evaluated and operands are read for all instruction types. For load and store instructions, address generation is performed and address modifications are written to a register file. For branch instructions, branch fetch packet in PG phase 311 is affected. For all single-cycle instructions, the results are written to a register file. All single-cycle instructions complete during the E1 phase 331.

0033During the E2 phase 332, for load instructions, the address is sent to memory. For store instructions, the address and data are sent to memory. Single-cycle instructions that saturate results set the SAT bit in the control status register (CSR) if saturation occurs. For single cycle 16 by 16 multiply instructions, the results are written to a register file. For M unit non-multiply instructions, the results are written to a register file. All ordinary multiply unit instructions complete during E2 phase 322.

0034During E3 phase 333, data memory accesses are performed. Any multiply instruction that saturates results sets the SAT bit in the control status register (CSR) if saturation occurs. Store instructions complete during the E3 phase 333.

0035During E4 phase 334, for load instructions, data is brought to the CPU boundary. For multiply extension instructions, the results are written to a register file. Multiply extension instructions complete during the E4 phase 334.

0036During E5 phase 335, load instructions write data into a register. Load instructions complete during the E5 phase 335.

0037<figref idref="DRAWINGS">FIG. 4</figref> illustrates an example of the instruction coding of instructions used by digital signal processor core 110 (prior art). Each instruction consists of 32 bits and controls the operation of one of the eight functional units. The bit fields are defined as follows. The creg field (bits 29 to 31) is the conditional register field. These bits identify whether the instruction is conditional and identify the predicate register. The z bit (bit 28) indicates whether the predication is based upon zero or not zero in the predicate register. If z=1, the test is for equality with zero. If z=0, the test is for nonzero. The case of creg=0 and z=0 is treated as always true to allow unconditional instruction execution. The creg field is encoded in the instruction opcode as shown in Table 1.

0038<tables id="TABLE-US-00001" num="00001"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="offset" colwidth="14pt" align="left" /><colspec colname="1" colwidth="63pt" align="left" /><colspec colname="2" colwidth="84pt" align="center" /><colspec colname="3" colwidth="56pt" align="center" /><thead><row><entry /><entry namest="offset" nameend="3" rowsep="1">TABLE 1</entry></row></thead><tbody valign="top"><row><entry /><entry namest="offset" nameend="3" align="center" rowsep="1" /></row><row><entry /><entry>Conditional</entry><entry>creg</entry><entry>z</entry></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="6"><colspec colname="offset" colwidth="14pt" align="left" /><colspec colname="1" colwidth="63pt" align="left" /><colspec colname="2" colwidth="14pt" align="center" /><colspec colname="3" colwidth="56pt" align="center" /><colspec colname="4" colwidth="14pt" align="center" /><colspec colname="5" colwidth="56pt" align="center" /><tbody valign="top"><row><entry /><entry>Register</entry><entry>31</entry><entry>30</entry><entry>29</entry><entry>28</entry></row><row><entry /><entry namest="offset" nameend="5" align="center" rowsep="1" /></row><row><entry /><entry>Unconditional</entry><entry>0</entry><entry>0</entry><entry>0</entry><entry>0</entry></row><row><entry /><entry>Reserved</entry><entry>0</entry><entry>0</entry><entry>0</entry><entry>1</entry></row><row><entry /><entry>B0</entry><entry>0</entry><entry>0</entry><entry>1</entry><entry>z</entry></row><row><entry /><entry>B1</entry><entry>0</entry><entry>1</entry><entry>0</entry><entry>z</entry></row><row><entry /><entry>B2</entry><entry>0</entry><entry>1</entry><entry>1</entry><entry>z</entry></row><row><entry /><entry>A1</entry><entry>1</entry><entry>0</entry><entry>0</entry><entry>z</entry></row><row><entry /><entry>A2</entry><entry>1</entry><entry>0</entry><entry>1</entry><entry>z</entry></row><row><entry /><entry>A0</entry><entry>1</entry><entry>1</entry><entry>0</entry><entry>z</entry></row><row><entry /><entry>Reserved</entry><entry>1</entry><entry>1</entry><entry>1</entry><entry>x</entry></row><row><entry /><entry namest="offset" nameend="5" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0039Note that “z” in the z bit column refers to the zero/not zero comparison selection noted above and “x” is a don't care state. This coding can only specify a subset of the 32 registers in each register file as predicate registers. This selection was made to preserve bits in the instruction coding.

0040The dst field (bits 23 to 27) specifies one of the 32 registers in the corresponding register file as the destination of the instruction results.

0041The scr2 field (bits 18 to 22) specifies one of the 32 registers in the corresponding register file as the second source operand.

0042The scr1/cst field (bits 13 to 17) has several meanings depending on the instruction opcode field (bits 3 to 12). The first meaning specifies one of the 32 registers of the corresponding register file as the first operand. The second meaning is a 5-bit immediate constant. Depending on the instruction type, this is treated as an unsigned integer and zero extended to 32 bits or is treated as a signed integer and sign extended to 32 bits. Lastly, this field can specify one of the 32 registers in the opposite register file if the instruction invokes one of the register file cross paths 27 or 37.

0043The opcode field (bits 3 to 12) specifies the type of instruction and designates appropriate instruction options. A detailed explanation of this field is beyond the scope of this invention except for the instruction options detailed below.

0044The s bit (bit 1) designates the data path 20 or 30. If s=0, then data path 20 is selected. This limits the functional unit to L1 unit 22, S1 unit 23, M1 unit 24 and D1 unit 25 and the corresponding register file A 21. Similarly, s=1 selects data path 20 limiting the functional unit to L2 unit 32, S2 unit 33, M2 unit 34 and D2 unit 35 and the corresponding register file B 31.

0045The p bit (bit 0) marks the execute packets. The p-bit determines whether the instruction executes in parallel with the following instruction. The p-bits are scanned from lower to higher address. If p=1 for the current instruction, then the next instruction executes in parallel with the current instruction. If p=0 for the current instruction, then the next instruction executes in the cycle after the current instruction. All instructions executing in parallel constitute an execute packet. An execute packet can contain up to eight instructions. Each instruction in an execute packet must use a different functional unit.

0046<figref idref="DRAWINGS">FIG. 5</figref> illustrates the details of plural cache lines such as used in L1I cache 121, L1D cache 123 and L2 cache 130 illustrated in <figref idref="DRAWINGS">FIG. 1</figref>. Cache 500 illustrated in <figref idref="DRAWINGS">FIG. 5</figref> includes cache lines 510, 520 and 520 are representative of the internal structure of cache 500. Each of cache lines 510, 520 and 530 includes: respective address tags 511, 521 and 522; respective valid bits 512, 522 and 523; respective dirty bits 513, 523 and 533; respective least recently used (LRU) indicators 514, 524 and 534; and respective data words 515, 525 and 535. Each cache line 510, 520 and 530 includes plural respective data words 515, 525 and 535. The bit length of data words 515, 525 and 535 is set by the minimal addressable data amount of CPU 110. This is typically 8 bits/1 byte.

0047Cache 500 stores data from more distant memories such as external memory 161 which are accessed by a multi-bit address. Cache 500 is organized to facilitate this storage and to facilitate finding such data in the cache. Each cache line 510, 520 and 530 typically stores 2N respective data words 515, 525 and 535, when N is an integer. The position of data words 515, 525 and 535 within the corresponding cache line 510, 520 and 530 along the dimension 501 serves as a proxy for the least significant bits of the address.

0048The position of cached data within lines along dimension 502 serves as a proxy for the next most significant bits of the address. The corresponding address tags 511, 521 and 531 form the remainder of the data word address. To determine if a memory access is to data cached within cache 500 (a cache hit), cache 500 compares the address tags for all cache lines to the most significant bits of the memory location accessed. Upon a detecting a match, the position within the cache line along dimension 501 corresponds to the least significant bits of the address permitting identification of the data word accessed.

0049Each data word 510, 520 and 530 includes a corresponding valid bit 512, 522 and 532. A first state of this valid bit indicates the corresponding data words 515, 525 or 535 are valid. An opposite state of this valid bit indicates the corresponding data words 515, 525 or 535 are not valid. There are several instances where data stored within cache 500 would not be valid. Upon initial activation of digital signal processor system 100 the L1I cache 121, L1D 123 cache and L2 cache 130 would not be loaded. Thus they would not store valid data. Accordingly, all cache lines are initially marked invalid. During a cache access a match of a requested address with address tags 511, 521 or 531 would not detect a match unless the corresponding valid bit 512, 522 or 532 indicated the data was valid.

0050Each data word 510, 520 and 530 includes a corresponding dirty bit 513, 523 and 533. A first state of this valid bit indicates the corresponding data words 515, 525 or 535 are dirty. An opposite state of this valid bit indicates the corresponding data words 515, 525 or 535 are not dirty (clean). Cache memory is generally used for both read accessed and write accesses. Upon a cache hit for a write access, the write data is written into the corresponding location within cache 500. According to the preferred writeback technique, this write data is not immediately forwarded to external memory 161. Instead the respective dirty bit 513, 523 or 533 is set to indicate dirty. A dirty indication means that there has been a write to the cached data not currently reflected in the base memory. According to the writeback technique this data is written to the base memory with the expectation that this writeback can accumulate plural writes to the memory location and nearby memory locations within the same cache line to reduce traffic on the bus to external memory 161.

0051The least recently used (LRU) bits 514, 524 and 534 are used when a cache line is replaced. Because the cache cannot hold all the data stored in the large, slow memory, the data within the cache must be replaced with new data regularly. Using a data words location within dimensions 501 and 502 as proxy for the least significant bits introduces a problem in locating data within cache 500. If there is only a single cache line having the same location on dimensions 501 and 502, then plural data from the large, slow memory will alias to the same cache line in cache 500. This is data having the same least significant address bits corresponding to dimensions 501 and 502 but differing most significant address bits. An access to such aliased data would require the previous data at that cache line to be replaced. This is considered disadvantageous. A typical prior art cache is set associative. Thus a set of cache lines have the same location on dimensions 501 and 502. Typical sets include two members (two-way set associative) or four members (four-way set associative). Each cache line of such a set is called a way. A cache miss to an address that aliases to one of these sets needs only to evict one of these ways. Determination of which way to evict is typically made based on prior usage of these ways. According to both the temporal and spatial locality principles more recently used cache ways are more likely to be reused than less recently used cache ways. LRU bits 514, 524 and 534 track accesses to cache ways within the set. When data is to be replaced the LRU bits indicate the least recently used way for replacement. Maintaining cache coherence requires writeback of a dirty way upon such replacement.

0052<figref idref="DRAWINGS">FIG. 6</figref> is a block diagram illustrating a computing system including a local memory arbiter according to an embodiment of the invention. <figref idref="DRAWINGS">FIG. 6</figref> illustrates system on a chip (SoC) 600. SoC 600 includes one or more DSP cores 610, SRAM/Caches 620 and shared memory 630. SoC 600 is preferably formed on a common semiconductor substrate. These elements can also be implemented in separate substrates, circuit boards and packages. For example shared memory 630 could be implemented in a separate semiconductor substrate. <figref idref="DRAWINGS">FIG. 6</figref> illustrates four DSP cores 610, but SoC 600 may include fewer or more DSP cores 610.

0053Each DSP core 610 preferably includes a level one data cache such as L1 SRAM/cache 612. In the preferred embodiment each L1 SRAM/cache 612 may be configured with selected amounts of memory directly accessible by the corresponding DSP core 610 (SRAM) and data cache. Each DSP core 610 has a corresponding level two combined cache L2 SRAM/cache 620. As with L1 SRAM/cache 612, each L2 SRAM/cache 620 is preferably configurable with selected amounts of directly accessible memory (SRAM) and data cache. Each L2 SRAM/cache 620 includes a prefetch unit 622. Each prefetch unit 622 prefetchs data for the corresponding L2 SRAM/cache 620 based upon anticipating the needs of the corresponding DSP core 610. Each DSP core 610 is further coupled to shared memory 630. Shared memory 630 is usually slower and typically less expensive memory than L2 SRAM/cache 620 or L1 SRAM/cache 612. Shared memory 630 typically stores program and data information shared between the DSP cores 610.

0054In various embodiments, each DSP core 610 includes a corresponding local memory arbiter 624 for reordering memory commands in accordance with a set of reordering rules. Each local memory arbiter 624 arbitrates and schedules memory requests from differing streams at a local level before sending the memory requests to central memory arbiter 634. A local memory arbiter 624 may arbitrate between more than one DSP core 610. Central memory arbiter 634 controls memory accesses for shared memory 630 that are generated by differing DSP cores 610 that do not share a common local memory arbiter 624.

0055<figref idref="DRAWINGS">FIG. 7</figref> is a further view of the digital signal processor system 100 of this invention. CPU 110 is bidirectionally connected to L1I cache 121 and L1D cache 123. L1I cache 121 and L1D cache 123 are shown together because they are at the same level in the memory hierarchy. These level one caches are bidirectionally connected to L2 130. L2 cache 130 is in turn bidirectionally connected to external memory 161 and peripherals 169. External memory 161 and peripherals 169 are shown together because they are at the same level in the memory hierarchy. Data transfers into and out of L1D cache 123 is controlled by data memory controller (DMC) 710. Data transfers into and out of L1I cache 121 is controlled by program memory controller (PMC) 720. Data transfers into and out of L2 130 including both cache and directly addressable memory (SRAM) are controlled by unified memory controller (UMC) 730.

0056<figref idref="DRAWINGS">FIG. 7</figref> illustrates further details of DMC 710 and UMC 730. DMC 710 includes L1D cache tags 711. These tags are the non-data part of cache lines 510, 520 and 530 illustrated in <figref idref="DRAWINGS">FIG. 5</figref> for L1D cache 123. UMC 730 includes two sets of cache tags. The first set of cache tags are L2 tags 731. These are non-data part of cache lines 510, 520 and 530 illustrated in <figref idref="DRAWINGS">FIG. 5</figref> for L2 cache 130. The second set of cache tags are shadow tags 732. As shown by bus 715 shadow tags 732 generally correspond to L1D cache tags 711 except these are located in UMC 730. Shadow tags 732 include at least the valid and dirty status of the corresponding cache lines in L1D cache 123.

0057UMC 730 uses shadow tags 732 to implement snoop read and write coherence. UMC 730 tracks the status of L1D cache lines. Shadow tags 732 are used only for snoops intending to keep L2 SRAM coherent with the level one data cache. Thus updates for all external cache lines are ignored. Shadow tags 732 are updated on all L1D cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM. These interactions happen on different interfaces, but the traffic on that interface includes level one data cache accesses to both external and level two directly addressable lines. These interactions create extra traffic on these interfaces and creating extra stalls to the CPU. Thus in this invention shadow tags 732 are updated only on a subset of less than all updates of the level one tags 711.

0058These tag updates are pipelined out from DMC 710 to UMC 730. Command ordering requirements require DMC 710 to ensure that all tag updates prior to a particular command have been send out to shadow tags 732. L1D cache 123 and CPU 110 stall until that is complete. The performance improvement from this invention is a result of having to do this very few times. Additional improvements come from reduced dynamic power consumption as a result of largely reduced accesses to the shadow tags 732.

0059<figref idref="DRAWINGS">FIGS. 8</figref>, 9 and 10 are flow charts illustrating the operation of this invention. UMC 730 includes a shadow copy of L1D tags 711. Shadow tags 732 contain a subset of the information held in L1D tags 711. Shadow tags 732 track what addresses L1D 123 holds and whether the cache lines associated with these addresses are clean or dirty. UMC 730 queries shadow tags 732 whenever an outside DMA request reads from or writes to L2 SRAM.

0060<figref idref="DRAWINGS">FIG. 8</figref> illustrates action when a CPU 110 loads that misses L1D cache 123 occurs. On such a CPU 110 load, L2 cache 130 returns cacheability information on the requested address and data (test block 801). If this data is cacheable (Yes at test block 801), L1D cache 123 then caches this data (block 803). If necessary this includes replacing a clean line or evicting a dirty cache line (block 802). If this data is not cacheable (No at test block 801), the CPU load completes in external memory (block 804).

0061<figref idref="DRAWINGS">FIG. 9</figref> illustrates action when a DMA read is received at UMC 730. On such a DMA read test block 901 determines from shadow tags 732 if the L1D cache 123 holds valid and dirty data for this address. If a valid and dirty copy of the data sought in the DMA read is held in L1D cache 123 (Yes at test block 901), then UMC 730 snoops this address in L1D cache 123. Such a snoop is a read request to L1D cache 123 for this data (block 902). If a valid and dirty copy of the data sought in the DMA read is not held in L1D 123 (No at test block 901), then the data is read from L2 cache 130 (block 903). In this case either the L1D copy is clean and thus is the same as the L2 copy or L1D cache 123 does not hold a valid copy. In either case the read data is supplied to the DMA requestor (block 904).

0062<figref idref="DRAWINGS">FIG. 10</figref> illustrates action when a DMA write is received at UMC 730. On such as DMA write test block 1001 determines from shadow tags 732 if L1D cache 123 holds a valid copy of the data at this address. If L1D cache 123 holds a valid copy (Yes at test block 1001), then UMC 730 would ordinarily perform a snoop read this address in L1D cache 123. This invention performs an additional check. Test block 1002 determines if there is a pending L1D read to this address. This test would ordinarily be made on boundaries equal to the L1D cache line size. Thus any DMA write to an address in the same L1D cache line as a pending L1D read satisfies this test. The manner of making this check is described below in conjunction with <figref idref="DRAWINGS">FIG. 11</figref>. If L2 cache 130 receives a DMA write to the line that L1D cache 123 is reading (Yes at test block 1002), UMC 730 stalls this DMA access and all following accesses (block 1003). The DMA write remains stalled until the L1D read operation completes. This is evidenced by a No at test block 1002. On completion of any blocking L1D read operations (No at test block 1002), UMC 730 will send a snoop write to L1D cache 123 for that line (block 1004). This completes the write in L1D cache 123. In the preferred embodiment this data is also written to L2 cache 130 assuring cache coherence (block 1004). If L1D cache 123 does not hold a valid copy (No at test block 1001), then UMC 730 completes the DMA write in L2 cache 130 (block 1005).

0063<figref idref="DRAWINGS">FIG. 11</figref> illustrates hardware in the level one data cache controller and the level two memory controller handling interlocks on victim eviction from the level one cache. Some parts illustrated in <figref idref="DRAWINGS">FIG. 11</figref> are included in DMC 710 and some parts are included in UMC 730 as indicated by the dashed line. DMC 710 includes victim buffer 1111. Data identifying the cache line is entered into an entry within victim buffer 1111 when DMC 710 selects that line for eviction. Each victim buffer entry also includes the cache line data being evicted. In this case eviction means that the cache line is dirty and altered data must be written back on replacing the cache line. An entry is retired from victim buffer 1111 when the corresponding cache line data reaches UMC 730. DMC 710 has a snoop write port 1112 connected to UMC 730. UMC 730 supplies a snoop write on snoop write port 1112 when it receives a DMA access that may be cached within L1D cache 123. Comparator 1113 compares the snoop write address to the addresses of cache lines in victim buffer 1111. On a match to victim buffer 1111 the requested DMA write takes place in victim buffer 1111. If there is no match, DMC 710 signals no match to UMC 730.

0064Victim processing progresses until the cache line data passes to UMC 730. This cache line data is stored in victim buffer 1121. When passage of this data is acknowledged by UMC 730 DMC 710 retires the corresponding entry from victim buffer 1111. A cache line is entered into an entry within victim buffer 1121 when UMC 730 receives the cache line from DMC 710. An entry in victim buffer 1121 is retired when the data is committed to L2 cache 130. In UMC 730 a DMA write access is received at DMA write buffer 1122. Comparator 1123 compares the address of the DMA write with the addresses of cache lines in victim buffer 1121. On a match UMC 730, comparator 1123 stalls the DMA write until the allocate is committed to L2 cache 130. Writes to L2 cache 130 are expected to require only a few cycles so this stall is generally short. Alternatively UMC 730 performs the DMA write in victim buffer 1121 avoiding a stall. On a non-match UMC 730 sends a snoop write to DMC 710 via snoop write port 1124. In the preferred embodiment shadow tags comparator 1125 compares the address of the DMA write with shadow tags 732. This enables UMC 730 to determine whether the data is cached in L1D cache 123 before sending the snoop write. The snoop write is sent to DMC 710 only if shadow tags 732 indicate L1D cache 123 holds data corresponding to the DMA write. An entry is retired from DMA write buffer 1122 upon confirmation of write into victim buffer 1111 or victim buffer 1121. If neither L1D cache 123, victim buffer 1111 nor victim buffer 1121 hold the data, then UMC 730 completes the write into L2 SRAM. In this case there is no potentially interfering cache copy of the data to be corrupted.

0065When L1D cache 123 evicts a line, either due to a user controlled coherence operation or while processing a read miss for a dirty line, multiple locks are set. This prevents data corruption by a DMA write to the same line as the victim. The life of the DMA transaction and the L1D victim in the L1D and L2 controller are tracked. Various locks set when they interact. Initially L1D cache 123 owns the victim and UMC 730 is allowed to send snoop writes to the victim line. Upon such a snoop L1D cache 123 checks for the status of all pending snoops and victims in its pipeline and handles data updates in the correct order. After UMC 730 sees the victim from DMC 710, it flushes any DMA requests in its pipeline to that line and then starts processing the L1D cache victim. At this time instead of checking just shadow tags 732, UMC 730 also checks if the DMA hits either the victim in processes. If L1D cache 123 still has the victim in its cache or victim buffer, UMC 730 will snoop to that line. If the line is being evicted, UMC 730 stalls any DMA request to that line.

0066This invention also includes a new protocol to control the transfer of the L1D cache victim line between DMC 710 and UMC 730. The protocol starts when DMC 710 sends information to UMC 730 on a victim line before the victim starts. This allows UMC 730 to setup its locks. When the read victim starts, there is a handshake between the DMC 710 and UMC 730 based on these locks and the possible presence of any DMA request or potential snoops in the L2 pipeline. Once the victim is accepted, the UMC 730 owns the victim line and prevents any access to it.

0067Prior art systems would stall the L1D victim if there was any DMA to the line being evicted. This caused performance degradation. Other prior art solutions included a complex handshake through which the L2 controller and the L1D cache controller tracked the state of the victim. This included control bits that forced the L1D cache controller to commit the snoop to either its cache or victim buffer. This handshake also added latency cycles to the DMA.

0068In this invention both controllers track the status of the victim line, and then decides whether to snoop or not. This is tracked through a number of interface signals. These operations do not add cycles to the DMA. This tracking instead is used to correctly commit data to the victim line in various stages of its life.

Contents6

Every citation, both ways

Citations
Document	Relation	Office	Cited during
CN107844430A	Cited by	China	Search report
US10860480B2	Cited by	United States of America	Applicant
US2002169935A1	Cites	United States of America	Search report
US2003084250A1	Cites	United States of America	Search report
US2005132140A1	Cites	United States of America	Search report
US2008109606A1	Cites	United States of America	Search report
US2010153650A1	Cites	United States of America	Search report
US5526510A	Cites	United States of America	Search report
US5564035A	Cites	United States of America	Search report
US5708792A	Cites	United States of America	Search report
US5860117A	Cites	United States of America	Search report
US6058447A	Cites	United States of America	Search report
US6148372A	Cites	United States of America	Search report
US6275909B1	Cites	United States of America	Search report
US6321305B1	Cites	United States of America	Search report
US6408345B1	Cites	United States of America	Search report
US6477622B1	Cites	United States of America	Search report
US6484238B1	Cites	United States of America	Search report
US8117395B1	Cites	United States of America	Search report
US20020169935A1	Cites	United States of America	Search report
US20030084250A1	Cites	United States of America	Search report
US20050132140A1	Cites	United States of America	Search report
US20080109606A1	Cites	United States of America	Search report
US20100153650A1	Cites	United States of America	Search report

68 members in 1 office

This recordMember, by publication datePriority claim

Priority claims2

Priority claims
Document	Office	Kind	Date
38728310	United States of America	P	2010-09-28
201113247209	United States of America	A	2011-09-28

Members68

Family members, oldest first
Document	Office	Kind
US2012075005A1	United States of America	A1	2012-03-29
US2012079102A1	United States of America	A1	2012-03-29
US2012079155A1	United States of America	A1	2012-03-29
US2012079203A1	United States of America	A1	2012-03-29
US2012079204A1	United States of America	A1	2012-03-29
US2012079247A1	United States of America	A1	2012-03-29
US2012191913A1	United States of America	A1	2012-07-26
US2012191914A1	United States of America	A1	2012-07-26
US2012191915A1	United States of America	A1	2012-07-26
US2012191916A1	United States of America	A1	2012-07-26
US2012192027A1	United States of America	A1	2012-07-26
US2012197954A1	United States of America	A1	2012-08-02
US2012198160A1	United States of America	A1	2012-08-02
US2012198161A1	United States of America	A1	2012-08-02
US2012198162A1	United States of America	A1	2012-08-02
US2012198163A1	United States of America	A1	2012-08-02
US2012198164A1	United States of America	A1	2012-08-02
US2012198165A1	United States of America	A1	2012-08-02
US2012198166A1	United States of America	A1	2012-08-02
US2012198171A1	United States of America	A1	2012-08-02
US2012198192A1	United States of America	A1	2012-08-02
US2012198272A1	United States of America	A1	2012-08-02
US2012198310A1	United States of America	A1	2012-08-02
US2012260031A1	United States of America	A1	2012-10-11
US2012290755A1	United States of America	A1	2012-11-15
US2012290756A1	United States of America	A1	2012-11-15
US2012314833A1	United States of America	A1	2012-12-13
US8532247B2	United States of America	B2	2013-09-10
US2013243148A1	United States of America	A1	2013-09-19
US8547164B2	United States of America	B2	2013-10-01
US8560896B2	United States of America	B2	2013-10-15
US8598932B2	United States of America	B2	2013-12-03
US8607000B2	United States of America	B2	2013-12-10
US8656105B2	United States of America	B2	2014-02-18
US8661199B2	United States of America	B2	2014-02-25
US8683115B2	United States of America	B2	2014-03-25
US8683137B2	United States of America	B2	2014-03-25
US8707127B2	United States of America	B2	2014-04-22
US8732398B2	United States of America	B2	2014-05-20
US8732416B2	United States of America	B2	2014-05-20
US8832166B2	United States of America	B2	2014-09-09
US8856446B2	United States of America	B2	2014-10-07
US8880855B2	United States of America	B2	2014-11-04
US8904110B2	United States of America	B2	2014-12-02
US8904115B2	United States of America	B2	2014-12-02
US8904260B2	United States of America	B2	2014-12-02
US9003122B2	United States of America	B2	2015-04-07
US9009408B2	United States of America	B2	2015-04-14
US2015178221A1	United States of America	A1	2015-06-25
US9075743B2	United States of America	B2	2015-07-07
US9075744B2	United States of America	B2	2015-07-07
US2015269090A1	United States of America	A1	2015-09-24
US9183084B2	United States of America	B2	2015-11-10
US9189331B2	United States of America	B2	2015-11-17
US9195610B2	United States of America	B2	2015-11-24
US2016034396A1	United States of America	A1	2016-02-04
US9268708B2This record	United States of America	B2	2016-02-23
US9298643B2	United States of America	B2	2016-03-29
US9575901B2	United States of America	B2	2017-02-21
US2017097894A1	United States of America	A1	2017-04-06
US9965395B2	United States of America	B2	2018-05-08
US2018129608A9	United States of America	A9	2018-05-10
US2019004967A1	United States of America	A1	2019-01-03
US10713180B2	United States of America	B2	2020-07-14
US2020401532A1	United States of America	A1	2020-12-24
US11537532B2	United States of America	B2	2022-12-27
US2023244611A1	United States of America	A1	2023-08-03
US12524351B2	United States of America	B2	2026-01-13

38 transactions on the USPTO file

Allowed after 1 non-final rejection.

Non-final rejections: 1
Final rejections: 0
RCEs: 0
Appeals: 0

Over time

Point at a mark for the transaction

Transactions

Prosecution transactions, newest first
	Event	Code
2023-07-21	Payment of Maintenance Fee, 8th Year, Large EntityM1552	M1552
2019-07-16	Payment of Maintenance Fee, 4th Year, Large EntityM1551	M1551
2016-02-23	Recordation of Patent Grant MailedPGM/	PGM/
2016-02-23	Patent Issue Date Used in PTA CalculationAllowedPTAC	PTAC
2016-02-04	Email NotificationEML_NTR	EML_NTR
2016-02-03	Issue Notification MailedAllowedWPIR	WPIR
2016-01-12	Dispatch to FDCD1935	D1935
2016-01-07	Application Is Considered Ready for IssuePILS	PILS
2016-01-06	Supplemental Papers - Oath or DeclarationC600	C600
2016-01-06	Issue Fee Payment VerifiedN084	N084
2016-01-06	Issue Fee Payment ReceivedIFEE	IFEE
2015-12-14	Electronic ReviewELC_RVW	ELC_RVW
2015-12-14	Email NotificationEML_NTF	EML_NTF
2015-12-14	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2015-12-09	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2015-11-20	Date Forwarded to ExaminerFWDX	FWDX
2015-11-12	Response after Non-Final ActionA...	A...
2015-08-31	Application ready for PDX access by participating foreign officesCCRDY	CCRDY
2015-08-14	Electronic ReviewELC_RVW	ELC_RVW
2015-08-14	Email NotificationEML_NTF	EML_NTF
2015-08-14	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2015-08-10	Non-Final RejectionNon-final rejectionCTNF	CTNF
2015-06-26	Email NotificationEML_NTR	EML_NTR
2015-06-25	PG-Pub Issue NotificationPG-ISSUE	PG-ISSUE
2015-03-18	Case Docketed to Examiner in GAUDOCK	DOCK
2015-03-18	Email NotificationEML_NTR	EML_NTR
2015-03-18	Application Is Now CompleteCOMP	COMP
2015-03-18	Filing ReceiptFLRCPT.O	FLRCPT.O
2015-03-18	Application Is Now CompleteCOMP	COMP
2015-03-17	Application Dispatched from OIPEOIPE	OIPE
2015-03-17	FITF set to NO - revise initial settingFTFI	FTFI
2015-03-06	Cleared by OIPE CSRL194	L194
2015-03-04	Preliminary AmendmentA.PE	A.PE
2015-03-04	Patent Term Adjustment - Ready for ExaminationPTA.RFE	PTA.RFE
2015-03-04	Applicants have given acceptable permission for participating foreignAPPERMS	APPERMS
2015-03-04	IFW Scan & PACR Auto Security ReviewSCAN	SCAN
2015-03-04	Entity Status Set To Undiscounted (Initial Default Setting or Status Change)BIG.	BIG.
2015-03-04	Initial Exam Team nnIEXX	IEXX

3 legal events, as the office reported them to INPADOC

Over the term

Point at a mark for the event

Events

Legal events, newest first
	Event	Code
2023-07-21	Maintenance fee paymentMAFP	MAFP
2019-07-16	Maintenance fee paymentMAFP	MAFP
2016-02-03	Information on status: patent grantGrantedPATENTED CASESTCF	STCF