Vertical transistor and method to form vertical transistor contact node

CROSS REFERENCE TO RELATED APPLICATION

0001This application claims the benefit of Taiwan patent application No. 103118454, filed on May 27, 2014, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

00021. Field of the Invention

0003The present invention generally relates to a vertical transistor structure and a method of forming a contact node of the vertical transistor structure. In particular, the present invention for forming a composite contact node in the vertical transistor structure, whereby the outward contact resistance of the vertical transistor structure can be reduced.

00042. Description of the Prior Art

0005Dynamic random access memory (DRAM) is a semiconductor element wherein a capacitor structure is electrically connected to a gate structure. The storage capacitor is the core elements of the dynamic random access memory, which is responsible for storing the signal or data. Depending on the position of the storage capacitor, the dynamic random access memory can be divided into trench type and stacked capacitor structures. When considering the manufacturing capacity, the physical limit of the material, leakage current, precision and exposure and etching processes, the stacked capacitor structure has advantage over the trench capacitor.

0006A trench capacitor is usually located under the gate electrode, and stacked capacitor structure is located above the gate electrode, so manufacturing steps for the stacked capacitor structure will fall after the gate electrode structure fabrication steps. Therefore, the gate structure at the time of manufacture, it will leave an upward node, to be connected with the stacked capacitor structure. Thus, when a stack capacitor structure is completed, contact node for electrically connecting the capacitor and the gate structure is formed.

0007However, the current process simply uses silicon as a material for the node, so the contact node does not have an ideal low contact resistance (outward contact resistance), which has become one obstacle to the performance improvement of the dynamic random access memory.

SUMMARY OF THE INVENTION

0008The present invention, therefore, discloses a vertical transistor structure and a method for forming contact node of the vertical transistor structure. In order to solve the problem of contact resistance when simply using silicon as a electrical contact node, the present invention particularly proposes a composite contact node in the vertical transistor structure, which can reduce the outward contact resistance of the gate structure in the vertical transistor structure.

0009In one aspect, the present invention discloses a vertical transistor structure, comprising a substrate having a protruding structure; an offset layer covering a top surface of the protruding structure; and an interlayer on the offset layer, wherein the interlayer comprises a composite conductive layer formed from the offset layer. In particular, the interlayer acts as a contact node in the vertical transistor structure.

0010In one embodiment, the substrate is a doped silicon substrate.

0011In another embodiment, the protruding structure is a cubic shaped structure.

0012In another embodiment, the protruding structure is an island-like pillar.

0013In another embodiment, the offset layer is a deposited silicon layer.

0014In another embodiment, the vertical transistor structure further comprises a conductive layer atop the offset layer, wherein the conductive layer comprises tungsten or titanium.

0015In another embodiment, the composite conductive layer is a metal silicide between the offset layer and the conductive layer.

0016In another embodiment, the composite conductive layer comprises tungsten silicide.

0017In another embodiment, the interlayer comprises a conductive material layer.

0018In another embodiment, the conductive material layer comprises tungsten or titanium, wherein the composite conductive layer is a metal silicide between the offset layer and the conductive layer.

0019In one aspect, the present invention discloses a method for fabricating a contact node of a vertical transistor, including the steps of: <ul id="ul0001" list-style="none"><li id="ul0001-0001" num="0000"><ul id="ul0002" list-style="none"><li id="ul0002-0001" num="0020">providing a stack material layer comprising a hard mask layer, an offset layer, and a conductive layer;</li><li id="ul0002-0002" num="0021">patterning the hard mask layer to form an etch hard mask;</li><li id="ul0002-0003" num="0022">etching the stack material layer not covered by the etch hard mask to form a protruding structure; and</li><li id="ul0002-0004" num="0023">subjecting the stack material layer to an annealing process thereby forming an interlayer comprising a composite conductive layer.</li></ul></li></ul>

0024In one embodiment, the stack material layer comprises, in the order of, the hard mask layer, the conductive layer, and the offset layer, wherein the offset layer and the conductive layer react together to form the composite conductive layer.

0025In another embodiment, the stack material layer further comprises a substrate and a conductive material layer, wherein the offset layer covers the substrate, and wherein the offset layer and the conductive layer react together to form the composite conductive layer.

0026In another embodiment, the offset layer is a deposited silicon layer.

0027In another embodiment, the conductive layer comprises tungsten or titanium.

0028In another embodiment, the composite conductive layer is a metal silicide layer.

0029In another embodiment, the interlayer further comprises a conductive material layer.

0030In another embodiment, the conductive material layer comprises tungsten or titanium.

0031In another embodiment, the method further comprising: <ul id="ul0003" list-style="none"><li id="ul0003-0001" num="0000"><ul id="ul0004" list-style="none"><li id="ul0004-0001" num="0032">performing an oxidation process to form a gate oxide layer on surfaces of the protruding structure.</li></ul></li></ul>

0033In another embodiment, the method further comprising: <ul id="ul0005" list-style="none"><li id="ul0005-0001" num="0000"><ul id="ul0006" list-style="none"><li id="ul0006-0001" num="0034">forming a spacer on surfaces of the protruding structure.</li></ul></li></ul>

0035In another embodiment, the method further comprising: <ul id="ul0007" list-style="none"><li id="ul0007-0001" num="0000"><ul id="ul0008" list-style="none"><li id="ul0008-0001" num="0036">forming a dielectric layer to cover the protruding structure; and</li><li id="ul0008-0002" num="0037">partially removing the dielectric layer, and removing the conductive layer without exposing underlying said interlayer.</li></ul></li></ul>

0038Since the present invention uses annealing process, the laminated material layer includes the interlayer comprising the composite conductive layer, and able to provide contact node with stable physical and chemical properties and low contact resistance, so as to improve the performance of dynamic random access memory.

0039These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

<figref idref="DRAWINGS">FIG. 1</figref> to <figref idref="DRAWINGS">FIG. 10</figref>, <figref idref="DRAWINGS">FIG. 5A</figref> to <figref idref="DRAWINGS">FIG. 10A</figref>, and <figref idref="DRAWINGS">FIG. 9B</figref> illustrate a preferred process for forming the vertical transistor structure according to the invention;

<figref idref="DRAWINGS">FIG. 11</figref> and <figref idref="DRAWINGS">FIG. 11A</figref> illustrate a preferred process for forming contact node of the vertical transistor structure according to the invention; and

<figref idref="DRAWINGS">FIG. 12</figref> and <figref idref="DRAWINGS">FIG. 12A</figref> illustrate one preferred embodiment of vertical transistor structure with contact node according to the invention.

DETAILED DESCRIPTION

0043The present invention provides a vertical transistor structure having a composite contact node and a method for forming such composite contact node in the vertical transistor structure. To address the problem of unsatisfactory contact resistance because only silicon material is typically used as an electrical contact node, the present invention provides a composite contact node in the vertical transistor structure. The proposed composite contact node can reduce the outward contact resistance of a gate structure of the vertical transistor structure. Further, the conductive material used in the composite contact node can help to form a landing pad with the lower electrode of the other elements.

0044According to one aspect of the present invention, a method for forming a contact node of a vertical transistor structure is provided. Referring to <figref idref="DRAWINGS">FIG. 3</figref>, a laminated material layer <b>10</b> is prepared. The laminated material layer <b>10</b> comprises a substrate <b>11</b>, a buffer layer (offset layer) <b>12</b>, a conductive layer <b>13</b>, and a hard mask layer <b>14</b>. As necessary, referring to <figref idref="DRAWINGS">FIG. 4</figref>, in addition to the substrate <b>11</b>, the buffer layer <b>12</b>, the conductive layer <b>13</b> and the hard mask layer <b>14</b>, the laminated material layer <b>10</b> may also comprise a conductive material layer <b>15</b>, and the buffer layer <b>12</b> still directly covers the substrate <b>11</b>. In <figref idref="DRAWINGS">FIG. 3</figref> or <figref idref="DRAWINGS">FIG. 4</figref>, with or without a conductive material layer <b>15</b> in the laminated material layer <b>10</b>, the hard mask layer <b>14</b> will be the topmost layer.

0045The process for forming the aforesaid laminated material layer is shown in <figref idref="DRAWINGS">FIG. 1</figref> or <figref idref="DRAWINGS">FIG. 2</figref>. The substrate <b>11</b> may be subjected to, for example, sputtering or deposition process, to sequentially form thereon the buffer layer <b>12</b>, the conductive layer <b>13</b>, conductive material layer <b>15</b> as necessary, and the hard mask layer <b>14</b>.

0046The substrate <b>11</b> is typically a semiconductor material such as silicon. Depending on the design requirements, typically, the substrate <b>11</b> is appropriately doped with, for example, P-type or N-type dopants. The buffer layer <b>12</b> may be a semiconductor material such as deposited silicon layer (deposited Si), which is located on the substrate <b>11</b>. The buffer layer <b>12</b> is used as a buffer between the substrate <b>11</b> and the adjacent conductive layer <b>13</b> or the conductive material layer <b>15</b> as necessary. The conductive layer <b>13</b> is typically a metallic material, preferably those capable of forming a metal silicide with silicon to have stable physical and chemical properties and low resistance, such as tungsten or titanium. The conductive material layer <b>15</b> as required may be of another metal materials, preferably those capable of forming a metal silicide with silicon to have stable physical and chemical properties and low resistance, such as tungsten or titanium. It noteworthy that the conductive layer <b>13</b> and the conductive material layer <b>15</b> are mutually different. The hard mask layer <b>14</b> may be a patternable material such as silicon nitride.

0047Please refer to <figref idref="DRAWINGS">FIG. 5</figref>, the hard mask layer <b>14</b> is patterned to form an etch mask layer <b>14</b>′. The etch mask layer <b>14</b>′ is used as vertical gate post (not shown) when a vertical transistor structure (not shown) is subsequently defined and constructed. The step of patterning the hard mask layer <b>14</b> may involve the use of photoresist materials (not shown) in combination with the conventional lithography, etching and other procedures to thereby form the etch mask layer <b>14</b>′. <figref idref="DRAWINGS">FIG. 5A</figref> is a top view of <figref idref="DRAWINGS">FIG. 5</figref>, which includes the conductive material layer <b>15</b>. As shown in <figref idref="DRAWINGS">FIG. 5A</figref>, the etch mask layer <b>14</b>′ each has rectangular pattern and is not connected to an adjacent etch mask layer <b>14</b>′.

0048Referring to <figref idref="DRAWINGS">FIG. 6</figref>, using the etching mask layer <b>14</b>′ and suitable etchant, the laminated material layer <b>10</b> is etched. The material layers in the laminated material layer <b>10</b>, such as the conductive material layer <b>15</b> as required, the conductive layer <b>13</b>, the buffer layer <b>12</b> and the substrate <b>11</b>, may be etched with one-step etch or multi-step etch process. Mixed formulations or etch recipes may be used to etch the laminated material layer <b>10</b> to form protruding structures <b>20</b>. Preferably, over-etching the substrate <b>11</b> may be implemented such that the lower part of the protruding structures <b>20</b> is exposed within the substrate <b>11</b>. By adjusting the depth when over etching the substrate <b>11</b>, a desired height of the vertical transistor structure may be achieved. <figref idref="DRAWINGS">FIG. 6A</figref> is a top view of <figref idref="DRAWINGS">FIG. 6</figref>, which includes the conductive material layer <b>15</b>. Each protruding structure <b>20</b> is capped by etch mask layer <b>14</b>′ and is a cubic shaped structure, for example, an isolated island-like pillar. The protruding structures <b>20</b> are not physically connected to one another.

0049As shown in <figref idref="DRAWINGS">FIG. 7</figref> and <figref idref="DRAWINGS">FIG. 7A</figref>, the protruding structures <b>20</b> formed in the laminated material layer <b>10</b> are subjected to annealing treatment. By performing the annealing treatment, reaction may occur at the interface between the buffer layer <b>12</b> and the conductive layer <b>13</b>, or at the interface between the buffer layer <b>12</b> and the conductive material layer <b>15</b>, thereby forming a new material layer. The new material layer interposed between the buffer layer <b>12</b> and the conductive layer <b>13</b> is referred to as interlayer <b>21</b>. The aforesaid annealing process may be carried out at 600° C. to 1200° C. in a furnace or rapid thermal processing apparatus.

0050For example, referring to <figref idref="DRAWINGS">FIG. 7</figref>, in a case that the conductive material layer is not required, the buffer layer <b>12</b> reacts with the conductive layer <b>13</b> to form the composite conductive layer <b>16</b>. As shown in <figref idref="DRAWINGS">FIG. 7A</figref>, in a case that the conductive material layer is required, the buffer layer <b>12</b> reacts with the conductive material layer <b>15</b> to form the composite conductive layer <b>16</b>. It depends on which of the conductive layer <b>13</b> or the conductive material layer <b>15</b> is in direct contact with the buffer layer <b>12</b>. Therefore, the interlayer <b>21</b> may be only composite conductive layer <b>16</b>, or further comprises the conductive material layer <b>15</b> as required. The formed composite conductive layer <b>16</b> may be comprised of metal silicide, such as those having stable physical and chemical properties and low resistance. If the conductive layer <b>13</b> and the conductive material layer <b>15</b> comprise tungsten or titanium, the composite conductive layer <b>16</b> may be metal silicide of tungsten or titanium, for example, tungsten silicide or titanium silicide.

0051According to another embodiment of the invention, the method for forming the contact node of the vertical transistor structure further comprises forming gate oxide layer that is required in the vertical transistor structure. For example, referring to <figref idref="DRAWINGS">FIG. 8</figref> and <figref idref="DRAWINGS">FIG. 8A</figref>, the exposed protruding structures <b>20</b> are subjected to an oxidation process. When the surfaces of the exposed protruding structures <b>20</b> contain silicon, for example, the substrate <b>11</b> and the buffer layer <b>12</b>, gate oxide layer <b>22</b> is formed on the surfaces of the exposed protruding structures <b>20</b> after oxidation. The aforesaid oxidation process may be in-situ steam growth (ISSG) process. The gate oxide layer <b>22</b> may have an effective oxide thickness of 1 nm to 20 nm.

0052According to another embodiment of the invention, the method for forming the contact node of the vertical transistor structure further comprises forming a spacer surrounding the vertical transistor structure. For example, referring to <figref idref="DRAWINGS">FIG. 9</figref> and <figref idref="DRAWINGS">FIG. 9A</figref>, after forming the gate oxide layer <b>22</b>, a spacer is formed on the surface of each the protruding structures <b>20</b> to protect the gate oxide layer <b>22</b>. As shown in <figref idref="DRAWINGS">FIG. 9B</figref>, to form the spacer <b>23</b>, one-layer or multi-layer spacer material film <b>23</b>′ is conformally formed on the surface of each of the protruding structures <b>20</b>. The spacer material film <b>23</b>′ may be comprised of a dielectric material, for example, silicon nitride, silicon oxide, or a combination thereof. Subsequently, as shown in <figref idref="DRAWINGS">FIG. 9</figref> and <figref idref="DRAWINGS">FIG. 9A</figref>, a selective etching process is performed to remove portions of the spacer material film <b>23</b>′, for example, the horizontal portions thereof, thereby transforming the spacer material film <b>23</b>′ into spacer <b>23</b> that can be used to protect the gate oxide layer <b>22</b> on the surface of each of the protruding structures <b>20</b>.

0053Please refer to <figref idref="DRAWINGS">FIG. 10</figref> and <figref idref="DRAWINGS">FIG. 10A</figref>, according to another embodiment of the invention, the method for forming the contact node of the vertical transistor structure further comprises forming a dielectric layer <b>24</b> to cover the protruding structures <b>20</b>. For example, as shown in <figref idref="DRAWINGS">FIG. 9</figref> and <figref idref="DRAWINGS">FIG. 9A</figref>, after the formation of the spacer <b>23</b>, a dielectric layer <b>24</b> is formed to cover the protruding structures <b>20</b> having thereon the gate oxide layer <b>22</b> and the spacer <b>23</b>. Each of the protruding structures <b>20</b> having thereon the gate oxide layer <b>22</b> and the spacer <b>23</b> becomes independent and isolated vertical transistor <b>1</b> due to the isolation of the dielectric layer <b>24</b>.

0054According to another embodiment of the invention, referring to <figref idref="DRAWINGS">FIG. 11</figref> and <figref idref="DRAWINGS">FIG. 11A</figref>, after the formation of the vertical transistor structure <b>1</b>, the method further comprises the step of forming a contact node of the vertical transistor structure <b>1</b>. For example, after forming the dielectric layer <b>24</b> to cover the protruding structures <b>20</b> with gate oxide layer <b>22</b> and spacer <b>23</b>, the dielectric layer <b>24</b> is partially removed, while trying to remove the conductive layer <b>13</b> or conductive material layer <b>15</b> that is in direct contact with the composite conductive layer <b>16</b>. Chemical mechanical polishing (CMP) may be used, using the material layer above the composite conductive layer <b>16</b> as the polishing stop layer, such that the polishing stops at the bottom of the material layer above the composite conductive layer <b>16</b>, such as the bottom of the conductive layer <b>13</b> or conductive material layer <b>15</b>. In this way, the conductive layer <b>13</b> or the conductive material layer <b>15</b> can be removed as much as possible to reduce the vertical height of the vertical transistor structure <b>1</b>, while the underlying composite conductive layer <b>16</b> is not exposed.

0055The present invention vertical transistor structure is now complete, with very low contact resistance node <b>30</b> (composite conductive layer <b>16</b> protected by a very thin upper layer) as an electrical connection between the vertical transistor structure <b>1</b> and a stacked capacitor (not shown). Because of this the contact node <b>30</b> having the desired physical properties of low contact resistance and is stable, it can effectively improve the performance of dynamic random access memory.

0056After the above steps, the present invention can be obtained in another aspect provided by, a vertical transistor structure with a very low resistance contact node. <figref idref="DRAWINGS">FIG. 12</figref> and <figref idref="DRAWINGS">FIG. 12A</figref> respectively illustrate different embodiments of the invention vertical transistor structure with low resistance contact node <b>30</b>. As depicted in <figref idref="DRAWINGS">FIG. 12</figref>, the present invention discloses a vertical transistor structure <b>1</b> with ultra-low ohmic contact node <b>30</b>, comprising a substrate <b>11</b>, a buffer layer <b>12</b>, a conductive layer <b>13</b>, a composite conductive layer <b>16</b>, an interlayer <b>21</b>, a gate oxide layer <b>22</b>, and spacer <b>23</b>. The substrate <b>11</b> has protruding structures <b>20</b>, and the buffer layer <b>12</b> covers the top surface of the protruding structures <b>20</b>. The protruding structure is a cubic shaped structure, for example, an island-like pillar and disconnected from one another. The conductive layer <b>13</b> is located on the buffer layer <b>12</b>. The interlayer <b>21</b> is interposed between the buffer layer <b>12</b> and the conductive layer <b>13</b>, which is a composite conductive layer <b>16</b> formed by reacting the conductive layer <b>13</b> with the buffer layer <b>12</b>. In particular, the interlayer <b>21</b> is used as a contact node <b>30</b> of the vertical transistor structures <b>1</b>. The dielectric layer <b>24</b> is located between the vertical transistor structures <b>1</b> for insulating purposes between the vertical transistor structures <b>1</b>.

0057As shown in <figref idref="DRAWINGS">FIG. 12</figref> and <figref idref="DRAWINGS">FIG. 12A</figref>, the present invention discloses an extremely low resistance contact node <b>30</b> of vertical transistor structure <b>1</b>. The vertical transistor structure <b>1</b> may comprise a substrate <b>11</b>, a buffer layer <b>12</b>, a conductive layer <b>13</b>, a conductive material layer <b>15</b>, a composite conductive layer <b>16</b>, an interlayer <b>21</b>, a gate oxide layer <b>22</b>, and spacer <b>23</b>. The substrate <b>11</b> has protruding structures <b>20</b>, and the buffer layer <b>12</b> covers the top surface of the protruding structures <b>20</b>. The protruding structure is a cubic shaped structure, for example, an island-like pillar and disconnected from one another. The conductive layer <b>13</b> is located on the buffer layer <b>12</b>. The conductive layer <b>13</b> is located on the conductive material layer <b>15</b> such that the interlayer <b>21</b> comprising the conductive material layer <b>15</b> and the composite conductive layer <b>16</b> is interposed between the buffer layer <b>12</b> and the conductive layer <b>13</b>. The composite conductive layer <b>16</b> is formed by reacting the conductive layer <b>13</b> with the buffer layer <b>12</b>. In particular, the interlayer <b>21</b> and the conductive layer <b>13</b> are used as a contact node <b>30</b> of the vertical transistor structures <b>1</b>. The dielectric layer <b>24</b> is located between the vertical transistor structures <b>1</b> for insulating purposes between the vertical transistor structures <b>1</b>.

0058The substrate <b>11</b> is typically a semiconductor material such as silicon. Depending on the design requirements, typically, the substrate <b>11</b> is appropriately doped with, for example, P-type or N-type dopants. The buffer layer <b>12</b> may be a semiconductor material such as deposited silicon layer (deposited Si), which is located between the substrate <b>11</b> and the conductive layer <b>13</b>. The buffer layer <b>12</b> is used as a buffer between the substrate <b>11</b> and the adjacent conductive layer <b>13</b>. The conductive layer <b>13</b> is typically a metallic material, preferably those capable of forming a metal silicide with silicon to have stable physical and chemical properties and low resistance, such as tungsten or titanium. The conductive material layer <b>15</b> as required may be of another metal materials, preferably those capable of forming a metal silicide with silicon to have stable physical and chemical properties and low resistance, such as tungsten or titanium. It noteworthy that the conductive layer <b>13</b> and the conductive material layer <b>15</b> are mutually different.

0059The material layer interposed between the buffer layer <b>12</b> and the conductive layer <b>13</b> is interlayer <b>21</b>. The composite conductive layer <b>16</b> may be comprised of metal silicide, such as those having stable physical and chemical properties and low resistance. If the conductive layer <b>13</b> and the conductive material layer <b>15</b> comprise tungsten or titanium, the composite conductive layer <b>16</b> may be metal silicide of tungsten or titanium, for example, tungsten silicide or titanium silicide. In addition, the vertical transistor structure <b>1</b> also includes the gate oxide layer <b>22</b> on the surface of the protruding structure <b>20</b>, and the spacer <b>23</b> around the protruding structure <b>20</b>, used to protect the gate oxide layer <b>22</b>. The gate oxide layer <b>22</b> may have an effective oxide thickness of 1 nm-20 nm. As shown, the spacer <b>23</b> and the gate oxide layer <b>22</b> are buried in the dielectric layer <b>24</b>.

0060Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.