Semiconductor test device and method for fabricating the same

CROSS-REFERENCE TO RELATED APPLICATION

0001This application claims priority from Korean Patent Application No. 10-2013-0020636 filed on Feb. 26, 2013 in the Korean Intellectual Property Office, and all the benefits accruing therefrom under 35 U.S.C. 119, the contents of which in its entirety are herein incorporated by reference.

BACKGROUND

00021. Field

0003Example embodiments relate to semiconductor test devices and/or methods for fabricating the same.

00042. Description of the Related Art

0005As a semiconductor device becomes compact and highly integrated, improving the accuracy and reliability of the semiconductor device becomes an important research issue. Thus, various tests are being conducted on the semiconductor device. In particular, because the semiconductor device is sensitive to a temperature, research to figure out where and how heat is generated in the semiconductor device is being underway.

0006In order to measure temperature characteristics of a material used in a semiconductor chip, a thermal test die may be used. Temperatures of the semiconductor chip and resistances depending on the temperatures of the semiconductor chip may be measured using the thermal test die.

SUMMARY

0007Example embodiments of the present inventive concepts provide semiconductor test devices, which can effectively sense a temperature and can facilitate wiring of a test substrate.

0008Example embodiments of the present inventive concepts also provide methods of fabricating semiconductor test devices, which can effectively sense a temperature and can facilitate wiring of a test substrate.

0009These and other aspects of the present inventive concepts will be described in or be apparent from the following description of the example embodiments.

0010According to example embodiments of the present inventive concepts, a semiconductor test device may include a first thermal test flip chip cell including a first heater and a first sensor, the first thermal test flip chip cell including a plurality of first bumps arranged on a bottom surface thereof, the plurality of first bumps configured to electrically connect to the first heater and the first sensor, and a test substrate formed under the first thermal test flip chip cell, the test substrate including a first ball array arranged on a bottom surface thereof in a first direction, the first ball array configured to electrically connect to the plurality of first bumps.

0011According to example embodiments of the present inventive concepts, a method of fabricating a semiconductor test device may include providing a first thermal test flip chip cell and a test substrate, the first thermal test flip chip cell including a first heater and a first sensor, and a plurality of first bumps arranged on a bottom surface thereof, the test substrate under the first thermal test flip chip cell and including a first ball array arranged on a bottom surface of the test substrate in a first direction, connecting the first heater and the first sensor to the plurality of first bumps, and connecting the plurality of first bumps to the first ball array.

0012According to example embodiments of the present inventive concepts, a semiconductor test device may include at least one thermal test flip chip cell including a heater and at least one sensor, the at least one thermal test flip chip cell including a plurality of bumps arranged on a bottom surface thereof, the plurality of bumps configured to electrically connect to the heater and the at least one sensor, and a test substrate under the at least one thermal test flip chip cell, the test substrate including at least one ball array arranged on a bottom surface thereof in a first direction, the first ball array configured to electrically connect to the plurality of bumps.

BRIEF DESCRIPTION OF THE DRAWINGS

0013The above and other features and advantages of the present inventive concepts will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings in which:

0014<figref idref="DRAWINGS">FIG. 1</figref> is a side view of a semiconductor test device according to example embodiments of the present inventive concepts;

0015<figref idref="DRAWINGS">FIG. 2</figref> illustrates a portion of the thermal test flip chip cell shown in <figref idref="DRAWINGS">FIG. 1</figref>;

0016<figref idref="DRAWINGS">FIGS. 3 and 4</figref> are plan views of the thermal test flip chip cell shown in <figref idref="DRAWINGS">FIG. 1</figref>;

0017<figref idref="DRAWINGS">FIGS. 5 to 7</figref> are bottom views of the thermal test flip chip cell shown in <figref idref="DRAWINGS">FIG. 1</figref>;

0018<figref idref="DRAWINGS">FIG. 8</figref> is a bottom surface of a thermal test flip chip cell according to example embodiments of the present inventive concepts;

0019<figref idref="DRAWINGS">FIG. 9</figref> is a bottom surface of a test substrate according to example embodiments of the present inventive concepts;

0020<figref idref="DRAWINGS">FIG. 10</figref> is a plan view of a flip chip cell according to example embodiments of the present inventive concepts;

0021<figref idref="DRAWINGS">FIG. 11</figref> is a bottom surface of the flip chip cell shown in <figref idref="DRAWINGS">FIG. 10</figref>;

0022<figref idref="DRAWINGS">FIGS. 12 and 13</figref> are bottom surfaces of a test substrate according to example embodiments of the present inventive concepts; and

0023<figref idref="DRAWINGS">FIG. 14</figref> is a flowchart illustrating a method for fabricating a semiconductor test device according to example embodiments of the present inventive concepts.

DETAILED DESCRIPTION

0024Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. Example embodiments may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. The same reference numbers indicate the same components throughout the specification. In the attached figures, the thickness of layers and regions is exaggerated for clarity.

0025It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items. Other words used to describe the relationship between elements or layers should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” “on” versus “directly on”).

0026It will be understood that, although the terms “first”, “second”, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments.

0027Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

0028The use of the terms “a” and “an” and “the” and similar referents in the context of describing example embodiments (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The terms “comprising,” “having,” “including,” and “containing” are to be construed as open-ended terms (i.e., meaning “including, but not limited to,”) unless otherwise noted. Example embodiments will be described with reference to perspective views, cross-sectional views, and/or plan views, in which the example embodiments of are shown. Thus, the profile of example views may be modified according to manufacturing techniques and/or allowances. That is, the example embodiments are not intended to limit the scope of example embodiments but cover all changes and modifications that can be caused due to a change in manufacturing process. Thus, regions shown in the drawings are illustrated in schematic form and the shapes of the regions are presented simply by way of illustration and not as a limitation.

0029Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It is noted that the use of any and all examples, or example terms provided herein is intended merely to better illuminate the example embodiments and is not a limitation on the scope of example embodiments unless otherwise specified. Further, unless defined otherwise, those defined in commonly-used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

0030Hereinafter, a semiconductor test device according to example embodiments of the present inventive concepts will be described with reference to <figref idref="DRAWINGS">FIG. 1</figref>.

0031<figref idref="DRAWINGS">FIG. 1</figref> is a side view of a semiconductor test device according to example embodiments of the present inventive concepts.

0032Referring to <figref idref="DRAWINGS">FIG. 1</figref>, the semiconductor test device according to the example embodiments of the present inventive concepts may include a test substrate <b>30</b> and a thermal test flip chip cell FC formed on the test substrate <b>30</b>.

0033The thermal test flip chip cell FC may be fabricated to test temperature characteristics of a flip chip. Therefore, the thermal test flip chip cell FC may be formed using the same material as the flip chip to be tested.

0034A heater <b>10</b> and a sensor D may be formed on the thermal test flip chip cell FC. The heater <b>10</b> may be configured to apply heat to the thermal test flip chip cell FC. In order to evenly apply heat to the thermal test flip chip cell FC, the heater <b>10</b> may cover a substantial portion of a top surface of the thermal test flip chip cell FC. For example, if the heater <b>10</b> covers at least 85% of the top surface of the thermal test flip chip cell FC, the heat can be evenly applied to substantially the entire surface of the thermal test flip chip cell FC.

0035In order to evenly apply heat to the thermal test flip chip cell FC, the heater <b>10</b> may include, for example, a resistor. The resistance may generate heat while consuming power, but example embodiments are not limited thereto. The heater <b>10</b> may apply heat to the thermal test flip chip cell FC using an element other than the resistor.

0036The sensor D may be formed on the thermal test flip chip cell FC and may measure the temperature of the thermal test flip chip cell FC. The sensor D may include, for example, a diode, but example embodiments are not limited thereto. The position of the thermal test flip chip cell FC, on which the sensor D may be disposed, and the number of sensors disposed thereon, will later be described.

0037A plurality of bumps <b>20</b> may be arranged on the bottom surface of the thermal test flip chip cell FC. The plurality of bumps <b>20</b> may be connected to the heater <b>10</b> and the sensor D of the thermal test flip chip cell FC, which are electrically connected to the test substrate <b>30</b> through the plurality of bumps <b>20</b>.

0038The test substrate <b>30</b> may be disposed under the thermal test flip chip cell FC and may be electrically connected to the thermal test flip chip cell FC. Temperature characteristics of the thermal test flip chip cell FC may be measured through the test substrate <b>30</b>. The test substrate <b>30</b> may include a rigid substrate made of one or more semiconductor materials selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs and InP, a silicon on insulator (SOI) substrate, a quartz substrate or a glass substrate for display, or a flexible plastic substrate made of polyimide, polyethyleneterephthalate (PET), polyethylene naphthalate (PEN), polymethylmethacrylate (PMMA), polycarbonate (PC), or polyethersulfone (PES).

0039A plurality of balls <b>40</b> may be formed on a bottom surface of the test substrate <b>30</b>, and may be connected to the plurality of bumps <b>20</b> connected to the heater <b>10</b> and the sensor D. The plurality of bumps <b>20</b> and the plurality of balls <b>40</b> may be connected to each other by internal wiring in the test substrate <b>30</b> (now shown).

0040The test substrate <b>30</b> formed of a single layer is illustrated in <figref idref="DRAWINGS">FIG. 1</figref> as an example, but example embodiments are not limited thereto. The test substrate <b>30</b> may include multiple layers.

0041The thermal test flip chip cell of the semiconductor test device according to example embodiments of the present inventive concepts will now be described with reference to <figref idref="DRAWINGS">FIGS. 2 to 7</figref>.

0042<figref idref="DRAWINGS">FIG. 2</figref> illustrates a portion of the thermal test flip chip cell shown in <figref idref="DRAWINGS">FIG. 1</figref>, <figref idref="DRAWINGS">FIGS. 3 and 4</figref> are plan views of the thermal test flip chip cell shown in <figref idref="DRAWINGS">FIG. 1</figref>, and <figref idref="DRAWINGS">FIGS. 5 to 7</figref> are bottom views of the thermal test flip chip cell shown in <figref idref="DRAWINGS">FIG. 1</figref>.

0043Referring to <figref idref="DRAWINGS">FIG. 2</figref>, the thermal test flip chip cell FC may be selected from a thermal test flip chip cell array. The thermal test flip chip cell array may include a plurality of thermal test flip chip cells FC<b>11</b> to FC<b>83</b>. The thermal test flip chip cell array may be formed in a wafer and may be separated into the plurality of thermal test flip chip cells FC<b>11</b> to FC<b>83</b> by sawing. Some thermal test flip chip cells FC may be selected to form a block (BL of <figref idref="DRAWINGS">FIG. 10</figref>), which will later be described.

0044Referring to <figref idref="DRAWINGS">FIG. 3</figref>, in order to apply heat to the thermal test flip chip cells FC and to measure temperature characteristics of the thermal test flip chip cells FC, at least one sensor D and at least one heater <b>10</b> may be provided. The sensor D may be disposed at a central portion of a top surface of each of the thermal test flip chip cells FC, and the heater <b>10</b> may cover the top surface of each of the thermal test flip chip cells FC, where the sensor D is not disposed.

0045<figref idref="DRAWINGS">FIG. 3</figref> illustrates the heater <b>10</b> having a rectangle shape with first to fourth corners C<b>1</b> to C<b>4</b> removed, but example embodiments are not limited thereto. The heater <b>10</b> may be arranged in any shape as long as it can cover a desired (or alternatively, predetermined) portion of the top surface of the thermal test flip chip cell FC, for example, 85% or greater.

0046Referring to <figref idref="DRAWINGS">FIGS. 3 and 4</figref>, the sensor D may include a plurality of sensors. For example, the sensor D may include a first sub sensor D<b>1</b> and second sub sensors D<b>2</b> and D<b>3</b>. The first sub sensor D<b>1</b> may be disposed at the central portion of the thermal test flip chip cell FC, and the second sub sensors D<b>2</b> and D<b>3</b> may be disposed at two or more locations of the first to fourth corners C<b>1</b> to C<b>4</b> of the thermal test flip chip cell FC. The first to fourth corners C<b>1</b> to C<b>4</b> may be four corner portions of the thermal test flip chip cell FC, and may correspond to exposed portions of the top surface of the thermal test flip chip cell FC by the heater <b>10</b>. The second sub sensors D<b>2</b> and D<b>3</b> may be disposed at two or more locations of the first to fourth corners C<b>1</b> to C<b>4</b>. <figref idref="DRAWINGS">FIG. 4</figref> illustrates two second sub sensors D<b>2</b> and D<b>3</b> disposed on the top surface of the thermal test flip chip cell FC and at the second corner C<b>2</b> and the third corner C<b>3</b>, but example embodiments are not limited thereto. For example, the second sub sensors D<b>2</b> and D<b>3</b> may also be disposed at the first second corner C<b>1</b> and the third corner C<b>3</b>. Further, third sub sensors may be provided.

0047When the sensor D includes three or more sensors, including, for example, the first sub sensor D<b>1</b> and the second sub sensors D<b>2</b> and D<b>3</b>, the temperatures can be effectively measured, as will described later.

0048Referring to <figref idref="DRAWINGS">FIG. 5</figref>, a plurality of bumps <b>20</b> may be arranged on a bottom surface of the thermal test flip chip cell FC. <figref idref="DRAWINGS">FIG. 5</figref> illustrates <b>25</b> bumps arranged in a 5×5 array, but example embodiments are not limited thereto. The thermal test flip chip cell FC may include various numbers of bumps <b>20</b>.

0049Because temperature characteristics of the thermal test flip chip cell FC may be measured by using the heater <b>10</b> and the sensor D, the heater <b>10</b> and the sensor D may be connected to a power supply device supplying power and a data collecting device measuring a change in the temperature. The plurality of bumps <b>20</b> may connect the heater <b>10</b> and the sensor D to the power supply device and the data collecting device. To connect both of the heater <b>10</b> and the sensor D to two devices (i.e., the power supply device and the data collecting device), each of the heater <b>10</b> and the sensor D may be connected to at least two bumps <b>20</b>. For example, the heater <b>10</b> may be electrically connected to at least two bumps <b>20</b> and the sensor D may also be electrically connected to at least two bumps <b>20</b>. One of the respective two bumps may be connected to the power supply device and the other of the respective two bumps may be connected to the data collecting device. <figref idref="DRAWINGS">FIG. 6</figref> shows that the heater <b>10</b> and the sensor D of the thermal test flip chip cell FC shown in <figref idref="DRAWINGS">FIG. 3</figref> are connected to the plurality of bumps <b>20</b>. The heater <b>10</b> may be connected to bumps <b>20</b><i>a </i>and <b>20</b><i>b </i>of a first region <b>21</b>, the first sub sensor D<b>1</b> may be connected to bumps <b>20</b>D<b>1</b><i>a </i>and <b>20</b>D<b>1</b><i>b </i>of a second region <b>22</b>, and each of second sub sensors D<b>2</b> and D<b>3</b> may be connected to bumps <b>20</b>D<b>2</b><i>a </i>and <b>20</b>D<b>2</b><i>b </i>of a third region <b>23</b> and bumps <b>20</b>D<b>3</b><i>a </i>and <b>20</b>D<b>3</b><i>b </i>of a fourth bump <b>24</b>, but example embodiments are not limited thereto. If each of the heater <b>10</b> and sensor D is connected to respective two bumps <b>20</b>, positions of the bumps <b>20</b> connected to the heater <b>10</b> and the sensor D may vary in various manners.

0050In order to connect the heater <b>10</b> and the sensor D to the power supply device and the data collecting device, the heater <b>10</b> and the sensor D may be connected to more than two bumps <b>20</b>. For example, referring to <figref idref="DRAWINGS">FIG. 7</figref>, each of the heaters <b>10</b> and the sensor D may be electrically connected to four bumps. The heater <b>10</b> may be connected to the bumps <b>20</b><i>a </i>to <b>20</b><i>d </i>of the first region <b>21</b>, the first sub sensor D<b>1</b> may be connected to the bumps <b>20</b>D<b>1</b><i>a </i>to <b>20</b>D<b>1</b><i>d </i>of the second region <b>22</b>, and each of second sub sensors D<b>2</b> and D<b>3</b> may be connected to the bumps <b>20</b>D<b>2</b><i>a </i>to <b>20</b>D<b>2</b><i>d </i>of the third region <b>23</b> and the bumps <b>20</b>D<b>3</b><i>a </i>to <b>20</b>D<b>3</b><i>d </i>of the fourth bump <b>24</b>, but example embodiments are not limited thereto. If each of the heater <b>10</b> and sensor D is connected to four bumps <b>20</b>, positions of the bumps <b>20</b> connected to the heater <b>10</b> and the sensor D may vary in various manners. In a case where the heater <b>10</b> and the sensor D are connected to four bumps <b>20</b>, two of the four bumps <b>20</b> may be connected to the power supply and the other two may be connected to the data collecting device.

0051As many bumps <b>20</b> as the heater <b>10</b> and the sensor D can be connected to the power supply device and the data collecting device should be provided. Thus, referring to <figref idref="DRAWINGS">FIG. 6</figref>, because each of the heater <b>10</b> and the sensor D is connected to two bumps <b>20</b>, eight or more bumps <b>20</b> may be provided on the bottom surface of the thermal test flip chip cell FC. Referring to <figref idref="DRAWINGS">FIG. 7</figref>, because each of the heater <b>10</b> and the sensor D requires four bumps <b>20</b>, <b>16</b> or more bumps <b>20</b> may be provided on the bottom surface of the thermal test flip chip cell FC.

0052Hereinafter, a ball array disposed on the bottom surface of the test substrate and a connection relationship between the ball array and a plurality of bumps will be described.

0053<figref idref="DRAWINGS">FIG. 8</figref> is a bottom surface of a thermal test flip chip cell according to example embodiments of the present inventive concepts, and <figref idref="DRAWINGS">FIG. 9</figref> is a bottom surface of a test substrate according to example embodiments of the present inventive concepts.

0054For brevity, it is assumed that the thermal test flip chip cell FC includes one heater <b>10</b> and one sensor D, the heater <b>10</b> is electrically connected to four bumps <b>20</b><i>a </i>to <b>20</b><i>d </i>and the sensor D is electrically connected to four bumps <b>20</b>D<b>1</b><i>a </i>to <b>20</b>D<b>1</b><i>d. </i>

0055To connect the heater <b>10</b> and the sensor D to the power supply device and the data collecting device, the heater <b>10</b> and the sensor D may be connected to the plurality of bumps <b>20</b>, which are connected to the plurality of balls <b>40</b> disposed on the bottom surface of the test substrate <b>30</b>.

0056The plurality of balls <b>40</b> and the plurality of bumps <b>20</b> may be matched to each other in one-to-one correspondence. For example, one bump <b>20</b> may be electrically connected to one ball <b>40</b>. If all of the plurality of bumps <b>20</b> disposed on the bottom surface of the thermal test flip chip cell FC are connected to the plurality of balls <b>40</b> in one-to-one correspondence, because only some of the plurality of bumps <b>20</b> may be connected to the heater <b>10</b> and the sensor D, the bumps <b>20</b> that are not connected to the heater <b>10</b> and the sensor D may be unnecessarily connected to the balls <b>40</b>. In this case, the number of balls disposed on the bottom surface of the test substrate <b>30</b> may be larger than necessary, thereby making the test substrate <b>30</b> bulky. For example, all of the balls <b>40</b> may not be accommodated on the bottom surface of the test substrate <b>30</b>. The plurality of balls <b>40</b> corresponding to one thermal test flip chip cell FC may be electrically connected to the plurality of bumps <b>20</b> electrically connected to the heater <b>10</b> and the sensor D. <figref idref="DRAWINGS">FIG. 8</figref> illustrates that only eight bumps <b>20</b> among the plurality of bumps <b>20</b> are connected to the heater <b>10</b> and the sensor D, and thus the number of balls <b>40</b> connected to the thermal test flip chip cell FC is 8. Eight bumps <b>20</b><i>a </i>to <b>20</b><i>d </i>and <b>20</b>D<b>1</b><i>a </i>to <b>20</b>D<b>1</b><i>d </i>may be matched to eight balls <b>40</b><i>a </i>to <b>40</b><i>d </i>and <b>40</b>D<b>1</b><i>a </i>to <b>40</b>D<b>1</b><i>d </i>in one-to-one correspondence.

0057The plurality of balls <b>40</b> corresponding to one thermal test flip chip cell FC may form a ball array <b>50</b>. As shown in <figref idref="DRAWINGS">FIG. 9</figref>, the ball array <b>50</b> may be arranged in a first direction (e.g., in the Y-axis direction). If the plurality of balls <b>40</b> is arranged in a line, the plurality of balls <b>40</b> may be easily electrically connected to each other, which will later be described.

0058Next, a semiconductor test device according to example embodiments of the present inventive concepts will be described with reference to <figref idref="DRAWINGS">FIGS. 2 and 10</figref> to <b>13</b>.

0059<figref idref="DRAWINGS">FIG. 10</figref> is a plan view of a flip chip cell according to example embodiments of the present inventive concepts, <figref idref="DRAWINGS">FIG. 11</figref> is a bottom surface of the flip chip cell shown in <figref idref="DRAWINGS">FIG. 10</figref>, and <figref idref="DRAWINGS">FIGS. 12 and 13</figref> are bottom surfaces of a test substrate according to example embodiments of the present inventive concepts.

0060The semiconductor test device according to example embodiments of the present inventive concepts may include a plurality of thermal test flip chip cells FC. A flip chip actually used in a product may be larger than a thermal test flip chip cell FC and may have various sizes. Because the thermal test flip chip cell FC is used to measure temperature characteristics of the actually used flip chip, the plurality of thermal test flip chip cells FC may be formed to have the same size as the actually used flip chip. The plurality of thermal test flip chip cells FC may form a block BL.

0061<figref idref="DRAWINGS">FIG. 10</figref> illustrates that six thermal test flip chip cells FC are arranged in a 2×3 array. The six thermal test flip chip cells FC may form one block BL. For example, one block BL may include a first thermal test flip chip cell FC<b>11</b>, a second thermal test flip chip cell FC<b>21</b>, a third thermal test flip chip cell FC<b>12</b>, a fourth thermal test flip chip cell FC<b>22</b>, a fifth thermal test flip chip cell FC<b>13</b> and a sixth thermal test flip chip cell FC<b>23</b>. The heater <b>10</b> and the sensor D may be formed on each of the thermal test flip chip cells FC<b>11</b> to FC<b>23</b>, and the plurality of bumps <b>20</b> may be formed on the bottom surface of each of the thermal test flip chip cells FC<b>11</b> to FC<b>23</b>. In <figref idref="DRAWINGS">FIG. 10</figref>, 3 sensors D may be formed on a top surface of each of the thermal test flip chip cells FC, but example embodiments are not limited thereto.

0062As shown in <figref idref="DRAWINGS">FIG. 10</figref>, three sensors may be formed on the top surface of each of the thermal test flip chip cells FC. For example, second sub sensors D<b>2</b> and D<b>3</b> may be disposed at opposite side with respect to a first sub sensor D<b>1</b>, and the first and second sub sensors D may be arranged in a straight line, thereby effectively measuring temperatures of the block BL. The second sub sensors D<b>2</b> and D<b>3</b> may be additionally provided to measure temperatures at various locations of the block BL, compared to a case of providing only one sensor D. For example, the temperatures can be measured at locations close to the center of the block BL. In general, most elements and circuits of a flip chip are positioned at a central portion of the flip chip. Therefore, measuring temperatures at various locations close to the center of the block BL may be helpful to approximate temperature characteristics of the actually used flip chip. In <figref idref="DRAWINGS">FIG. 10</figref>, the center of the block BL may be a contact portion between the third thermal test flip chip cell FC<b>12</b> and the fourth thermal test flip chip cell FC<b>22</b>. Thus, first sub sensors D<b>1</b> of the third and fourth thermal test flip chip cells FC<b>12</b> and FC<b>22</b>, second sub sensors D<b>2</b> and D<b>3</b> of the third thermal test flip chip cell FC<b>12</b>, and second sub sensors D<b>2</b> and D<b>3</b> of the fourth thermal test flip chip cell FC, can measure the temperatures at various locations around the center of the block BL.

0063If the block BL has a 2×2 array, e.g., if the block BL includes only four thermal test flip chip cells including first to fourth thermal test flip chip cells FC<b>11</b>, FC<b>21</b>, FC<b>12</b> and FC<b>22</b>, the center of the block BL may correspond to a vertex making contact with all of the first to fourth thermal test flip chip cells FC<b>11</b>, FC<b>21</b>, FC<b>12</b> and FC<b>22</b>. Thus, the second sub sensor D<b>2</b> of the second thermal test flip chip cell FC<b>21</b> and the second sub sensor D<b>3</b> of the third thermal test flip chip cell FC<b>12</b>, which are positioned to be closer to the center of the block BL than the first sub sensor D<b>1</b>, can measure the temperatures of various locations around the center of the 2×2 block.

0064Consequently, if the block BL includes thermal test flip chip cells FC in an N×N array, where N is a natural number, the temperature of the center of the block BL can be measured through the second sub sensors D<b>2</b> and D<b>3</b>. If the block BL includes thermal test flip chip cells FC in an N×M array, where M is a natural number different from N, the temperatures of the center of the block BL can be determined by measuring temperatures at various locations in the vicinity of the center of the block BL, compared to a case where the thermal test flip chip cell FC includes one sensor D.

0065In order to obtain various data concerning temperature characteristics, one thermal test flip chip cell FC may include many sensors D. As the number of sensors D increases, the number of bumps <b>20</b> disposed on the bottom surface of the thermal test flip chip cell FC may increase. Because wirings for connecting the bumps <b>20</b> to the balls <b>40</b> and connecting the bumps <b>20</b> to the heater <b>10</b> and the sensor D become complex, the number of sensors D included in one thermal test flip chip cell FC may not be indefinitely increased.

0066Hereinafter, a connection relationship between a ball array disposed on the bottom surface of a test substrate and a plurality of bumps will be described with reference to <figref idref="DRAWINGS">FIGS. 11 to 13</figref>. For brevity, it is assumed that one thermal test flip chip cell FC includes one heater <b>10</b> and one sensor D, and each of the heater <b>10</b> and the sensor D is electrically connected to four bumps.

0067Referring to <figref idref="DRAWINGS">FIG. 11</figref>, one block (BL of <figref idref="DRAWINGS">FIG. 10</figref>) may include six thermal test flip chip cells FC. Each of the thermal test flip chip cells FC may include a heater <b>10</b> and a sensor D, which are electrically connected to a plurality of bumps <b>20</b> disposed on a bottom surface of each of the thermal test flip chip cells FC. For example, the heater <b>10</b> of a first thermal test flip chip cell FC may be electrically connected to four bumps <b>21</b><i>a </i>to <b>21</b><i>d</i>, and the sensor D is electrically connected to four bumps <b>21</b>D<b>1</b><i>a </i>to <b>21</b>D<b>1</b><i>d</i>. These connection arrangements also apply to second to sixth thermal test flip chip cells FC<b>21</b>, FC<b>12</b>, FC<b>22</b>, FC<b>13</b> and FC<b>23</b>.

0068The thermal test flip chip cells FC<b>11</b> to FC<b>23</b> may be electrically connected to ball arrays <b>50</b> (shown in <figref idref="DRAWINGS">FIG. 12</figref>) disposed on a bottom surface of the test substrate <b>30</b>. Because each of the thermal test flip chip cells FC uses eight bumps <b>20</b> to connect the heater <b>10</b> and the sensor D to a power supply device and a data collecting device, the ball arrays <b>50</b> may include eight balls <b>40</b>. Each of the ball arrays <b>50</b> may be arranged in a first direction (e.g., in the Y-axis direction). The first thermal test flip chip cell FC<b>11</b> may be electrically connected to a first ball array <b>51</b>, the second thermal test flip chip cell FC<b>21</b> may be electrically connected to a second ball array <b>52</b>, the third thermal test flip chip cell FC<b>21</b> may be electrically connected to a third ball array <b>53</b>, the fourth thermal test flip chip cell FC<b>22</b> may be electrically connected to a fourth ball array <b>54</b>, the fifth thermal test flip chip cell FC<b>13</b> may be electrically connected to a fifth ball array <b>55</b>, and the sixth thermal test flip chip cell FC<b>23</b> may be electrically connected to a sixth ball array <b>56</b>. For example, in the first thermal test flip chip cell FC<b>11</b>, eight bumps <b>21</b><i>a </i>to <b>21</b><i>d </i>and <b>21</b>D<b>1</b><i>a </i>to <b>21</b>D<b>1</b><i>d </i>connected to the heater <b>10</b> and the sensor D may be connected to eight balls <b>41</b><i>a </i>to <b>41</b><i>d </i>and <b>41</b>D<b>1</b><i>a </i>to <b>41</b>D<b>1</b><i>d </i>included in the first ball array <b>51</b> in one-to-one correspondence. In the second thermal test flip chip cell FC<b>21</b> disposed at one side of the first thermal test flip chip cell FC<b>11</b>, eight bumps <b>22</b><i>a </i>to <b>22</b><i>d </i>and <b>22</b>D<b>1</b><i>a </i>to <b>22</b>D <b>1</b><i>d </i>connected to the heater <b>10</b> and the sensor D may be connected to eight balls <b>42</b><i>a </i>to <b>42</b><i>d </i>and <b>42</b>D<b>1</b><i>a </i>to <b>42</b>D<b>1</b><i>d </i>included in the second ball array <b>52</b> in one-to-one correspondence. In the same manner, bumps <b>20</b> included in the third to sixth thermal test flip chip cells FC<b>12</b>, FC<b>22</b>, FC<b>13</b> and FC<b>23</b> may be connected to the third to sixth ball arrays <b>53</b> to <b>56</b>, respectively. The first to sixth ball arrays <b>51</b> to <b>56</b> may be arranged in a second direction to be parallel with each other.

0069The balls <b>40</b> included in each of the ball arrays <b>50</b> may be connected to the bumps <b>20</b>, respectively, in the same order. For example, the first to fourth balls <b>41</b><i>a </i>to <b>41</b><i>d </i>of the first ball array <b>51</b>, which are included eight balls <b>40</b> arranged in the first direction, may be electrically connected to the heater <b>10</b> of the first thermal test flip chip cell FC<b>11</b>, and the fifth to eighth balls <b>41</b>D<b>1</b><i>a </i>to <b>41</b>D<b>1</b><i>d </i>may be electrically connected to the sensor D of the first thermal test flip chip cell FC<b>11</b>. The first to fourth balls <b>42</b><i>a </i>to <b>42</b><i>d </i>of the second ball array <b>52</b> may be electrically connected to the heater <b>10</b> of the second thermal test flip chip cell FC<b>21</b>, and the fifth to eighth balls <b>42</b>D<b>1</b><i>a </i>to <b>42</b>D<b>1</b><i>d </i>may be electrically connected to the sensor D of the second thermal test flip chip cell FC<b>21</b>. These connection arrangements also apply to the third to sixth ball arrays <b>53</b> to <b>56</b>.

0070If the balls <b>40</b> included in each of the ball arrays <b>50</b> are connected to the heater <b>10</b> and the sensor D of the thermal test flip chip cell FC, respectively, in the same order, wirings for connecting the balls <b>40</b> can be easily formed. The heater <b>10</b> and the sensor D of the first thermal test flip chip cell FC<b>11</b> may be connected to the power supply device and the data collecting device through the balls <b>40</b> of the test substrate <b>30</b>. For example, the power supply device and the data collecting device may be connected to each block BL including a plurality of thermal test flip chip cells FC because measuring temperature characteristics of the entire block BL, rather than a portion of the block BL, may be useful in fabricating an actual flip chip having the same size as the block BL. For example, if the balls <b>40</b> are randomly arranged on the bottom surface of the test substrate <b>30</b>, it may be difficult to form wirings for connecting the bumps <b>20</b> to the balls <b>40</b> and connecting the balls <b>40</b> to the power supply device and the data collecting device. For example, as the number of heaters <b>10</b> and/or sensors D included in one thermal test flip chip cell FC increase, and/or the number of thermal test flip chip cells FC included in a block BL increases, forming the wirings becomes complicated.

0071According to example embodiments of the present inventive concepts, the plurality of balls <b>40</b> connected to one thermal test flip chip cell FC may be arranged in the first direction (e.g., in the Y-axis direction), forming a plurality of ball arrays <b>50</b>, and the plurality of ball arrays <b>50</b> connected to the plurality of thermal test flip chip cells FC included in the block BL may be arranged in the second direction to be parallel with each other, thereby easily forming the wirings.

0072Referring to <figref idref="DRAWINGS">FIG. 13</figref>, in order to electrically connect the balls <b>40</b> to the power supply device and the data collecting device, the balls <b>40</b> may be electrically connected to each other in a second direction (e.g., in the X-axis direction) because, for example, the balls <b>40</b> corresponding to the heater <b>10</b> and the sensor D may be at the same position in each of the ball arrays <b>50</b>. Therefore, among the plurality of balls <b>40</b> disposed on the bottom surface of the test substrate <b>30</b>, the balls <b>40</b> arranged in the second direction may be electrically connected to each other, thereby easily forming the wirings. Lines L connecting the plurality of balls <b>40</b> in the second direction may extend in the second direction. <figref idref="DRAWINGS">FIG. 13</figref> illustrates the lines L directly connecting the balls <b>40</b> as an example, but example embodiments are not limited thereto. The lines L may be formed within the test substrate <b>30</b> to extend in the second direction.

0073For example, the first direction and the second direction may be different from each other. In particular, the first direction and the second direction may be perpendicular to each other, but example embodiments are not limited thereto. For example, the ball arrays <b>50</b> may be arranged in the second direction, and In this case, the respective ball arrays <b>50</b> may be arranged in the first direction to be parallel to each other, and the lines L may also be formed in the first direction.

0074Hereinafter, a method for fabricating a semiconductor test device according to example embodiments of the present inventive concepts will be described with reference to <figref idref="DRAWINGS">FIGS. 1</figref>, <b>3</b>, <b>8</b> to <b>12</b> and <b>14</b>. The same and/or similar details as those described above will be omitted.

0075<figref idref="DRAWINGS">FIG. 14</figref> is a flowchart illustrating a method for fabricating a semiconductor test device according to example embodiments of the present inventive concepts.

0076Referring to <figref idref="DRAWINGS">FIG. 14</figref>, a first thermal test flip chip cell and a test substrate may be provided (S<b>100</b>).

0077Referring to <figref idref="DRAWINGS">FIGS. 1</figref>, <b>3</b>, <b>8</b> and <b>9</b>, the first thermal test flip chip cell FC may include a first heater <b>10</b> and a first sensor D, and a plurality of first bumps <b>20</b> may be disposed on a bottom surface of the first thermal test flip chip FC. A test substrate <b>30</b> may be provided under the first thermal test flip chip, and the test substrate <b>30</b> may include a plurality of balls <b>40</b>, which forms a plurality of first ball arrays <b>50</b> disposed on a bottom surface of the test substrate <b>30</b>. The first ball array <b>50</b> may be arranged in the first direction (e.g., in the Y-axis direction).

0078Referring to <figref idref="DRAWINGS">FIG. 10</figref>, the semiconductor test device may include a plurality of thermal test flip chip cells FC. For example, the semiconductor test device may include a first thermal test flip chip FC<b>11</b> and a second thermal test flip chip FC<b>21</b> disposed on the test substrate <b>30</b>. The second thermal test flip chip FC<b>21</b> may be disposed at one side of the first thermal test flip chip FC<b>11</b>. The second thermal test flip chip FC<b>21</b> may include a second heater <b>10</b> and a second sensor D and a plurality of second bumps <b>20</b> disposed on a bottom surface of the second thermal test flip chip cell FC.

0079Next, referring again to <figref idref="DRAWINGS">FIG. 14</figref>, a heater and a sensor may be connected to the plurality of bumps <b>20</b> (S<b>200</b>). Referring to <figref idref="DRAWINGS">FIGS. 6 to 8</figref>, the first heater <b>10</b> and the first sensor D may be electrically connected to some of the plurality of first bumps <b>20</b>.

0080If the semiconductor test device further includes the second thermal test flip chip FC<b>21</b>, as shown in <figref idref="DRAWINGS">FIG. 11</figref>, a second heater <b>10</b> and a second sensor D included in the second thermal test flip chip FC<b>21</b> may be electrically connected to the plurality of second bumps <b>20</b>.

0081The connection relationship between the first heater <b>10</b> and the first sensor D and the plurality of bumps <b>20</b> may be the same as described above. As such, a detailed description thereof will not be given.

0082Next, referring again to <figref idref="DRAWINGS">FIG. 14</figref>, the plurality of first bumps connected to the first heater <b>10</b> and the first sensor D may be connected to the first ball array (S<b>300</b>). Referring to <figref idref="DRAWINGS">FIGS. 8 and 9</figref>, the first ball array <b>50</b> arranged in the first direction (e.g., in the Y-axis direction) and the plurality of first bumps <b>20</b> may be electrically connected to each other. For example, the plurality of first bumps <b>20</b> connected to the first heater <b>10</b> and the first sensor D may be electrically connected to the plurality of balls <b>40</b> included in the first ball array <b>50</b> in one-to-one correspondence. Therefore, the number of the plurality of first bumps <b>20</b> connected to the first heater <b>10</b> and the first sensor D may be equal to the number of the plurality of balls <b>40</b> included in the first ball array <b>50</b>.

0083If the semiconductor test device further includes a second thermal test flip chip FC<b>21</b>, as shown in <figref idref="DRAWINGS">FIGS. 11 and 12</figref>, the test substrate <b>30</b> may include a second ball array <b>50</b> disposed on a bottom surface of the test substrate <b>30</b>. The second ball array <b>50</b> electrically connected to the plurality of second bumps <b>20</b> of the second thermal test flip chip FC<b>21</b> may be arranged in the second direction (e.g., in the X-axis direction) to be parallel with the first ball array <b>50</b>.

0084The connection relationship between the plurality of bumps <b>20</b> and the ball arrays <b>50</b> may be the same as described above. Thus, a detailed description thereof will not be given.

0085While example embodiments have been particularly shown and described with reference to some example embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of example embodiments as defined by the following claims. It is therefore desired that the example embodiments be considered in all respects as illustrative and not restrictive, and reference be made to the appended claims rather than the foregoing description to the example embodiments.