Region-weighted accounting of multi-threaded processor core according to dispatch state

BACKGROUND

The present disclosure relates to multi-threaded processor core accounting, and more specifically relates to efficiently computing thread resource utilization during dispatch cycles. Today's processors may be superscalar in nature such that a single processor decodes, dispatches, and executes multiple instructions on each processor cycle. These processors may also support simultaneous multi-threading (SMT) modes, which allows a processor to concurrently execute more than one software program (thread) at a time.

BRIEF SUMMARY

According to one embodiment of the present disclosure, an approach is provided in which a thread is selected from multiple active threads, along with a corresponding weighting value. Computational logic determines whether one of the multiple threads is dispatching an instruction and, if so, computes a dispatch weighting value using the selected weighting value and a dispatch factor that indicates a weighting adjustment of the selected weighting value. In turn, a resource utilization value of the selected thread is computed using the dispatch weighting value.

The foregoing is a summary and thus contains, by necessity, simplifications, generalizations, and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting. Other aspects, inventive features, and advantages of the present disclosure, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth below.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The present disclosure may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings, wherein:

<figref idref="DRAWINGS">FIG. 1</figref> is a diagram showing a processor tracking resource utilization by computing dispatch weighting values during a dispatch cycle using a dispatch factor;

<figref idref="DRAWINGS">FIG. 2</figref> is a diagram showing an embodiment of weighting computational logic <b>102</b> that generates weighting values based upon a processor's operating environment and whether a thread dispatches an instruction;

<figref idref="DRAWINGS">FIG. 3</figref> is a table showing relationships between processor modes and register fields for which to retrieve a weighting value;

<figref idref="DRAWINGS">FIG. 4</figref> is a table showing region-weighted mode register (RWMR) partitioned into multiple register fields and a dispatch factor field, as well as the RWMR being reassigned to support Single LPAR and simultaneous multiple LPAR operation;

<figref idref="DRAWINGS">FIG. 5</figref> is a table showing a relationship between dispatch factor bits, a dispatch factor, and a dispatch weighting value numerator;

<figref idref="DRAWINGS">FIG. 6</figref> is a flowchart showing steps taken in computing resource utilization values on a per thread basis;

<figref idref="DRAWINGS">FIG. 7</figref> is a flowchart showing steps taken in computing a fractional weighting value for a selected thread;

<figref idref="DRAWINGS">FIG. 8</figref> is a flowchart showing steps taken in computing fractional weighting values and adding the fractional weighting values to fractional accumulators using a distributed round robin sequence;

<figref idref="DRAWINGS">FIG. 9</figref> is a table showing a distributed cycle round robin sequence that adds weighting values to active threads over time;

<figref idref="DRAWINGS">FIG. 10</figref> illustrates a simplified example of a computer system capable of performing the computing operations described herein; and

<figref idref="DRAWINGS">FIG. 11</figref> provides an extension of the information handling system environment shown in <figref idref="DRAWINGS">FIG. 10</figref> to illustrate that the methods described herein can be performed on a wide variety of information handling systems that operate in a networked environment.

DETAILED DESCRIPTION

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiment was chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.

As will be appreciated by one skilled in the art, aspects of the present disclosure may be embodied as a system, method or computer program product. Accordingly, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.

Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Computer program code for carrying out operations for aspects of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).

Aspects of the present disclosure are described below with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

The following detailed description will generally follow the summary of the disclosure, as set forth above, further explaining and expanding the definitions of the various aspects and embodiments of the disclosure as necessary.

<figref idref="DRAWINGS">FIG. 1</figref> is a diagram showing a processor tracking resource utilization by computing dispatch weighting values during a dispatch cycle using a dispatch factor. Processor <b>100</b> includes weighting computational logic <b>102</b>, which receives various inputs to compute weighting values for active threads. These weighting values are stored in fractional PURR (processor utilization resource register) accumulators <b>160</b>-<b>165</b>, which are eventually stored in their corresponding thread's (threads <b>190</b>-<b>195</b>) processor utilization resource register (PURR <b>180</b>-<b>185</b>). In turn, processor <b>100</b> tracks resource utilization on a per-thread basis. As those skilled in the art can appreciate, weighting computational logic <b>102</b> may comprise hardware logic, software code, or a combination of hardware logic and software code.

Region-weighted mode register (RWMR) <b>115</b> includes register fields <b>118</b>. Register fields <b>118</b> includes multiple register fields, each of which stores a particular non-dispatch weighting value for use by weighting computational logic <b>102</b> based upon processor <b>100</b>'s operating environment (e.g., the number of active threads, the number of running threads, etc). In one embodiment, register fields <b>118</b> includes thirteen different weighting values that are stored in thirteen different register fields (see <figref idref="DRAWINGS">FIG. 4</figref> and corresponding text for further details).

RWMR <b>115</b> also includes dispatch factor field <b>120</b> that stores a dispatch factor. Weighting computational logic <b>102</b> decreases or increases retrieved weighting values (stored in register fields <b>118</b>) using the dispatch factor when one or more active threads dispatches an instruction. As such, RWMR <b>115</b> does not store separate dispatch weighting values for each of the non-dispatch weighting values included in register fields <b>118</b>, thus reducing the size of RWMR <b>115</b>.

In one embodiment, register fields <b>118</b> include run weighting values, which are applied to threads in a run state. In this embodiment, weighting computational logic <b>102</b> uses the run weighting values to compute idle weighting values, which are applied to threads in an idle state. In another embodiment, register fields <b>118</b> include idle weighting values, which are applied to threads in an idle state. In this embodiment, weighting computational logic <b>102</b> uses the run weighting values to compute run weighting values, which are applied to threads in an idle state.

In yet another embodiment, in order to minimize the number of bits required for register fields <b>118</b>, weighting values may include a combination of run weighting values and idle weighting values. In this embodiment, register fields <b>118</b> includes run weighting values for times at which processor <b>100</b>'s operating environment has a large number of threads in the run state (4-8 threads). Continuing with this embodiment, register fields <b>118</b> includes idle weighting values for times at which processor <b>100</b>'s operating environment has a small number of threads are in the run state (1-3 threads) (see <figref idref="DRAWINGS">FIG. 3</figref> and corresponding text for further details).

In one embodiment, a processor designates a run latch status bit for each hardware thread. In this embodiment, when an operating system enters an idle state, or if a thread is suspended, the run latch for that particular thread is disabled (each run latch signal operates independently). In this embodiment, major regions of hardware thread concurrency may be defined by the number and location of threads that have their corresponding run latch asserted. As such, the run latch state guides idle and non-idle weighting values to appropriate Fractional PURR Accumulators.

Weighting computational logic <b>102</b> uses several inputs to identify which register field from register fields <b>118</b> to retrieve a specific weighting value. One input used by weighting computational logic <b>102</b> to identify the register field is summary thread context <b>110</b>. Summary thread context <b>110</b> provides an indication to weighting computational logic <b>102</b> of the number of active threads. In one embodiment, summary thread context <b>110</b> indicates a “ceiling” on the number of hardware threads that are readily available to an operating system. The concept of thread context allows a processor to decouple dynamic changes in an SMT core mode from the context in which a user wishes to evaluate utilization. Summary thread context <b>110</b> may also be used to determine whether to accumulate idle PURR counts for threads that are suspended (e.g., in NAP mode).

Hypervisor <b>108</b> receives thread context <b>106</b> included in logical partitioning control register (LPCR) <b>105</b>, which are individual bits (e.g., bits <b>0</b>-<b>7</b>) that indicate which threads are active (online). In turn, hypervisor <b>108</b> interprets these bits and provides summary thread context <b>110</b>. In one embodiment, hypervisor <b>108</b> uses the following criteria to determine summary thread context <b>110</b>: <ul id="ul0001" list-style="none"><li id="ul0001-0001" num="0000"><ul id="ul0002" list-style="none"><li id="ul0002-0001" num="0035">1 thread active: Summary Thread Context 1;</li><li id="ul0002-0002" num="0036">2 threads active: Summary Thread Context 2;</li><li id="ul0002-0003" num="0037">3-4 threads active: Summary Thread Context 4;</li><li id="ul0002-0004" num="0038">5-8 threads active: Summary Thread Context 8.</li></ul></li></ul>

Another input that weighting computational logic <b>102</b> uses to identify the register field is simultaneous multithreading (SMT) mode <b>128</b>. SMT mode logic <b>125</b> monitors the number of interrupts and sleeps that occurs in processor <b>100</b> and sets the SMT mode accordingly, which defines the resources allocated and the number of threads that are active (running or idle). In one embodiment, SMT mode <b>128</b> may be SMT<b>1</b> (up to one thread active), SMT<b>2</b> (up to two threads active), SMT<b>4</b> (up to four threads active), and SMT<b>8</b> (up to 8 threads active).

Weighting computational logic <b>102</b> also uses run signals <b>135</b> (provided by run logic <b>130</b>) to determine whether to apply, for each particular thread, a run weighting value or an idle weighting value. Run signals <b>135</b> identify which threads are in the “run” state. For example, assuming that threads 0-4 are active and run signals <b>135</b> indicate that threads 0 and 1 are in the run state, weighting computational logic <b>102</b> knows to compute a run weighting value for threads 0 and 1, and compute an idle weighting value for threads 2-4 (or a dispatch run weighting value/dispatch idle weighting value when one or more active threads executes a dispatch instruction as discussed below).

Dispatch logic <b>140</b> includes dispatch valid signals <b>145</b>, which indicate whether one or more active threads are dispatching an instruction. As such, weighting computational logic <b>102</b> determines whether to use dispatch factor <b>120</b> to compute dispatch run weighting values and dispatch idle weighting values. In one embodiment, a particular thread does not need to be dispatching an instruction to receive a dispatch weighting value. Rather, when any one of the active threads is dispatching an instruction, each of the active threads receives either a dispatch run weighting value or a dispatch idle weight value. Using the example above and assuming thread 0 is dispatching an instruction, both thread 0 and thread 1 receive a dispatch run weighting value (because they are both in the run state). In this example, threads 2-4 would receive a dispatch idle weighting value.

At particular intervals (e.g., processor clock cycle), weighting computational logic <b>102</b> computes and stores a “fractional” weighting value in each active thread's corresponding fractional PURR accumulator (accumulators <b>160</b>-<b>165</b>). In due course, these fractional weighting values are stored as accumulated values (values <b>170</b>-<b>175</b>) in their corresponding thread's PURR (<b>180</b>-<b>185</b>). In one embodiment, weighting computational logic <b>102</b> uses a distributed cycle round robin sequence to add weighting values to threads over time. In this embodiment, the distributed cycle round robin sequence uses pointers (one for run threads and one for idle threads) to track which thread to add weighting values for a particular cycle (see <figref idref="DRAWINGS">FIGS. 8-9</figref> and corresponding text for further details). In one embodiment, weighting computational logic <b>102</b> utilizes the entirety of the inputs discussed above, including multiple RWMR fields, in order to accurately model the performance and resource utilization of the processor <b>100</b>.

<figref idref="DRAWINGS">FIG. 2</figref> is a diagram showing an embodiment of weighting computational logic <b>102</b> that generates weighting values based upon a processor's operating environment and whether a thread dispatches an instruction. Weighting computational logic <b>102</b> includes register weight location selector <b>200</b>, which uses summary thread context <b>110</b>, SMT mode <b>128</b>, and run signals <b>135</b> to identify register field in register fields <b>118</b> and retrieve a corresponding weighting value. The example in <figref idref="DRAWINGS">FIG. 2</figref> pertains to an embodiment when RWMR <b>115</b> includes run weighting values (as opposed to idle weighting values).

Register weight location selector <b>200</b> identifies processor <b>100</b>'s summary thread context via summary thread context <b>110</b>, and identifies processor <b>100</b>'s SMT mode via SMT mode <b>128</b>. In turn, register weight location selector <b>200</b> identifies the number of threads in the run state via run signals <b>135</b>. With this information, register weight location selector <b>200</b> identifies a particular register field; retrieves a run weighting value from the identified register field, and stores the run weighting value in run weight store <b>210</b> (see <figref idref="DRAWINGS">FIG. 3</figref> and corresponding text for further details).

In turn, idle weight computational logic <b>220</b> uses the run weighting value to compute an idle weighting value, which it stores in idle weight store <b>230</b>. For example, assuming that eight threads are active (SMT<b>8</b>); six threads are in the run state, and the stored run weighting value (per thread) is 9/64: <ul id="ul0003" list-style="none"><li id="ul0003-0001" num="0000"><ul id="ul0004" list-style="none"><li id="ul0004-0001" num="0046">Total run weighting value (6 threads): 6* 9/64= 54/64;</li><li id="ul0004-0002" num="0047">Total idle weighting value: 64/64− 54/64= 10/64</li><li id="ul0004-0003" num="0048">Per Thread Idle weighting value (2 threads): ( 10/64)/2= 5/64</li></ul></li></ul>

When one of the active threads is dispatching an instruction (indicated by dispatch valid signals <b>145</b>), per thread fractional charge computation logic <b>240</b> computes dispatch run weighting values and idle weighting values using a dispatch factor stored in dispatch factor field <b>120</b>. Continuing with the example above, assuming that the dispatch factor is 1/16, per thread fractional charge computation logic <b>240</b> multiplies the run weighting value by 1 1/16: <ul id="ul0005" list-style="none"><li id="ul0005-0001" num="0000"><ul id="ul0006" list-style="none"><li id="ul0006-0001" num="0050">Per Thread Dispatch run weighting value: ( 17/16*9)/64= 10/64;</li><li id="ul0006-0002" num="0051">Total Dispatch run weighting value: 6* 10/64= 60/64;</li><li id="ul0006-0003" num="0052">Total dispatch idle weighting value: 64/64− 60/64= 4/64</li><li id="ul0006-0004" num="0053">Per Thread Dispatch Idle weighting value (2 threads): ( 4/64)/2= 2/64</li></ul></li></ul>

As disclosed herein, dispatch run weighting values may be rounded off to a maximum value if they exceed the maximum value. Likewise, dispatch idle weighting values may be rounded off to a minimum value (e.g., 0) if they fall below the minimum value.

Along with determining whether a dispatch is occurring (via dispatch valid signals <b>145</b>), per thread fractional charge computation logic <b>240</b> identifies which threads are in the run state (via run signals <b>135</b>) and stores (dispatch) run weighting values in the identified threads' corresponding fractional PURR accumulators <b>250</b>. Likewise, per thread fractional charge computation logic <b>240</b> identifies which threads are in the idle state (via run signals <b>135</b>) and stores (dispatch) idle weighting values in the identified threads' corresponding fractional PURR accumulators <b>250</b>.

<figref idref="DRAWINGS">FIG. 3</figref> is a table showing relationships between processor modes and register fields for which to retrieve a weighting value. In one embodiment a particular register field is selected based upon three criteria, which are the summary thread context (depends upon the number of active threads), the number of threads running, and the SMT mode. Once the register field is selected, the weighting value for a particular thread is based upon the retrieved weighting value from the selected register field; whether the thread is in a run state or idle state; and whether one of the threads dispatches an instruction (on one of the active threads).

Table <b>300</b> corresponds to an embodiment of a hypervisor identifying a summary thread context of “8.” Other embodiment tables are not included in this disclosure (e.g., for summary context of 1, 2, 4, etc.) for simplicity purposes. In addition, table <b>300</b> is just one example of assigning register fields based upon the number of threads running and a particular SMT mode.

Rows <b>305</b>-<b>345</b> correspond to the number of threads in the run state (column <b>350</b>). In one embodiment, in order to save RWMR field bits while still providing a potentially large value to the running thread, register fields may include a combination of run weighting values and idle weighting values. In this embodiment, the register fields include run weighting values for times at which processor <b>100</b>'s operating environment has a large number of threads in the run state (4-8 threads), and includes idle weighting values for times at which processor <b>100</b>'s operating environment has a small number of threads are in the run state (1-3 threads). In this embodiment, regarding a small number of running threads, the corresponding register field may include a small value in a 4-bit field, which gives running thread(s) a large value (e.g., 50 decimal). Otherwise, more bits are required to represent large values for running threads (thus larger registers). Likewise, when a larger number of running threads are available (4 or more), the weighting value is used for the run weighting value since there are enough bits times number of running threads to achieve large values. In either case, the total count of run weighting values and idle weighting values add to 64/64 (includes dispatch run weighting values and dispatch idle weighting values).

Column <b>355</b> shows that when processor <b>100</b> is in SMT<b>1</b> mode, a valid number of running threads is 0 or 1. Column <b>360</b> shows that when processor <b>100</b> is in SMT<b>2</b> mode, a valid number of running threads is between 0-2. Column <b>365</b> shows that when processor <b>100</b> is in SMT<b>4</b> mode, a valid number of running threads is between 0-4. And, column <b>370</b> shows that when processor <b>100</b> is in SMT<b>8</b> mode, a valid number of running threads is between 0-8.

As an example of using weighting values, assume that the system is in summary thread context 8, SMT<b>2</b> mode, and one thread is running (row <b>310</b>). Table <b>300</b> shows to retrieve a weighting value from register field “RF<b>3</b>” and use the weighting value (WV<b>3</b>) as an idle weighting value (column <b>375</b>). As such: <br />Idle Weighting Value=WV3<br />Non-Dispatch Idle Weighting Value=(WV3)×(online thread count−run thread count)<br />Dispatch Idle Weighting Value=(WV3−Dispatch Factor)×(online thread count−run thread count)<br />Non-Dispatch Run Weighting Value=64−(Non-Dispatch Idle Weighting Value)<br />Dispatch Run Weighting Value=64−Dispatch Idle Weighting Value

As another example of using weighting values, assume that the system is in summary thread context 8, SMT<b>8</b> mode, and five threads are running (row <b>330</b>). Table <b>300</b> shows to retrieve a weighting value from register field “RF<b>12</b>” and use the corresponding weighting value (WV<b>12</b>) as a run weighting value (column <b>375</b>). As such: <br />Run Weighting Value=WV12<br />Non-Dispatch Run Weighting Value=(WV12)×(run thread count)<br />Dispatch Run Weighting Value=(WV12+Dispatch Factor)×(run thread count)<br />Non-Dispatch Idle Weighting Value=64−(Non-Dispatch Run Weighting Value)<br />Dispatch Idle Weighting Value=64−Dispatch Run Weighting Value

As discussed herein, when a dispatch run weighting value or dispatch idle weighting value exceeds a maximum/minimum value (based on the number of threads), such values will be rounded off accordingly (see <figref idref="DRAWINGS">FIG. 7</figref> and corresponding text for further details).

A few of table <b>300</b>'s cells include two register fields (SMT<b>8</b>, <b>4</b> threads running). For these processing environments, weighting values from a particular register location may be used based upon which regions the threads are active. For example, if four threads are running in the same region, then the weighting value from RF<b>8</b> is used. If two threads are running in one region, and the other two threads are running in a different region, then the weighting value from RF<b>10</b> is used. This is because different regions may be used to best match the expected performance of a processor for a particular state and resource allocation. In one embodiment, a maximum of thirteen regions are defined as the best match to differing machine performance regions relative to bits used in defining the region values.

<figref idref="DRAWINGS">FIG. 4</figref> is a table showing region-weighted mode register partitioned into multiple register fields (RF<b>1</b>-RF<b>13</b>) and a dispatch factor field. Table <b>400</b> shows that the dispatch factor value is stored in bits <b>1</b>-<b>3</b>, whether a system is in a single logical partition (LPAR) mode (column <b>420</b>) or a multi-LPAR mode (e.g., 4-LPAR) (column <b>430</b>) (see <figref idref="DRAWINGS">FIG. 5</figref> and corresponding text for further details). As can be seen, when a system is in multi-LPAR mode, the RWMR uses some of the same register fields (RF<b>4</b>, RF<b>6</b>, RF<b>8</b>, and RF<b>10</b>) to store weighting values as it does for the single LPAR mode.

<figref idref="DRAWINGS">FIG. 5</figref> is a table showing a relationship between dispatch factor bits (included in dispatch factor field <b>120</b>), a dispatch factor, and a dispatch weighting value numerator. Table <b>500</b> shows, in one embodiment, that the dispatch factor may be represented by three bits (column <b>510</b>). As those skilled in the art may appreciate, more or less bits may be used based upon the required dispatch factor resolution. Column <b>520</b> shows dispatch factor values that correspond to the various bit values shown in column <b>510</b>, and column <b>530</b> shows an embodiment of computing dispatch weightings based on the dispatch factor. For example, when the dispatch factor is ¼, a dispatch run weighting value may be computed by multiplying the run weighting value's numerator by 1¼ (5/4). In this example, assuming a run weighting value is 4/64, the dispatch run weighting value is [(5/4)*4]/64, which equals 5/64. In one embodiment, computational logic may compute a dispatch fraction (¼* 4/64= 1/64) and add the dispatch fraction to the weighting value to compute the dispatch run weighting value ( 1/64+ 4/64= 5/64).

<figref idref="DRAWINGS">FIG. 6</figref> is a flowchart showing steps taken in computing resource utilization values on a per thread basis. The steps shown in <figref idref="DRAWINGS">FIG. 6</figref> may be performed using software, firmware, or hardware (e.g., <figref idref="DRAWINGS">FIGS. 1 and 2</figref>). Processing commences at <b>600</b>, whereupon processing identifies a summary thread context based upon thread context information stored in LPCR register <b>105</b> (step <b>605</b>). As discussed herein, in one embodiment, the summary thread context may be 1, 2, 4, or 8, depending upon the number of active threads. In this embodiment: <ul id="ul0007" list-style="none"><li id="ul0007-0001" num="0000"><ul id="ul0008" list-style="none"><li id="ul0008-0001" num="0067">1 thread active: Summary Thread Context 1;</li><li id="ul0008-0002" num="0068">2 threads active: Summary Thread Context 2;</li><li id="ul0008-0003" num="0069">3-4 threads active: Summary Thread Context 4;</li><li id="ul0008-0004" num="0070">5-8 threads active: Summary Thread Context 8.</li></ul></li></ul>

At step <b>610</b>, processing identifies the number of threads that are running (vs. number of threads that are idle). Processing, at step <b>615</b>, identifies a register location in and retrieves a weighting value from RWMR register <b>115</b> based upon the summary thread context, the number of threads running, and the simultaneous multi-thread (SMT) mode set by SMT mode logic <b>125</b> (see <figref idref="DRAWINGS">FIG. 3</figref> and corresponding text for further details). As discussed earlier, SMT mode logic sets an SMT mode of SMT<b>1</b>, SMT<b>2</b>, SMT<b>4</b>, or SMT<b>8</b> based upon the amount of interrupts and sleep commands in processor <b>100</b>. In one embodiment, RWMR register <b>115</b> may include idle weighting values instead of run weighting values. In this embodiment, processing retrieves an idle weighting value based upon the summary thread context, the number of threads idle, and the SMT mode set by SMT mode logic <b>125</b>.

Processing selects a first thread at step <b>620</b>, and proceeds to compute/store a fractional weighting value for the selected thread based upon the thread's state (idle state or a run state), and whether one of the active threads is dispatching an instruction. Processing then stores the fractional weighting value in one of fractional PURR accumulators <b>250</b> that correspond to the selected thread (pre-defined process block <b>625</b>, see <figref idref="DRAWINGS">FIG. 7</figref> and corresponding text for further details). In one embodiment, processing utilizes a distributed round robin sequence that iteratively selects different threads and stores fractional weighting values accordingly (see <figref idref="DRAWINGS">FIGS. 8-9</figref> and corresponding text for further details).

A determination is made as to whether there are more active threads for which to compute a fractional weighting value (decision <b>630</b>). For example, if three threads are active (e.g., 1 running and 2 idle), processing loops back to compute a fractional weighting value for all three threads. In one embodiment, such as a hardware embodiment similar to that shown in <figref idref="DRAWINGS">FIG. 1</figref>, a processor may concurrently compute fractional weighting values for each active thread.

If there are more threads for which to compute a fractional weighting value, decision <b>630</b> branches to “Yes” branch <b>632</b>, whereupon processing loops back to select the next active thread and compute/store a fractional weighting value for the selected thread. This looping continues until processing computes/stores a fractional weighting value for each thread, at which point decision <b>630</b> branches to “No” branch <b>638</b>.

A determination is made as to whether to add the fractional weighting values included in fractional PURR accumulators <b>250</b> to the accumulated weighting values stored in PURRs <b>650</b> (decision <b>640</b>). For example, processing may add the fractional weighting values in PURRs <b>650</b> every 100 clock cycles. If processing should add the fractional weighting values in PURRs <b>650</b>, decision <b>640</b> branches to “Yes” branch <b>642</b>, whereupon processing adds the fractional weighting values from fractional PURR accumulators <b>250</b> to corresponding PURRs <b>650</b>. On the other hand, if processing should not add the fractional weighting factors to PURRs <b>650</b> at this time, processing branches to “No” branch <b>648</b>, bypassing step <b>645</b>.

A determination is made as to whether to continue to compute thread fractional weighting values (decision <b>660</b>). If processing should continue, decision <b>660</b> branches to “Yes” branch <b>662</b>, which loops back to continue computing fractional weighting values. This looping continues until processing stops computing fractional weighting values, at which point decision <b>660</b> branches to “No” branch <b>668</b>. Processing, at step <b>670</b>, computes resource utilization values for each of the active threads based upon the values included in PURRs <b>650</b>, and processing ends at <b>670</b>.

<figref idref="DRAWINGS">FIG. 7</figref> is a flowchart showing steps taken in computing a fractional weighting value for a selected thread. Processing commences at <b>700</b>, whereupon processing identifies a thread state (e.g., idle state or run state) of the thread that was selected in <figref idref="DRAWINGS">FIG. 6</figref> (step <b>620</b>). A determination is made as to whether the thread state is a run state or idle state (decision <b>710</b>). If the selected thread is in the run state, decision <b>710</b> branches to “Run” branch <b>712</b>, whereupon processing selects or computes a run weighting value using the weighting value that was retrieved in step <b>615</b> shown in <figref idref="DRAWINGS">FIG. 6</figref>, depending on whether the retrieved weighting value is a run weighting value or an idle weighting value (step <b>715</b>).

A determination is made as to whether one of the active threads is dispatching an instruction (decision <b>720</b>). For example, processing may use dispatch valid signals <b>145</b> shown in <figref idref="DRAWINGS">FIG. 1</figref> to make such determination. If no dispatch is occurring, decision <b>720</b> branches to “No” branch <b>722</b>, whereupon processing adds the run weighting value (from step <b>715</b>) to a corresponding fractional PURR accumulator <b>250</b> at step <b>723</b> (e.g., to thread 1's fractional PURR accumulator). Processing returns at <b>725</b>.

On the other hand, if one of the active threads is dispatching an instruction (not necessarily the selected thread), decision <b>720</b> branches to “Yes” branch <b>728</b>, whereupon processing retrieves a dispatch factor, such as from dispatch factor field <b>120</b> shown in <figref idref="DRAWINGS">FIG. 1</figref> (step <b>730</b>). At step <b>735</b>, processing computes a dispatch run weighting value based upon the dispatch factor and the run weighting value from step <b>715</b>. For example, if the dispatch factor is ¼, then processing multiplies the run weight value's numerator by 1¼ (see <figref idref="DRAWINGS">FIG. 5</figref> and corresponding text for further details).

At step <b>740</b>, processing rounds off the dispatch run weighting value if it is over a maximum. For example, assuming six running threads; the dispatch factor is ¼; and the run weighting value is 9/64; then the calculated dispatch run weighting value=(9*1¼)/64= 11/64. Since six threads are running, each thread is allowed a maximum weighting of 10/64(6* 10/64= 60/64), which is the largest value without overflowing 64/64. Therefore, in this example, processing rounds off the dispatch run weighting value from 11/64 to 10/64.

At step <b>745</b>, processing adds the dispatch run weighting value to one of fractional PURR accumulators <b>250</b> that correspond to the selected thread, and processing returns at <b>750</b>.

Referring back to decision <b>710</b>, If the selected thread is in the idle state, decision <b>710</b> branches to “Idle” branch <b>714</b>, whereupon processing selects or computes an idle weighting value using the weighting value that was retrieved in step <b>615</b> shown in <figref idref="DRAWINGS">FIG. 6</figref> (step <b>755</b>). A determination is made as to whether one of the active threads is dispatching an instruction (decision <b>760</b>). If no dispatch is occurring, decision <b>760</b> branches to “No” branch <b>762</b>, whereupon processing adds the idle weighting value (from step <b>755</b>) to a corresponding fractional PURR accumulator <b>250</b> at step <b>763</b>. Processing returns at <b>765</b>.

On the other hand, if one of the active threads is dispatching an instruction, decision <b>760</b> branches to “Yes” branch <b>768</b>, whereupon processing retrieves the dispatch factor at step <b>770</b>. At step <b>775</b>, processing computes a dispatch idle weighting value based upon the dispatch factor and the idle weighting value from step <b>715</b>.

At step <b>780</b>, processing rounds off the dispatch run weighting value if it is over a maximum and, at step <b>785</b>, processing adds the dispatch idle weighting value to one of fractional PURR accumulators <b>250</b> that correspond to the selected thread. Processing returns at <b>790</b>.

In one embodiment, different weightings are computed once (e.g., run weighting value, idle weighting value, dispatch run weighting value, dispatch idle weighting value) and stored in corresponding fractional PURR accumulators <b>250</b> based on each thread's condition (idle, run, dispatch, etc.)

<figref idref="DRAWINGS">FIG. 8</figref> is a flowchart showing steps taken in computing fractional weighting values and adding the fractional weighting values to fractional accumulators using a distributed round robin sequence (see <figref idref="DRAWINGS">FIG. 9</figref> and corresponding text for further details). Processing commences at <b>800</b>, whereupon processing retrieves LPCR bits from LPCR register <b>105</b>, which identifies the number of active threads. At step <b>815</b>, processing initializes pointers (e.g., a run thread pointer and an idle thread pointer), and selects a first valid run thread and a first valid idle thread based on run logic <b>130</b> (indicates which threads that are in a run state).

At step <b>820</b>, processing calculates run weighting values and idle weighting values (or dispatch run weighting values and dispatch idle weighting values if one of threads is dispatching an instruction via dispatch logic <b>140</b>). These values are based on the weighting value retrieved from RWMR <b>115</b> (based on SMT mode and number of threads running). At step <b>825</b>, processing adds the run weighting value to one of fractional PURR accumulators <b>250</b> corresponding to a run thread identified by the run thread pointer. Next, at step <b>830</b>, processing adds the idle weighting value to one of fractional PURR accumulators <b>250</b> corresponding to an idle thread identified by the idle thread pointer. The example in <figref idref="DRAWINGS">FIG. 9</figref> shows threads 0, 1, and 2 are running, while threads 3-6 are idle. In this example, the run thread pointer is initially pointing at thread 0 (first running thread) and the idle thread pointer is initially pointing at thread 3 (first idle thread). Column <b>960</b> shows that the run weighting value is added to thread 0's fractional PURR accumulator, and the idle weighting value is added to thread 3's fractional PURR accumulator.

A determination is made as to whether to continue the distributed round robin sequence (decision <b>840</b>). If the distributed round robin sequence should continue, decision <b>840</b> branches to “Yes” branch <b>842</b>, which loops back to select the next run thread (adjust the run thread pointer) and select the next idle thread (adjust the idle thread pointer) at step <b>845</b>, and add weighting values to the selected threads' fractional PURR accumulators accordingly. This looping continues until distributed round robin sequence terminates, at which point decision <b>840</b> branches to “No” branch <b>848</b>, whereupon processing ends at <b>850</b>. In one embodiment, processing adds the weighting values included in fractional PURR accumulators <b>250</b> to thread PURRs and computes thread utilization values, such as that shown in FIG. <b>6</b>'s step <b>645</b>-<b>670</b>.

<figref idref="DRAWINGS">FIG. 9</figref> is a table showing a distributed cycle round robin sequence that adds weighting values to active threads over time. In one embodiment, the distributed cycle round robin sequence uses pointers (one for run threads and one for idle threads) to track which thread to add weighting values for a particular sequence. In this embodiment, a run weighting value (or dispatch run weighting value) and an idle weighting value (or dispatch idle weighting value) are re-computed for each sequence.

Table <b>900</b> includes rows <b>905</b>-<b>940</b>, which correspond to threads 0-7 (column <b>945</b>). Column <b>950</b> shows that seven threads are active (threads 0-6). Column <b>955</b> shows that threads 0-2 are in the run state, and threads 3-6 are in the idle state. As such, the run thread pointer cycles through threads 0-2, and the idle thread pointer cycles through threads 3-6.

Columns <b>960</b>-<b>990</b> show which thread receives weighting values based upon sequence <b>1</b>-<b>7</b>, respectively. Since the run thread pointer starts at the first run thread (thread 0), column <b>960</b> shows that a run weighting value is added to thread 0's fractional accumulator. Likewise, since the idle thread pointer starts at the first idle thread (thread 3), column <b>960</b> shows that the idle weighting value is added to thread 3's fractional accumulator.

During the second sequence (cycle), the run weighting value is added to thread 1's fractional accumulator and the idle weighting value is added to thread 4's fractional accumulator (column <b>965</b>). The third sequence shows that a dispatch (D) occurs. As such, a dispatch run weighting value is added to thread 2's fractional accumulator and a dispatch idle weighting value is added to thread 5's fractional accumulator (column <b>970</b>). Since, at the fourth sequence, the run thread pointer was at the last run thread (thread 2), the run thread pointer cycles back to thread 0 and adds the run weighting value to thread 0's fractional accumulator. The idle thread pointer, however, cycles to the next idle thread (thread 6), and adds the idle weighting value to thread 6's fractional accumulator. This process continues over time that, in turn, provides an accurate representation of weighting values between threads 0-6.

In one embodiment that includes only run threads or idle threads, the calculated value may be overridden to a 64 decimal and applied to the active threads. In another embodiment, the distributed cycle round robin sequence is used in single LPAR mode. In this embodiment when a system is in a multi-LPAR mode, each thread is updated each cycle due each LPAR operating independently and simplified charge calculations (see <figref idref="DRAWINGS">FIG. 4</figref> and corresponding text for further details).

<figref idref="DRAWINGS">FIG. 10</figref> illustrates information handling system <b>1000</b>, which is a simplified example of a computer system capable of performing the computing operations described herein. Information handling system <b>1000</b> includes one or more processors <b>1010</b> coupled to processor interface bus <b>1012</b>. Processor interface bus <b>1012</b> connects processors <b>1010</b> to Memory Controller Hub (MCH) <b>1015</b>. MCH <b>1015</b> connects to system memory <b>1020</b> and provides a means for processor(s) <b>1010</b> to access the system memory. Graphics controller <b>1025</b> also connects to MCH <b>1015</b>. In one embodiment, PCI Express bus <b>1018</b> connects MCH <b>1015</b> to graphics controller <b>1025</b>. Graphics controller <b>1025</b> connects to display device <b>1030</b>, such as a computer monitor.

MCH <b>1015</b> and I/O Controller Hub (ICH) <b>1035</b> connect to each other using bus <b>1019</b>. In one embodiment, the bus is a high-speed interface bus that transfers data at high speeds in each direction between MCH <b>1015</b> and ICH <b>1035</b>. In another embodiment, a Peripheral Component Interconnect (PCI) bus connects the MCH and the ICH. ICH <b>1035</b> is a chip that generally implements capabilities that operate at slower speeds than the capabilities provided by the MCH. ICH <b>1035</b> typically provides various busses used to connect various components. These busses include, for example, PCI and PCI Express busses, an ISA bus, a System Management Bus (SMBus or SMB), and/or a Low Pin Count (LPC) bus. The LPC bus often connects low-bandwidth devices, such as boot ROM <b>1096</b> and “legacy” I/O devices (using a “super I/O” chip). The “legacy” I/O devices (<b>1098</b>) can include, for example, serial and parallel ports, keyboard, mouse, and/or a floppy disk controller. The LPC bus also connects ICH <b>1035</b> to Trusted Platform Module (TPM) <b>1095</b>. Other components often included in ICH <b>1035</b> include a Direct Memory Access (DMA) controller, a Programmable Interrupt Controller (PIC), and a storage device controller, which connects ICH <b>1035</b> to nonvolatile storage device <b>1085</b>, such as a hard disk drive, using bus <b>1084</b>.

ExpressCard <b>1055</b> is a slot that connects hot-pluggable devices to the information handling system. ExpressCard <b>1055</b> supports both PCI Express and USB connectivity as it connects to ICH <b>1035</b> using both the Universal Serial Bus (USB) the PCI Express bus. ICH <b>1035</b> includes USB Controller <b>1040</b> that provides USB connectivity to devices that connect to the USB. These devices include webcam (camera) <b>1050</b>, infrared (IR) receiver <b>1048</b>, keyboard and trackpad <b>1044</b>, and Bluetooth device <b>1046</b>, which provides for wireless personal area networks (PANs). USB Controller <b>1040</b> also provides USB connectivity to other miscellaneous USB connected devices <b>1042</b>, such as a mouse, removable nonvolatile storage device <b>1045</b>, modems, network cards, ISDN connectors, fax, printers, USB hubs, and many other types of USB connected devices. While removable nonvolatile storage device <b>1045</b> is shown as a USB-connected device, removable nonvolatile storage device <b>1045</b> could be connected using a different interface, such as a Firewire interface, etcetera.

Wireless Local Area Network (LAN) device <b>1075</b> connects to ICH <b>1035</b> via the PCI or PCI Express bus <b>1072</b>. LAN device <b>1075</b> typically implements one of the IEEE 802.11 standards of over-the-air modulation techniques that all use the same protocol to wireless communicate between information handling system <b>1000</b> and another computer system or device. Optical storage device <b>1090</b> connects to ICH <b>1035</b> using Serial ATA (SATA) bus <b>1088</b>. Serial ATA adapters and devices communicate over a high-speed serial link. The Serial ATA bus also connects ICH <b>1035</b> to other forms of storage devices, such as hard disk drives. Audio circuitry <b>1060</b>, such as a sound card, connects to ICH <b>1035</b> via bus <b>1058</b>. Audio circuitry <b>1060</b> also provides functionality such as audio line-in and optical digital audio in port <b>1062</b>, optical digital output and headphone jack <b>1064</b>, internal speakers <b>1066</b>, and internal microphone <b>1068</b>. Ethernet controller <b>1070</b> connects to ICH <b>1035</b> using a bus, such as the PCI or PCI Express bus. Ethernet controller <b>1070</b> connects information handling system <b>1000</b> to a computer network, such as a Local Area Network (LAN), the Internet, and other public and private computer networks.

While <figref idref="DRAWINGS">FIG. 10</figref> shows one information handling system, an information handling system may take many forms. For example, an information handling system may take the form of a desktop, server, portable, laptop, notebook, or other form factor computer or data processing system. In addition, an information handling system may take other form factors such as a personal digital assistant (PDA), a gaming device, ATM machine, a portable telephone device, a communication device or other devices that include a processor and memory.

The Trusted Platform Module (TPM <b>1095</b>) shown in <figref idref="DRAWINGS">FIG. 10</figref> and described herein to provide security functions is but one example of a hardware security module (HSM). Therefore, the TPM described and claimed herein includes any type of HSM including, but not limited to, hardware security devices that conform to the Trusted Computing Groups (TCG) standard, and entitled “Trusted Platform Module (TPM) Specification Version 1.2.” The TPM is a hardware security subsystem that may be incorporated into any number of information handling systems, such as those outlined in <figref idref="DRAWINGS">FIG. 11</figref>.

<figref idref="DRAWINGS">FIG. 11</figref> provides an extension of the information handling system environment shown in <figref idref="DRAWINGS">FIG. 10</figref> to illustrate that the methods described herein can be performed on a wide variety of information handling systems that operate in a networked environment. Types of information handling systems range from small handheld devices, such as handheld computer/mobile telephone <b>1110</b> to large mainframe systems, such as mainframe computer <b>1170</b>. Examples of handheld computer <b>1110</b> include personal digital assistants (PDAs), personal entertainment devices, such as MP3 players, portable televisions, and compact disc players. Other examples of information handling systems include pen, or tablet, computer <b>1120</b>, laptop, or notebook, computer <b>1130</b>, workstation <b>1140</b>, personal computer system <b>1150</b>, and server <b>1160</b>. Other types of information handling systems that are not individually shown in <figref idref="DRAWINGS">FIG. 11</figref> are represented by information handling system <b>1180</b>. As shown, the various information handling systems can be networked together using computer network <b>1100</b>. Types of computer network that can be used to interconnect the various information handling systems include Local Area Networks (LANs), Wireless Local Area Networks (WLANs), the Internet, the Public Switched Telephone Network (PSTN), other wireless networks, and any other network topology that can be used to interconnect the information handling systems. Many of the information handling systems include nonvolatile data stores, such as hard drives and/or nonvolatile memory. Some of the information handling systems shown in <figref idref="DRAWINGS">FIG. 11</figref> depicts separate nonvolatile data stores (server <b>1160</b> utilizes nonvolatile data store <b>1165</b>, mainframe computer <b>1170</b> utilizes nonvolatile data store <b>1175</b>, and information handling system <b>1180</b> utilizes nonvolatile data store <b>1185</b>). The nonvolatile data store can be a component that is external to the various information handling systems or can be internal to one of the information handling systems. In addition, removable nonvolatile storage device <b>1045</b> can be shared among two or more information handling systems using various techniques, such as connecting the removable nonvolatile storage device <b>1045</b> to a USB port or other connector of the information handling systems.

While particular embodiments of the present disclosure have been shown and described, it will be obvious to those skilled in the art that, based upon the teachings herein, that changes and modifications may be made without departing from this disclosure and its broader aspects. Therefore, the appended claims are to encompass within their scope all such changes and modifications as are within the true spirit and scope of this disclosure. Furthermore, it is to be understood that the disclosure is solely defined by the appended claims. It will be understood by those with skill in the art that if a specific number of an introduced claim element is intended, such intent will be explicitly recited in the claim, and in the absence of such recitation no such limitation is present. For non-limiting example, as an aid to understanding, the following appended claims contain usage of the introductory phrases “at least one” and “one or more” to introduce claim elements. However, the use of such phrases should not be construed to imply that the introduction of a claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to disclosures containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an”; the same holds true for the use in the claims of definite articles.