Power module package

CROSS REFERENCE TO RELATED APPLICATION

0001This application claims the benefit of Korean Patent Application No. 10-2011-0112335, filed on Oct. 31, 2011, entitled “Power Module Package”, which is hereby incorporated by reference in its entirety into this application.

BACKGROUND OF THE INVENTION

00021. Technical Field

0003The present invention relates to a power module package.

00042. Description of the Related Art

0005As an amount of used energy increases worldwide, a power conversion apparatus such as an inverter for home and industry has been increasingly employed for an efficient use of energy and protection of an environment.

0006An intelligent power module (IPM) spotlighting along with an increase in the employment of the inverter is a core parts performing functions of rectifying a DC and converting an AC and may be applied to home appliances such as a refrigerator, a washing machine, an air conditioner, etc., industrial appliances such as an industrial motor, and next generation appliances such as HEV, EV, etc.

0007In general, if heat is greatly generated during a power conversion process, and the generated heat is not efficiently removed, a module and a whole system may deteriorate in terms of performance and be damaged. Furthermore, since multi-function and small-size parts are essential to the IPM according to a recent tendency, an efficient dissipation of heat due to the multi-function and small-size parts is also an important factor as well as a structure enhancement for multi-function and small-size.

0008Meanwhile, as one of conventional methods, a direct bonded copper (DBC) substrate obtained by sintering and bonding a copper substrate to both sides with respect to ceramic by applying heat and pressure is used.

0009However, the above-described DBC substrate has advantageously excellent heat dissipation and thermal conductivity characteristics, whereas it is disadvantageously expensive in terms of a processing characteristic, and it is difficult to manufacture a large size DBC substrate in terms of a thin ceramic characteristic.

0010Furthermore, the above-described DBC substrate has a structure in which the copper substrates are bonded to both sides of the ceramic, which may problematically cause delamination of the copper substrate from the ceramic.

SUMMARY OF THE INVENTION

0011The present invention has been made in an effort to provide a power module package having an improved heat dissipation characteristic.

0012Further, the present invention has been made in an effort to provide a power module package capable of minimizing an influence of heat generated from a power device to a control device.

0013Further, the present invention has been made in an effort to provide a power module package having reduced material cost and processing expense.

0014Further, the present invention has been made in an effort to provide a power module package capable of preventing delamination from occurring between metal layers.

0015According to a first preferred embodiment of the present invention, there is provided a power module package, including: a substrate having a ceramic layer formed in one surface thereof; a circuit pattern formed on the ceramic layer; a first lead frame having one side contacting the circuit pattern and the other side protruding toward the outside; and a first semiconductor chip mounted on one side of the first lead frame.

0016The power module package may further include: a bonding layer formed between the circuit pattern and the first lead frame.

0017The circuit pattern may include an electroless plating layer and an electroplating layer.

0018The power module package may further include: a second lead frame spaced apart from the first lead frame and electrically connected to the first semiconductor chip; and a second semiconductor chip mounted on the second lead frame.

0019The first lead frame and the second lead frame may be formed to have a step therebetween.

0020The power module package may further include: a molding material formed to surround the first semiconductor chip from a side of the substrate.

0021The substrate may be a metal substrate.

0022According to a second preferred embodiment of the present invention, there is provided a power module package including: a substrate having a ceramic layer formed in one surface thereof; a circuit pattern formed on the ceramic layer; and a lead frame bonded onto the circuit pattern.

0023The lead frame may include a first lead frame having one side contacting the circuit pattern and the other side protruding toward the outside and a second lead frame having one side contacting the circuit pattern and the other side protruding toward the outside, wherein one side of the first lead frame and one side of the second lead frame are spaced apart to face each other.

0024The power module package may further include: a first semiconductor chip mounted on the first lead frame; and a second semiconductor chip mounted on the second lead frame.

0025The power module package may further include: a first semiconductor chip mounted on the first lead frame; and a second semiconductor chip mounted on the circuit pattern.

0026The power module package may further include: a first semiconductor chip and a second semiconductor chip mounted on the circuit pattern, wherein the circuit pattern on which the first semiconductor chip is mounted and the circuit pattern on which the second semiconductor chip is mounted are spaced apart from each other.

0027The power module package may further include: a bonding layer formed between the circuit pattern and the lead frame.

0028The circuit pattern may include an electroless plating layer and an electroplating layer.

0029The power module package may further include: a molding material formed to surround an upper portion of the lead frame from a side of the substrate.

0030The substrate may be a metal substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

0031The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

0032<figref idref="DRAWINGS">FIG. 1</figref> is a cross-sectional view of a structure of a power module package according to a first embodiment of the present invention;

0033<figref idref="DRAWINGS">FIG. 2</figref> is a cross-sectional view of a structure of a power module package according to a second embodiment of the present invention;

0034<figref idref="DRAWINGS">FIG. 3</figref> is a cross-sectional view of a structure of a power module package according to a third embodiment of the present invention; and

0035<figref idref="DRAWINGS">FIG. 4</figref> is a cross-sectional view of a structure of a power module package according to a fourth embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

0036The objects, features and advantages of the present invention will be more clearly understood from the following detailed description of the preferred embodiments taken in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant descriptions thereof are omitted. Further, in the following description, the terms “first”, “second”, “one side”, “the other side” and the like are used to differentiate a certain component from other components, but the configuration of such components should not be construed to be limited by the terms. Further, in the description of the present invention, when it is determined that the detailed description of the related art would obscure the gist of the present invention, the description thereof will be omitted.

0037Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

First Embodiment

0038<figref idref="DRAWINGS">FIG. 1</figref> is a cross-sectional view of a structure of a power module package <b>100</b> according to a first embodiment of the present invention.

0039Referring to <figref idref="DRAWINGS">FIG. 1</figref>, the power module package <b>100</b> of the present embodiment includes a substrate <b>101</b> having a ceramic layer <b>103</b> formed in one surface thereof and a circuit pattern formed on the ceramic layer <b>103</b>.

0040Also, in the present embodiment, the power module package <b>100</b> may further include a first lead frame <b>110</b> contacting the circuit pattern and a second lead frame <b>120</b> spaced apart from the first lead frame <b>110</b>.

0041Also, in the present embodiment, the power module package <b>100</b> may further include a first semiconductor chip <b>130</b> mounted on the first lead frame <b>110</b> and a second semiconductor chip <b>140</b> mounted on the second lead frame <b>120</b>.

0042Although the substrate <b>101</b> may be a metal substrate in the present embodiment, the present invention is not limited thereto. For example, the substrate <b>101</b> may include a printed circuit board (PCB), an insulated metal substrate (IMS), a pre-molded substrate.

0043In the present embodiment, the ceramic layer <b>103</b> may be formed in one surface of the substrate <b>101</b>.

0044In this regard, the ceramic layer <b>103</b> may be formed through a spray process, a dipping process, a bar coating process, a spin coating process, etc. However, the present invention is not particularly limited thereto.

0045In this regard, since it is easy to form ceramic having a desired thickness according to the ceramic characteristics, the ceramic layer <b>103</b> having various thicknesses from 1 μm and 500 μm may be formed according to usage thereof.

0046Further, roughness is formed on the surface of the substrate <b>181</b> before forming the ceramic layer <b>103</b>, thereby enhancing a bonding force between the ceramic layer <b>103</b> and the substrate <b>101</b>.

0047In this regard, the roughness may be formed using a sand blast, plasma processing, wet surface processing, a brush buff, etc., but the present invention is not particularly limited thereto.

0048Also, in the present embodiment, a circuit pattern may be formed on the ceramic layer <b>103</b>.

0049In this regard, as shown in <figref idref="DRAWINGS">FIG. 1</figref>, the circuit pattern may include an electroless plating layer <b>105</b> and an electroplating layer <b>107</b>.

0050Further, the circuit pattern may be a metal layer pattern including copper (Cu) or copper alloy. In this case, copper (Cu) may provide excellent electric conductivity, and a nickel (Ni) layer for antioxide may be further formed on a copper circuit pattern.

0051Further, since the nickel (Ni) layer does not exhibit excellent coating property with respect to copper (Cu) and thus may also be oxidized, a metal (Au) layer may be further formed on the nickel (Ni) layer.

0052However, the circuit pattern is not limited to the structure of the present embodiment, and may include metal or metal alloy having excellent electric conductivity. For example, the circuit pattern may include aluminum or aluminum alloy.

0053In the present embodiment, an operation of forming the circuit pattern is as follows.

0054First, the seed layer <b>105</b> that is an electroless plating layer is formed on the ceramic layer <b>103</b> formed in one surface of the substrate <b>101</b>.

0055In this regard, the seed layer <b>105</b> may be formed by a wet plating process or a dry plating process. In this regard, the wet plating process may be an electroless plating process, the dry plating process may be a sputtering process, but the present invention is not particularly limited thereto.

0056In this regard, the electroless plating process may be performed by using one of nickel (Ni), copper (Cu), and silver (Ag), and the sputtering process may be performed by using one of titanium (Ti), chrome (Cr), and nickel (Ni), but the present invention is not particularly limited thereto.

0057Next, the plating layer <b>107</b> that is an electroplating layer is formed on the seed layer <b>105</b>.

0058In this regard, the plating layer <b>107</b> may also be formed by using the electroplating process or the sputtering process, and may be formed of copper (Cu), but the present invention is not particularly limited thereto. The plating layer <b>107</b> is formed of copper (Cu) exhibiting good solder bonding property since the plating layer <b>107</b> is bonded onto the first lead frame <b>110</b> by soldering at a subsequent process.

0059Next, an etching resist having an opening unit for forming a circuit pattern is formed on the plating layer <b>107</b>, an etching process is performed, and the plating layer <b>107</b> and the seed layer <b>105</b> exposed by the opening unit for forming the circuit pattern are removed, and thus the circuit pattern may be formed.

0060Although a substractive technique is described as a process of forming the circuit pattern in the present embodiment, the present invention is not limited thereto, and all processes for forming a circuit pattern generally used in a PCB field may be applied.

0061In the present embodiment, one side <b>110</b><i>a </i>of the first lead frame <b>110</b> is bonded onto the plating layer <b>107</b> of the circuit pattern formed on the ceramic layer <b>103</b>, and the other side <b>110</b><i>b </i>thereof may externally protrude form the substrate <b>101</b>.

0062At this time, a bonding layer <b>109</b> may be further formed between the one side <b>110</b><i>a </i>of the first lead frame <b>110</b> and the plating layer <b>107</b> of the circuit pattern.

0063In this regard, the bonding layer <b>109</b> may be soldering, and may be used to connect mechanically and electrically the one side <b>110</b><i>a </i>of the first lead frame <b>110</b> and the plating layer <b>107</b> to each other.

0064Further, in the present embodiment, the second lead frame <b>120</b> may not contact the substrate <b>101</b> but may be spaced apart from the first lead frame <b>110</b>. In this regard, the second lead frame <b>120</b> may be formed to have a step from the first lead frame <b>110</b>. Although one side <b>120</b><i>a </i>of the second lead frame <b>120</b> may be formed to overlap the one side <b>110</b><i>a </i>of the first lead frame <b>110</b> in <figref idref="DRAWINGS">FIG. 1</figref>, this is merely an example, and the one side <b>120</b><i>a </i>of the second lead frame <b>120</b> may be formed not to overlap the one side <b>110</b><i>a </i>of the first lead frame <b>110</b>.

0065Further, although a pair of lead frames <b>110</b> and <b>120</b> is shown in <figref idref="DRAWINGS">FIG. 1</figref>, this is merely a cross-sectional view, and it will be obvious that several pairs of lead frames may be formed.

0066As described above, a ceramic layer having excellent characteristics of heat dissipation is formed on one surface of a metal substrate, a circuit pattern of a minimum thickness is formed on the ceramic layer, and a lead frame is bonded onto the circuit pattern, and thus the lead frame functions as a heat dissipation substrate, thereby reducing manufacturing cost of the heat dissipation substrate and simultaneously enhancing the characteristics of heat dissipation.

0067In the present embodiment, as shown in <figref idref="DRAWINGS">FIG. 1</figref>, power module package <b>100</b> may further include a first semiconductor chip <b>130</b> mounted on the first lead frame <b>110</b> and a second semiconductor chip <b>140</b> mounted on the second lead frame <b>120</b>.

0068Although not shown in <figref idref="DRAWINGS">FIG. 1</figref>, the first semiconductor chips <b>130</b> and the second semiconductor chip <b>140</b> may be bonded onto the first lead frame <b>110</b> and the second lead frame <b>120</b>, respectively, by using a bonding member (not shown). The bonding adhesive (not shown) may be conductive or non-conductive.

0069For example, the bonding adhesive (not shown) may be formed by gold plating or may be a conductive paste or a conductive tape. Further, the bonding adhesive (not shown) may be a solder, metal epoxy, a metal paste, resin-based epoxy, or a bonding tape having excellent heat resistance.

0070For example, the bonding tape that may be used as the bonding adhesive (not shown) may be a high temperature tape such as a commercialized well-known glass tape, a silicon tape, a Teflon tape, a stainless foil tape, and a ceramic tape. The bonding adhesive (not shown) may be formed of a combination of the above materials, but the present invention is not particularly limited thereto.

0071In this regard, the first semiconductor chips <b>130</b> may use a silicon controlled rectifier (SCR), a power transistor, an insulated gate bipolar transistor (IGBT), a Morse transistor, a power rectifier, a power regulator, an inverter, a converter, or a high power semiconductor chip of a combination of theses or diode.

0072Further, the second semiconductor chip <b>140</b> may include a low power semiconductor chip for controlling the high power semiconductor chip, for example, a control device for controlling a power device.

0073In the present embodiment, the first semiconductor chip <b>130</b> and the second semiconductor chip <b>140</b> respectively bonded onto the first lead frame <b>110</b> and the second lead frame <b>120</b> may be electrically connected to the first lead frame <b>110</b> and the second lead frame <b>120</b> respectively through wire bonding using a wire <b>150</b>.

0074In this regard, a wire bonding process may be preformed through ball bonding, wedge bonding, and stitch bonding that are well-known in the art to which the present invention pertains, but the present invention is not particularly limited thereto.

0075Meanwhile, although the first semiconductor chip <b>130</b> mounted on the first lead frame <b>110</b> and the second semiconductor chip <b>140</b> mounted on the second lead frame <b>120</b> are wire-bonded to the same lead frame in <figref idref="DRAWINGS">FIG. 1</figref>, this is merely a cross-sectional view, and it will be obvious that each semiconductor chip may be wire-bonded to different lead frames.

0076Further, in the present embodiment, as shown in <figref idref="DRAWINGS">FIG. 1</figref>, the power module package <b>100</b> may further include a molding material <b>150</b> formed to surround the first semiconductor chip <b>130</b> mounted on the first lead frame <b>110</b> and the second semiconductor chip <b>140</b> mounted on the second lead frame <b>120</b> that are bonded on the substrate <b>101</b>, as an example from a side of the substrate <b>101</b> to a top portion thereof.

0077The molding material <b>150</b> includes a wire and protects the first semiconductor chip <b>130</b> and the second semiconductor chip <b>140</b> from an external environment and may use, for example, an epoxy molding compound (EMC), etc., but the present invention is not particularly limited thereto.

0078In this regard, although the molding material <b>150</b> is formed from a center portion of the side of the substrate <b>101</b> to the top portion thereof in <figref idref="DRAWINGS">FIG. 1</figref>, this is merely an example and the present invention is not particularly limited thereto. The molding material <b>150</b> may be formed in the whole side of the substrate <b>101</b>.

0079Further, a heat sink may be attached to a bottom surface of the substrate <b>101</b> so as to improve the heat dissipation characteristic.

0080The power module package <b>100</b> according to the present embodiment applies a substrate in which a ceramic layer is formed to a power unit, and thus heat generated from the power unit does not influence to a control unit but may be directly discharged to the heat sink, thereby improving the heat dissipation characteristic and simultaneously maximizing a thermal separation.

0081Furthermore, the control unit and the power unit are designed to have a step, thereby minimizing a thermal transfer effect by a molding material.

Second Embodiment

0082<figref idref="DRAWINGS">FIG. 2</figref> is a cross-sectional view of a structure of a power module package <b>200</b> according to a second embodiment of the present invention.

0083Redundant descriptions between the first embodiment and the second embodiment will be omitted here, and the same reference numerals will denote the same elements therebetween.

0084Referring to <figref idref="DRAWINGS">FIG. 2</figref>, the power module package <b>200</b> according to the present embodiment has a structure in which both the first lead frame <b>110</b> and the second lead frame <b>120</b> are bonded onto the substrate <b>101</b>.

0085That is, one side of the first lead frame <b>110</b> contacts a plating layer <b>107</b><i>a </i>of a circuit pattern formed on the ceramic layer <b>103</b> formed on one surface of the substrate <b>101</b>, and the other side thereof protrudes from the substrate <b>101</b> toward the outside.

0086Likewise, one side of the second lead frame <b>120</b> contacts a plating layer <b>107</b><i>b </i>of a circuit pattern formed on the ceramic layer <b>103</b> formed on one surface of the substrate <b>101</b>, and the other side thereof protrudes from the substrate <b>101</b> toward the outside.

0087In this regard, one side of the first lead frame <b>110</b> and one side of the second lead frame <b>120</b> are spaced apart to face each other and bonded to the substrate <b>101</b>, and the plating layers <b>107</b><i>a </i>and <b>107</b><i>b </i>of the circuit patterns contacting the first lead frame <b>110</b> and the second lead frame <b>120</b> are also spaced apart from each other on the ceramic layer <b>103</b>.

0088Also, in the present embodiment, the power module package <b>200</b> may further include the first semiconductor chip <b>130</b> mounted on the first lead frame <b>110</b> and the second semiconductor chip <b>140</b> mounted on the second lead frame <b>120</b>.

0089The power module package <b>200</b> according to the present embodiment forms a ceramic layer having excellent characteristics of heat dissipation on one surface of a metal substrate having excellent heat dissipation characteristic and thermal conductivity, forms a circuit pattern of a minimum thickness on the ceramic layer, and bonds a lead frame onto the circuit pattern, and thus the lead frame functions as a heat dissipation substrate, thereby reducing manufacturing cost of a heat dissipation substrate and simultaneously enhancing the characteristics of heat dissipation.

Third Embodiment

0090<figref idref="DRAWINGS">FIG. 3</figref> is a cross-sectional view of a structure of a power module package <b>300</b> according to a second embodiment of the present invention.

0091Redundant descriptions between the first embodiment and the second embodiment will be omitted here, and the same reference numerals will denote the same elements therebetween.

0092Referring to <figref idref="DRAWINGS">FIG. 3</figref>, unlike the power module package <b>200</b> described according to the above-described second embodiment, the power module package <b>300</b> according to the present embodiment has a structure in which the first semiconductor chip <b>130</b> is mounted on the first lead frame <b>110</b>, and the second semiconductor chip <b>140</b> is bonded onto the plating layer <b>107</b><i>b </i>of the circuit pattern formed on the ceramic layer <b>103</b> of the substrate <b>101</b>.

0093The power module package <b>300</b> according to the present embodiment directly bonds the second semiconductor chip <b>140</b> that is a low power semiconductor chip for generating a relatively small amount of heat onto the plating layer <b>107</b><i>b </i>of the circuit pattern formed on the substrate <b>101</b>, thereby reducing cost of the overall products by reducing uses of lead frames.

Fourth Embodiment

0094<figref idref="DRAWINGS">FIG. 4</figref> is a cross-sectional view of a structure of a power module package <b>400</b> according to a second embodiment of the present invention.

0095Redundant descriptions between the first embodiment and the second embodiment will be omitted here, and the same reference numerals will denote the same elements therebetween.

0096Referring to <figref idref="DRAWINGS">FIG. 4</figref>, unlike the power module package <b>200</b> described according to the above-described second embodiment, the power module package <b>400</b> according to the present embodiment has a structure in which both the first semiconductor chip <b>130</b> and the second semiconductor chip <b>140</b> are bonded onto the plating layers <b>107</b><i>b </i>and <b>107</b><i>c </i>of the circuit pattern formed on the ceramic layer <b>103</b> of the substrate <b>101</b>.

0097As described above, the first semiconductor chip <b>130</b> and the second semiconductor chip <b>140</b> are bonded onto the plating layers <b>107</b><i>b </i>and <b>107</b><i>c </i>of the circuit pattern formed on the ceramic layer <b>103</b> of the substrate <b>101</b>, and thus the heat dissipation characteristic may be somewhat lower than that of the power module package <b>200</b> according to the second embodiment, whereas uses of lead frames are greatly reduced, thereby dramatically reducing cost of the overall products.

0098According to the present invention, a lead frame is bonded onto a meal substrate including a ceramic layer having excellent dissipation and insulation characteristics, and thus heat generated from a heating device mounted in the lead frame is dissipated using the lead frame and the metal substrate, thereby improving a dissipation characteristic.

0099Further, a power device and a control device are mounted to be thermally separated from each other, thereby minimizing an influence of heat generated from the power device to the control device.

0100Furthermore, the lead frame is bonded to the metal substrate in which a wire layer is formed through a plating process, which does not need using a thick copper foil, thereby preventing delamination from occurring due to stress between metal layers.

0101Although the embodiments of the present invention have been disclosed for illustrative purposes, it will be appreciated that the present invention is not limited thereto, and those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention.

0102Accordingly, any and all modifications, variations or equivalent arrangements should be considered to be within the scope of the invention, and the detailed scope of the invention will be disclosed by the accompanying claims.